2 * Copyright 2010 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
27 #include "util/u_blitter.h"
28 #include "util/u_memory.h"
29 #include "util/u_format.h"
30 #include "pipebuffer/pb_buffer.h"
31 #include "pipe/p_shader_tokens.h"
32 #include "tgsi/tgsi_parse.h"
33 #include "r600_formats.h"
34 #include "r600_pipe.h"
37 static void r600_spi_update(struct r600_pipe_context
*rctx
);
39 static bool r600_conv_pipe_prim(unsigned pprim
, unsigned *prim
)
41 static const int prim_conv
[] = {
42 V_008958_DI_PT_POINTLIST
,
43 V_008958_DI_PT_LINELIST
,
44 V_008958_DI_PT_LINELOOP
,
45 V_008958_DI_PT_LINESTRIP
,
46 V_008958_DI_PT_TRILIST
,
47 V_008958_DI_PT_TRISTRIP
,
48 V_008958_DI_PT_TRIFAN
,
49 V_008958_DI_PT_QUADLIST
,
50 V_008958_DI_PT_QUADSTRIP
,
51 V_008958_DI_PT_POLYGON
,
58 *prim
= prim_conv
[pprim
];
60 fprintf(stderr
, "%s:%d unsupported %d\n", __func__
, __LINE__
, pprim
);
66 /* common state between evergreen and r600 */
67 void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
)
69 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
70 struct r600_pipe_blend
*blend
= (struct r600_pipe_blend
*)state
;
71 struct r600_pipe_state
*rstate
;
75 rstate
= &blend
->rstate
;
76 rctx
->states
[rstate
->id
] = rstate
;
77 rctx
->cb_target_mask
= blend
->cb_target_mask
;
78 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
81 void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
83 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
84 struct r600_pipe_dsa
*dsa
= state
;
85 struct r600_pipe_state
*rstate
;
89 rstate
= &dsa
->rstate
;
90 rctx
->states
[rstate
->id
] = rstate
;
91 rctx
->alpha_ref
= dsa
->alpha_ref
;
92 rctx
->alpha_ref_dirty
= true;
93 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
96 void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
)
98 struct r600_pipe_rasterizer
*rs
= (struct r600_pipe_rasterizer
*)state
;
99 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
104 rctx
->clamp_vertex_color
= rs
->clamp_vertex_color
;
105 rctx
->clamp_fragment_color
= rs
->clamp_fragment_color
;
106 rctx
->flatshade
= rs
->flatshade
;
107 rctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
108 rctx
->rasterizer
= rs
;
110 rctx
->states
[rs
->rstate
.id
] = &rs
->rstate
;
111 r600_context_pipe_state_set(&rctx
->ctx
, &rs
->rstate
);
113 if (rctx
->chip_class
>= EVERGREEN
) {
114 evergreen_polygon_offset_update(rctx
);
116 r600_polygon_offset_update(rctx
);
118 if (rctx
->ps_shader
&& rctx
->vs_shader
)
119 rctx
->spi_dirty
= true;
122 void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
)
124 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
125 struct r600_pipe_rasterizer
*rs
= (struct r600_pipe_rasterizer
*)state
;
127 if (rctx
->rasterizer
== rs
) {
128 rctx
->rasterizer
= NULL
;
130 if (rctx
->states
[rs
->rstate
.id
] == &rs
->rstate
) {
131 rctx
->states
[rs
->rstate
.id
] = NULL
;
136 void r600_sampler_view_destroy(struct pipe_context
*ctx
,
137 struct pipe_sampler_view
*state
)
139 struct r600_pipe_sampler_view
*resource
= (struct r600_pipe_sampler_view
*)state
;
141 pipe_resource_reference(&state
->texture
, NULL
);
145 void r600_delete_state(struct pipe_context
*ctx
, void *state
)
147 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
148 struct r600_pipe_state
*rstate
= (struct r600_pipe_state
*)state
;
150 if (rctx
->states
[rstate
->id
] == rstate
) {
151 rctx
->states
[rstate
->id
] = NULL
;
153 for (int i
= 0; i
< rstate
->nregs
; i
++) {
154 pipe_resource_reference((struct pipe_resource
**)&rstate
->regs
[i
].bo
, NULL
);
159 void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
161 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
162 struct r600_vertex_element
*v
= (struct r600_vertex_element
*)state
;
164 rctx
->vertex_elements
= v
;
166 u_vbuf_bind_vertex_elements(rctx
->vbuf_mgr
, state
,
169 rctx
->states
[v
->rstate
.id
] = &v
->rstate
;
170 r600_context_pipe_state_set(&rctx
->ctx
, &v
->rstate
);
174 void r600_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
176 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
177 struct r600_vertex_element
*v
= (struct r600_vertex_element
*)state
;
179 if (rctx
->states
[v
->rstate
.id
] == &v
->rstate
) {
180 rctx
->states
[v
->rstate
.id
] = NULL
;
182 if (rctx
->vertex_elements
== state
)
183 rctx
->vertex_elements
= NULL
;
185 pipe_resource_reference((struct pipe_resource
**)&v
->fetch_shader
, NULL
);
186 u_vbuf_destroy_vertex_elements(rctx
->vbuf_mgr
, v
->vmgr_elements
);
191 void r600_set_index_buffer(struct pipe_context
*ctx
,
192 const struct pipe_index_buffer
*ib
)
194 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
197 pipe_resource_reference(&rctx
->index_buffer
.buffer
, ib
->buffer
);
198 memcpy(&rctx
->index_buffer
, ib
, sizeof(rctx
->index_buffer
));
200 pipe_resource_reference(&rctx
->index_buffer
.buffer
, NULL
);
201 memset(&rctx
->index_buffer
, 0, sizeof(rctx
->index_buffer
));
204 /* TODO make this more like a state */
207 void r600_set_vertex_buffers(struct pipe_context
*ctx
, unsigned count
,
208 const struct pipe_vertex_buffer
*buffers
)
210 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
214 for (i
= 0; i
< count
; i
++) {
215 if (!buffers
[i
].buffer
) {
216 if (rctx
->chip_class
>= EVERGREEN
) {
217 evergreen_context_pipe_state_set_fs_resource(&rctx
->ctx
, NULL
, i
);
219 r600_context_pipe_state_set_fs_resource(&rctx
->ctx
, NULL
, i
);
223 for (; i
< rctx
->vbuf_mgr
->nr_real_vertex_buffers
; i
++) {
224 if (rctx
->chip_class
>= EVERGREEN
) {
225 evergreen_context_pipe_state_set_fs_resource(&rctx
->ctx
, NULL
, i
);
227 r600_context_pipe_state_set_fs_resource(&rctx
->ctx
, NULL
, i
);
231 u_vbuf_set_vertex_buffers(rctx
->vbuf_mgr
, count
, buffers
);
234 void *r600_create_vertex_elements(struct pipe_context
*ctx
,
236 const struct pipe_vertex_element
*elements
)
238 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
239 struct r600_vertex_element
*v
= CALLOC_STRUCT(r600_vertex_element
);
247 u_vbuf_create_vertex_elements(rctx
->vbuf_mgr
, count
,
248 elements
, v
->elements
);
250 if (r600_vertex_elements_build_fetch_shader(rctx
, v
)) {
258 void *r600_create_shader_state(struct pipe_context
*ctx
,
259 const struct pipe_shader_state
*state
)
261 struct r600_pipe_shader
*shader
= CALLOC_STRUCT(r600_pipe_shader
);
264 shader
->tokens
= tgsi_dup_tokens(state
->tokens
);
266 r
= r600_pipe_shader_create(ctx
, shader
);
273 void r600_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
275 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
277 /* TODO delete old shader */
278 rctx
->ps_shader
= (struct r600_pipe_shader
*)state
;
280 r600_context_pipe_state_set(&rctx
->ctx
, &rctx
->ps_shader
->rstate
);
282 if (rctx
->ps_shader
&& rctx
->vs_shader
) {
283 rctx
->spi_dirty
= true;
284 r600_adjust_gprs(rctx
);
288 void r600_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
290 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
292 /* TODO delete old shader */
293 rctx
->vs_shader
= (struct r600_pipe_shader
*)state
;
295 r600_context_pipe_state_set(&rctx
->ctx
, &rctx
->vs_shader
->rstate
);
297 if (rctx
->ps_shader
&& rctx
->vs_shader
) {
298 rctx
->spi_dirty
= true;
299 r600_adjust_gprs(rctx
);
303 void r600_delete_ps_shader(struct pipe_context
*ctx
, void *state
)
305 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
306 struct r600_pipe_shader
*shader
= (struct r600_pipe_shader
*)state
;
308 if (rctx
->ps_shader
== shader
) {
309 rctx
->ps_shader
= NULL
;
312 free(shader
->tokens
);
313 r600_pipe_shader_destroy(ctx
, shader
);
317 void r600_delete_vs_shader(struct pipe_context
*ctx
, void *state
)
319 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
320 struct r600_pipe_shader
*shader
= (struct r600_pipe_shader
*)state
;
322 if (rctx
->vs_shader
== shader
) {
323 rctx
->vs_shader
= NULL
;
326 free(shader
->tokens
);
327 r600_pipe_shader_destroy(ctx
, shader
);
331 static void r600_update_alpha_ref(struct r600_pipe_context
*rctx
)
334 struct r600_pipe_state rstate
;
336 alpha_ref
= rctx
->alpha_ref
;
338 if (rctx
->export_16bpc
)
339 alpha_ref
&= ~0x1FFF;
340 r600_pipe_state_add_reg(&rstate
, R_028438_SX_ALPHA_REF
, alpha_ref
, 0xFFFFFFFF, NULL
, 0);
342 r600_context_pipe_state_set(&rctx
->ctx
, &rstate
);
343 rctx
->alpha_ref_dirty
= false;
346 /* FIXME optimize away spi update when it's not needed */
347 static void r600_spi_block_init(struct r600_pipe_context
*rctx
, struct r600_pipe_state
*rstate
)
351 rstate
->id
= R600_PIPE_STATE_SPI
;
352 for (i
= 0; i
< 32; i
++) {
353 r600_pipe_state_add_reg(rstate
, R_028644_SPI_PS_INPUT_CNTL_0
+ i
* 4, 0, 0xFFFFFFFF, NULL
, 0);
357 static void r600_spi_update(struct r600_pipe_context
*rctx
)
359 struct r600_pipe_shader
*shader
= rctx
->ps_shader
;
360 struct r600_pipe_state
*rstate
= &rctx
->spi
;
361 struct r600_shader
*rshader
= &shader
->shader
;
362 unsigned i
, tmp
, sid
;
364 if (rctx
->spi
.id
== 0)
365 r600_spi_block_init(rctx
, &rctx
->spi
);
368 for (i
= 0; i
< rshader
->ninput
; i
++) {
370 sid
= rshader
->input
[i
].spi_sid
;
372 if (!sid
&& (rctx
->chip_class
>= EVERGREEN
))
375 tmp
= S_028644_SEMANTIC(sid
);
377 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_COLOR
||
378 rshader
->input
[i
].name
== TGSI_SEMANTIC_BCOLOR
||
379 rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
) {
380 tmp
|= S_028644_FLAT_SHADE(rctx
->flatshade
);
383 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_GENERIC
&&
384 rctx
->sprite_coord_enable
& (1 << rshader
->input
[i
].sid
)) {
385 tmp
|= S_028644_PT_SPRITE_TEX(1);
388 if (rctx
->chip_class
< EVERGREEN
) {
389 if (rshader
->input
[i
].centroid
)
390 tmp
|= S_028644_SEL_CENTROID(1);
392 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_LINEAR
)
393 tmp
|= S_028644_SEL_LINEAR(1);
396 r600_pipe_state_mod_reg(rstate
, tmp
);
399 rctx
->spi_dirty
= false;
400 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
403 void r600_set_constant_buffer(struct pipe_context
*ctx
, uint shader
, uint index
,
404 struct pipe_resource
*buffer
)
406 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
407 struct r600_resource
*rbuffer
= r600_resource(buffer
);
408 struct r600_pipe_resource_state
*rstate
;
411 /* Note that the state tracker can unbind constant buffers by
414 if (buffer
== NULL
) {
418 r600_upload_const_buffer(rctx
, &rbuffer
, &offset
);
421 case PIPE_SHADER_VERTEX
:
422 rctx
->vs_const_buffer
.nregs
= 0;
423 r600_pipe_state_add_reg(&rctx
->vs_const_buffer
,
424 R_028180_ALU_CONST_BUFFER_SIZE_VS_0
,
425 ALIGN_DIVUP(buffer
->width0
>> 4, 16),
426 0xFFFFFFFF, NULL
, 0);
427 r600_pipe_state_add_reg(&rctx
->vs_const_buffer
,
428 R_028980_ALU_CONST_CACHE_VS_0
,
429 offset
>> 8, 0xFFFFFFFF, rbuffer
, RADEON_USAGE_READ
);
430 r600_context_pipe_state_set(&rctx
->ctx
, &rctx
->vs_const_buffer
);
432 rstate
= &rctx
->vs_const_buffer_resource
[index
];
434 if (rctx
->chip_class
>= EVERGREEN
) {
435 evergreen_pipe_init_buffer_resource(rctx
, rstate
);
437 r600_pipe_init_buffer_resource(rctx
, rstate
);
441 if (rctx
->chip_class
>= EVERGREEN
) {
442 evergreen_pipe_mod_buffer_resource(rstate
, rbuffer
, offset
, 16, RADEON_USAGE_READ
);
443 evergreen_context_pipe_state_set_vs_resource(&rctx
->ctx
, rstate
, index
);
445 r600_pipe_mod_buffer_resource(rstate
, rbuffer
, offset
, 16, RADEON_USAGE_READ
);
446 r600_context_pipe_state_set_vs_resource(&rctx
->ctx
, rstate
, index
);
449 case PIPE_SHADER_FRAGMENT
:
450 rctx
->ps_const_buffer
.nregs
= 0;
451 r600_pipe_state_add_reg(&rctx
->ps_const_buffer
,
452 R_028140_ALU_CONST_BUFFER_SIZE_PS_0
,
453 ALIGN_DIVUP(buffer
->width0
>> 4, 16),
454 0xFFFFFFFF, NULL
, 0);
455 r600_pipe_state_add_reg(&rctx
->ps_const_buffer
,
456 R_028940_ALU_CONST_CACHE_PS_0
,
457 offset
>> 8, 0xFFFFFFFF, rbuffer
, RADEON_USAGE_READ
);
458 r600_context_pipe_state_set(&rctx
->ctx
, &rctx
->ps_const_buffer
);
460 rstate
= &rctx
->ps_const_buffer_resource
[index
];
462 if (rctx
->chip_class
>= EVERGREEN
) {
463 evergreen_pipe_init_buffer_resource(rctx
, rstate
);
465 r600_pipe_init_buffer_resource(rctx
, rstate
);
468 if (rctx
->chip_class
>= EVERGREEN
) {
469 evergreen_pipe_mod_buffer_resource(rstate
, rbuffer
, offset
, 16, RADEON_USAGE_READ
);
470 evergreen_context_pipe_state_set_ps_resource(&rctx
->ctx
, rstate
, index
);
472 r600_pipe_mod_buffer_resource(rstate
, rbuffer
, offset
, 16, RADEON_USAGE_READ
);
473 r600_context_pipe_state_set_ps_resource(&rctx
->ctx
, rstate
, index
);
477 R600_ERR("unsupported %d\n", shader
);
481 if (buffer
!= &rbuffer
->b
.b
.b
)
482 pipe_resource_reference((struct pipe_resource
**)&rbuffer
, NULL
);
485 static void r600_vertex_buffer_update(struct r600_pipe_context
*rctx
)
487 struct r600_pipe_resource_state
*rstate
;
488 struct r600_resource
*rbuffer
;
489 struct pipe_vertex_buffer
*vertex_buffer
;
490 unsigned i
, count
, offset
;
492 if (rctx
->vertex_elements
->vbuffer_need_offset
) {
493 /* one resource per vertex elements */
494 count
= rctx
->vertex_elements
->count
;
496 /* bind vertex buffer once */
497 count
= rctx
->vbuf_mgr
->nr_real_vertex_buffers
;
500 for (i
= 0 ; i
< count
; i
++) {
501 rstate
= &rctx
->fs_resource
[i
];
503 if (rctx
->vertex_elements
->vbuffer_need_offset
) {
504 /* one resource per vertex elements */
505 unsigned vbuffer_index
;
506 vbuffer_index
= rctx
->vertex_elements
->elements
[i
].vertex_buffer_index
;
507 vertex_buffer
= &rctx
->vbuf_mgr
->real_vertex_buffer
[vbuffer_index
];
508 rbuffer
= (struct r600_resource
*)vertex_buffer
->buffer
;
509 offset
= rctx
->vertex_elements
->vbuffer_offset
[i
];
511 /* bind vertex buffer once */
512 vertex_buffer
= &rctx
->vbuf_mgr
->real_vertex_buffer
[i
];
513 rbuffer
= (struct r600_resource
*)vertex_buffer
->buffer
;
516 if (vertex_buffer
== NULL
|| rbuffer
== NULL
)
518 offset
+= vertex_buffer
->buffer_offset
;
521 if (rctx
->chip_class
>= EVERGREEN
) {
522 evergreen_pipe_init_buffer_resource(rctx
, rstate
);
524 r600_pipe_init_buffer_resource(rctx
, rstate
);
528 if (rctx
->chip_class
>= EVERGREEN
) {
529 evergreen_pipe_mod_buffer_resource(rstate
, rbuffer
, offset
, vertex_buffer
->stride
, RADEON_USAGE_READ
);
530 evergreen_context_pipe_state_set_fs_resource(&rctx
->ctx
, rstate
, i
);
532 r600_pipe_mod_buffer_resource(rstate
, rbuffer
, offset
, vertex_buffer
->stride
, RADEON_USAGE_READ
);
533 r600_context_pipe_state_set_fs_resource(&rctx
->ctx
, rstate
, i
);
538 static int r600_shader_rebuild(struct pipe_context
* ctx
, struct r600_pipe_shader
* shader
)
540 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
543 r600_pipe_shader_destroy(ctx
, shader
);
544 r
= r600_pipe_shader_create(ctx
, shader
);
548 r600_context_pipe_state_set(&rctx
->ctx
, &shader
->rstate
);
553 static void r600_update_derived_state(struct r600_pipe_context
*rctx
)
555 if (!rctx
->blitter
->running
) {
556 if (rctx
->have_depth_fb
|| rctx
->have_depth_texture
)
557 r600_flush_depth_textures(rctx
);
560 if (rctx
->chip_class
< EVERGREEN
) {
561 r600_update_sampler_states(rctx
);
564 if (rctx
->vs_shader
->shader
.clamp_color
!= rctx
->clamp_vertex_color
) {
565 r600_shader_rebuild(&rctx
->context
, rctx
->vs_shader
);
568 if ((rctx
->ps_shader
->shader
.clamp_color
!= rctx
->clamp_fragment_color
) ||
569 ((rctx
->chip_class
>= EVERGREEN
) && rctx
->ps_shader
->shader
.fs_write_all
&&
570 (rctx
->ps_shader
->shader
.nr_cbufs
!= rctx
->nr_cbufs
))) {
571 r600_shader_rebuild(&rctx
->context
, rctx
->ps_shader
);
574 if (rctx
->spi_dirty
) {
575 r600_spi_update(rctx
);
578 if (rctx
->alpha_ref_dirty
) {
579 r600_update_alpha_ref(rctx
);
583 void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*dinfo
)
585 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
586 struct pipe_draw_info info
= *dinfo
;
587 struct r600_draw rdraw
= {};
588 struct pipe_index_buffer ib
= {};
592 (info
.indexed
&& !rctx
->index_buffer
.buffer
) ||
593 !r600_conv_pipe_prim(info
.mode
, &prim
)) {
597 r600_update_derived_state(rctx
);
599 u_vbuf_draw_begin(rctx
->vbuf_mgr
, dinfo
);
600 r600_vertex_buffer_update(rctx
);
602 rdraw
.vgt_num_indices
= info
.count
;
603 rdraw
.vgt_num_instances
= info
.instance_count
;
606 /* Adjust min/max_index by the index bias. */
607 if (info
.max_index
!= ~0) {
608 info
.min_index
+= info
.index_bias
;
609 info
.max_index
+= info
.index_bias
;
612 /* Initialize the index buffer struct. */
613 pipe_resource_reference(&ib
.buffer
, rctx
->index_buffer
.buffer
);
614 ib
.index_size
= rctx
->index_buffer
.index_size
;
615 ib
.offset
= rctx
->index_buffer
.offset
+ info
.start
* ib
.index_size
;
617 /* Translate or upload, if needed. */
618 r600_translate_index_buffer(rctx
, &ib
, info
.count
);
620 if (u_vbuf_resource(ib
.buffer
)->user_ptr
) {
621 r600_upload_index_buffer(rctx
, &ib
, info
.count
);
624 /* Initialize the r600_draw struct with index buffer info. */
625 if (ib
.index_size
== 4) {
626 rdraw
.vgt_index_type
= VGT_INDEX_32
|
627 (R600_BIG_ENDIAN
? VGT_DMA_SWAP_32_BIT
: 0);
629 rdraw
.vgt_index_type
= VGT_INDEX_16
|
630 (R600_BIG_ENDIAN
? VGT_DMA_SWAP_16_BIT
: 0);
632 rdraw
.indices
= (struct r600_resource
*)ib
.buffer
;
633 rdraw
.indices_bo_offset
= ib
.offset
;
634 rdraw
.vgt_draw_initiator
= V_0287F0_DI_SRC_SEL_DMA
;
636 info
.index_bias
= info
.start
;
637 rdraw
.vgt_draw_initiator
= V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
640 mask
= (1ULL << ((unsigned)rctx
->framebuffer
.nr_cbufs
* 4)) - 1;
642 if (rctx
->vgt
.id
!= R600_PIPE_STATE_VGT
) {
643 rctx
->vgt
.id
= R600_PIPE_STATE_VGT
;
645 r600_pipe_state_add_reg(&rctx
->vgt
, R_008958_VGT_PRIMITIVE_TYPE
, prim
, 0xFFFFFFFF, NULL
, 0);
646 r600_pipe_state_add_reg(&rctx
->vgt
, R_028238_CB_TARGET_MASK
, rctx
->cb_target_mask
& mask
, 0xFFFFFFFF, NULL
, 0);
647 r600_pipe_state_add_reg(&rctx
->vgt
, R_028400_VGT_MAX_VTX_INDX
, info
.max_index
, 0xFFFFFFFF, NULL
, 0);
648 r600_pipe_state_add_reg(&rctx
->vgt
, R_028404_VGT_MIN_VTX_INDX
, info
.min_index
, 0xFFFFFFFF, NULL
, 0);
649 r600_pipe_state_add_reg(&rctx
->vgt
, R_028408_VGT_INDX_OFFSET
, info
.index_bias
, 0xFFFFFFFF, NULL
, 0);
650 r600_pipe_state_add_reg(&rctx
->vgt
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
, info
.restart_index
, 0xFFFFFFFF, NULL
, 0);
651 r600_pipe_state_add_reg(&rctx
->vgt
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, info
.primitive_restart
, 0xFFFFFFFF, NULL
, 0);
652 r600_pipe_state_add_reg(&rctx
->vgt
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0, 0xFFFFFFFF, NULL
, 0);
653 r600_pipe_state_add_reg(&rctx
->vgt
, R_03CFF4_SQ_VTX_START_INST_LOC
, info
.start_instance
, 0xFFFFFFFF, NULL
, 0);
654 r600_pipe_state_add_reg(&rctx
->vgt
, R_028814_PA_SU_SC_MODE_CNTL
,
656 S_028814_PROVOKING_VTX_LAST(1), NULL
, 0);
660 r600_pipe_state_mod_reg(&rctx
->vgt
, prim
);
661 r600_pipe_state_mod_reg(&rctx
->vgt
, rctx
->cb_target_mask
& mask
);
662 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.max_index
);
663 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.min_index
);
664 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.index_bias
);
665 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.restart_index
);
666 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.primitive_restart
);
667 r600_pipe_state_mod_reg(&rctx
->vgt
, 0);
668 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.start_instance
);
669 if (info
.mode
== PIPE_PRIM_QUADS
|| info
.mode
== PIPE_PRIM_QUAD_STRIP
|| info
.mode
== PIPE_PRIM_POLYGON
) {
670 r600_pipe_state_mod_reg(&rctx
->vgt
, S_028814_PROVOKING_VTX_LAST(1));
673 r600_context_pipe_state_set(&rctx
->ctx
, &rctx
->vgt
);
675 if (rctx
->chip_class
>= EVERGREEN
) {
676 evergreen_context_draw(&rctx
->ctx
, &rdraw
);
678 r600_context_draw(&rctx
->ctx
, &rdraw
);
681 if (rctx
->framebuffer
.zsbuf
)
683 struct pipe_resource
*tex
= rctx
->framebuffer
.zsbuf
->texture
;
684 ((struct r600_resource_texture
*)tex
)->dirty_db
= TRUE
;
687 pipe_resource_reference(&ib
.buffer
, NULL
);
688 u_vbuf_draw_end(rctx
->vbuf_mgr
);
691 void _r600_pipe_state_add_reg(struct r600_context
*ctx
,
692 struct r600_pipe_state
*state
,
693 u32 offset
, u32 value
, u32 mask
,
694 u32 range_id
, u32 block_id
,
695 struct r600_resource
*bo
,
696 enum radeon_bo_usage usage
)
698 struct r600_range
*range
;
699 struct r600_block
*block
;
701 if (bo
) assert(usage
);
703 range
= &ctx
->range
[range_id
];
704 block
= range
->blocks
[block_id
];
705 state
->regs
[state
->nregs
].block
= block
;
706 state
->regs
[state
->nregs
].id
= (offset
- block
->start_offset
) >> 2;
708 state
->regs
[state
->nregs
].value
= value
;
709 state
->regs
[state
->nregs
].mask
= mask
;
710 state
->regs
[state
->nregs
].bo
= bo
;
711 state
->regs
[state
->nregs
].bo_usage
= usage
;
714 assert(state
->nregs
< R600_BLOCK_MAX_REG
);
717 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state
*state
,
718 u32 offset
, u32 value
, u32 mask
,
719 struct r600_resource
*bo
,
720 enum radeon_bo_usage usage
)
722 if (bo
) assert(usage
);
724 state
->regs
[state
->nregs
].id
= offset
;
725 state
->regs
[state
->nregs
].block
= NULL
;
726 state
->regs
[state
->nregs
].value
= value
;
727 state
->regs
[state
->nregs
].mask
= mask
;
728 state
->regs
[state
->nregs
].bo
= bo
;
729 state
->regs
[state
->nregs
].bo_usage
= usage
;
732 assert(state
->nregs
< R600_BLOCK_MAX_REG
);