r600g: add cs memory usage accounting and limit it v3
[mesa.git] / src / gallium / drivers / r600 / r600_state_common.c
1 /*
2 * Copyright 2010 Red Hat Inc.
3 * 2010 Jerome Glisse
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
26 */
27 #include "r600_formats.h"
28 #include "r600_shader.h"
29 #include "r600d.h"
30
31 #include "util/u_draw_quad.h"
32 #include "util/u_index_modify.h"
33 #include "util/u_memory.h"
34 #include "util/u_upload_mgr.h"
35 #include "tgsi/tgsi_parse.h"
36 #include <byteswap.h>
37
38 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
39
40 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw)
41 {
42 cb->buf = CALLOC(1, 4 * num_dw);
43 cb->max_num_dw = num_dw;
44 }
45
46 void r600_release_command_buffer(struct r600_command_buffer *cb)
47 {
48 FREE(cb->buf);
49 }
50
51 void r600_init_atom(struct r600_context *rctx,
52 struct r600_atom *atom,
53 unsigned id,
54 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
55 unsigned num_dw)
56 {
57 assert(id < R600_NUM_ATOMS);
58 assert(rctx->atoms[id] == NULL);
59 rctx->atoms[id] = atom;
60 atom->id = id;
61 atom->emit = emit;
62 atom->num_dw = num_dw;
63 atom->dirty = false;
64 }
65
66 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom)
67 {
68 r600_emit_command_buffer(rctx->rings.gfx.cs, ((struct r600_cso_state*)atom)->cb);
69 }
70
71 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom)
72 {
73 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
74 struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom;
75 unsigned alpha_ref = a->sx_alpha_ref;
76
77 if (rctx->chip_class >= EVERGREEN && a->cb0_export_16bpc) {
78 alpha_ref &= ~0x1FFF;
79 }
80
81 r600_write_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL,
82 a->sx_alpha_test_control |
83 S_028410_ALPHA_TEST_BYPASS(a->bypass));
84 r600_write_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref);
85 }
86
87 static void r600_texture_barrier(struct pipe_context *ctx)
88 {
89 struct r600_context *rctx = (struct r600_context *)ctx;
90
91 rctx->flags |= R600_CONTEXT_WAIT_3D_IDLE;
92 rctx->flags |= R600_CONTEXT_INVAL_READ_CACHES;
93 rctx->flags |= R600_CONTEXT_FLUSH_AND_INV;
94 }
95
96 static unsigned r600_conv_pipe_prim(unsigned prim)
97 {
98 static const unsigned prim_conv[] = {
99 V_008958_DI_PT_POINTLIST,
100 V_008958_DI_PT_LINELIST,
101 V_008958_DI_PT_LINELOOP,
102 V_008958_DI_PT_LINESTRIP,
103 V_008958_DI_PT_TRILIST,
104 V_008958_DI_PT_TRISTRIP,
105 V_008958_DI_PT_TRIFAN,
106 V_008958_DI_PT_QUADLIST,
107 V_008958_DI_PT_QUADSTRIP,
108 V_008958_DI_PT_POLYGON,
109 V_008958_DI_PT_LINELIST_ADJ,
110 V_008958_DI_PT_LINESTRIP_ADJ,
111 V_008958_DI_PT_TRILIST_ADJ,
112 V_008958_DI_PT_TRISTRIP_ADJ,
113 V_008958_DI_PT_RECTLIST
114 };
115 return prim_conv[prim];
116 }
117
118 /* common state between evergreen and r600 */
119
120 static void r600_bind_blend_state_internal(struct r600_context *rctx,
121 struct r600_blend_state *blend, bool blend_disable)
122 {
123 unsigned color_control;
124 bool update_cb = false;
125
126 rctx->alpha_to_one = blend->alpha_to_one;
127 rctx->dual_src_blend = blend->dual_src_blend;
128
129 if (!blend_disable) {
130 r600_set_cso_state_with_cb(&rctx->blend_state, blend, &blend->buffer);
131 color_control = blend->cb_color_control;
132 } else {
133 /* Blending is disabled. */
134 r600_set_cso_state_with_cb(&rctx->blend_state, blend, &blend->buffer_no_blend);
135 color_control = blend->cb_color_control_no_blend;
136 }
137
138 /* Update derived states. */
139 if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) {
140 rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
141 update_cb = true;
142 }
143 if (rctx->chip_class <= R700 &&
144 rctx->cb_misc_state.cb_color_control != color_control) {
145 rctx->cb_misc_state.cb_color_control = color_control;
146 update_cb = true;
147 }
148 if (rctx->cb_misc_state.dual_src_blend != blend->dual_src_blend) {
149 rctx->cb_misc_state.dual_src_blend = blend->dual_src_blend;
150 update_cb = true;
151 }
152 if (update_cb) {
153 rctx->cb_misc_state.atom.dirty = true;
154 }
155 }
156
157 static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
158 {
159 struct r600_context *rctx = (struct r600_context *)ctx;
160 struct r600_blend_state *blend = (struct r600_blend_state *)state;
161
162 if (blend == NULL)
163 return;
164
165 r600_bind_blend_state_internal(rctx, blend, rctx->force_blend_disable);
166 }
167
168 static void r600_set_blend_color(struct pipe_context *ctx,
169 const struct pipe_blend_color *state)
170 {
171 struct r600_context *rctx = (struct r600_context *)ctx;
172
173 rctx->blend_color.state = *state;
174 rctx->blend_color.atom.dirty = true;
175 }
176
177 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom)
178 {
179 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
180 struct pipe_blend_color *state = &rctx->blend_color.state;
181
182 r600_write_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
183 r600_write_value(cs, fui(state->color[0])); /* R_028414_CB_BLEND_RED */
184 r600_write_value(cs, fui(state->color[1])); /* R_028418_CB_BLEND_GREEN */
185 r600_write_value(cs, fui(state->color[2])); /* R_02841C_CB_BLEND_BLUE */
186 r600_write_value(cs, fui(state->color[3])); /* R_028420_CB_BLEND_ALPHA */
187 }
188
189 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom)
190 {
191 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
192 struct r600_vgt_state *a = (struct r600_vgt_state *)atom;
193
194 r600_write_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, a->vgt_multi_prim_ib_reset_en);
195 r600_write_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, a->vgt_multi_prim_ib_reset_indx);
196 }
197
198 void r600_emit_vgt2_state(struct r600_context *rctx, struct r600_atom *atom)
199 {
200 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
201 struct r600_vgt2_state *a = (struct r600_vgt2_state *)atom;
202
203 r600_write_context_reg(cs, R_028408_VGT_INDX_OFFSET, a->vgt_indx_offset);
204 }
205
206 static void r600_set_clip_state(struct pipe_context *ctx,
207 const struct pipe_clip_state *state)
208 {
209 struct r600_context *rctx = (struct r600_context *)ctx;
210 struct pipe_constant_buffer cb;
211
212 rctx->clip_state.state = *state;
213 rctx->clip_state.atom.dirty = true;
214
215 cb.buffer = NULL;
216 cb.user_buffer = state->ucp;
217 cb.buffer_offset = 0;
218 cb.buffer_size = 4*4*8;
219 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, R600_UCP_CONST_BUFFER, &cb);
220 pipe_resource_reference(&cb.buffer, NULL);
221 }
222
223 static void r600_set_stencil_ref(struct pipe_context *ctx,
224 const struct r600_stencil_ref *state)
225 {
226 struct r600_context *rctx = (struct r600_context *)ctx;
227
228 rctx->stencil_ref.state = *state;
229 rctx->stencil_ref.atom.dirty = true;
230 }
231
232 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom)
233 {
234 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
235 struct r600_stencil_ref_state *a = (struct r600_stencil_ref_state*)atom;
236
237 r600_write_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
238 r600_write_value(cs, /* R_028430_DB_STENCILREFMASK */
239 S_028430_STENCILREF(a->state.ref_value[0]) |
240 S_028430_STENCILMASK(a->state.valuemask[0]) |
241 S_028430_STENCILWRITEMASK(a->state.writemask[0]));
242 r600_write_value(cs, /* R_028434_DB_STENCILREFMASK_BF */
243 S_028434_STENCILREF_BF(a->state.ref_value[1]) |
244 S_028434_STENCILMASK_BF(a->state.valuemask[1]) |
245 S_028434_STENCILWRITEMASK_BF(a->state.writemask[1]));
246 }
247
248 static void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
249 const struct pipe_stencil_ref *state)
250 {
251 struct r600_context *rctx = (struct r600_context *)ctx;
252 struct r600_dsa_state *dsa = (struct r600_dsa_state*)rctx->dsa_state.cso;
253 struct r600_stencil_ref ref;
254
255 rctx->stencil_ref.pipe_state = *state;
256
257 if (!dsa)
258 return;
259
260 ref.ref_value[0] = state->ref_value[0];
261 ref.ref_value[1] = state->ref_value[1];
262 ref.valuemask[0] = dsa->valuemask[0];
263 ref.valuemask[1] = dsa->valuemask[1];
264 ref.writemask[0] = dsa->writemask[0];
265 ref.writemask[1] = dsa->writemask[1];
266
267 r600_set_stencil_ref(ctx, &ref);
268 }
269
270 static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
271 {
272 struct r600_context *rctx = (struct r600_context *)ctx;
273 struct r600_dsa_state *dsa = state;
274 struct r600_stencil_ref ref;
275
276 if (state == NULL)
277 return;
278
279 r600_set_cso_state_with_cb(&rctx->dsa_state, dsa, &dsa->buffer);
280
281 ref.ref_value[0] = rctx->stencil_ref.pipe_state.ref_value[0];
282 ref.ref_value[1] = rctx->stencil_ref.pipe_state.ref_value[1];
283 ref.valuemask[0] = dsa->valuemask[0];
284 ref.valuemask[1] = dsa->valuemask[1];
285 ref.writemask[0] = dsa->writemask[0];
286 ref.writemask[1] = dsa->writemask[1];
287
288 r600_set_stencil_ref(ctx, &ref);
289
290 /* Update alphatest state. */
291 if (rctx->alphatest_state.sx_alpha_test_control != dsa->sx_alpha_test_control ||
292 rctx->alphatest_state.sx_alpha_ref != dsa->alpha_ref) {
293 rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control;
294 rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref;
295 rctx->alphatest_state.atom.dirty = true;
296 }
297 }
298
299 static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
300 {
301 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
302 struct r600_context *rctx = (struct r600_context *)ctx;
303
304 if (state == NULL)
305 return;
306
307 rctx->rasterizer = rs;
308
309 r600_set_cso_state_with_cb(&rctx->rasterizer_state, rs, &rs->buffer);
310
311 if (rs->offset_enable &&
312 (rs->offset_units != rctx->poly_offset_state.offset_units ||
313 rs->offset_scale != rctx->poly_offset_state.offset_scale)) {
314 rctx->poly_offset_state.offset_units = rs->offset_units;
315 rctx->poly_offset_state.offset_scale = rs->offset_scale;
316 rctx->poly_offset_state.atom.dirty = true;
317 }
318
319 /* Update clip_misc_state. */
320 if (rctx->clip_misc_state.pa_cl_clip_cntl != rs->pa_cl_clip_cntl ||
321 rctx->clip_misc_state.clip_plane_enable != rs->clip_plane_enable) {
322 rctx->clip_misc_state.pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
323 rctx->clip_misc_state.clip_plane_enable = rs->clip_plane_enable;
324 rctx->clip_misc_state.atom.dirty = true;
325 }
326
327 /* Workaround for a missing scissor enable on r600. */
328 if (rctx->chip_class == R600 &&
329 rs->scissor_enable != rctx->scissor.enable) {
330 rctx->scissor.enable = rs->scissor_enable;
331 rctx->scissor.atom.dirty = true;
332 }
333
334 /* Re-emit PA_SC_LINE_STIPPLE. */
335 rctx->last_primitive_type = -1;
336 }
337
338 static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
339 {
340 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
341
342 r600_release_command_buffer(&rs->buffer);
343 FREE(rs);
344 }
345
346 static void r600_sampler_view_destroy(struct pipe_context *ctx,
347 struct pipe_sampler_view *state)
348 {
349 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
350
351 pipe_resource_reference(&state->texture, NULL);
352 FREE(resource);
353 }
354
355 void r600_sampler_states_dirty(struct r600_context *rctx,
356 struct r600_sampler_states *state)
357 {
358 if (state->dirty_mask) {
359 if (state->dirty_mask & state->has_bordercolor_mask) {
360 rctx->flags |= R600_CONTEXT_WAIT_3D_IDLE;
361 }
362 state->atom.num_dw =
363 util_bitcount(state->dirty_mask & state->has_bordercolor_mask) * 11 +
364 util_bitcount(state->dirty_mask & ~state->has_bordercolor_mask) * 5;
365 state->atom.dirty = true;
366 }
367 }
368
369 static void r600_bind_sampler_states(struct pipe_context *pipe,
370 unsigned shader,
371 unsigned start,
372 unsigned count, void **states)
373 {
374 struct r600_context *rctx = (struct r600_context *)pipe;
375 struct r600_textures_info *dst = &rctx->samplers[shader];
376 struct r600_pipe_sampler_state **rstates = (struct r600_pipe_sampler_state**)states;
377 int seamless_cube_map = -1;
378 unsigned i;
379 /* This sets 1-bit for states with index >= count. */
380 uint32_t disable_mask = ~((1ull << count) - 1);
381 /* These are the new states set by this function. */
382 uint32_t new_mask = 0;
383
384 assert(start == 0); /* XXX fix below */
385
386 for (i = 0; i < count; i++) {
387 struct r600_pipe_sampler_state *rstate = rstates[i];
388
389 if (rstate == dst->states.states[i]) {
390 continue;
391 }
392
393 if (rstate) {
394 if (rstate->border_color_use) {
395 dst->states.has_bordercolor_mask |= 1 << i;
396 } else {
397 dst->states.has_bordercolor_mask &= ~(1 << i);
398 }
399 seamless_cube_map = rstate->seamless_cube_map;
400
401 new_mask |= 1 << i;
402 } else {
403 disable_mask |= 1 << i;
404 }
405 }
406
407 memcpy(dst->states.states, rstates, sizeof(void*) * count);
408 memset(dst->states.states + count, 0, sizeof(void*) * (NUM_TEX_UNITS - count));
409
410 dst->states.enabled_mask &= ~disable_mask;
411 dst->states.dirty_mask &= dst->states.enabled_mask;
412 dst->states.enabled_mask |= new_mask;
413 dst->states.dirty_mask |= new_mask;
414 dst->states.has_bordercolor_mask &= dst->states.enabled_mask;
415
416 r600_sampler_states_dirty(rctx, &dst->states);
417
418 /* Seamless cubemap state. */
419 if (rctx->chip_class <= R700 &&
420 seamless_cube_map != -1 &&
421 seamless_cube_map != rctx->seamless_cube_map.enabled) {
422 /* change in TA_CNTL_AUX need a pipeline flush */
423 rctx->flags |= R600_CONTEXT_WAIT_3D_IDLE;
424 rctx->seamless_cube_map.enabled = seamless_cube_map;
425 rctx->seamless_cube_map.atom.dirty = true;
426 }
427 }
428
429 static void r600_bind_vs_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
430 {
431 r600_bind_sampler_states(ctx, PIPE_SHADER_VERTEX, 0, count, states);
432 }
433
434 static void r600_bind_ps_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
435 {
436 r600_bind_sampler_states(ctx, PIPE_SHADER_FRAGMENT, 0, count, states);
437 }
438
439 static void r600_delete_sampler_state(struct pipe_context *ctx, void *state)
440 {
441 free(state);
442 }
443
444 static void r600_delete_blend_state(struct pipe_context *ctx, void *state)
445 {
446 struct r600_blend_state *blend = (struct r600_blend_state*)state;
447
448 r600_release_command_buffer(&blend->buffer);
449 r600_release_command_buffer(&blend->buffer_no_blend);
450 FREE(blend);
451 }
452
453 static void r600_delete_dsa_state(struct pipe_context *ctx, void *state)
454 {
455 struct r600_dsa_state *dsa = (struct r600_dsa_state *)state;
456
457 r600_release_command_buffer(&dsa->buffer);
458 free(dsa);
459 }
460
461 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
462 {
463 struct r600_context *rctx = (struct r600_context *)ctx;
464
465 r600_set_cso_state(&rctx->vertex_fetch_shader, state);
466 }
467
468 static void r600_delete_vertex_elements(struct pipe_context *ctx, void *state)
469 {
470 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state;
471 pipe_resource_reference((struct pipe_resource**)&shader->buffer, NULL);
472 FREE(shader);
473 }
474
475 static void r600_set_index_buffer(struct pipe_context *ctx,
476 const struct pipe_index_buffer *ib)
477 {
478 struct r600_context *rctx = (struct r600_context *)ctx;
479
480 if (ib) {
481 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
482 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
483 r600_context_add_resource_size(ctx, ib->buffer);
484 } else {
485 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
486 }
487 }
488
489 void r600_vertex_buffers_dirty(struct r600_context *rctx)
490 {
491 if (rctx->vertex_buffer_state.dirty_mask) {
492 rctx->flags |= R600_CONTEXT_INVAL_READ_CACHES;
493 rctx->vertex_buffer_state.atom.num_dw = (rctx->chip_class >= EVERGREEN ? 12 : 11) *
494 util_bitcount(rctx->vertex_buffer_state.dirty_mask);
495 rctx->vertex_buffer_state.atom.dirty = true;
496 }
497 }
498
499 static void r600_set_vertex_buffers(struct pipe_context *ctx,
500 unsigned start_slot, unsigned count,
501 const struct pipe_vertex_buffer *input)
502 {
503 struct r600_context *rctx = (struct r600_context *)ctx;
504 struct r600_vertexbuf_state *state = &rctx->vertex_buffer_state;
505 struct pipe_vertex_buffer *vb = state->vb + start_slot;
506 unsigned i;
507 uint32_t disable_mask = 0;
508 /* These are the new buffers set by this function. */
509 uint32_t new_buffer_mask = 0;
510
511 /* Set vertex buffers. */
512 if (input) {
513 for (i = 0; i < count; i++) {
514 if (memcmp(&input[i], &vb[i], sizeof(struct pipe_vertex_buffer))) {
515 if (input[i].buffer) {
516 vb[i].stride = input[i].stride;
517 vb[i].buffer_offset = input[i].buffer_offset;
518 pipe_resource_reference(&vb[i].buffer, input[i].buffer);
519 new_buffer_mask |= 1 << i;
520 r600_context_add_resource_size(ctx, input[i].buffer);
521 } else {
522 pipe_resource_reference(&vb[i].buffer, NULL);
523 disable_mask |= 1 << i;
524 }
525 }
526 }
527 } else {
528 for (i = 0; i < count; i++) {
529 pipe_resource_reference(&vb[i].buffer, NULL);
530 }
531 disable_mask = ((1ull << count) - 1);
532 }
533
534 disable_mask <<= start_slot;
535 new_buffer_mask <<= start_slot;
536
537 rctx->vertex_buffer_state.enabled_mask &= ~disable_mask;
538 rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask;
539 rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask;
540 rctx->vertex_buffer_state.dirty_mask |= new_buffer_mask;
541
542 r600_vertex_buffers_dirty(rctx);
543 }
544
545 void r600_sampler_views_dirty(struct r600_context *rctx,
546 struct r600_samplerview_state *state)
547 {
548 if (state->dirty_mask) {
549 rctx->flags |= R600_CONTEXT_INVAL_READ_CACHES;
550 state->atom.num_dw = (rctx->chip_class >= EVERGREEN ? 14 : 13) *
551 util_bitcount(state->dirty_mask);
552 state->atom.dirty = true;
553 }
554 }
555
556 static void r600_set_sampler_views(struct pipe_context *pipe, unsigned shader,
557 unsigned start, unsigned count,
558 struct pipe_sampler_view **views)
559 {
560 struct r600_context *rctx = (struct r600_context *) pipe;
561 struct r600_textures_info *dst = &rctx->samplers[shader];
562 struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
563 uint32_t dirty_sampler_states_mask = 0;
564 unsigned i;
565 /* This sets 1-bit for textures with index >= count. */
566 uint32_t disable_mask = ~((1ull << count) - 1);
567 /* These are the new textures set by this function. */
568 uint32_t new_mask = 0;
569
570 /* Set textures with index >= count to NULL. */
571 uint32_t remaining_mask;
572
573 assert(start == 0); /* XXX fix below */
574
575 remaining_mask = dst->views.enabled_mask & disable_mask;
576
577 while (remaining_mask) {
578 i = u_bit_scan(&remaining_mask);
579 assert(dst->views.views[i]);
580
581 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
582 }
583
584 for (i = 0; i < count; i++) {
585 if (rviews[i] == dst->views.views[i]) {
586 continue;
587 }
588
589 if (rviews[i]) {
590 struct r600_texture *rtex =
591 (struct r600_texture*)rviews[i]->base.texture;
592
593 if (rviews[i]->base.texture->target != PIPE_BUFFER) {
594 if (rtex->is_depth && !rtex->is_flushing_texture) {
595 dst->views.compressed_depthtex_mask |= 1 << i;
596 } else {
597 dst->views.compressed_depthtex_mask &= ~(1 << i);
598 }
599
600 /* Track compressed colorbuffers. */
601 if (rtex->cmask_size && rtex->fmask_size) {
602 dst->views.compressed_colortex_mask |= 1 << i;
603 } else {
604 dst->views.compressed_colortex_mask &= ~(1 << i);
605 }
606 }
607 /* Changing from array to non-arrays textures and vice versa requires
608 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
609 if (rctx->chip_class <= R700 &&
610 (dst->states.enabled_mask & (1 << i)) &&
611 (rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
612 rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) {
613 dirty_sampler_states_mask |= 1 << i;
614 }
615
616 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]);
617 new_mask |= 1 << i;
618 r600_context_add_resource_size(pipe, views[i]->texture);
619 } else {
620 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
621 disable_mask |= 1 << i;
622 }
623 }
624
625 dst->views.enabled_mask &= ~disable_mask;
626 dst->views.dirty_mask &= dst->views.enabled_mask;
627 dst->views.enabled_mask |= new_mask;
628 dst->views.dirty_mask |= new_mask;
629 dst->views.compressed_depthtex_mask &= dst->views.enabled_mask;
630 dst->views.compressed_colortex_mask &= dst->views.enabled_mask;
631 dst->views.dirty_txq_constants = TRUE;
632 dst->views.dirty_buffer_constants = TRUE;
633 r600_sampler_views_dirty(rctx, &dst->views);
634
635 if (dirty_sampler_states_mask) {
636 dst->states.dirty_mask |= dirty_sampler_states_mask;
637 r600_sampler_states_dirty(rctx, &dst->states);
638 }
639 }
640
641 static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
642 struct pipe_sampler_view **views)
643 {
644 r600_set_sampler_views(ctx, PIPE_SHADER_VERTEX, 0, count, views);
645 }
646
647 static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
648 struct pipe_sampler_view **views)
649 {
650 r600_set_sampler_views(ctx, PIPE_SHADER_FRAGMENT, 0, count, views);
651 }
652
653 static void r600_set_viewport_state(struct pipe_context *ctx,
654 const struct pipe_viewport_state *state)
655 {
656 struct r600_context *rctx = (struct r600_context *)ctx;
657
658 rctx->viewport.state = *state;
659 rctx->viewport.atom.dirty = true;
660 }
661
662 void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom)
663 {
664 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
665 struct pipe_viewport_state *state = &rctx->viewport.state;
666
667 r600_write_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE_0, 6);
668 r600_write_value(cs, fui(state->scale[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
669 r600_write_value(cs, fui(state->translate[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
670 r600_write_value(cs, fui(state->scale[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
671 r600_write_value(cs, fui(state->translate[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
672 r600_write_value(cs, fui(state->scale[2])); /* R_02844C_PA_CL_VPORT_ZSCALE_0 */
673 r600_write_value(cs, fui(state->translate[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
674 }
675
676 /* Compute the key for the hw shader variant */
677 static INLINE struct r600_shader_key r600_shader_selector_key(struct pipe_context * ctx,
678 struct r600_pipe_shader_selector * sel)
679 {
680 struct r600_context *rctx = (struct r600_context *)ctx;
681 struct r600_shader_key key;
682 memset(&key, 0, sizeof(key));
683
684 if (sel->type == PIPE_SHADER_FRAGMENT) {
685 key.color_two_side = rctx->rasterizer && rctx->rasterizer->two_side;
686 key.alpha_to_one = rctx->alpha_to_one &&
687 rctx->rasterizer && rctx->rasterizer->multisample_enable &&
688 !rctx->framebuffer.cb0_is_integer;
689 key.nr_cbufs = rctx->framebuffer.state.nr_cbufs;
690 /* Dual-source blending only makes sense with nr_cbufs == 1. */
691 if (key.nr_cbufs == 1 && rctx->dual_src_blend)
692 key.nr_cbufs = 2;
693 }
694 return key;
695 }
696
697 /* Select the hw shader variant depending on the current state.
698 * (*dirty) is set to 1 if current variant was changed */
699 static int r600_shader_select(struct pipe_context *ctx,
700 struct r600_pipe_shader_selector* sel,
701 unsigned *dirty)
702 {
703 struct r600_shader_key key;
704 struct r600_context *rctx = (struct r600_context *)ctx;
705 struct r600_pipe_shader * shader = NULL;
706 int r;
707
708 key = r600_shader_selector_key(ctx, sel);
709
710 /* Check if we don't need to change anything.
711 * This path is also used for most shaders that don't need multiple
712 * variants, it will cost just a computation of the key and this
713 * test. */
714 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
715 return 0;
716 }
717
718 /* lookup if we have other variants in the list */
719 if (sel->num_shaders > 1) {
720 struct r600_pipe_shader *p = sel->current, *c = p->next_variant;
721
722 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
723 p = c;
724 c = c->next_variant;
725 }
726
727 if (c) {
728 p->next_variant = c->next_variant;
729 shader = c;
730 }
731 }
732
733 if (unlikely(!shader)) {
734 shader = CALLOC(1, sizeof(struct r600_pipe_shader));
735 shader->selector = sel;
736
737 r = r600_pipe_shader_create(ctx, shader, key);
738 if (unlikely(r)) {
739 R600_ERR("Failed to build shader variant (type=%u) %d\n",
740 sel->type, r);
741 sel->current = NULL;
742 return r;
743 }
744
745 /* We don't know the value of nr_ps_max_color_exports until we built
746 * at least one variant, so we may need to recompute the key after
747 * building first variant. */
748 if (sel->type == PIPE_SHADER_FRAGMENT &&
749 sel->num_shaders == 0) {
750 sel->nr_ps_max_color_exports = shader->shader.nr_ps_max_color_exports;
751 key = r600_shader_selector_key(ctx, sel);
752 }
753
754 shader->key = key;
755 sel->num_shaders++;
756 }
757
758 if (dirty)
759 *dirty = 1;
760
761 shader->next_variant = sel->current;
762 sel->current = shader;
763
764 if (rctx->ps_shader &&
765 rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
766 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
767 rctx->cb_misc_state.atom.dirty = true;
768 }
769 return 0;
770 }
771
772 static void *r600_create_shader_state(struct pipe_context *ctx,
773 const struct pipe_shader_state *state,
774 unsigned pipe_shader_type)
775 {
776 struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector);
777 int r;
778
779 sel->type = pipe_shader_type;
780 sel->tokens = tgsi_dup_tokens(state->tokens);
781 sel->so = state->stream_output;
782
783 r = r600_shader_select(ctx, sel, NULL);
784 if (r)
785 return NULL;
786
787 return sel;
788 }
789
790 static void *r600_create_ps_state(struct pipe_context *ctx,
791 const struct pipe_shader_state *state)
792 {
793 return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
794 }
795
796 static void *r600_create_vs_state(struct pipe_context *ctx,
797 const struct pipe_shader_state *state)
798 {
799 return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
800 }
801
802 static void r600_bind_ps_state(struct pipe_context *ctx, void *state)
803 {
804 struct r600_context *rctx = (struct r600_context *)ctx;
805
806 if (!state)
807 state = rctx->dummy_pixel_shader;
808
809 rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
810 r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
811
812 r600_context_add_resource_size(ctx, (struct pipe_resource *)rctx->ps_shader->current->bo);
813
814 if (rctx->chip_class <= R700) {
815 bool multiwrite = rctx->ps_shader->current->shader.fs_write_all;
816
817 if (rctx->cb_misc_state.multiwrite != multiwrite) {
818 rctx->cb_misc_state.multiwrite = multiwrite;
819 rctx->cb_misc_state.atom.dirty = true;
820 }
821 }
822
823 if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
824 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
825 rctx->cb_misc_state.atom.dirty = true;
826 }
827
828 if (rctx->chip_class >= EVERGREEN) {
829 evergreen_update_db_shader_control(rctx);
830 } else {
831 r600_update_db_shader_control(rctx);
832 }
833 }
834
835 static void r600_bind_vs_state(struct pipe_context *ctx, void *state)
836 {
837 struct r600_context *rctx = (struct r600_context *)ctx;
838
839 rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
840 if (state) {
841 r600_context_pipe_state_set(rctx, &rctx->vs_shader->current->rstate);
842
843 r600_context_add_resource_size(ctx, (struct pipe_resource *)rctx->vs_shader->current->bo);
844
845 /* Update clip misc state. */
846 if (rctx->vs_shader->current->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
847 rctx->vs_shader->current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write) {
848 rctx->clip_misc_state.pa_cl_vs_out_cntl = rctx->vs_shader->current->pa_cl_vs_out_cntl;
849 rctx->clip_misc_state.clip_dist_write = rctx->vs_shader->current->shader.clip_dist_write;
850 rctx->clip_misc_state.atom.dirty = true;
851 }
852 }
853 }
854
855 static void r600_delete_shader_selector(struct pipe_context *ctx,
856 struct r600_pipe_shader_selector *sel)
857 {
858 struct r600_pipe_shader *p = sel->current, *c;
859 while (p) {
860 c = p->next_variant;
861 r600_pipe_shader_destroy(ctx, p);
862 free(p);
863 p = c;
864 }
865
866 free(sel->tokens);
867 free(sel);
868 }
869
870
871 static void r600_delete_ps_state(struct pipe_context *ctx, void *state)
872 {
873 struct r600_context *rctx = (struct r600_context *)ctx;
874 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
875
876 if (rctx->ps_shader == sel) {
877 rctx->ps_shader = NULL;
878 }
879
880 r600_delete_shader_selector(ctx, sel);
881 }
882
883 static void r600_delete_vs_state(struct pipe_context *ctx, void *state)
884 {
885 struct r600_context *rctx = (struct r600_context *)ctx;
886 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
887
888 if (rctx->vs_shader == sel) {
889 rctx->vs_shader = NULL;
890 }
891
892 r600_delete_shader_selector(ctx, sel);
893 }
894
895 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
896 {
897 if (state->dirty_mask) {
898 rctx->flags |= R600_CONTEXT_INVAL_READ_CACHES;
899 state->atom.num_dw = rctx->chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
900 : util_bitcount(state->dirty_mask)*19;
901 state->atom.dirty = true;
902 }
903 }
904
905 static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
906 struct pipe_constant_buffer *input)
907 {
908 struct r600_context *rctx = (struct r600_context *)ctx;
909 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
910 struct pipe_constant_buffer *cb;
911 const uint8_t *ptr;
912
913 /* Note that the state tracker can unbind constant buffers by
914 * passing NULL here.
915 */
916 if (unlikely(!input)) {
917 state->enabled_mask &= ~(1 << index);
918 state->dirty_mask &= ~(1 << index);
919 pipe_resource_reference(&state->cb[index].buffer, NULL);
920 return;
921 }
922
923 cb = &state->cb[index];
924 cb->buffer_size = input->buffer_size;
925
926 ptr = input->user_buffer;
927
928 if (ptr) {
929 /* Upload the user buffer. */
930 if (R600_BIG_ENDIAN) {
931 uint32_t *tmpPtr;
932 unsigned i, size = input->buffer_size;
933
934 if (!(tmpPtr = malloc(size))) {
935 R600_ERR("Failed to allocate BE swap buffer.\n");
936 return;
937 }
938
939 for (i = 0; i < size / 4; ++i) {
940 tmpPtr[i] = bswap_32(((uint32_t *)ptr)[i]);
941 }
942
943 u_upload_data(rctx->uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer);
944 free(tmpPtr);
945 } else {
946 u_upload_data(rctx->uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer);
947 }
948 /* account it in gtt */
949 rctx->gtt += input->buffer_size;
950 } else {
951 /* Setup the hw buffer. */
952 cb->buffer_offset = input->buffer_offset;
953 pipe_resource_reference(&cb->buffer, input->buffer);
954 r600_context_add_resource_size(ctx, input->buffer);
955 }
956
957 state->enabled_mask |= 1 << index;
958 state->dirty_mask |= 1 << index;
959 r600_constant_buffers_dirty(rctx, state);
960 }
961
962 static struct pipe_stream_output_target *
963 r600_create_so_target(struct pipe_context *ctx,
964 struct pipe_resource *buffer,
965 unsigned buffer_offset,
966 unsigned buffer_size)
967 {
968 struct r600_context *rctx = (struct r600_context *)ctx;
969 struct r600_so_target *t;
970
971 t = CALLOC_STRUCT(r600_so_target);
972 if (!t) {
973 return NULL;
974 }
975
976 u_suballocator_alloc(rctx->allocator_so_filled_size, 4,
977 &t->buf_filled_size_offset,
978 (struct pipe_resource**)&t->buf_filled_size);
979 if (!t->buf_filled_size) {
980 FREE(t);
981 return NULL;
982 }
983
984 t->b.reference.count = 1;
985 t->b.context = ctx;
986 pipe_resource_reference(&t->b.buffer, buffer);
987 t->b.buffer_offset = buffer_offset;
988 t->b.buffer_size = buffer_size;
989 return &t->b;
990 }
991
992 static void r600_so_target_destroy(struct pipe_context *ctx,
993 struct pipe_stream_output_target *target)
994 {
995 struct r600_so_target *t = (struct r600_so_target*)target;
996 pipe_resource_reference(&t->b.buffer, NULL);
997 pipe_resource_reference((struct pipe_resource**)&t->buf_filled_size, NULL);
998 FREE(t);
999 }
1000
1001 static void r600_set_so_targets(struct pipe_context *ctx,
1002 unsigned num_targets,
1003 struct pipe_stream_output_target **targets,
1004 unsigned append_bitmask)
1005 {
1006 struct r600_context *rctx = (struct r600_context *)ctx;
1007 unsigned i;
1008
1009 /* Stop streamout. */
1010 if (rctx->num_so_targets && !rctx->streamout_start) {
1011 r600_context_streamout_end(rctx);
1012 }
1013
1014 /* Set the new targets. */
1015 for (i = 0; i < num_targets; i++) {
1016 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]);
1017 r600_context_add_resource_size(ctx, targets[i]->buffer);
1018 }
1019 for (; i < rctx->num_so_targets; i++) {
1020 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL);
1021 }
1022
1023 rctx->num_so_targets = num_targets;
1024 rctx->streamout_start = num_targets != 0;
1025 rctx->streamout_append_bitmask = append_bitmask;
1026 }
1027
1028 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1029 {
1030 struct r600_context *rctx = (struct r600_context*)pipe;
1031
1032 if (rctx->sample_mask.sample_mask == (uint16_t)sample_mask)
1033 return;
1034
1035 rctx->sample_mask.sample_mask = sample_mask;
1036 rctx->sample_mask.atom.dirty = true;
1037 }
1038
1039 /*
1040 * On r600/700 hw we don't have vertex fetch swizzle, though TBO
1041 * doesn't require full swizzles it does need masking and setting alpha
1042 * to one, so we setup a set of 5 constants with the masks + alpha value
1043 * then in the shader, we AND the 4 components with 0xffffffff or 0,
1044 * then OR the alpha with the value given here.
1045 * We use a 6th constant to store the txq buffer size in
1046 */
1047 static void r600_setup_buffer_constants(struct r600_context *rctx, int shader_type)
1048 {
1049 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1050 int bits;
1051 uint32_t array_size;
1052 struct pipe_constant_buffer cb;
1053 int i, j;
1054
1055 if (!samplers->views.dirty_buffer_constants)
1056 return;
1057
1058 samplers->views.dirty_buffer_constants = FALSE;
1059
1060 bits = util_last_bit(samplers->views.enabled_mask);
1061 array_size = bits * 8 * sizeof(uint32_t) * 4;
1062 samplers->buffer_constants = realloc(samplers->buffer_constants, array_size);
1063 memset(samplers->buffer_constants, 0, array_size);
1064 for (i = 0; i < bits; i++) {
1065 if (samplers->views.enabled_mask & (1 << i)) {
1066 int offset = i * 8;
1067 const struct util_format_description *desc;
1068 desc = util_format_description(samplers->views.views[i]->base.format);
1069
1070 for (j = 0; j < 4; j++)
1071 if (j < desc->nr_channels)
1072 samplers->buffer_constants[offset+j] = 0xffffffff;
1073 else
1074 samplers->buffer_constants[offset+j] = 0x0;
1075 if (desc->nr_channels < 4) {
1076 if (desc->channel[0].pure_integer)
1077 samplers->buffer_constants[offset+4] = 1;
1078 else
1079 samplers->buffer_constants[offset+4] = 0x3f800000;
1080 } else
1081 samplers->buffer_constants[offset + 4] = 0;
1082
1083 samplers->buffer_constants[offset + 5] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
1084 }
1085 }
1086
1087 cb.buffer = NULL;
1088 cb.user_buffer = samplers->buffer_constants;
1089 cb.buffer_offset = 0;
1090 cb.buffer_size = array_size;
1091 rctx->context.set_constant_buffer(&rctx->context, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
1092 pipe_resource_reference(&cb.buffer, NULL);
1093 }
1094
1095 /* On evergreen we only need to store the buffer size for TXQ */
1096 static void eg_setup_buffer_constants(struct r600_context *rctx, int shader_type)
1097 {
1098 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1099 int bits;
1100 uint32_t array_size;
1101 struct pipe_constant_buffer cb;
1102 int i;
1103
1104 if (!samplers->views.dirty_buffer_constants)
1105 return;
1106
1107 samplers->views.dirty_buffer_constants = FALSE;
1108
1109 bits = util_last_bit(samplers->views.enabled_mask);
1110 array_size = bits * sizeof(uint32_t) * 4;
1111 samplers->buffer_constants = realloc(samplers->buffer_constants, array_size);
1112 memset(samplers->buffer_constants, 0, array_size);
1113 for (i = 0; i < bits; i++)
1114 if (samplers->views.enabled_mask & (1 << i))
1115 samplers->buffer_constants[i] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
1116
1117 cb.buffer = NULL;
1118 cb.user_buffer = samplers->buffer_constants;
1119 cb.buffer_offset = 0;
1120 cb.buffer_size = array_size;
1121 rctx->context.set_constant_buffer(&rctx->context, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
1122 pipe_resource_reference(&cb.buffer, NULL);
1123 }
1124
1125 static void r600_setup_txq_cube_array_constants(struct r600_context *rctx, int shader_type)
1126 {
1127 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1128 int bits;
1129 uint32_t array_size;
1130 struct pipe_constant_buffer cb;
1131 int i;
1132
1133 if (!samplers->views.dirty_txq_constants)
1134 return;
1135
1136 samplers->views.dirty_txq_constants = FALSE;
1137
1138 bits = util_last_bit(samplers->views.enabled_mask);
1139 array_size = bits * sizeof(uint32_t) * 4;
1140 samplers->txq_constants = realloc(samplers->txq_constants, array_size);
1141 memset(samplers->txq_constants, 0, array_size);
1142 for (i = 0; i < bits; i++)
1143 if (samplers->views.enabled_mask & (1 << i))
1144 samplers->txq_constants[i] = samplers->views.views[i]->base.texture->array_size / 6;
1145
1146 cb.buffer = NULL;
1147 cb.user_buffer = samplers->txq_constants;
1148 cb.buffer_offset = 0;
1149 cb.buffer_size = array_size;
1150 rctx->context.set_constant_buffer(&rctx->context, shader_type, R600_TXQ_CONST_BUFFER, &cb);
1151 pipe_resource_reference(&cb.buffer, NULL);
1152 }
1153
1154 static bool r600_update_derived_state(struct r600_context *rctx)
1155 {
1156 struct pipe_context * ctx = (struct pipe_context*)rctx;
1157 unsigned ps_dirty = 0;
1158 bool blend_disable;
1159
1160 if (!rctx->blitter->running) {
1161 unsigned i;
1162
1163 /* Decompress textures if needed. */
1164 for (i = 0; i < PIPE_SHADER_TYPES; i++) {
1165 struct r600_samplerview_state *views = &rctx->samplers[i].views;
1166 if (views->compressed_depthtex_mask) {
1167 r600_decompress_depth_textures(rctx, views);
1168 }
1169 if (views->compressed_colortex_mask) {
1170 r600_decompress_color_textures(rctx, views);
1171 }
1172 }
1173 }
1174
1175 r600_shader_select(ctx, rctx->ps_shader, &ps_dirty);
1176
1177 if (rctx->ps_shader && rctx->rasterizer &&
1178 ((rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable) ||
1179 (rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade))) {
1180
1181 if (rctx->chip_class >= EVERGREEN)
1182 evergreen_pipe_shader_ps(ctx, rctx->ps_shader->current);
1183 else
1184 r600_pipe_shader_ps(ctx, rctx->ps_shader->current);
1185
1186 ps_dirty = 1;
1187 }
1188
1189 if (ps_dirty)
1190 r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
1191
1192 /* on R600 we stuff masks + txq info into one constant buffer */
1193 /* on evergreen we only need a txq info one */
1194 if (rctx->chip_class < EVERGREEN) {
1195 if (rctx->ps_shader && rctx->ps_shader->current->shader.uses_tex_buffers)
1196 r600_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
1197 if (rctx->vs_shader && rctx->vs_shader->current->shader.uses_tex_buffers)
1198 r600_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
1199 } else {
1200 if (rctx->ps_shader && rctx->ps_shader->current->shader.uses_tex_buffers)
1201 eg_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
1202 if (rctx->vs_shader && rctx->vs_shader->current->shader.uses_tex_buffers)
1203 eg_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
1204 }
1205
1206
1207 if (rctx->ps_shader && rctx->ps_shader->current->shader.has_txq_cube_array_z_comp)
1208 r600_setup_txq_cube_array_constants(rctx, PIPE_SHADER_FRAGMENT);
1209 if (rctx->vs_shader && rctx->vs_shader->current->shader.has_txq_cube_array_z_comp)
1210 r600_setup_txq_cube_array_constants(rctx, PIPE_SHADER_VERTEX);
1211
1212 if (rctx->chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
1213 if (!r600_adjust_gprs(rctx)) {
1214 /* discard rendering */
1215 return false;
1216 }
1217 }
1218
1219 blend_disable = (rctx->dual_src_blend &&
1220 rctx->ps_shader->current->nr_ps_color_outputs < 2);
1221
1222 if (blend_disable != rctx->force_blend_disable) {
1223 rctx->force_blend_disable = blend_disable;
1224 r600_bind_blend_state_internal(rctx,
1225 rctx->blend_state.cso,
1226 blend_disable);
1227 }
1228 return true;
1229 }
1230
1231 static unsigned r600_conv_prim_to_gs_out(unsigned mode)
1232 {
1233 static const int prim_conv[] = {
1234 V_028A6C_OUTPRIM_TYPE_POINTLIST,
1235 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1236 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1237 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1238 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1239 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1240 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1241 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1242 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1243 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1244 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1245 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1246 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1247 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1248 V_028A6C_OUTPRIM_TYPE_TRISTRIP
1249 };
1250 assert(mode < Elements(prim_conv));
1251
1252 return prim_conv[mode];
1253 }
1254
1255 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1256 {
1257 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
1258 struct r600_clip_misc_state *state = &rctx->clip_misc_state;
1259
1260 r600_write_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
1261 state->pa_cl_clip_cntl |
1262 (state->clip_dist_write ? 0 : state->clip_plane_enable & 0x3F));
1263 r600_write_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
1264 state->pa_cl_vs_out_cntl |
1265 (state->clip_plane_enable & state->clip_dist_write));
1266 }
1267
1268 static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
1269 {
1270 struct r600_context *rctx = (struct r600_context *)ctx;
1271 struct pipe_draw_info info = *dinfo;
1272 struct pipe_index_buffer ib = {};
1273 unsigned i;
1274 struct r600_block *dirty_block = NULL, *next_block = NULL;
1275 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
1276
1277 if (!info.count && (info.indexed || !info.count_from_stream_output)) {
1278 assert(0);
1279 return;
1280 }
1281
1282 if (!rctx->vs_shader) {
1283 assert(0);
1284 return;
1285 }
1286
1287 /* make sure that the gfx ring is only one active */
1288 if (rctx->rings.dma.cs) {
1289 rctx->rings.dma.flush(rctx, RADEON_FLUSH_ASYNC);
1290 }
1291
1292 if (!r600_update_derived_state(rctx)) {
1293 /* useless to render because current rendering command
1294 * can't be achieved
1295 */
1296 return;
1297 }
1298
1299 if (info.indexed) {
1300 /* Initialize the index buffer struct. */
1301 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
1302 ib.user_buffer = rctx->index_buffer.user_buffer;
1303 ib.index_size = rctx->index_buffer.index_size;
1304 ib.offset = rctx->index_buffer.offset + info.start * ib.index_size;
1305
1306 /* Translate 8-bit indices to 16-bit. */
1307 if (ib.index_size == 1) {
1308 struct pipe_resource *out_buffer = NULL;
1309 unsigned out_offset;
1310 void *ptr;
1311
1312 u_upload_alloc(rctx->uploader, 0, info.count * 2,
1313 &out_offset, &out_buffer, &ptr);
1314
1315 util_shorten_ubyte_elts_to_userptr(
1316 &rctx->context, &ib, 0, ib.offset, info.count, ptr);
1317
1318 pipe_resource_reference(&ib.buffer, NULL);
1319 ib.user_buffer = NULL;
1320 ib.buffer = out_buffer;
1321 ib.offset = out_offset;
1322 ib.index_size = 2;
1323 }
1324
1325 /* Upload the index buffer.
1326 * The upload is skipped for small index counts on little-endian machines
1327 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
1328 * Note: Instanced rendering in combination with immediate indices hangs. */
1329 if (ib.user_buffer && (R600_BIG_ENDIAN || info.instance_count > 1 ||
1330 info.count*ib.index_size > 20)) {
1331 u_upload_data(rctx->uploader, 0, info.count * ib.index_size,
1332 ib.user_buffer, &ib.offset, &ib.buffer);
1333 ib.user_buffer = NULL;
1334 }
1335 } else {
1336 info.index_bias = info.start;
1337 }
1338
1339 /* Enable stream out if needed. */
1340 if (rctx->streamout_start) {
1341 r600_context_streamout_begin(rctx);
1342 rctx->streamout_start = FALSE;
1343 }
1344
1345 /* Set the index offset and multi primitive */
1346 if (rctx->vgt2_state.vgt_indx_offset != info.index_bias) {
1347 rctx->vgt2_state.vgt_indx_offset = info.index_bias;
1348 rctx->vgt2_state.atom.dirty = true;
1349 }
1350 if (rctx->vgt_state.vgt_multi_prim_ib_reset_en != info.primitive_restart ||
1351 rctx->vgt_state.vgt_multi_prim_ib_reset_indx != info.restart_index) {
1352 rctx->vgt_state.vgt_multi_prim_ib_reset_en = info.primitive_restart;
1353 rctx->vgt_state.vgt_multi_prim_ib_reset_indx = info.restart_index;
1354 rctx->vgt_state.atom.dirty = true;
1355 }
1356
1357 /* Emit states. */
1358 r600_need_cs_space(rctx, ib.user_buffer ? 5 : 0, TRUE);
1359 r600_flush_emit(rctx);
1360
1361 for (i = 0; i < R600_NUM_ATOMS; i++) {
1362 if (rctx->atoms[i] == NULL || !rctx->atoms[i]->dirty) {
1363 continue;
1364 }
1365 r600_emit_atom(rctx, rctx->atoms[i]);
1366 }
1367 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) {
1368 r600_context_block_emit_dirty(rctx, dirty_block, 0 /* pkt_flags */);
1369 }
1370 rctx->pm4_dirty_cdwords = 0;
1371
1372 /* Update start instance. */
1373 if (rctx->last_start_instance != info.start_instance) {
1374 r600_write_ctl_const(cs, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
1375 rctx->last_start_instance = info.start_instance;
1376 }
1377
1378 /* Update the primitive type. */
1379 if (rctx->last_primitive_type != info.mode) {
1380 unsigned ls_mask = 0;
1381
1382 if (info.mode == PIPE_PRIM_LINES)
1383 ls_mask = 1;
1384 else if (info.mode == PIPE_PRIM_LINE_STRIP ||
1385 info.mode == PIPE_PRIM_LINE_LOOP)
1386 ls_mask = 2;
1387
1388 r600_write_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
1389 S_028A0C_AUTO_RESET_CNTL(ls_mask) |
1390 (rctx->rasterizer ? rctx->rasterizer->pa_sc_line_stipple : 0));
1391 r600_write_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
1392 r600_conv_prim_to_gs_out(info.mode));
1393 r600_write_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE,
1394 r600_conv_pipe_prim(info.mode));
1395
1396 rctx->last_primitive_type = info.mode;
1397 }
1398
1399 /* Draw packets. */
1400 cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->predicate_drawing);
1401 cs->buf[cs->cdw++] = info.instance_count;
1402 if (info.indexed) {
1403 cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->predicate_drawing);
1404 cs->buf[cs->cdw++] = ib.index_size == 4 ?
1405 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
1406 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
1407
1408 if (ib.user_buffer) {
1409 unsigned size_bytes = info.count*ib.index_size;
1410 unsigned size_dw = align(size_bytes, 4) / 4;
1411 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_IMMD, 1 + size_dw, rctx->predicate_drawing);
1412 cs->buf[cs->cdw++] = info.count;
1413 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_IMMEDIATE;
1414 memcpy(cs->buf+cs->cdw, ib.user_buffer, size_bytes);
1415 cs->cdw += size_dw;
1416 } else {
1417 uint64_t va = r600_resource_va(ctx->screen, ib.buffer) + ib.offset;
1418 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->predicate_drawing);
1419 cs->buf[cs->cdw++] = va;
1420 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
1421 cs->buf[cs->cdw++] = info.count;
1422 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
1423 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->predicate_drawing);
1424 cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, &rctx->rings.gfx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
1425 }
1426 } else {
1427 if (info.count_from_stream_output) {
1428 struct r600_so_target *t = (struct r600_so_target*)info.count_from_stream_output;
1429 uint64_t va = r600_resource_va(&rctx->screen->screen, (void*)t->buf_filled_size) + t->buf_filled_size_offset;
1430
1431 r600_write_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
1432
1433 cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0);
1434 cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG;
1435 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */
1436 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
1437 cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */
1438 cs->buf[cs->cdw++] = 0; /* unused */
1439
1440 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1441 cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, &rctx->rings.gfx, t->buf_filled_size, RADEON_USAGE_READ);
1442 }
1443
1444 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->predicate_drawing);
1445 cs->buf[cs->cdw++] = info.count;
1446 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
1447 (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
1448 }
1449
1450 #if R600_TRACE_CS
1451 if (rctx->screen->trace_bo) {
1452 r600_trace_emit(rctx);
1453 }
1454 #endif
1455
1456 /* Set the depth buffer as dirty. */
1457 if (rctx->framebuffer.state.zsbuf) {
1458 struct pipe_surface *surf = rctx->framebuffer.state.zsbuf;
1459 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
1460
1461 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1462 }
1463 if (rctx->framebuffer.compressed_cb_mask) {
1464 struct pipe_surface *surf;
1465 struct r600_texture *rtex;
1466 unsigned mask = rctx->framebuffer.compressed_cb_mask;
1467
1468 do {
1469 unsigned i = u_bit_scan(&mask);
1470 surf = rctx->framebuffer.state.cbufs[i];
1471 rtex = (struct r600_texture*)surf->texture;
1472
1473 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1474
1475 } while (mask);
1476 }
1477
1478 pipe_resource_reference(&ib.buffer, NULL);
1479 }
1480
1481 void r600_draw_rectangle(struct blitter_context *blitter,
1482 int x1, int y1, int x2, int y2, float depth,
1483 enum blitter_attrib_type type, const union pipe_color_union *attrib)
1484 {
1485 struct r600_context *rctx = (struct r600_context*)util_blitter_get_pipe(blitter);
1486 struct pipe_viewport_state viewport;
1487 struct pipe_resource *buf = NULL;
1488 unsigned offset = 0;
1489 float *vb;
1490
1491 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
1492 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
1493 return;
1494 }
1495
1496 /* Some operations (like color resolve on r6xx) don't work
1497 * with the conventional primitive types.
1498 * One that works is PT_RECTLIST, which we use here. */
1499
1500 /* setup viewport */
1501 viewport.scale[0] = 1.0f;
1502 viewport.scale[1] = 1.0f;
1503 viewport.scale[2] = 1.0f;
1504 viewport.scale[3] = 1.0f;
1505 viewport.translate[0] = 0.0f;
1506 viewport.translate[1] = 0.0f;
1507 viewport.translate[2] = 0.0f;
1508 viewport.translate[3] = 0.0f;
1509 rctx->context.set_viewport_state(&rctx->context, &viewport);
1510
1511 /* Upload vertices. The hw rectangle has only 3 vertices,
1512 * I guess the 4th one is derived from the first 3.
1513 * The vertex specification should match u_blitter's vertex element state. */
1514 u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, &offset, &buf, (void**)&vb);
1515 vb[0] = x1;
1516 vb[1] = y1;
1517 vb[2] = depth;
1518 vb[3] = 1;
1519
1520 vb[8] = x1;
1521 vb[9] = y2;
1522 vb[10] = depth;
1523 vb[11] = 1;
1524
1525 vb[16] = x2;
1526 vb[17] = y1;
1527 vb[18] = depth;
1528 vb[19] = 1;
1529
1530 if (attrib) {
1531 memcpy(vb+4, attrib->f, sizeof(float)*4);
1532 memcpy(vb+12, attrib->f, sizeof(float)*4);
1533 memcpy(vb+20, attrib->f, sizeof(float)*4);
1534 }
1535
1536 /* draw */
1537 util_draw_vertex_buffer(&rctx->context, NULL, buf, rctx->blitter->vb_slot, offset,
1538 R600_PRIM_RECTANGLE_LIST, 3, 2);
1539 pipe_resource_reference(&buf, NULL);
1540 }
1541
1542 void _r600_pipe_state_add_reg_bo(struct r600_context *ctx,
1543 struct r600_pipe_state *state,
1544 uint32_t offset, uint32_t value,
1545 uint32_t range_id, uint32_t block_id,
1546 struct r600_resource *bo,
1547 enum radeon_bo_usage usage)
1548
1549 {
1550 struct r600_range *range;
1551 struct r600_block *block;
1552
1553 if (bo) assert(usage);
1554
1555 range = &ctx->range[range_id];
1556 block = range->blocks[block_id];
1557 state->regs[state->nregs].block = block;
1558 state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
1559
1560 state->regs[state->nregs].value = value;
1561 state->regs[state->nregs].bo = bo;
1562 state->regs[state->nregs].bo_usage = usage;
1563
1564 state->nregs++;
1565 assert(state->nregs < R600_BLOCK_MAX_REG);
1566 }
1567
1568 void _r600_pipe_state_add_reg(struct r600_context *ctx,
1569 struct r600_pipe_state *state,
1570 uint32_t offset, uint32_t value,
1571 uint32_t range_id, uint32_t block_id)
1572 {
1573 _r600_pipe_state_add_reg_bo(ctx, state, offset, value,
1574 range_id, block_id, NULL, 0);
1575 }
1576
1577 uint32_t r600_translate_stencil_op(int s_op)
1578 {
1579 switch (s_op) {
1580 case PIPE_STENCIL_OP_KEEP:
1581 return V_028800_STENCIL_KEEP;
1582 case PIPE_STENCIL_OP_ZERO:
1583 return V_028800_STENCIL_ZERO;
1584 case PIPE_STENCIL_OP_REPLACE:
1585 return V_028800_STENCIL_REPLACE;
1586 case PIPE_STENCIL_OP_INCR:
1587 return V_028800_STENCIL_INCR;
1588 case PIPE_STENCIL_OP_DECR:
1589 return V_028800_STENCIL_DECR;
1590 case PIPE_STENCIL_OP_INCR_WRAP:
1591 return V_028800_STENCIL_INCR_WRAP;
1592 case PIPE_STENCIL_OP_DECR_WRAP:
1593 return V_028800_STENCIL_DECR_WRAP;
1594 case PIPE_STENCIL_OP_INVERT:
1595 return V_028800_STENCIL_INVERT;
1596 default:
1597 R600_ERR("Unknown stencil op %d", s_op);
1598 assert(0);
1599 break;
1600 }
1601 return 0;
1602 }
1603
1604 uint32_t r600_translate_fill(uint32_t func)
1605 {
1606 switch(func) {
1607 case PIPE_POLYGON_MODE_FILL:
1608 return 2;
1609 case PIPE_POLYGON_MODE_LINE:
1610 return 1;
1611 case PIPE_POLYGON_MODE_POINT:
1612 return 0;
1613 default:
1614 assert(0);
1615 return 0;
1616 }
1617 }
1618
1619 unsigned r600_tex_wrap(unsigned wrap)
1620 {
1621 switch (wrap) {
1622 default:
1623 case PIPE_TEX_WRAP_REPEAT:
1624 return V_03C000_SQ_TEX_WRAP;
1625 case PIPE_TEX_WRAP_CLAMP:
1626 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1627 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1628 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1629 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1630 return V_03C000_SQ_TEX_CLAMP_BORDER;
1631 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1632 return V_03C000_SQ_TEX_MIRROR;
1633 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1634 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1635 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1636 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1637 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1638 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1639 }
1640 }
1641
1642 unsigned r600_tex_filter(unsigned filter)
1643 {
1644 switch (filter) {
1645 default:
1646 case PIPE_TEX_FILTER_NEAREST:
1647 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1648 case PIPE_TEX_FILTER_LINEAR:
1649 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1650 }
1651 }
1652
1653 unsigned r600_tex_mipfilter(unsigned filter)
1654 {
1655 switch (filter) {
1656 case PIPE_TEX_MIPFILTER_NEAREST:
1657 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1658 case PIPE_TEX_MIPFILTER_LINEAR:
1659 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1660 default:
1661 case PIPE_TEX_MIPFILTER_NONE:
1662 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1663 }
1664 }
1665
1666 unsigned r600_tex_compare(unsigned compare)
1667 {
1668 switch (compare) {
1669 default:
1670 case PIPE_FUNC_NEVER:
1671 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1672 case PIPE_FUNC_LESS:
1673 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1674 case PIPE_FUNC_EQUAL:
1675 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1676 case PIPE_FUNC_LEQUAL:
1677 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1678 case PIPE_FUNC_GREATER:
1679 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1680 case PIPE_FUNC_NOTEQUAL:
1681 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1682 case PIPE_FUNC_GEQUAL:
1683 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1684 case PIPE_FUNC_ALWAYS:
1685 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1686 }
1687 }
1688
1689 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
1690 {
1691 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
1692 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
1693 (linear_filter &&
1694 (wrap == PIPE_TEX_WRAP_CLAMP ||
1695 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
1696 }
1697
1698 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
1699 {
1700 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
1701 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
1702
1703 return (state->border_color.ui[0] || state->border_color.ui[1] ||
1704 state->border_color.ui[2] || state->border_color.ui[3]) &&
1705 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
1706 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
1707 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
1708 }
1709
1710 /* keep this at the end of this file, please */
1711 void r600_init_common_state_functions(struct r600_context *rctx)
1712 {
1713 rctx->context.create_fs_state = r600_create_ps_state;
1714 rctx->context.create_vs_state = r600_create_vs_state;
1715 rctx->context.create_vertex_elements_state = r600_create_vertex_fetch_shader;
1716 rctx->context.bind_blend_state = r600_bind_blend_state;
1717 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1718 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler_states;
1719 rctx->context.bind_fs_state = r600_bind_ps_state;
1720 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1721 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1722 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler_states;
1723 rctx->context.bind_vs_state = r600_bind_vs_state;
1724 rctx->context.delete_blend_state = r600_delete_blend_state;
1725 rctx->context.delete_depth_stencil_alpha_state = r600_delete_dsa_state;
1726 rctx->context.delete_fs_state = r600_delete_ps_state;
1727 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1728 rctx->context.delete_sampler_state = r600_delete_sampler_state;
1729 rctx->context.delete_vertex_elements_state = r600_delete_vertex_elements;
1730 rctx->context.delete_vs_state = r600_delete_vs_state;
1731 rctx->context.set_blend_color = r600_set_blend_color;
1732 rctx->context.set_clip_state = r600_set_clip_state;
1733 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1734 rctx->context.set_sample_mask = r600_set_sample_mask;
1735 rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1736 rctx->context.set_viewport_state = r600_set_viewport_state;
1737 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1738 rctx->context.set_index_buffer = r600_set_index_buffer;
1739 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views;
1740 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views;
1741 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1742 rctx->context.texture_barrier = r600_texture_barrier;
1743 rctx->context.create_stream_output_target = r600_create_so_target;
1744 rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1745 rctx->context.set_stream_output_targets = r600_set_so_targets;
1746 rctx->context.draw_vbo = r600_draw_vbo;
1747 }
1748
1749 #if R600_TRACE_CS
1750 void r600_trace_emit(struct r600_context *rctx)
1751 {
1752 struct r600_screen *rscreen = rctx->screen;
1753 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
1754 uint64_t va;
1755 uint32_t reloc;
1756
1757 va = r600_resource_va(&rscreen->screen, (void*)rscreen->trace_bo);
1758 reloc = r600_context_bo_reloc(rctx, &rctx->rings.gfx, rscreen->trace_bo, RADEON_USAGE_READWRITE);
1759 r600_write_value(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
1760 r600_write_value(cs, va & 0xFFFFFFFFUL);
1761 r600_write_value(cs, (va >> 32UL) & 0xFFUL);
1762 r600_write_value(cs, cs->cdw);
1763 r600_write_value(cs, rscreen->cs_count);
1764 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1765 r600_write_value(cs, reloc);
1766 }
1767 #endif