2 * Copyright 2010 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
27 #include "r600_formats.h"
28 #include "r600_shader.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_index_modify.h"
33 #include "util/u_memory.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_math.h"
36 #include "tgsi/tgsi_parse.h"
37 #include "tgsi/tgsi_scan.h"
38 #include "tgsi/tgsi_ureg.h"
40 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
)
43 cb
->buf
= CALLOC(1, 4 * num_dw
);
44 cb
->max_num_dw
= num_dw
;
47 void r600_release_command_buffer(struct r600_command_buffer
*cb
)
52 void r600_add_atom(struct r600_context
*rctx
,
53 struct r600_atom
*atom
,
56 assert(id
< R600_NUM_ATOMS
);
57 assert(rctx
->atoms
[id
] == NULL
);
58 rctx
->atoms
[id
] = atom
;
62 void r600_init_atom(struct r600_context
*rctx
,
63 struct r600_atom
*atom
,
65 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
68 atom
->emit
= (void*)emit
;
69 atom
->num_dw
= num_dw
;
70 r600_add_atom(rctx
, atom
, id
);
73 void r600_emit_cso_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
75 r600_emit_command_buffer(rctx
->b
.gfx
.cs
, ((struct r600_cso_state
*)atom
)->cb
);
78 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
80 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
81 struct r600_alphatest_state
*a
= (struct r600_alphatest_state
*)atom
;
82 unsigned alpha_ref
= a
->sx_alpha_ref
;
84 if (rctx
->b
.chip_class
>= EVERGREEN
&& a
->cb0_export_16bpc
) {
88 radeon_set_context_reg(cs
, R_028410_SX_ALPHA_TEST_CONTROL
,
89 a
->sx_alpha_test_control
|
90 S_028410_ALPHA_TEST_BYPASS(a
->bypass
));
91 radeon_set_context_reg(cs
, R_028438_SX_ALPHA_REF
, alpha_ref
);
94 static void r600_texture_barrier(struct pipe_context
*ctx
)
96 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
98 rctx
->b
.flags
|= R600_CONTEXT_INV_TEX_CACHE
|
99 R600_CONTEXT_FLUSH_AND_INV_CB
|
100 R600_CONTEXT_FLUSH_AND_INV
|
101 R600_CONTEXT_WAIT_3D_IDLE
;
104 static unsigned r600_conv_pipe_prim(unsigned prim
)
106 static const unsigned prim_conv
[] = {
107 [PIPE_PRIM_POINTS
] = V_008958_DI_PT_POINTLIST
,
108 [PIPE_PRIM_LINES
] = V_008958_DI_PT_LINELIST
,
109 [PIPE_PRIM_LINE_LOOP
] = V_008958_DI_PT_LINELOOP
,
110 [PIPE_PRIM_LINE_STRIP
] = V_008958_DI_PT_LINESTRIP
,
111 [PIPE_PRIM_TRIANGLES
] = V_008958_DI_PT_TRILIST
,
112 [PIPE_PRIM_TRIANGLE_STRIP
] = V_008958_DI_PT_TRISTRIP
,
113 [PIPE_PRIM_TRIANGLE_FAN
] = V_008958_DI_PT_TRIFAN
,
114 [PIPE_PRIM_QUADS
] = V_008958_DI_PT_QUADLIST
,
115 [PIPE_PRIM_QUAD_STRIP
] = V_008958_DI_PT_QUADSTRIP
,
116 [PIPE_PRIM_POLYGON
] = V_008958_DI_PT_POLYGON
,
117 [PIPE_PRIM_LINES_ADJACENCY
] = V_008958_DI_PT_LINELIST_ADJ
,
118 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_008958_DI_PT_LINESTRIP_ADJ
,
119 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_008958_DI_PT_TRILIST_ADJ
,
120 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_008958_DI_PT_TRISTRIP_ADJ
,
121 [PIPE_PRIM_PATCHES
] = V_008958_DI_PT_PATCH
,
122 [R600_PRIM_RECTANGLE_LIST
] = V_008958_DI_PT_RECTLIST
124 assert(prim
< ARRAY_SIZE(prim_conv
));
125 return prim_conv
[prim
];
128 unsigned r600_conv_prim_to_gs_out(unsigned mode
)
130 static const int prim_conv
[] = {
131 [PIPE_PRIM_POINTS
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
132 [PIPE_PRIM_LINES
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
133 [PIPE_PRIM_LINE_LOOP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
134 [PIPE_PRIM_LINE_STRIP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
135 [PIPE_PRIM_TRIANGLES
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
136 [PIPE_PRIM_TRIANGLE_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
137 [PIPE_PRIM_TRIANGLE_FAN
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
138 [PIPE_PRIM_QUADS
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
139 [PIPE_PRIM_QUAD_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
140 [PIPE_PRIM_POLYGON
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
141 [PIPE_PRIM_LINES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
142 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
143 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
144 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
145 [PIPE_PRIM_PATCHES
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
146 [R600_PRIM_RECTANGLE_LIST
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
148 assert(mode
< ARRAY_SIZE(prim_conv
));
150 return prim_conv
[mode
];
153 /* common state between evergreen and r600 */
155 static void r600_bind_blend_state_internal(struct r600_context
*rctx
,
156 struct r600_blend_state
*blend
, bool blend_disable
)
158 unsigned color_control
;
159 bool update_cb
= false;
161 rctx
->alpha_to_one
= blend
->alpha_to_one
;
162 rctx
->dual_src_blend
= blend
->dual_src_blend
;
164 if (!blend_disable
) {
165 r600_set_cso_state_with_cb(rctx
, &rctx
->blend_state
, blend
, &blend
->buffer
);
166 color_control
= blend
->cb_color_control
;
168 /* Blending is disabled. */
169 r600_set_cso_state_with_cb(rctx
, &rctx
->blend_state
, blend
, &blend
->buffer_no_blend
);
170 color_control
= blend
->cb_color_control_no_blend
;
173 /* Update derived states. */
174 if (rctx
->cb_misc_state
.blend_colormask
!= blend
->cb_target_mask
) {
175 rctx
->cb_misc_state
.blend_colormask
= blend
->cb_target_mask
;
178 if (rctx
->b
.chip_class
<= R700
&&
179 rctx
->cb_misc_state
.cb_color_control
!= color_control
) {
180 rctx
->cb_misc_state
.cb_color_control
= color_control
;
183 if (rctx
->cb_misc_state
.dual_src_blend
!= blend
->dual_src_blend
) {
184 rctx
->cb_misc_state
.dual_src_blend
= blend
->dual_src_blend
;
188 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
192 static void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
)
194 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
195 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
198 r600_set_cso_state_with_cb(rctx
, &rctx
->blend_state
, NULL
, NULL
);
202 r600_bind_blend_state_internal(rctx
, blend
, rctx
->force_blend_disable
);
205 static void r600_set_blend_color(struct pipe_context
*ctx
,
206 const struct pipe_blend_color
*state
)
208 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
210 rctx
->blend_color
.state
= *state
;
211 r600_mark_atom_dirty(rctx
, &rctx
->blend_color
.atom
);
214 void r600_emit_blend_color(struct r600_context
*rctx
, struct r600_atom
*atom
)
216 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
217 struct pipe_blend_color
*state
= &rctx
->blend_color
.state
;
219 radeon_set_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
220 radeon_emit(cs
, fui(state
->color
[0])); /* R_028414_CB_BLEND_RED */
221 radeon_emit(cs
, fui(state
->color
[1])); /* R_028418_CB_BLEND_GREEN */
222 radeon_emit(cs
, fui(state
->color
[2])); /* R_02841C_CB_BLEND_BLUE */
223 radeon_emit(cs
, fui(state
->color
[3])); /* R_028420_CB_BLEND_ALPHA */
226 void r600_emit_vgt_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
228 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
229 struct r600_vgt_state
*a
= (struct r600_vgt_state
*)atom
;
231 radeon_set_context_reg(cs
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, a
->vgt_multi_prim_ib_reset_en
);
232 radeon_set_context_reg_seq(cs
, R_028408_VGT_INDX_OFFSET
, 2);
233 radeon_emit(cs
, a
->vgt_indx_offset
); /* R_028408_VGT_INDX_OFFSET */
234 radeon_emit(cs
, a
->vgt_multi_prim_ib_reset_indx
); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
235 if (a
->last_draw_was_indirect
) {
236 a
->last_draw_was_indirect
= false;
237 radeon_set_ctl_const(cs
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
241 static void r600_set_clip_state(struct pipe_context
*ctx
,
242 const struct pipe_clip_state
*state
)
244 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
246 rctx
->clip_state
.state
= *state
;
247 r600_mark_atom_dirty(rctx
, &rctx
->clip_state
.atom
);
248 rctx
->driver_consts
[PIPE_SHADER_VERTEX
].vs_ucp_dirty
= true;
251 static void r600_set_stencil_ref(struct pipe_context
*ctx
,
252 const struct r600_stencil_ref
*state
)
254 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
256 rctx
->stencil_ref
.state
= *state
;
257 r600_mark_atom_dirty(rctx
, &rctx
->stencil_ref
.atom
);
260 void r600_emit_stencil_ref(struct r600_context
*rctx
, struct r600_atom
*atom
)
262 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
263 struct r600_stencil_ref_state
*a
= (struct r600_stencil_ref_state
*)atom
;
265 radeon_set_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
266 radeon_emit(cs
, /* R_028430_DB_STENCILREFMASK */
267 S_028430_STENCILREF(a
->state
.ref_value
[0]) |
268 S_028430_STENCILMASK(a
->state
.valuemask
[0]) |
269 S_028430_STENCILWRITEMASK(a
->state
.writemask
[0]));
270 radeon_emit(cs
, /* R_028434_DB_STENCILREFMASK_BF */
271 S_028434_STENCILREF_BF(a
->state
.ref_value
[1]) |
272 S_028434_STENCILMASK_BF(a
->state
.valuemask
[1]) |
273 S_028434_STENCILWRITEMASK_BF(a
->state
.writemask
[1]));
276 static void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
277 const struct pipe_stencil_ref
*state
)
279 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
280 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)rctx
->dsa_state
.cso
;
281 struct r600_stencil_ref ref
;
283 rctx
->stencil_ref
.pipe_state
= *state
;
288 ref
.ref_value
[0] = state
->ref_value
[0];
289 ref
.ref_value
[1] = state
->ref_value
[1];
290 ref
.valuemask
[0] = dsa
->valuemask
[0];
291 ref
.valuemask
[1] = dsa
->valuemask
[1];
292 ref
.writemask
[0] = dsa
->writemask
[0];
293 ref
.writemask
[1] = dsa
->writemask
[1];
295 r600_set_stencil_ref(ctx
, &ref
);
298 static void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
300 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
301 struct r600_dsa_state
*dsa
= state
;
302 struct r600_stencil_ref ref
;
305 r600_set_cso_state_with_cb(rctx
, &rctx
->dsa_state
, NULL
, NULL
);
309 r600_set_cso_state_with_cb(rctx
, &rctx
->dsa_state
, dsa
, &dsa
->buffer
);
311 ref
.ref_value
[0] = rctx
->stencil_ref
.pipe_state
.ref_value
[0];
312 ref
.ref_value
[1] = rctx
->stencil_ref
.pipe_state
.ref_value
[1];
313 ref
.valuemask
[0] = dsa
->valuemask
[0];
314 ref
.valuemask
[1] = dsa
->valuemask
[1];
315 ref
.writemask
[0] = dsa
->writemask
[0];
316 ref
.writemask
[1] = dsa
->writemask
[1];
317 if (rctx
->zwritemask
!= dsa
->zwritemask
) {
318 rctx
->zwritemask
= dsa
->zwritemask
;
319 if (rctx
->b
.chip_class
>= EVERGREEN
) {
320 /* work around some issue when not writing to zbuffer
321 * we are having lockup on evergreen so do not enable
322 * hyperz when not writing zbuffer
324 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
328 r600_set_stencil_ref(ctx
, &ref
);
330 /* Update alphatest state. */
331 if (rctx
->alphatest_state
.sx_alpha_test_control
!= dsa
->sx_alpha_test_control
||
332 rctx
->alphatest_state
.sx_alpha_ref
!= dsa
->alpha_ref
) {
333 rctx
->alphatest_state
.sx_alpha_test_control
= dsa
->sx_alpha_test_control
;
334 rctx
->alphatest_state
.sx_alpha_ref
= dsa
->alpha_ref
;
335 r600_mark_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
339 static void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
)
341 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
342 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
347 rctx
->rasterizer
= rs
;
349 r600_set_cso_state_with_cb(rctx
, &rctx
->rasterizer_state
, rs
, &rs
->buffer
);
351 if (rs
->offset_enable
&&
352 (rs
->offset_units
!= rctx
->poly_offset_state
.offset_units
||
353 rs
->offset_scale
!= rctx
->poly_offset_state
.offset_scale
||
354 rs
->offset_units_unscaled
!= rctx
->poly_offset_state
.offset_units_unscaled
)) {
355 rctx
->poly_offset_state
.offset_units
= rs
->offset_units
;
356 rctx
->poly_offset_state
.offset_scale
= rs
->offset_scale
;
357 rctx
->poly_offset_state
.offset_units_unscaled
= rs
->offset_units_unscaled
;
358 r600_mark_atom_dirty(rctx
, &rctx
->poly_offset_state
.atom
);
361 /* Update clip_misc_state. */
362 if (rctx
->clip_misc_state
.pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
||
363 rctx
->clip_misc_state
.clip_plane_enable
!= rs
->clip_plane_enable
) {
364 rctx
->clip_misc_state
.pa_cl_clip_cntl
= rs
->pa_cl_clip_cntl
;
365 rctx
->clip_misc_state
.clip_plane_enable
= rs
->clip_plane_enable
;
366 r600_mark_atom_dirty(rctx
, &rctx
->clip_misc_state
.atom
);
369 r600_viewport_set_rast_deps(&rctx
->b
, rs
->scissor_enable
, rs
->clip_halfz
);
371 /* Re-emit PA_SC_LINE_STIPPLE. */
372 rctx
->last_primitive_type
= -1;
375 static void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
)
377 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
379 r600_release_command_buffer(&rs
->buffer
);
383 static void r600_sampler_view_destroy(struct pipe_context
*ctx
,
384 struct pipe_sampler_view
*state
)
386 struct r600_pipe_sampler_view
*view
= (struct r600_pipe_sampler_view
*)state
;
388 if (view
->tex_resource
->gpu_address
&&
389 view
->tex_resource
->b
.b
.target
== PIPE_BUFFER
)
390 LIST_DELINIT(&view
->list
);
392 pipe_resource_reference(&state
->texture
, NULL
);
396 void r600_sampler_states_dirty(struct r600_context
*rctx
,
397 struct r600_sampler_states
*state
)
399 if (state
->dirty_mask
) {
400 if (state
->dirty_mask
& state
->has_bordercolor_mask
) {
401 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
404 util_bitcount(state
->dirty_mask
& state
->has_bordercolor_mask
) * 11 +
405 util_bitcount(state
->dirty_mask
& ~state
->has_bordercolor_mask
) * 5;
406 r600_mark_atom_dirty(rctx
, &state
->atom
);
410 static void r600_bind_sampler_states(struct pipe_context
*pipe
,
411 enum pipe_shader_type shader
,
413 unsigned count
, void **states
)
415 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
416 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
417 struct r600_pipe_sampler_state
**rstates
= (struct r600_pipe_sampler_state
**)states
;
418 int seamless_cube_map
= -1;
420 /* This sets 1-bit for states with index >= count. */
421 uint32_t disable_mask
= ~((1ull << count
) - 1);
422 /* These are the new states set by this function. */
423 uint32_t new_mask
= 0;
425 assert(start
== 0); /* XXX fix below */
432 for (i
= 0; i
< count
; i
++) {
433 struct r600_pipe_sampler_state
*rstate
= rstates
[i
];
435 if (rstate
== dst
->states
.states
[i
]) {
440 if (rstate
->border_color_use
) {
441 dst
->states
.has_bordercolor_mask
|= 1 << i
;
443 dst
->states
.has_bordercolor_mask
&= ~(1 << i
);
445 seamless_cube_map
= rstate
->seamless_cube_map
;
449 disable_mask
|= 1 << i
;
453 memcpy(dst
->states
.states
, rstates
, sizeof(void*) * count
);
454 memset(dst
->states
.states
+ count
, 0, sizeof(void*) * (NUM_TEX_UNITS
- count
));
456 dst
->states
.enabled_mask
&= ~disable_mask
;
457 dst
->states
.dirty_mask
&= dst
->states
.enabled_mask
;
458 dst
->states
.enabled_mask
|= new_mask
;
459 dst
->states
.dirty_mask
|= new_mask
;
460 dst
->states
.has_bordercolor_mask
&= dst
->states
.enabled_mask
;
462 r600_sampler_states_dirty(rctx
, &dst
->states
);
464 /* Seamless cubemap state. */
465 if (rctx
->b
.chip_class
<= R700
&&
466 seamless_cube_map
!= -1 &&
467 seamless_cube_map
!= rctx
->seamless_cube_map
.enabled
) {
468 /* change in TA_CNTL_AUX need a pipeline flush */
469 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
470 rctx
->seamless_cube_map
.enabled
= seamless_cube_map
;
471 r600_mark_atom_dirty(rctx
, &rctx
->seamless_cube_map
.atom
);
475 static void r600_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
480 static void r600_delete_blend_state(struct pipe_context
*ctx
, void *state
)
482 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
483 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
485 if (rctx
->blend_state
.cso
== state
) {
486 ctx
->bind_blend_state(ctx
, NULL
);
489 r600_release_command_buffer(&blend
->buffer
);
490 r600_release_command_buffer(&blend
->buffer_no_blend
);
494 static void r600_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
496 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
497 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)state
;
499 if (rctx
->dsa_state
.cso
== state
) {
500 ctx
->bind_depth_stencil_alpha_state(ctx
, NULL
);
503 r600_release_command_buffer(&dsa
->buffer
);
507 static void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
509 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
511 r600_set_cso_state(rctx
, &rctx
->vertex_fetch_shader
, state
);
514 static void r600_delete_vertex_elements(struct pipe_context
*ctx
, void *state
)
516 struct r600_fetch_shader
*shader
= (struct r600_fetch_shader
*)state
;
517 r600_resource_reference(&shader
->buffer
, NULL
);
521 static void r600_set_index_buffer(struct pipe_context
*ctx
,
522 const struct pipe_index_buffer
*ib
)
524 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
527 pipe_resource_reference(&rctx
->index_buffer
.buffer
, ib
->buffer
);
528 memcpy(&rctx
->index_buffer
, ib
, sizeof(*ib
));
529 r600_context_add_resource_size(ctx
, ib
->buffer
);
531 pipe_resource_reference(&rctx
->index_buffer
.buffer
, NULL
);
535 void r600_vertex_buffers_dirty(struct r600_context
*rctx
)
537 if (rctx
->vertex_buffer_state
.dirty_mask
) {
538 rctx
->vertex_buffer_state
.atom
.num_dw
= (rctx
->b
.chip_class
>= EVERGREEN
? 12 : 11) *
539 util_bitcount(rctx
->vertex_buffer_state
.dirty_mask
);
540 r600_mark_atom_dirty(rctx
, &rctx
->vertex_buffer_state
.atom
);
544 static void r600_set_vertex_buffers(struct pipe_context
*ctx
,
545 unsigned start_slot
, unsigned count
,
546 const struct pipe_vertex_buffer
*input
)
548 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
549 struct r600_vertexbuf_state
*state
= &rctx
->vertex_buffer_state
;
550 struct pipe_vertex_buffer
*vb
= state
->vb
+ start_slot
;
552 uint32_t disable_mask
= 0;
553 /* These are the new buffers set by this function. */
554 uint32_t new_buffer_mask
= 0;
556 /* Set vertex buffers. */
558 for (i
= 0; i
< count
; i
++) {
559 if (memcmp(&input
[i
], &vb
[i
], sizeof(struct pipe_vertex_buffer
))) {
560 if (input
[i
].buffer
) {
561 vb
[i
].stride
= input
[i
].stride
;
562 vb
[i
].buffer_offset
= input
[i
].buffer_offset
;
563 pipe_resource_reference(&vb
[i
].buffer
, input
[i
].buffer
);
564 new_buffer_mask
|= 1 << i
;
565 r600_context_add_resource_size(ctx
, input
[i
].buffer
);
567 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
568 disable_mask
|= 1 << i
;
573 for (i
= 0; i
< count
; i
++) {
574 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
576 disable_mask
= ((1ull << count
) - 1);
579 disable_mask
<<= start_slot
;
580 new_buffer_mask
<<= start_slot
;
582 rctx
->vertex_buffer_state
.enabled_mask
&= ~disable_mask
;
583 rctx
->vertex_buffer_state
.dirty_mask
&= rctx
->vertex_buffer_state
.enabled_mask
;
584 rctx
->vertex_buffer_state
.enabled_mask
|= new_buffer_mask
;
585 rctx
->vertex_buffer_state
.dirty_mask
|= new_buffer_mask
;
587 r600_vertex_buffers_dirty(rctx
);
590 void r600_sampler_views_dirty(struct r600_context
*rctx
,
591 struct r600_samplerview_state
*state
)
593 if (state
->dirty_mask
) {
594 state
->atom
.num_dw
= (rctx
->b
.chip_class
>= EVERGREEN
? 14 : 13) *
595 util_bitcount(state
->dirty_mask
);
596 r600_mark_atom_dirty(rctx
, &state
->atom
);
600 static void r600_set_sampler_views(struct pipe_context
*pipe
,
601 enum pipe_shader_type shader
,
602 unsigned start
, unsigned count
,
603 struct pipe_sampler_view
**views
)
605 struct r600_context
*rctx
= (struct r600_context
*) pipe
;
606 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
607 struct r600_pipe_sampler_view
**rviews
= (struct r600_pipe_sampler_view
**)views
;
608 uint32_t dirty_sampler_states_mask
= 0;
610 /* This sets 1-bit for textures with index >= count. */
611 uint32_t disable_mask
= ~((1ull << count
) - 1);
612 /* These are the new textures set by this function. */
613 uint32_t new_mask
= 0;
615 /* Set textures with index >= count to NULL. */
616 uint32_t remaining_mask
;
618 assert(start
== 0); /* XXX fix below */
625 remaining_mask
= dst
->views
.enabled_mask
& disable_mask
;
627 while (remaining_mask
) {
628 i
= u_bit_scan(&remaining_mask
);
629 assert(dst
->views
.views
[i
]);
631 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
634 for (i
= 0; i
< count
; i
++) {
635 if (rviews
[i
] == dst
->views
.views
[i
]) {
640 struct r600_texture
*rtex
=
641 (struct r600_texture
*)rviews
[i
]->base
.texture
;
642 bool is_buffer
= rviews
[i
]->base
.texture
->target
== PIPE_BUFFER
;
644 if (!is_buffer
&& rtex
->db_compatible
) {
645 dst
->views
.compressed_depthtex_mask
|= 1 << i
;
647 dst
->views
.compressed_depthtex_mask
&= ~(1 << i
);
650 /* Track compressed colorbuffers. */
651 if (!is_buffer
&& rtex
->cmask
.size
) {
652 dst
->views
.compressed_colortex_mask
|= 1 << i
;
654 dst
->views
.compressed_colortex_mask
&= ~(1 << i
);
657 /* Changing from array to non-arrays textures and vice versa requires
658 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
659 if (rctx
->b
.chip_class
<= R700
&&
660 (dst
->states
.enabled_mask
& (1 << i
)) &&
661 (rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_1D_ARRAY
||
662 rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_2D_ARRAY
) != dst
->is_array_sampler
[i
]) {
663 dirty_sampler_states_mask
|= 1 << i
;
666 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], views
[i
]);
668 r600_context_add_resource_size(pipe
, views
[i
]->texture
);
670 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
671 disable_mask
|= 1 << i
;
675 dst
->views
.enabled_mask
&= ~disable_mask
;
676 dst
->views
.dirty_mask
&= dst
->views
.enabled_mask
;
677 dst
->views
.enabled_mask
|= new_mask
;
678 dst
->views
.dirty_mask
|= new_mask
;
679 dst
->views
.compressed_depthtex_mask
&= dst
->views
.enabled_mask
;
680 dst
->views
.compressed_colortex_mask
&= dst
->views
.enabled_mask
;
681 dst
->views
.dirty_buffer_constants
= TRUE
;
682 r600_sampler_views_dirty(rctx
, &dst
->views
);
684 if (dirty_sampler_states_mask
) {
685 dst
->states
.dirty_mask
|= dirty_sampler_states_mask
;
686 r600_sampler_states_dirty(rctx
, &dst
->states
);
690 static void r600_update_compressed_colortex_mask(struct r600_samplerview_state
*views
)
692 uint32_t mask
= views
->enabled_mask
;
695 unsigned i
= u_bit_scan(&mask
);
696 struct pipe_resource
*res
= views
->views
[i
]->base
.texture
;
698 if (res
&& res
->target
!= PIPE_BUFFER
) {
699 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
701 if (rtex
->cmask
.size
) {
702 views
->compressed_colortex_mask
|= 1 << i
;
704 views
->compressed_colortex_mask
&= ~(1 << i
);
710 /* Compute the key for the hw shader variant */
711 static inline union r600_shader_key
r600_shader_selector_key(struct pipe_context
* ctx
,
712 struct r600_pipe_shader_selector
* sel
)
714 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
715 union r600_shader_key key
;
716 memset(&key
, 0, sizeof(key
));
719 case PIPE_SHADER_VERTEX
: {
720 key
.vs
.as_ls
= (rctx
->tes_shader
!= NULL
);
722 key
.vs
.as_es
= (rctx
->gs_shader
!= NULL
);
724 if (rctx
->ps_shader
->current
->shader
.gs_prim_id_input
&& !rctx
->gs_shader
) {
725 key
.vs
.as_gs_a
= true;
726 key
.vs
.prim_id_out
= rctx
->ps_shader
->current
->shader
.input
[rctx
->ps_shader
->current
->shader
.ps_prim_id_input
].spi_sid
;
730 case PIPE_SHADER_GEOMETRY
:
732 case PIPE_SHADER_FRAGMENT
: {
733 key
.ps
.color_two_side
= rctx
->rasterizer
&& rctx
->rasterizer
->two_side
;
734 key
.ps
.alpha_to_one
= rctx
->alpha_to_one
&&
735 rctx
->rasterizer
&& rctx
->rasterizer
->multisample_enable
&&
736 !rctx
->framebuffer
.cb0_is_integer
;
737 key
.ps
.nr_cbufs
= rctx
->framebuffer
.state
.nr_cbufs
;
738 /* Dual-source blending only makes sense with nr_cbufs == 1. */
739 if (key
.ps
.nr_cbufs
== 1 && rctx
->dual_src_blend
)
743 case PIPE_SHADER_TESS_EVAL
:
744 key
.tes
.as_es
= (rctx
->gs_shader
!= NULL
);
746 case PIPE_SHADER_TESS_CTRL
:
747 key
.tcs
.prim_mode
= rctx
->tes_shader
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
756 /* Select the hw shader variant depending on the current state.
757 * (*dirty) is set to 1 if current variant was changed */
758 static int r600_shader_select(struct pipe_context
*ctx
,
759 struct r600_pipe_shader_selector
* sel
,
762 union r600_shader_key key
;
763 struct r600_pipe_shader
* shader
= NULL
;
766 memset(&key
, 0, sizeof(key
));
767 key
= r600_shader_selector_key(ctx
, sel
);
769 /* Check if we don't need to change anything.
770 * This path is also used for most shaders that don't need multiple
771 * variants, it will cost just a computation of the key and this
773 if (likely(sel
->current
&& memcmp(&sel
->current
->key
, &key
, sizeof(key
)) == 0)) {
777 /* lookup if we have other variants in the list */
778 if (sel
->num_shaders
> 1) {
779 struct r600_pipe_shader
*p
= sel
->current
, *c
= p
->next_variant
;
781 while (c
&& memcmp(&c
->key
, &key
, sizeof(key
)) != 0) {
787 p
->next_variant
= c
->next_variant
;
792 if (unlikely(!shader
)) {
793 shader
= CALLOC(1, sizeof(struct r600_pipe_shader
));
794 shader
->selector
= sel
;
796 r
= r600_pipe_shader_create(ctx
, shader
, key
);
798 R600_ERR("Failed to build shader variant (type=%u) %d\n",
805 /* We don't know the value of nr_ps_max_color_exports until we built
806 * at least one variant, so we may need to recompute the key after
807 * building first variant. */
808 if (sel
->type
== PIPE_SHADER_FRAGMENT
&&
809 sel
->num_shaders
== 0) {
810 sel
->nr_ps_max_color_exports
= shader
->shader
.nr_ps_max_color_exports
;
811 key
= r600_shader_selector_key(ctx
, sel
);
814 memcpy(&shader
->key
, &key
, sizeof(key
));
821 shader
->next_variant
= sel
->current
;
822 sel
->current
= shader
;
827 static void *r600_create_shader_state(struct pipe_context
*ctx
,
828 const struct pipe_shader_state
*state
,
829 unsigned pipe_shader_type
)
831 struct r600_pipe_shader_selector
*sel
= CALLOC_STRUCT(r600_pipe_shader_selector
);
834 sel
->type
= pipe_shader_type
;
835 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
836 sel
->so
= state
->stream_output
;
837 tgsi_scan_shader(state
->tokens
, &sel
->info
);
839 switch (pipe_shader_type
) {
840 case PIPE_SHADER_GEOMETRY
:
841 sel
->gs_output_prim
=
842 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
843 sel
->gs_max_out_vertices
=
844 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
845 sel
->gs_num_invocations
=
846 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
848 case PIPE_SHADER_VERTEX
:
849 case PIPE_SHADER_TESS_CTRL
:
850 sel
->lds_patch_outputs_written_mask
= 0;
851 sel
->lds_outputs_written_mask
= 0;
853 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
854 unsigned name
= sel
->info
.output_semantic_name
[i
];
855 unsigned index
= sel
->info
.output_semantic_index
[i
];
858 case TGSI_SEMANTIC_TESSINNER
:
859 case TGSI_SEMANTIC_TESSOUTER
:
860 case TGSI_SEMANTIC_PATCH
:
861 sel
->lds_patch_outputs_written_mask
|=
862 1llu << r600_get_lds_unique_index(name
, index
);
865 sel
->lds_outputs_written_mask
|=
866 1llu << r600_get_lds_unique_index(name
, index
);
877 static void *r600_create_ps_state(struct pipe_context
*ctx
,
878 const struct pipe_shader_state
*state
)
880 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_FRAGMENT
);
883 static void *r600_create_vs_state(struct pipe_context
*ctx
,
884 const struct pipe_shader_state
*state
)
886 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_VERTEX
);
889 static void *r600_create_gs_state(struct pipe_context
*ctx
,
890 const struct pipe_shader_state
*state
)
892 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_GEOMETRY
);
895 static void *r600_create_tcs_state(struct pipe_context
*ctx
,
896 const struct pipe_shader_state
*state
)
898 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_TESS_CTRL
);
901 static void *r600_create_tes_state(struct pipe_context
*ctx
,
902 const struct pipe_shader_state
*state
)
904 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_TESS_EVAL
);
907 static void r600_bind_ps_state(struct pipe_context
*ctx
, void *state
)
909 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
912 state
= rctx
->dummy_pixel_shader
;
914 rctx
->ps_shader
= (struct r600_pipe_shader_selector
*)state
;
917 static struct tgsi_shader_info
*r600_get_vs_info(struct r600_context
*rctx
)
920 return &rctx
->gs_shader
->info
;
921 else if (rctx
->tes_shader
)
922 return &rctx
->tes_shader
->info
;
923 else if (rctx
->vs_shader
)
924 return &rctx
->vs_shader
->info
;
929 static void r600_bind_vs_state(struct pipe_context
*ctx
, void *state
)
931 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
936 rctx
->vs_shader
= (struct r600_pipe_shader_selector
*)state
;
937 r600_update_vs_writes_viewport_index(&rctx
->b
, r600_get_vs_info(rctx
));
938 rctx
->b
.streamout
.stride_in_dw
= rctx
->vs_shader
->so
.stride
;
941 static void r600_bind_gs_state(struct pipe_context
*ctx
, void *state
)
943 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
945 rctx
->gs_shader
= (struct r600_pipe_shader_selector
*)state
;
946 r600_update_vs_writes_viewport_index(&rctx
->b
, r600_get_vs_info(rctx
));
950 rctx
->b
.streamout
.stride_in_dw
= rctx
->gs_shader
->so
.stride
;
953 static void r600_bind_tcs_state(struct pipe_context
*ctx
, void *state
)
955 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
957 rctx
->tcs_shader
= (struct r600_pipe_shader_selector
*)state
;
960 static void r600_bind_tes_state(struct pipe_context
*ctx
, void *state
)
962 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
964 rctx
->tes_shader
= (struct r600_pipe_shader_selector
*)state
;
965 r600_update_vs_writes_viewport_index(&rctx
->b
, r600_get_vs_info(rctx
));
969 rctx
->b
.streamout
.stride_in_dw
= rctx
->tes_shader
->so
.stride
;
972 static void r600_delete_shader_selector(struct pipe_context
*ctx
,
973 struct r600_pipe_shader_selector
*sel
)
975 struct r600_pipe_shader
*p
= sel
->current
, *c
;
978 r600_pipe_shader_destroy(ctx
, p
);
988 static void r600_delete_ps_state(struct pipe_context
*ctx
, void *state
)
990 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
991 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
993 if (rctx
->ps_shader
== sel
) {
994 rctx
->ps_shader
= NULL
;
997 r600_delete_shader_selector(ctx
, sel
);
1000 static void r600_delete_vs_state(struct pipe_context
*ctx
, void *state
)
1002 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1003 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1005 if (rctx
->vs_shader
== sel
) {
1006 rctx
->vs_shader
= NULL
;
1009 r600_delete_shader_selector(ctx
, sel
);
1013 static void r600_delete_gs_state(struct pipe_context
*ctx
, void *state
)
1015 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1016 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1018 if (rctx
->gs_shader
== sel
) {
1019 rctx
->gs_shader
= NULL
;
1022 r600_delete_shader_selector(ctx
, sel
);
1025 static void r600_delete_tcs_state(struct pipe_context
*ctx
, void *state
)
1027 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1028 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1030 if (rctx
->tcs_shader
== sel
) {
1031 rctx
->tcs_shader
= NULL
;
1034 r600_delete_shader_selector(ctx
, sel
);
1037 static void r600_delete_tes_state(struct pipe_context
*ctx
, void *state
)
1039 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1040 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1042 if (rctx
->tes_shader
== sel
) {
1043 rctx
->tes_shader
= NULL
;
1046 r600_delete_shader_selector(ctx
, sel
);
1049 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
)
1051 if (state
->dirty_mask
) {
1052 state
->atom
.num_dw
= rctx
->b
.chip_class
>= EVERGREEN
? util_bitcount(state
->dirty_mask
)*20
1053 : util_bitcount(state
->dirty_mask
)*19;
1054 r600_mark_atom_dirty(rctx
, &state
->atom
);
1058 static void r600_set_constant_buffer(struct pipe_context
*ctx
, uint shader
, uint index
,
1059 const struct pipe_constant_buffer
*input
)
1061 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1062 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
1063 struct pipe_constant_buffer
*cb
;
1066 /* Note that the state tracker can unbind constant buffers by
1067 * passing NULL here.
1069 if (unlikely(!input
|| (!input
->buffer
&& !input
->user_buffer
))) {
1070 state
->enabled_mask
&= ~(1 << index
);
1071 state
->dirty_mask
&= ~(1 << index
);
1072 pipe_resource_reference(&state
->cb
[index
].buffer
, NULL
);
1076 cb
= &state
->cb
[index
];
1077 cb
->buffer_size
= input
->buffer_size
;
1079 ptr
= input
->user_buffer
;
1082 /* Upload the user buffer. */
1083 if (R600_BIG_ENDIAN
) {
1085 unsigned i
, size
= input
->buffer_size
;
1087 if (!(tmpPtr
= malloc(size
))) {
1088 R600_ERR("Failed to allocate BE swap buffer.\n");
1092 for (i
= 0; i
< size
/ 4; ++i
) {
1093 tmpPtr
[i
] = util_cpu_to_le32(((uint32_t *)ptr
)[i
]);
1096 u_upload_data(rctx
->b
.uploader
, 0, size
, 256, tmpPtr
, &cb
->buffer_offset
, &cb
->buffer
);
1099 u_upload_data(rctx
->b
.uploader
, 0, input
->buffer_size
, 256, ptr
, &cb
->buffer_offset
, &cb
->buffer
);
1101 /* account it in gtt */
1102 rctx
->b
.gtt
+= input
->buffer_size
;
1104 /* Setup the hw buffer. */
1105 cb
->buffer_offset
= input
->buffer_offset
;
1106 pipe_resource_reference(&cb
->buffer
, input
->buffer
);
1107 r600_context_add_resource_size(ctx
, input
->buffer
);
1110 state
->enabled_mask
|= 1 << index
;
1111 state
->dirty_mask
|= 1 << index
;
1112 r600_constant_buffers_dirty(rctx
, state
);
1115 static void r600_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
1117 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
1119 if (rctx
->sample_mask
.sample_mask
== (uint16_t)sample_mask
)
1122 rctx
->sample_mask
.sample_mask
= sample_mask
;
1123 r600_mark_atom_dirty(rctx
, &rctx
->sample_mask
.atom
);
1126 static void r600_update_driver_const_buffers(struct r600_context
*rctx
)
1130 struct pipe_constant_buffer cb
;
1131 for (sh
= 0; sh
< PIPE_SHADER_TYPES
; sh
++) {
1132 struct r600_shader_driver_constants_info
*info
= &rctx
->driver_consts
[sh
];
1133 if (!info
->vs_ucp_dirty
&&
1134 !info
->texture_const_dirty
&&
1135 !info
->ps_sample_pos_dirty
)
1138 ptr
= info
->constants
;
1139 size
= info
->alloc_size
;
1140 if (info
->vs_ucp_dirty
) {
1141 assert(sh
== PIPE_SHADER_VERTEX
);
1143 ptr
= rctx
->clip_state
.state
.ucp
;
1144 size
= R600_UCP_SIZE
;
1146 memcpy(ptr
, rctx
->clip_state
.state
.ucp
, R600_UCP_SIZE
);
1148 info
->vs_ucp_dirty
= false;
1151 if (info
->ps_sample_pos_dirty
) {
1152 assert(sh
== PIPE_SHADER_FRAGMENT
);
1154 ptr
= rctx
->sample_positions
;
1155 size
= R600_UCP_SIZE
;
1157 memcpy(ptr
, rctx
->sample_positions
, R600_UCP_SIZE
);
1159 info
->ps_sample_pos_dirty
= false;
1162 if (info
->texture_const_dirty
) {
1165 if (sh
== PIPE_SHADER_VERTEX
)
1166 memcpy(ptr
, rctx
->clip_state
.state
.ucp
, R600_UCP_SIZE
);
1167 if (sh
== PIPE_SHADER_FRAGMENT
)
1168 memcpy(ptr
, rctx
->sample_positions
, R600_UCP_SIZE
);
1170 info
->texture_const_dirty
= false;
1173 cb
.user_buffer
= ptr
;
1174 cb
.buffer_offset
= 0;
1175 cb
.buffer_size
= size
;
1176 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, sh
, R600_BUFFER_INFO_CONST_BUFFER
, &cb
);
1177 pipe_resource_reference(&cb
.buffer
, NULL
);
1181 static void *r600_alloc_buf_consts(struct r600_context
*rctx
, int shader_type
,
1182 int array_size
, uint32_t *base_offset
)
1184 struct r600_shader_driver_constants_info
*info
= &rctx
->driver_consts
[shader_type
];
1185 if (array_size
+ R600_UCP_SIZE
> info
->alloc_size
) {
1186 info
->constants
= realloc(info
->constants
, array_size
+ R600_UCP_SIZE
);
1187 info
->alloc_size
= array_size
+ R600_UCP_SIZE
;
1189 memset(info
->constants
+ (R600_UCP_SIZE
/ 4), 0, array_size
);
1190 info
->texture_const_dirty
= true;
1191 *base_offset
= R600_UCP_SIZE
;
1192 return info
->constants
;
1195 * On r600/700 hw we don't have vertex fetch swizzle, though TBO
1196 * doesn't require full swizzles it does need masking and setting alpha
1197 * to one, so we setup a set of 5 constants with the masks + alpha value
1198 * then in the shader, we AND the 4 components with 0xffffffff or 0,
1199 * then OR the alpha with the value given here.
1200 * We use a 6th constant to store the txq buffer size in
1201 * we use 7th slot for number of cube layers in a cube map array.
1203 static void r600_setup_buffer_constants(struct r600_context
*rctx
, int shader_type
)
1205 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1207 uint32_t array_size
;
1209 uint32_t *constants
;
1210 uint32_t base_offset
;
1211 if (!samplers
->views
.dirty_buffer_constants
)
1214 samplers
->views
.dirty_buffer_constants
= FALSE
;
1216 bits
= util_last_bit(samplers
->views
.enabled_mask
);
1217 array_size
= bits
* 8 * sizeof(uint32_t) * 4;
1219 constants
= r600_alloc_buf_consts(rctx
, shader_type
, array_size
, &base_offset
);
1221 for (i
= 0; i
< bits
; i
++) {
1222 if (samplers
->views
.enabled_mask
& (1 << i
)) {
1223 int offset
= (base_offset
/ 4) + i
* 8;
1224 const struct util_format_description
*desc
;
1225 desc
= util_format_description(samplers
->views
.views
[i
]->base
.format
);
1227 for (j
= 0; j
< 4; j
++)
1228 if (j
< desc
->nr_channels
)
1229 constants
[offset
+j
] = 0xffffffff;
1231 constants
[offset
+j
] = 0x0;
1232 if (desc
->nr_channels
< 4) {
1233 if (desc
->channel
[0].pure_integer
)
1234 constants
[offset
+4] = 1;
1236 constants
[offset
+4] = fui(1.0);
1238 constants
[offset
+ 4] = 0;
1240 constants
[offset
+ 5] = samplers
->views
.views
[i
]->base
.texture
->width0
/ util_format_get_blocksize(samplers
->views
.views
[i
]->base
.format
);
1241 constants
[offset
+ 6] = samplers
->views
.views
[i
]->base
.texture
->array_size
/ 6;
1247 /* On evergreen we store two values
1248 * 1. buffer size for TXQ
1249 * 2. number of cube layers in a cube map array.
1251 static void eg_setup_buffer_constants(struct r600_context
*rctx
, int shader_type
)
1253 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1255 uint32_t array_size
;
1257 uint32_t *constants
;
1258 uint32_t base_offset
;
1259 if (!samplers
->views
.dirty_buffer_constants
)
1262 samplers
->views
.dirty_buffer_constants
= FALSE
;
1264 bits
= util_last_bit(samplers
->views
.enabled_mask
);
1265 array_size
= bits
* 2 * sizeof(uint32_t) * 4;
1267 constants
= r600_alloc_buf_consts(rctx
, shader_type
, array_size
,
1270 for (i
= 0; i
< bits
; i
++) {
1271 if (samplers
->views
.enabled_mask
& (1 << i
)) {
1272 uint32_t offset
= (base_offset
/ 4) + i
* 2;
1273 constants
[offset
] = samplers
->views
.views
[i
]->base
.texture
->width0
/ util_format_get_blocksize(samplers
->views
.views
[i
]->base
.format
);
1274 constants
[offset
+ 1] = samplers
->views
.views
[i
]->base
.texture
->array_size
/ 6;
1279 /* set sample xy locations as array of fragment shader constants */
1280 void r600_set_sample_locations_constant_buffer(struct r600_context
*rctx
)
1283 struct pipe_context
*ctx
= &rctx
->b
.b
;
1285 assert(rctx
->framebuffer
.nr_samples
< R600_UCP_SIZE
);
1286 assert(rctx
->framebuffer
.nr_samples
<= ARRAY_SIZE(rctx
->sample_positions
)/4);
1288 memset(rctx
->sample_positions
, 0, 4 * 4 * 16);
1289 for (i
= 0; i
< rctx
->framebuffer
.nr_samples
; i
++) {
1290 ctx
->get_sample_position(ctx
, rctx
->framebuffer
.nr_samples
, i
, &rctx
->sample_positions
[4*i
]);
1291 /* Also fill in center-zeroed positions used for interpolateAtSample */
1292 rctx
->sample_positions
[4*i
+ 2] = rctx
->sample_positions
[4*i
+ 0] - 0.5f
;
1293 rctx
->sample_positions
[4*i
+ 3] = rctx
->sample_positions
[4*i
+ 1] - 0.5f
;
1296 rctx
->driver_consts
[PIPE_SHADER_FRAGMENT
].ps_sample_pos_dirty
= true;
1299 static void update_shader_atom(struct pipe_context
*ctx
,
1300 struct r600_shader_state
*state
,
1301 struct r600_pipe_shader
*shader
)
1303 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1305 state
->shader
= shader
;
1307 state
->atom
.num_dw
= shader
->command_buffer
.num_dw
;
1308 r600_context_add_resource_size(ctx
, (struct pipe_resource
*)shader
->bo
);
1310 state
->atom
.num_dw
= 0;
1312 r600_mark_atom_dirty(rctx
, &state
->atom
);
1315 static void update_gs_block_state(struct r600_context
*rctx
, unsigned enable
)
1317 if (rctx
->shader_stages
.geom_enable
!= enable
) {
1318 rctx
->shader_stages
.geom_enable
= enable
;
1319 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1322 if (rctx
->gs_rings
.enable
!= enable
) {
1323 rctx
->gs_rings
.enable
= enable
;
1324 r600_mark_atom_dirty(rctx
, &rctx
->gs_rings
.atom
);
1326 if (enable
&& !rctx
->gs_rings
.esgs_ring
.buffer
) {
1327 unsigned size
= 0x1C000;
1328 rctx
->gs_rings
.esgs_ring
.buffer
=
1329 pipe_buffer_create(rctx
->b
.b
.screen
, PIPE_BIND_CUSTOM
,
1330 PIPE_USAGE_DEFAULT
, size
);
1331 rctx
->gs_rings
.esgs_ring
.buffer_size
= size
;
1335 rctx
->gs_rings
.gsvs_ring
.buffer
=
1336 pipe_buffer_create(rctx
->b
.b
.screen
, PIPE_BIND_CUSTOM
,
1337 PIPE_USAGE_DEFAULT
, size
);
1338 rctx
->gs_rings
.gsvs_ring
.buffer_size
= size
;
1342 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_GEOMETRY
,
1343 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.esgs_ring
);
1344 if (rctx
->tes_shader
) {
1345 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_TESS_EVAL
,
1346 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.gsvs_ring
);
1348 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_VERTEX
,
1349 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.gsvs_ring
);
1352 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_GEOMETRY
,
1353 R600_GS_RING_CONST_BUFFER
, NULL
);
1354 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_VERTEX
,
1355 R600_GS_RING_CONST_BUFFER
, NULL
);
1356 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_TESS_EVAL
,
1357 R600_GS_RING_CONST_BUFFER
, NULL
);
1362 static void r600_update_clip_state(struct r600_context
*rctx
,
1363 struct r600_pipe_shader
*current
)
1365 if (current
->pa_cl_vs_out_cntl
!= rctx
->clip_misc_state
.pa_cl_vs_out_cntl
||
1366 current
->shader
.clip_dist_write
!= rctx
->clip_misc_state
.clip_dist_write
||
1367 current
->shader
.vs_position_window_space
!= rctx
->clip_misc_state
.clip_disable
||
1368 current
->shader
.vs_out_viewport
!= rctx
->clip_misc_state
.vs_out_viewport
) {
1369 rctx
->clip_misc_state
.pa_cl_vs_out_cntl
= current
->pa_cl_vs_out_cntl
;
1370 rctx
->clip_misc_state
.clip_dist_write
= current
->shader
.clip_dist_write
;
1371 rctx
->clip_misc_state
.clip_disable
= current
->shader
.vs_position_window_space
;
1372 rctx
->clip_misc_state
.vs_out_viewport
= current
->shader
.vs_out_viewport
;
1373 r600_mark_atom_dirty(rctx
, &rctx
->clip_misc_state
.atom
);
1377 static void r600_generate_fixed_func_tcs(struct r600_context
*rctx
)
1379 struct ureg_src const0
, const1
;
1380 struct ureg_dst tessouter
, tessinner
;
1381 struct ureg_program
*ureg
= ureg_create(PIPE_SHADER_TESS_CTRL
);
1384 return; /* if we get here, we're screwed */
1386 assert(!rctx
->fixed_func_tcs_shader
);
1388 ureg_DECL_constant2D(ureg
, 0, 3, R600_LDS_INFO_CONST_BUFFER
);
1389 const0
= ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT
, 2),
1390 R600_LDS_INFO_CONST_BUFFER
);
1391 const1
= ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT
, 3),
1392 R600_LDS_INFO_CONST_BUFFER
);
1394 tessouter
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSOUTER
, 0);
1395 tessinner
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSINNER
, 0);
1397 ureg_MOV(ureg
, tessouter
, const0
);
1398 ureg_MOV(ureg
, tessinner
, const1
);
1401 rctx
->fixed_func_tcs_shader
=
1402 ureg_create_shader_and_destroy(ureg
, &rctx
->b
.b
);
1405 #define SELECT_SHADER_OR_FAIL(x) do { \
1406 r600_shader_select(ctx, rctx->x##_shader, &x##_dirty); \
1407 if (unlikely(!rctx->x##_shader->current)) \
1411 #define UPDATE_SHADER(hw, sw) do { \
1412 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) \
1413 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1416 #define UPDATE_SHADER_CLIP(hw, sw) do { \
1417 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1418 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1419 clip_so_current = rctx->sw##_shader->current; \
1423 #define UPDATE_SHADER_GS(hw, hw2, sw) do { \
1424 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1425 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1426 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw2)], rctx->sw##_shader->current->gs_copy_shader); \
1427 clip_so_current = rctx->sw##_shader->current->gs_copy_shader; \
1431 #define SET_NULL_SHADER(hw) do { \
1432 if (rctx->hw_shader_stages[(hw)].shader) \
1433 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], NULL); \
1436 static bool r600_update_derived_state(struct r600_context
*rctx
)
1438 struct pipe_context
* ctx
= (struct pipe_context
*)rctx
;
1439 bool ps_dirty
= false, vs_dirty
= false, gs_dirty
= false;
1440 bool tcs_dirty
= false, tes_dirty
= false, fixed_func_tcs_dirty
= false;
1442 bool need_buf_const
;
1443 struct r600_pipe_shader
*clip_so_current
= NULL
;
1445 if (!rctx
->blitter
->running
) {
1449 counter
= p_atomic_read(&rctx
->screen
->b
.compressed_colortex_counter
);
1450 if (counter
!= rctx
->b
.last_compressed_colortex_counter
) {
1451 rctx
->b
.last_compressed_colortex_counter
= counter
;
1453 for (i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1454 r600_update_compressed_colortex_mask(&rctx
->samplers
[i
].views
);
1458 /* Decompress textures if needed. */
1459 for (i
= 0; i
< PIPE_SHADER_TYPES
; i
++) {
1460 struct r600_samplerview_state
*views
= &rctx
->samplers
[i
].views
;
1461 if (views
->compressed_depthtex_mask
) {
1462 r600_decompress_depth_textures(rctx
, views
);
1464 if (views
->compressed_colortex_mask
) {
1465 r600_decompress_color_textures(rctx
, views
);
1470 SELECT_SHADER_OR_FAIL(ps
);
1472 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1474 update_gs_block_state(rctx
, rctx
->gs_shader
!= NULL
);
1476 if (rctx
->gs_shader
)
1477 SELECT_SHADER_OR_FAIL(gs
);
1480 if (rctx
->tcs_shader
) {
1481 SELECT_SHADER_OR_FAIL(tcs
);
1483 UPDATE_SHADER(EG_HW_STAGE_HS
, tcs
);
1484 } else if (rctx
->tes_shader
) {
1485 if (!rctx
->fixed_func_tcs_shader
) {
1486 r600_generate_fixed_func_tcs(rctx
);
1487 if (!rctx
->fixed_func_tcs_shader
)
1491 SELECT_SHADER_OR_FAIL(fixed_func_tcs
);
1493 UPDATE_SHADER(EG_HW_STAGE_HS
, fixed_func_tcs
);
1495 SET_NULL_SHADER(EG_HW_STAGE_HS
);
1497 if (rctx
->tes_shader
) {
1498 SELECT_SHADER_OR_FAIL(tes
);
1501 SELECT_SHADER_OR_FAIL(vs
);
1503 if (rctx
->gs_shader
) {
1504 if (!rctx
->shader_stages
.geom_enable
) {
1505 rctx
->shader_stages
.geom_enable
= true;
1506 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1509 /* gs_shader provides GS and VS (copy shader) */
1510 UPDATE_SHADER_GS(R600_HW_STAGE_GS
, R600_HW_STAGE_VS
, gs
);
1512 /* vs_shader is used as ES */
1514 if (rctx
->tes_shader
) {
1515 /* VS goes to LS, TES goes to ES */
1516 UPDATE_SHADER(R600_HW_STAGE_ES
, tes
);
1517 UPDATE_SHADER(EG_HW_STAGE_LS
, vs
);
1519 /* vs_shader is used as ES */
1520 UPDATE_SHADER(R600_HW_STAGE_ES
, vs
);
1521 SET_NULL_SHADER(EG_HW_STAGE_LS
);
1524 if (unlikely(rctx
->hw_shader_stages
[R600_HW_STAGE_GS
].shader
)) {
1525 SET_NULL_SHADER(R600_HW_STAGE_GS
);
1526 SET_NULL_SHADER(R600_HW_STAGE_ES
);
1527 rctx
->shader_stages
.geom_enable
= false;
1528 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1531 if (rctx
->tes_shader
) {
1532 /* if TES is loaded and no geometry, TES runs on hw VS, VS runs on hw LS */
1533 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS
, tes
);
1534 UPDATE_SHADER(EG_HW_STAGE_LS
, vs
);
1536 SET_NULL_SHADER(EG_HW_STAGE_LS
);
1537 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS
, vs
);
1541 /* Update clip misc state. */
1542 if (clip_so_current
) {
1543 r600_update_clip_state(rctx
, clip_so_current
);
1544 rctx
->b
.streamout
.enabled_stream_buffers_mask
= clip_so_current
->enabled_stream_buffers_mask
;
1547 if (unlikely(ps_dirty
|| rctx
->hw_shader_stages
[R600_HW_STAGE_PS
].shader
!= rctx
->ps_shader
->current
||
1548 rctx
->rasterizer
->sprite_coord_enable
!= rctx
->ps_shader
->current
->sprite_coord_enable
||
1549 rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
)) {
1551 if (rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
1552 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
1553 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1556 if (rctx
->b
.chip_class
<= R700
) {
1557 bool multiwrite
= rctx
->ps_shader
->current
->shader
.fs_write_all
;
1559 if (rctx
->cb_misc_state
.multiwrite
!= multiwrite
) {
1560 rctx
->cb_misc_state
.multiwrite
= multiwrite
;
1561 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1565 if (unlikely(!ps_dirty
&& rctx
->ps_shader
&& rctx
->rasterizer
&&
1566 ((rctx
->rasterizer
->sprite_coord_enable
!= rctx
->ps_shader
->current
->sprite_coord_enable
) ||
1567 (rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
)))) {
1569 if (rctx
->b
.chip_class
>= EVERGREEN
)
1570 evergreen_update_ps_state(ctx
, rctx
->ps_shader
->current
);
1572 r600_update_ps_state(ctx
, rctx
->ps_shader
->current
);
1575 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1577 UPDATE_SHADER(R600_HW_STAGE_PS
, ps
);
1579 if (rctx
->b
.chip_class
>= EVERGREEN
) {
1580 evergreen_update_db_shader_control(rctx
);
1582 r600_update_db_shader_control(rctx
);
1585 /* on R600 we stuff masks + txq info into one constant buffer */
1586 /* on evergreen we only need a txq info one */
1587 if (rctx
->ps_shader
) {
1588 need_buf_const
= rctx
->ps_shader
->current
->shader
.uses_tex_buffers
|| rctx
->ps_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1589 if (need_buf_const
) {
1590 if (rctx
->b
.chip_class
< EVERGREEN
)
1591 r600_setup_buffer_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1593 eg_setup_buffer_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1597 if (rctx
->vs_shader
) {
1598 need_buf_const
= rctx
->vs_shader
->current
->shader
.uses_tex_buffers
|| rctx
->vs_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1599 if (need_buf_const
) {
1600 if (rctx
->b
.chip_class
< EVERGREEN
)
1601 r600_setup_buffer_constants(rctx
, PIPE_SHADER_VERTEX
);
1603 eg_setup_buffer_constants(rctx
, PIPE_SHADER_VERTEX
);
1607 if (rctx
->gs_shader
) {
1608 need_buf_const
= rctx
->gs_shader
->current
->shader
.uses_tex_buffers
|| rctx
->gs_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1609 if (need_buf_const
) {
1610 if (rctx
->b
.chip_class
< EVERGREEN
)
1611 r600_setup_buffer_constants(rctx
, PIPE_SHADER_GEOMETRY
);
1613 eg_setup_buffer_constants(rctx
, PIPE_SHADER_GEOMETRY
);
1617 r600_update_driver_const_buffers(rctx
);
1619 if (rctx
->b
.chip_class
< EVERGREEN
&& rctx
->ps_shader
&& rctx
->vs_shader
) {
1620 if (!r600_adjust_gprs(rctx
)) {
1621 /* discard rendering */
1626 if (rctx
->b
.chip_class
== EVERGREEN
) {
1627 if (!evergreen_adjust_gprs(rctx
)) {
1628 /* discard rendering */
1633 blend_disable
= (rctx
->dual_src_blend
&&
1634 rctx
->ps_shader
->current
->nr_ps_color_outputs
< 2);
1636 if (blend_disable
!= rctx
->force_blend_disable
) {
1637 rctx
->force_blend_disable
= blend_disable
;
1638 r600_bind_blend_state_internal(rctx
,
1639 rctx
->blend_state
.cso
,
1646 void r600_emit_clip_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1648 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1649 struct r600_clip_misc_state
*state
= &rctx
->clip_misc_state
;
1651 radeon_set_context_reg(cs
, R_028810_PA_CL_CLIP_CNTL
,
1652 state
->pa_cl_clip_cntl
|
1653 (state
->clip_dist_write
? 0 : state
->clip_plane_enable
& 0x3F) |
1654 S_028810_CLIP_DISABLE(state
->clip_disable
));
1655 radeon_set_context_reg(cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
1656 state
->pa_cl_vs_out_cntl
|
1657 (state
->clip_plane_enable
& state
->clip_dist_write
));
1658 /* reuse needs to be set off if we write oViewport */
1659 if (rctx
->b
.chip_class
>= EVERGREEN
)
1660 radeon_set_context_reg(cs
, R_028AB4_VGT_REUSE_OFF
,
1661 S_028AB4_REUSE_OFF(state
->vs_out_viewport
));
1664 static void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*dinfo
)
1666 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1667 struct pipe_draw_info info
= *dinfo
;
1668 struct pipe_index_buffer ib
= {};
1669 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1670 bool render_cond_bit
= rctx
->b
.render_cond
&& !rctx
->b
.render_cond_force_off
;
1672 unsigned num_patches
, dirty_fb_counter
;
1674 if (!info
.indirect
&& !info
.count
&& (info
.indexed
|| !info
.count_from_stream_output
)) {
1678 if (!rctx
->vs_shader
|| !rctx
->ps_shader
) {
1683 /* make sure that the gfx ring is only one active */
1684 if (radeon_emitted(rctx
->b
.dma
.cs
, 0)) {
1685 rctx
->b
.dma
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
1688 /* Re-emit the framebuffer state if needed. */
1689 dirty_fb_counter
= p_atomic_read(&rctx
->b
.screen
->dirty_fb_counter
);
1690 if (dirty_fb_counter
!= rctx
->b
.last_dirty_fb_counter
) {
1691 rctx
->b
.last_dirty_fb_counter
= dirty_fb_counter
;
1692 r600_mark_atom_dirty(rctx
, &rctx
->framebuffer
.atom
);
1695 if (!r600_update_derived_state(rctx
)) {
1696 /* useless to render because current rendering command
1703 /* Initialize the index buffer struct. */
1704 pipe_resource_reference(&ib
.buffer
, rctx
->index_buffer
.buffer
);
1705 ib
.user_buffer
= rctx
->index_buffer
.user_buffer
;
1706 ib
.index_size
= rctx
->index_buffer
.index_size
;
1707 ib
.offset
= rctx
->index_buffer
.offset
;
1708 if (!info
.indirect
) {
1709 ib
.offset
+= info
.start
* ib
.index_size
;
1712 /* Translate 8-bit indices to 16-bit. */
1713 if (unlikely(ib
.index_size
== 1)) {
1714 struct pipe_resource
*out_buffer
= NULL
;
1715 unsigned out_offset
;
1717 unsigned start
, count
;
1719 if (likely(!info
.indirect
)) {
1724 /* Have to get start/count from indirect buffer, slow path ahead... */
1725 struct r600_resource
*indirect_resource
= (struct r600_resource
*)info
.indirect
;
1726 unsigned *data
= r600_buffer_map_sync_with_rings(&rctx
->b
, indirect_resource
,
1727 PIPE_TRANSFER_READ
);
1729 data
+= info
.indirect_offset
/ sizeof(unsigned);
1730 start
= data
[2] * ib
.index_size
;
1739 u_upload_alloc(rctx
->b
.uploader
, start
, count
* 2, 256,
1740 &out_offset
, &out_buffer
, &ptr
);
1742 util_shorten_ubyte_elts_to_userptr(
1743 &rctx
->b
.b
, &ib
, 0, ib
.offset
+ start
, count
, ptr
);
1745 pipe_resource_reference(&ib
.buffer
, NULL
);
1746 ib
.user_buffer
= NULL
;
1747 ib
.buffer
= out_buffer
;
1748 ib
.offset
= out_offset
;
1752 /* Upload the index buffer.
1753 * The upload is skipped for small index counts on little-endian machines
1754 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
1755 * Indirect draws never use immediate indices.
1756 * Note: Instanced rendering in combination with immediate indices hangs. */
1757 if (ib
.user_buffer
&& (R600_BIG_ENDIAN
|| info
.indirect
||
1758 info
.instance_count
> 1 ||
1759 info
.count
*ib
.index_size
> 20)) {
1760 u_upload_data(rctx
->b
.uploader
, 0, info
.count
* ib
.index_size
, 256,
1761 ib
.user_buffer
, &ib
.offset
, &ib
.buffer
);
1762 ib
.user_buffer
= NULL
;
1765 info
.index_bias
= info
.start
;
1768 /* Set the index offset and primitive restart. */
1769 if (rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
!= info
.primitive_restart
||
1770 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
!= info
.restart_index
||
1771 rctx
->vgt_state
.vgt_indx_offset
!= info
.index_bias
||
1772 (rctx
->vgt_state
.last_draw_was_indirect
&& !info
.indirect
)) {
1773 rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
= info
.primitive_restart
;
1774 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
= info
.restart_index
;
1775 rctx
->vgt_state
.vgt_indx_offset
= info
.index_bias
;
1776 r600_mark_atom_dirty(rctx
, &rctx
->vgt_state
.atom
);
1779 /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
1780 if (rctx
->b
.chip_class
== R600
) {
1781 rctx
->b
.flags
|= R600_CONTEXT_PS_PARTIAL_FLUSH
;
1782 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1785 if (rctx
->b
.chip_class
>= EVERGREEN
)
1786 evergreen_setup_tess_constants(rctx
, &info
, &num_patches
);
1789 r600_need_cs_space(rctx
, ib
.user_buffer
? 5 : 0, TRUE
);
1790 r600_flush_emit(rctx
);
1792 mask
= rctx
->dirty_atoms
;
1794 r600_emit_atom(rctx
, rctx
->atoms
[u_bit_scan64(&mask
)]);
1797 if (rctx
->b
.chip_class
== CAYMAN
) {
1798 /* Copied from radeonsi. */
1799 unsigned primgroup_size
= 128; /* recommended without a GS */
1800 bool ia_switch_on_eop
= false;
1801 bool partial_vs_wave
= false;
1803 if (rctx
->gs_shader
)
1804 primgroup_size
= 64; /* recommended with a GS */
1806 if ((rctx
->rasterizer
&& rctx
->rasterizer
->pa_sc_line_stipple
) ||
1807 (rctx
->b
.screen
->debug_flags
& DBG_SWITCH_ON_EOP
)) {
1808 ia_switch_on_eop
= true;
1811 if (r600_get_strmout_en(&rctx
->b
))
1812 partial_vs_wave
= true;
1814 radeon_set_context_reg(cs
, CM_R_028AA8_IA_MULTI_VGT_PARAM
,
1815 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop
) |
1816 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave
) |
1817 S_028AA8_PRIMGROUP_SIZE(primgroup_size
- 1));
1820 if (rctx
->b
.chip_class
>= EVERGREEN
) {
1821 uint32_t ls_hs_config
= evergreen_get_ls_hs_config(rctx
, &info
,
1824 evergreen_set_ls_hs_config(rctx
, cs
, ls_hs_config
);
1825 evergreen_set_lds_alloc(rctx
, cs
, rctx
->lds_alloc
);
1828 /* On R6xx, CULL_FRONT=1 culls all points, lines, and rectangles,
1829 * even though it should have no effect on those. */
1830 if (rctx
->b
.chip_class
== R600
&& rctx
->rasterizer
) {
1831 unsigned su_sc_mode_cntl
= rctx
->rasterizer
->pa_su_sc_mode_cntl
;
1832 unsigned prim
= info
.mode
;
1834 if (rctx
->gs_shader
) {
1835 prim
= rctx
->gs_shader
->gs_output_prim
;
1837 prim
= r600_conv_prim_to_gs_out(prim
); /* decrease the number of types to 3 */
1839 if (prim
== V_028A6C_OUTPRIM_TYPE_POINTLIST
||
1840 prim
== V_028A6C_OUTPRIM_TYPE_LINESTRIP
||
1841 info
.mode
== R600_PRIM_RECTANGLE_LIST
) {
1842 su_sc_mode_cntl
&= C_028814_CULL_FRONT
;
1844 radeon_set_context_reg(cs
, R_028814_PA_SU_SC_MODE_CNTL
, su_sc_mode_cntl
);
1847 /* Update start instance. */
1848 if (!info
.indirect
&& rctx
->last_start_instance
!= info
.start_instance
) {
1849 radeon_set_ctl_const(cs
, R_03CFF4_SQ_VTX_START_INST_LOC
, info
.start_instance
);
1850 rctx
->last_start_instance
= info
.start_instance
;
1853 /* Update the primitive type. */
1854 if (rctx
->last_primitive_type
!= info
.mode
) {
1855 unsigned ls_mask
= 0;
1857 if (info
.mode
== PIPE_PRIM_LINES
)
1859 else if (info
.mode
== PIPE_PRIM_LINE_STRIP
||
1860 info
.mode
== PIPE_PRIM_LINE_LOOP
)
1863 radeon_set_context_reg(cs
, R_028A0C_PA_SC_LINE_STIPPLE
,
1864 S_028A0C_AUTO_RESET_CNTL(ls_mask
) |
1865 (rctx
->rasterizer
? rctx
->rasterizer
->pa_sc_line_stipple
: 0));
1866 radeon_set_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
,
1867 r600_conv_pipe_prim(info
.mode
));
1869 rctx
->last_primitive_type
= info
.mode
;
1873 if (!info
.indirect
) {
1874 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, 0));
1875 radeon_emit(cs
, info
.instance_count
);
1878 if (unlikely(info
.indirect
)) {
1879 uint64_t va
= r600_resource(info
.indirect
)->gpu_address
;
1880 assert(rctx
->b
.chip_class
>= EVERGREEN
);
1882 // Invalidate so non-indirect draw calls reset this state
1883 rctx
->vgt_state
.last_draw_was_indirect
= true;
1884 rctx
->last_start_instance
= -1;
1886 radeon_emit(cs
, PKT3(EG_PKT3_SET_BASE
, 2, 0));
1887 radeon_emit(cs
, EG_DRAW_INDEX_INDIRECT_PATCH_TABLE_BASE
);
1888 radeon_emit(cs
, va
);
1889 radeon_emit(cs
, (va
>> 32UL) & 0xFF);
1891 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1892 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
1893 (struct r600_resource
*)info
.indirect
,
1895 RADEON_PRIO_DRAW_INDIRECT
));
1899 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
1900 radeon_emit(cs
, ib
.index_size
== 4 ?
1901 (VGT_INDEX_32
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_32_BIT
: 0)) :
1902 (VGT_INDEX_16
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_16_BIT
: 0)));
1904 if (ib
.user_buffer
) {
1905 unsigned size_bytes
= info
.count
*ib
.index_size
;
1906 unsigned size_dw
= align(size_bytes
, 4) / 4;
1907 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_IMMD
, 1 + size_dw
, render_cond_bit
));
1908 radeon_emit(cs
, info
.count
);
1909 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_IMMEDIATE
);
1910 radeon_emit_array(cs
, ib
.user_buffer
, size_dw
);
1912 uint64_t va
= r600_resource(ib
.buffer
)->gpu_address
+ ib
.offset
;
1914 if (likely(!info
.indirect
)) {
1915 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX
, 3, render_cond_bit
));
1916 radeon_emit(cs
, va
);
1917 radeon_emit(cs
, (va
>> 32UL) & 0xFF);
1918 radeon_emit(cs
, info
.count
);
1919 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_DMA
);
1920 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1921 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
1922 (struct r600_resource
*)ib
.buffer
,
1924 RADEON_PRIO_INDEX_BUFFER
));
1927 uint32_t max_size
= (ib
.buffer
->width0
- ib
.offset
) / ib
.index_size
;
1929 radeon_emit(cs
, PKT3(EG_PKT3_INDEX_BASE
, 1, 0));
1930 radeon_emit(cs
, va
);
1931 radeon_emit(cs
, (va
>> 32UL) & 0xFF);
1933 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1934 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
1935 (struct r600_resource
*)ib
.buffer
,
1937 RADEON_PRIO_INDEX_BUFFER
));
1939 radeon_emit(cs
, PKT3(EG_PKT3_INDEX_BUFFER_SIZE
, 0, 0));
1940 radeon_emit(cs
, max_size
);
1942 radeon_emit(cs
, PKT3(EG_PKT3_DRAW_INDEX_INDIRECT
, 1, render_cond_bit
));
1943 radeon_emit(cs
, info
.indirect_offset
);
1944 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_DMA
);
1948 if (unlikely(info
.count_from_stream_output
)) {
1949 struct r600_so_target
*t
= (struct r600_so_target
*)info
.count_from_stream_output
;
1950 uint64_t va
= t
->buf_filled_size
->gpu_address
+ t
->buf_filled_size_offset
;
1952 radeon_set_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
, t
->stride_in_dw
);
1954 radeon_emit(cs
, PKT3(PKT3_COPY_DW
, 4, 0));
1955 radeon_emit(cs
, COPY_DW_SRC_IS_MEM
| COPY_DW_DST_IS_REG
);
1956 radeon_emit(cs
, va
& 0xFFFFFFFFUL
); /* src address lo */
1957 radeon_emit(cs
, (va
>> 32UL) & 0xFFUL
); /* src address hi */
1958 radeon_emit(cs
, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2); /* dst register */
1959 radeon_emit(cs
, 0); /* unused */
1961 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1962 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
1963 t
->buf_filled_size
, RADEON_USAGE_READ
,
1964 RADEON_PRIO_SO_FILLED_SIZE
));
1967 if (likely(!info
.indirect
)) {
1968 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, render_cond_bit
));
1969 radeon_emit(cs
, info
.count
);
1972 radeon_emit(cs
, PKT3(EG_PKT3_DRAW_INDIRECT
, 1, render_cond_bit
));
1973 radeon_emit(cs
, info
.indirect_offset
);
1975 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
1976 (info
.count_from_stream_output
? S_0287F0_USE_OPAQUE(1) : 0));
1979 /* SMX returns CONTEXT_DONE too early workaround */
1980 if (rctx
->b
.family
== CHIP_R600
||
1981 rctx
->b
.family
== CHIP_RV610
||
1982 rctx
->b
.family
== CHIP_RV630
||
1983 rctx
->b
.family
== CHIP_RV635
) {
1984 /* if we have gs shader or streamout
1985 we need to do a wait idle after every draw */
1986 if (rctx
->gs_shader
|| r600_get_strmout_en(&rctx
->b
)) {
1987 radeon_set_config_reg(cs
, R_008040_WAIT_UNTIL
, S_008040_WAIT_3D_IDLE(1));
1991 /* ES ring rolling over at EOP - workaround */
1992 if (rctx
->b
.chip_class
== R600
) {
1993 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1994 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_SQ_NON_EVENT
));
1997 /* Set the depth buffer as dirty. */
1998 if (rctx
->framebuffer
.state
.zsbuf
) {
1999 struct pipe_surface
*surf
= rctx
->framebuffer
.state
.zsbuf
;
2000 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
2002 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2004 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
)
2005 rtex
->stencil_dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2007 if (rctx
->framebuffer
.compressed_cb_mask
) {
2008 struct pipe_surface
*surf
;
2009 struct r600_texture
*rtex
;
2010 unsigned mask
= rctx
->framebuffer
.compressed_cb_mask
;
2013 unsigned i
= u_bit_scan(&mask
);
2014 surf
= rctx
->framebuffer
.state
.cbufs
[i
];
2015 rtex
= (struct r600_texture
*)surf
->texture
;
2017 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2022 pipe_resource_reference(&ib
.buffer
, NULL
);
2023 rctx
->b
.num_draw_calls
++;
2026 uint32_t r600_translate_stencil_op(int s_op
)
2029 case PIPE_STENCIL_OP_KEEP
:
2030 return V_028800_STENCIL_KEEP
;
2031 case PIPE_STENCIL_OP_ZERO
:
2032 return V_028800_STENCIL_ZERO
;
2033 case PIPE_STENCIL_OP_REPLACE
:
2034 return V_028800_STENCIL_REPLACE
;
2035 case PIPE_STENCIL_OP_INCR
:
2036 return V_028800_STENCIL_INCR
;
2037 case PIPE_STENCIL_OP_DECR
:
2038 return V_028800_STENCIL_DECR
;
2039 case PIPE_STENCIL_OP_INCR_WRAP
:
2040 return V_028800_STENCIL_INCR_WRAP
;
2041 case PIPE_STENCIL_OP_DECR_WRAP
:
2042 return V_028800_STENCIL_DECR_WRAP
;
2043 case PIPE_STENCIL_OP_INVERT
:
2044 return V_028800_STENCIL_INVERT
;
2046 R600_ERR("Unknown stencil op %d", s_op
);
2053 uint32_t r600_translate_fill(uint32_t func
)
2056 case PIPE_POLYGON_MODE_FILL
:
2058 case PIPE_POLYGON_MODE_LINE
:
2060 case PIPE_POLYGON_MODE_POINT
:
2068 unsigned r600_tex_wrap(unsigned wrap
)
2072 case PIPE_TEX_WRAP_REPEAT
:
2073 return V_03C000_SQ_TEX_WRAP
;
2074 case PIPE_TEX_WRAP_CLAMP
:
2075 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER
;
2076 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
2077 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL
;
2078 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
2079 return V_03C000_SQ_TEX_CLAMP_BORDER
;
2080 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
2081 return V_03C000_SQ_TEX_MIRROR
;
2082 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
2083 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
2084 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
2085 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
2086 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
2087 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER
;
2091 unsigned r600_tex_mipfilter(unsigned filter
)
2094 case PIPE_TEX_MIPFILTER_NEAREST
:
2095 return V_03C000_SQ_TEX_Z_FILTER_POINT
;
2096 case PIPE_TEX_MIPFILTER_LINEAR
:
2097 return V_03C000_SQ_TEX_Z_FILTER_LINEAR
;
2099 case PIPE_TEX_MIPFILTER_NONE
:
2100 return V_03C000_SQ_TEX_Z_FILTER_NONE
;
2104 unsigned r600_tex_compare(unsigned compare
)
2108 case PIPE_FUNC_NEVER
:
2109 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER
;
2110 case PIPE_FUNC_LESS
:
2111 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS
;
2112 case PIPE_FUNC_EQUAL
:
2113 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL
;
2114 case PIPE_FUNC_LEQUAL
:
2115 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
2116 case PIPE_FUNC_GREATER
:
2117 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER
;
2118 case PIPE_FUNC_NOTEQUAL
:
2119 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
2120 case PIPE_FUNC_GEQUAL
:
2121 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
2122 case PIPE_FUNC_ALWAYS
:
2123 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
2127 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
2129 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
2130 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
2132 (wrap
== PIPE_TEX_WRAP_CLAMP
||
2133 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
2136 bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
)
2138 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
2139 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
2141 return (state
->border_color
.ui
[0] || state
->border_color
.ui
[1] ||
2142 state
->border_color
.ui
[2] || state
->border_color
.ui
[3]) &&
2143 (wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) ||
2144 wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) ||
2145 wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
));
2148 void r600_emit_shader(struct r600_context
*rctx
, struct r600_atom
*a
)
2151 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2152 struct r600_pipe_shader
*shader
= ((struct r600_shader_state
*)a
)->shader
;
2157 r600_emit_command_buffer(cs
, &shader
->command_buffer
);
2158 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2159 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, shader
->bo
,
2160 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
));
2163 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
2164 const unsigned char *swizzle_view
,
2168 unsigned char swizzle
[4];
2169 unsigned result
= 0;
2170 const uint32_t tex_swizzle_shift
[4] = {
2173 const uint32_t vtx_swizzle_shift
[4] = {
2176 const uint32_t swizzle_bit
[4] = {
2179 const uint32_t *swizzle_shift
= tex_swizzle_shift
;
2182 swizzle_shift
= vtx_swizzle_shift
;
2185 util_format_compose_swizzles(swizzle_format
, swizzle_view
, swizzle
);
2187 memcpy(swizzle
, swizzle_format
, 4);
2191 for (i
= 0; i
< 4; i
++) {
2192 switch (swizzle
[i
]) {
2193 case PIPE_SWIZZLE_Y
:
2194 result
|= swizzle_bit
[1] << swizzle_shift
[i
];
2196 case PIPE_SWIZZLE_Z
:
2197 result
|= swizzle_bit
[2] << swizzle_shift
[i
];
2199 case PIPE_SWIZZLE_W
:
2200 result
|= swizzle_bit
[3] << swizzle_shift
[i
];
2202 case PIPE_SWIZZLE_0
:
2203 result
|= V_038010_SQ_SEL_0
<< swizzle_shift
[i
];
2205 case PIPE_SWIZZLE_1
:
2206 result
|= V_038010_SQ_SEL_1
<< swizzle_shift
[i
];
2208 default: /* PIPE_SWIZZLE_X */
2209 result
|= swizzle_bit
[0] << swizzle_shift
[i
];
2215 /* texture format translate */
2216 uint32_t r600_translate_texformat(struct pipe_screen
*screen
,
2217 enum pipe_format format
,
2218 const unsigned char *swizzle_view
,
2219 uint32_t *word4_p
, uint32_t *yuv_format_p
,
2220 bool do_endian_swap
)
2222 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
2223 uint32_t result
= 0, word4
= 0, yuv_format
= 0;
2224 const struct util_format_description
*desc
;
2225 boolean uniform
= TRUE
;
2226 bool is_srgb_valid
= FALSE
;
2227 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
2228 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
2229 const unsigned char swizzle_xxxy
[4] = {0, 0, 0, 1};
2230 const unsigned char swizzle_zyx1
[4] = {2, 1, 0, 5};
2231 const unsigned char swizzle_zyxw
[4] = {2, 1, 0, 3};
2234 const uint32_t sign_bit
[4] = {
2235 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED
),
2236 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED
),
2237 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED
),
2238 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED
)
2241 /* Need to replace the specified texture formats in case of big-endian.
2242 * These formats are formats that have channels with number of bits
2243 * not divisible by 8.
2244 * Mesa conversion functions don't swap bits for those formats, and because
2245 * we transmit this over a serial bus to the GPU (PCIe), the
2246 * bit-endianess is important!!!
2247 * In case we have an "opposite" format, just use that for the swizzling
2248 * information. If we don't have such an "opposite" format, we need
2249 * to use a fixed swizzle info instead (see below)
2251 if (format
== PIPE_FORMAT_R4A4_UNORM
&& do_endian_swap
)
2252 format
= PIPE_FORMAT_A4R4_UNORM
;
2254 desc
= util_format_description(format
);
2256 /* Depth and stencil swizzling is handled separately. */
2257 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
) {
2258 /* Need to check for specific texture formats that don't have
2259 * an "opposite" format we can use. For those formats, we directly
2260 * specify the swizzling, which is the LE swizzling as defined in
2263 if (do_endian_swap
) {
2264 if (format
== PIPE_FORMAT_L4A4_UNORM
)
2265 word4
|= r600_get_swizzle_combined(swizzle_xxxy
, swizzle_view
, FALSE
);
2266 else if (format
== PIPE_FORMAT_B4G4R4A4_UNORM
)
2267 word4
|= r600_get_swizzle_combined(swizzle_zyxw
, swizzle_view
, FALSE
);
2268 else if (format
== PIPE_FORMAT_B4G4R4X4_UNORM
|| format
== PIPE_FORMAT_B5G6R5_UNORM
)
2269 word4
|= r600_get_swizzle_combined(swizzle_zyx1
, swizzle_view
, FALSE
);
2271 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
, FALSE
);
2273 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
, FALSE
);
2277 /* Colorspace (return non-RGB formats directly). */
2278 switch (desc
->colorspace
) {
2279 /* Depth stencil formats */
2280 case UTIL_FORMAT_COLORSPACE_ZS
:
2282 /* Depth sampler formats. */
2283 case PIPE_FORMAT_Z16_UNORM
:
2284 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2287 case PIPE_FORMAT_Z24X8_UNORM
:
2288 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
2289 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2292 case PIPE_FORMAT_X8Z24_UNORM
:
2293 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2294 if (rscreen
->b
.chip_class
< EVERGREEN
)
2296 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
2299 case PIPE_FORMAT_Z32_FLOAT
:
2300 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2301 result
= FMT_32_FLOAT
;
2303 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
2304 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2305 result
= FMT_X24_8_32_FLOAT
;
2307 /* Stencil sampler formats. */
2308 case PIPE_FORMAT_S8_UINT
:
2309 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2310 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2313 case PIPE_FORMAT_X24S8_UINT
:
2314 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2315 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
2318 case PIPE_FORMAT_S8X24_UINT
:
2319 if (rscreen
->b
.chip_class
< EVERGREEN
)
2321 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2322 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2325 case PIPE_FORMAT_X32_S8X24_UINT
:
2326 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2327 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
2328 result
= FMT_X24_8_32_FLOAT
;
2334 case UTIL_FORMAT_COLORSPACE_YUV
:
2335 yuv_format
|= (1 << 30);
2337 case PIPE_FORMAT_UYVY
:
2338 case PIPE_FORMAT_YUYV
:
2342 goto out_unknown
; /* XXX */
2344 case UTIL_FORMAT_COLORSPACE_SRGB
:
2345 word4
|= S_038010_FORCE_DEGAMMA(1);
2352 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
2354 case PIPE_FORMAT_RGTC1_SNORM
:
2355 case PIPE_FORMAT_LATC1_SNORM
:
2356 word4
|= sign_bit
[0];
2357 case PIPE_FORMAT_RGTC1_UNORM
:
2358 case PIPE_FORMAT_LATC1_UNORM
:
2361 case PIPE_FORMAT_RGTC2_SNORM
:
2362 case PIPE_FORMAT_LATC2_SNORM
:
2363 word4
|= sign_bit
[0] | sign_bit
[1];
2364 case PIPE_FORMAT_RGTC2_UNORM
:
2365 case PIPE_FORMAT_LATC2_UNORM
:
2373 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
2374 if (!util_format_s3tc_enabled
) {
2379 case PIPE_FORMAT_DXT1_RGB
:
2380 case PIPE_FORMAT_DXT1_RGBA
:
2381 case PIPE_FORMAT_DXT1_SRGB
:
2382 case PIPE_FORMAT_DXT1_SRGBA
:
2384 is_srgb_valid
= TRUE
;
2386 case PIPE_FORMAT_DXT3_RGBA
:
2387 case PIPE_FORMAT_DXT3_SRGBA
:
2389 is_srgb_valid
= TRUE
;
2391 case PIPE_FORMAT_DXT5_RGBA
:
2392 case PIPE_FORMAT_DXT5_SRGBA
:
2394 is_srgb_valid
= TRUE
;
2401 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
2402 if (rscreen
->b
.chip_class
< EVERGREEN
)
2406 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
2407 case PIPE_FORMAT_BPTC_SRGBA
:
2409 is_srgb_valid
= TRUE
;
2411 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
2412 word4
|= sign_bit
[0] | sign_bit
[1] | sign_bit
[2];
2414 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
2422 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
2424 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
2425 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
2428 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
2429 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
2437 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
2438 result
= FMT_5_9_9_9_SHAREDEXP
;
2440 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
2441 result
= FMT_10_11_11_FLOAT
;
2446 for (i
= 0; i
< desc
->nr_channels
; i
++) {
2447 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2448 word4
|= sign_bit
[i
];
2452 /* R8G8Bx_SNORM - XXX CxV8U8 */
2454 /* See whether the components are of the same size. */
2455 for (i
= 1; i
< desc
->nr_channels
; i
++) {
2456 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
2459 /* Non-uniform formats. */
2461 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
2462 desc
->channel
[0].pure_integer
)
2463 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2464 switch(desc
->nr_channels
) {
2466 if (desc
->channel
[0].size
== 5 &&
2467 desc
->channel
[1].size
== 6 &&
2468 desc
->channel
[2].size
== 5) {
2474 if (desc
->channel
[0].size
== 5 &&
2475 desc
->channel
[1].size
== 5 &&
2476 desc
->channel
[2].size
== 5 &&
2477 desc
->channel
[3].size
== 1) {
2478 result
= FMT_1_5_5_5
;
2481 if (desc
->channel
[0].size
== 10 &&
2482 desc
->channel
[1].size
== 10 &&
2483 desc
->channel
[2].size
== 10 &&
2484 desc
->channel
[3].size
== 2) {
2485 result
= FMT_2_10_10_10
;
2493 /* Find the first non-VOID channel. */
2494 for (i
= 0; i
< 4; i
++) {
2495 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2503 /* uniform formats */
2504 switch (desc
->channel
[i
].type
) {
2505 case UTIL_FORMAT_TYPE_UNSIGNED
:
2506 case UTIL_FORMAT_TYPE_SIGNED
:
2508 if (!desc
->channel
[i
].normalized
&&
2509 desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
) {
2513 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
2514 desc
->channel
[i
].pure_integer
)
2515 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2517 switch (desc
->channel
[i
].size
) {
2519 switch (desc
->nr_channels
) {
2524 result
= FMT_4_4_4_4
;
2529 switch (desc
->nr_channels
) {
2537 result
= FMT_8_8_8_8
;
2538 is_srgb_valid
= TRUE
;
2543 switch (desc
->nr_channels
) {
2551 result
= FMT_16_16_16_16
;
2556 switch (desc
->nr_channels
) {
2564 result
= FMT_32_32_32_32
;
2570 case UTIL_FORMAT_TYPE_FLOAT
:
2571 switch (desc
->channel
[i
].size
) {
2573 switch (desc
->nr_channels
) {
2575 result
= FMT_16_FLOAT
;
2578 result
= FMT_16_16_FLOAT
;
2581 result
= FMT_16_16_16_16_FLOAT
;
2586 switch (desc
->nr_channels
) {
2588 result
= FMT_32_FLOAT
;
2591 result
= FMT_32_32_FLOAT
;
2594 result
= FMT_32_32_32_32_FLOAT
;
2603 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
&& !is_srgb_valid
)
2608 *yuv_format_p
= yuv_format
;
2611 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
2615 uint32_t r600_translate_colorformat(enum chip_class chip
, enum pipe_format format
,
2616 bool do_endian_swap
)
2618 const struct util_format_description
*desc
= util_format_description(format
);
2619 int channel
= util_format_get_first_non_void_channel(format
);
2622 #define HAS_SIZE(x,y,z,w) \
2623 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
2624 desc->channel[2].size == (z) && desc->channel[3].size == (w))
2626 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2627 return V_0280A0_COLOR_10_11_11_FLOAT
;
2629 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
||
2633 is_float
= desc
->channel
[channel
].type
== UTIL_FORMAT_TYPE_FLOAT
;
2635 switch (desc
->nr_channels
) {
2637 switch (desc
->channel
[0].size
) {
2639 return V_0280A0_COLOR_8
;
2642 return V_0280A0_COLOR_16_FLOAT
;
2644 return V_0280A0_COLOR_16
;
2647 return V_0280A0_COLOR_32_FLOAT
;
2649 return V_0280A0_COLOR_32
;
2653 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
2654 switch (desc
->channel
[0].size
) {
2657 return V_0280A0_COLOR_4_4
;
2659 return ~0U; /* removed on Evergreen */
2661 return V_0280A0_COLOR_8_8
;
2664 return V_0280A0_COLOR_16_16_FLOAT
;
2666 return V_0280A0_COLOR_16_16
;
2669 return V_0280A0_COLOR_32_32_FLOAT
;
2671 return V_0280A0_COLOR_32_32
;
2673 } else if (HAS_SIZE(8,24,0,0)) {
2674 return (do_endian_swap
? V_0280A0_COLOR_8_24
: V_0280A0_COLOR_24_8
);
2675 } else if (HAS_SIZE(24,8,0,0)) {
2676 return V_0280A0_COLOR_8_24
;
2680 if (HAS_SIZE(5,6,5,0)) {
2681 return V_0280A0_COLOR_5_6_5
;
2682 } else if (HAS_SIZE(32,8,24,0)) {
2683 return V_0280A0_COLOR_X24_8_32_FLOAT
;
2687 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
2688 desc
->channel
[0].size
== desc
->channel
[2].size
&&
2689 desc
->channel
[0].size
== desc
->channel
[3].size
) {
2690 switch (desc
->channel
[0].size
) {
2692 return V_0280A0_COLOR_4_4_4_4
;
2694 return V_0280A0_COLOR_8_8_8_8
;
2697 return V_0280A0_COLOR_16_16_16_16_FLOAT
;
2699 return V_0280A0_COLOR_16_16_16_16
;
2702 return V_0280A0_COLOR_32_32_32_32_FLOAT
;
2704 return V_0280A0_COLOR_32_32_32_32
;
2706 } else if (HAS_SIZE(5,5,5,1)) {
2707 return V_0280A0_COLOR_1_5_5_5
;
2708 } else if (HAS_SIZE(10,10,10,2)) {
2709 return V_0280A0_COLOR_2_10_10_10
;
2716 uint32_t r600_colorformat_endian_swap(uint32_t colorformat
, bool do_endian_swap
)
2718 if (R600_BIG_ENDIAN
) {
2719 switch(colorformat
) {
2720 /* 8-bit buffers. */
2721 case V_0280A0_COLOR_4_4
:
2722 case V_0280A0_COLOR_8
:
2725 /* 16-bit buffers. */
2726 case V_0280A0_COLOR_8_8
:
2728 * No need to do endian swaps on array formats,
2729 * as mesa<-->pipe formats conversion take into account
2734 case V_0280A0_COLOR_5_6_5
:
2735 case V_0280A0_COLOR_1_5_5_5
:
2736 case V_0280A0_COLOR_4_4_4_4
:
2737 case V_0280A0_COLOR_16
:
2738 return (do_endian_swap
? ENDIAN_8IN16
: ENDIAN_NONE
);
2740 /* 32-bit buffers. */
2741 case V_0280A0_COLOR_8_8_8_8
:
2743 * No need to do endian swaps on array formats,
2744 * as mesa<-->pipe formats conversion take into account
2749 case V_0280A0_COLOR_2_10_10_10
:
2750 case V_0280A0_COLOR_8_24
:
2751 case V_0280A0_COLOR_24_8
:
2752 case V_0280A0_COLOR_32_FLOAT
:
2753 return (do_endian_swap
? ENDIAN_8IN32
: ENDIAN_NONE
);
2755 case V_0280A0_COLOR_16_16_FLOAT
:
2756 case V_0280A0_COLOR_16_16
:
2757 return ENDIAN_8IN16
;
2759 /* 64-bit buffers. */
2760 case V_0280A0_COLOR_16_16_16_16
:
2761 case V_0280A0_COLOR_16_16_16_16_FLOAT
:
2762 return ENDIAN_8IN16
;
2764 case V_0280A0_COLOR_32_32_FLOAT
:
2765 case V_0280A0_COLOR_32_32
:
2766 case V_0280A0_COLOR_X24_8_32_FLOAT
:
2767 return ENDIAN_8IN32
;
2769 /* 128-bit buffers. */
2770 case V_0280A0_COLOR_32_32_32_32_FLOAT
:
2771 case V_0280A0_COLOR_32_32_32_32
:
2772 return ENDIAN_8IN32
;
2774 return ENDIAN_NONE
; /* Unsupported. */
2781 static void r600_invalidate_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
)
2783 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2784 struct r600_resource
*rbuffer
= r600_resource(buf
);
2785 unsigned i
, shader
, mask
;
2786 struct r600_pipe_sampler_view
*view
;
2788 /* Reallocate the buffer in the same pipe_resource. */
2789 r600_alloc_resource(&rctx
->screen
->b
, rbuffer
);
2791 /* We changed the buffer, now we need to bind it where the old one was bound. */
2792 /* Vertex buffers. */
2793 mask
= rctx
->vertex_buffer_state
.enabled_mask
;
2795 i
= u_bit_scan(&mask
);
2796 if (rctx
->vertex_buffer_state
.vb
[i
].buffer
== &rbuffer
->b
.b
) {
2797 rctx
->vertex_buffer_state
.dirty_mask
|= 1 << i
;
2798 r600_vertex_buffers_dirty(rctx
);
2801 /* Streamout buffers. */
2802 for (i
= 0; i
< rctx
->b
.streamout
.num_targets
; i
++) {
2803 if (rctx
->b
.streamout
.targets
[i
] &&
2804 rctx
->b
.streamout
.targets
[i
]->b
.buffer
== &rbuffer
->b
.b
) {
2805 if (rctx
->b
.streamout
.begin_emitted
) {
2806 r600_emit_streamout_end(&rctx
->b
);
2808 rctx
->b
.streamout
.append_bitmask
= rctx
->b
.streamout
.enabled_mask
;
2809 r600_streamout_buffers_dirty(&rctx
->b
);
2813 /* Constant buffers. */
2814 for (shader
= 0; shader
< PIPE_SHADER_TYPES
; shader
++) {
2815 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
2817 uint32_t mask
= state
->enabled_mask
;
2820 unsigned i
= u_bit_scan(&mask
);
2821 if (state
->cb
[i
].buffer
== &rbuffer
->b
.b
) {
2823 state
->dirty_mask
|= 1 << i
;
2827 r600_constant_buffers_dirty(rctx
, state
);
2831 /* Texture buffer objects - update the virtual addresses in descriptors. */
2832 LIST_FOR_EACH_ENTRY(view
, &rctx
->b
.texture_buffers
, list
) {
2833 if (view
->base
.texture
== &rbuffer
->b
.b
) {
2834 uint64_t offset
= view
->base
.u
.buf
.offset
;
2835 uint64_t va
= rbuffer
->gpu_address
+ offset
;
2837 view
->tex_resource_words
[0] = va
;
2838 view
->tex_resource_words
[2] &= C_038008_BASE_ADDRESS_HI
;
2839 view
->tex_resource_words
[2] |= S_038008_BASE_ADDRESS_HI(va
>> 32);
2842 /* Texture buffer objects - make bindings dirty if needed. */
2843 for (shader
= 0; shader
< PIPE_SHADER_TYPES
; shader
++) {
2844 struct r600_samplerview_state
*state
= &rctx
->samplers
[shader
].views
;
2846 uint32_t mask
= state
->enabled_mask
;
2849 unsigned i
= u_bit_scan(&mask
);
2850 if (state
->views
[i
]->base
.texture
== &rbuffer
->b
.b
) {
2852 state
->dirty_mask
|= 1 << i
;
2856 r600_sampler_views_dirty(rctx
, state
);
2861 static void r600_set_active_query_state(struct pipe_context
*ctx
, boolean enable
)
2863 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2865 /* Pipeline stat & streamout queries. */
2867 rctx
->b
.flags
&= ~R600_CONTEXT_STOP_PIPELINE_STATS
;
2868 rctx
->b
.flags
|= R600_CONTEXT_START_PIPELINE_STATS
;
2870 rctx
->b
.flags
&= ~R600_CONTEXT_START_PIPELINE_STATS
;
2871 rctx
->b
.flags
|= R600_CONTEXT_STOP_PIPELINE_STATS
;
2874 /* Occlusion queries. */
2875 if (rctx
->db_misc_state
.occlusion_queries_disabled
!= !enable
) {
2876 rctx
->db_misc_state
.occlusion_queries_disabled
= !enable
;
2877 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
2881 static void r600_set_occlusion_query_state(struct pipe_context
*ctx
, bool enable
)
2883 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2885 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
2888 static void r600_need_gfx_cs_space(struct pipe_context
*ctx
, unsigned num_dw
,
2889 bool include_draw_vbo
)
2891 r600_need_cs_space((struct r600_context
*)ctx
, num_dw
, include_draw_vbo
);
2894 /* keep this at the end of this file, please */
2895 void r600_init_common_state_functions(struct r600_context
*rctx
)
2897 rctx
->b
.b
.create_fs_state
= r600_create_ps_state
;
2898 rctx
->b
.b
.create_vs_state
= r600_create_vs_state
;
2899 rctx
->b
.b
.create_gs_state
= r600_create_gs_state
;
2900 rctx
->b
.b
.create_tcs_state
= r600_create_tcs_state
;
2901 rctx
->b
.b
.create_tes_state
= r600_create_tes_state
;
2902 rctx
->b
.b
.create_vertex_elements_state
= r600_create_vertex_fetch_shader
;
2903 rctx
->b
.b
.bind_blend_state
= r600_bind_blend_state
;
2904 rctx
->b
.b
.bind_depth_stencil_alpha_state
= r600_bind_dsa_state
;
2905 rctx
->b
.b
.bind_sampler_states
= r600_bind_sampler_states
;
2906 rctx
->b
.b
.bind_fs_state
= r600_bind_ps_state
;
2907 rctx
->b
.b
.bind_rasterizer_state
= r600_bind_rs_state
;
2908 rctx
->b
.b
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
2909 rctx
->b
.b
.bind_vs_state
= r600_bind_vs_state
;
2910 rctx
->b
.b
.bind_gs_state
= r600_bind_gs_state
;
2911 rctx
->b
.b
.bind_tcs_state
= r600_bind_tcs_state
;
2912 rctx
->b
.b
.bind_tes_state
= r600_bind_tes_state
;
2913 rctx
->b
.b
.delete_blend_state
= r600_delete_blend_state
;
2914 rctx
->b
.b
.delete_depth_stencil_alpha_state
= r600_delete_dsa_state
;
2915 rctx
->b
.b
.delete_fs_state
= r600_delete_ps_state
;
2916 rctx
->b
.b
.delete_rasterizer_state
= r600_delete_rs_state
;
2917 rctx
->b
.b
.delete_sampler_state
= r600_delete_sampler_state
;
2918 rctx
->b
.b
.delete_vertex_elements_state
= r600_delete_vertex_elements
;
2919 rctx
->b
.b
.delete_vs_state
= r600_delete_vs_state
;
2920 rctx
->b
.b
.delete_gs_state
= r600_delete_gs_state
;
2921 rctx
->b
.b
.delete_tcs_state
= r600_delete_tcs_state
;
2922 rctx
->b
.b
.delete_tes_state
= r600_delete_tes_state
;
2923 rctx
->b
.b
.set_blend_color
= r600_set_blend_color
;
2924 rctx
->b
.b
.set_clip_state
= r600_set_clip_state
;
2925 rctx
->b
.b
.set_constant_buffer
= r600_set_constant_buffer
;
2926 rctx
->b
.b
.set_sample_mask
= r600_set_sample_mask
;
2927 rctx
->b
.b
.set_stencil_ref
= r600_set_pipe_stencil_ref
;
2928 rctx
->b
.b
.set_vertex_buffers
= r600_set_vertex_buffers
;
2929 rctx
->b
.b
.set_index_buffer
= r600_set_index_buffer
;
2930 rctx
->b
.b
.set_sampler_views
= r600_set_sampler_views
;
2931 rctx
->b
.b
.sampler_view_destroy
= r600_sampler_view_destroy
;
2932 rctx
->b
.b
.texture_barrier
= r600_texture_barrier
;
2933 rctx
->b
.b
.set_stream_output_targets
= r600_set_streamout_targets
;
2934 rctx
->b
.b
.set_active_query_state
= r600_set_active_query_state
;
2935 rctx
->b
.b
.draw_vbo
= r600_draw_vbo
;
2936 rctx
->b
.invalidate_buffer
= r600_invalidate_buffer
;
2937 rctx
->b
.set_occlusion_query_state
= r600_set_occlusion_query_state
;
2938 rctx
->b
.need_gfx_cs_space
= r600_need_gfx_cs_space
;