src/gallium/drivers/r600/r600_state_common.c

   1 /*
   2  * Copyright 2010 Red Hat Inc.
   3  *           2010 Jerome Glisse
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie <airlied@redhat.com>
  25  *          Jerome Glisse <jglisse@redhat.com>
  26  */
  27 #include "util/u_blitter.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_format.h"
  30 #include "pipebuffer/pb_buffer.h"
  31 #include "pipe/p_shader_tokens.h"
  32 #include "tgsi/tgsi_parse.h"
  33 #include "r600_formats.h"
  34 #include "r600_pipe.h"
  35 #include "r600d.h"
  36
  37 static void r600_emit_surface_sync(struct r600_context *rctx, struct r600_atom *atom)
  38 {
  39         struct radeon_winsys_cs *cs = rctx->cs;
  40         struct r600_atom_surface_sync *a = (struct r600_atom_surface_sync*)atom;
  41
  42         cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
  43         cs->buf[cs->cdw++] = a->flush_flags;  /* CP_COHER_CNTL */
  44         cs->buf[cs->cdw++] = 0xffffffff;      /* CP_COHER_SIZE */
  45         cs->buf[cs->cdw++] = 0;               /* CP_COHER_BASE */
  46         cs->buf[cs->cdw++] = 0x0000000A;      /* POLL_INTERVAL */
  47
  48         a->flush_flags = 0;
  49 }
  50
  51 static void r600_emit_r6xx_flush_and_inv(struct r600_context *rctx, struct r600_atom *atom)
  52 {
  53         struct radeon_winsys_cs *cs = rctx->cs;
  54         cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
  55         cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
  56 }
  57
  58 static void r600_init_atom(struct r600_atom *atom,
  59                            void (*emit)(struct r600_context *ctx, struct r600_atom *state),
  60                            unsigned num_dw,
  61                            enum r600_atom_flags flags)
  62 {
  63         atom->emit = emit;
  64         atom->num_dw = num_dw;
  65         atom->flags = flags;
  66 }
  67
  68 void r600_init_common_atoms(struct r600_context *rctx)
  69 {
  70         r600_init_atom(&rctx->atom_surface_sync.atom,   r600_emit_surface_sync,         5, EMIT_EARLY);
  71         r600_init_atom(&rctx->atom_r6xx_flush_and_inv,  r600_emit_r6xx_flush_and_inv,   2, EMIT_EARLY);
  72 }
  73
  74 unsigned r600_get_cb_flush_flags(struct r600_context *rctx)
  75 {
  76         unsigned flags = 0;
  77
  78         if (rctx->framebuffer.nr_cbufs) {
  79                 flags |= S_0085F0_CB_ACTION_ENA(1) |
  80                          (((1 << rctx->framebuffer.nr_cbufs) - 1) << S_0085F0_CB0_DEST_BASE_ENA_SHIFT);
  81         }
  82
  83         /* Workaround for broken flushing on some R6xx chipsets. */
  84         if (rctx->family == CHIP_RV670 ||
  85             rctx->family == CHIP_RS780 ||
  86             rctx->family == CHIP_RS880) {
  87                 flags |=  S_0085F0_CB1_DEST_BASE_ENA(1) |
  88                           S_0085F0_DEST_BASE_0_ENA(1);
  89         }
  90         return flags;
  91 }
  92
  93 void r600_texture_barrier(struct pipe_context *ctx)
  94 {
  95         struct r600_context *rctx = (struct r600_context *)ctx;
  96
  97         rctx->atom_surface_sync.flush_flags |= S_0085F0_TC_ACTION_ENA(1) | r600_get_cb_flush_flags(rctx);
  98         r600_atom_dirty(rctx, &rctx->atom_surface_sync.atom);
  99 }
 100
 101 static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
 102 {
 103         static const int prim_conv[] = {
 104                 V_008958_DI_PT_POINTLIST,
 105                 V_008958_DI_PT_LINELIST,
 106                 V_008958_DI_PT_LINELOOP,
 107                 V_008958_DI_PT_LINESTRIP,
 108                 V_008958_DI_PT_TRILIST,
 109                 V_008958_DI_PT_TRISTRIP,
 110                 V_008958_DI_PT_TRIFAN,
 111                 V_008958_DI_PT_QUADLIST,
 112                 V_008958_DI_PT_QUADSTRIP,
 113                 V_008958_DI_PT_POLYGON,
 114                 -1,
 115                 -1,
 116                 -1,
 117                 -1
 118         };
 119
 120         *prim = prim_conv[pprim];
 121         if (*prim == -1) {
 122                 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim);
 123                 return false;
 124         }
 125         return true;
 126 }
 127
 128 /* common state between evergreen and r600 */
 129 void r600_bind_blend_state(struct pipe_context *ctx, void *state)
 130 {
 131         struct r600_context *rctx = (struct r600_context *)ctx;
 132         struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
 133         struct r600_pipe_state *rstate;
 134
 135         if (state == NULL)
 136                 return;
 137         rstate = &blend->rstate;
 138         rctx->states[rstate->id] = rstate;
 139         rctx->cb_target_mask = blend->cb_target_mask;
 140
 141         /* Replace every bit except MULTIWRITE_ENABLE. */
 142         rctx->cb_color_control &= ~C_028808_MULTIWRITE_ENABLE;
 143         rctx->cb_color_control |= blend->cb_color_control & C_028808_MULTIWRITE_ENABLE;
 144
 145         r600_context_pipe_state_set(rctx, rstate);
 146 }
 147
 148 void r600_set_blend_color(struct pipe_context *ctx,
 149                           const struct pipe_blend_color *state)
 150 {
 151         struct r600_context *rctx = (struct r600_context *)ctx;
 152         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 153
 154         if (rstate == NULL)
 155                 return;
 156
 157         rstate->id = R600_PIPE_STATE_BLEND_COLOR;
 158         r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), NULL, 0);
 159         r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), NULL, 0);
 160         r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), NULL, 0);
 161         r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), NULL, 0);
 162
 163         free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
 164         rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
 165         r600_context_pipe_state_set(rctx, rstate);
 166 }
 167
 168 static void r600_set_stencil_ref(struct pipe_context *ctx,
 169                                  const struct r600_stencil_ref *state)
 170 {
 171         struct r600_context *rctx = (struct r600_context *)ctx;
 172         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 173
 174         if (rstate == NULL)
 175                 return;
 176
 177         rstate->id = R600_PIPE_STATE_STENCIL_REF;
 178         r600_pipe_state_add_reg(rstate,
 179                                 R_028430_DB_STENCILREFMASK,
 180                                 S_028430_STENCILREF(state->ref_value[0]) |
 181                                 S_028430_STENCILMASK(state->valuemask[0]) |
 182                                 S_028430_STENCILWRITEMASK(state->writemask[0]),
 183                                 NULL, 0);
 184         r600_pipe_state_add_reg(rstate,
 185                                 R_028434_DB_STENCILREFMASK_BF,
 186                                 S_028434_STENCILREF_BF(state->ref_value[1]) |
 187                                 S_028434_STENCILMASK_BF(state->valuemask[1]) |
 188                                 S_028434_STENCILWRITEMASK_BF(state->writemask[1]),
 189                                 NULL, 0);
 190
 191         free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
 192         rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
 193         r600_context_pipe_state_set(rctx, rstate);
 194 }
 195
 196 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
 197                                const struct pipe_stencil_ref *state)
 198 {
 199         struct r600_context *rctx = (struct r600_context *)ctx;
 200         struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA];
 201         struct r600_stencil_ref ref;
 202
 203         rctx->stencil_ref = *state;
 204
 205         if (!dsa)
 206                 return;
 207
 208         ref.ref_value[0] = state->ref_value[0];
 209         ref.ref_value[1] = state->ref_value[1];
 210         ref.valuemask[0] = dsa->valuemask[0];
 211         ref.valuemask[1] = dsa->valuemask[1];
 212         ref.writemask[0] = dsa->writemask[0];
 213         ref.writemask[1] = dsa->writemask[1];
 214
 215         r600_set_stencil_ref(ctx, &ref);
 216 }
 217
 218 void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
 219 {
 220         struct r600_context *rctx = (struct r600_context *)ctx;
 221         struct r600_pipe_dsa *dsa = state;
 222         struct r600_pipe_state *rstate;
 223         struct r600_stencil_ref ref;
 224
 225         if (state == NULL)
 226                 return;
 227         rstate = &dsa->rstate;
 228         rctx->states[rstate->id] = rstate;
 229         rctx->alpha_ref = dsa->alpha_ref;
 230         rctx->alpha_ref_dirty = true;
 231         r600_context_pipe_state_set(rctx, rstate);
 232
 233         ref.ref_value[0] = rctx->stencil_ref.ref_value[0];
 234         ref.ref_value[1] = rctx->stencil_ref.ref_value[1];
 235         ref.valuemask[0] = dsa->valuemask[0];
 236         ref.valuemask[1] = dsa->valuemask[1];
 237         ref.writemask[0] = dsa->writemask[0];
 238         ref.writemask[1] = dsa->writemask[1];
 239
 240         r600_set_stencil_ref(ctx, &ref);
 241 }
 242
 243 void r600_bind_rs_state(struct pipe_context *ctx, void *state)
 244 {
 245         struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
 246         struct r600_context *rctx = (struct r600_context *)ctx;
 247
 248         if (state == NULL)
 249                 return;
 250
 251         rctx->sprite_coord_enable = rs->sprite_coord_enable;
 252         rctx->two_side = rs->two_side;
 253         rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
 254         rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
 255         rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
 256
 257         rctx->rasterizer = rs;
 258
 259         rctx->states[rs->rstate.id] = &rs->rstate;
 260         r600_context_pipe_state_set(rctx, &rs->rstate);
 261
 262         if (rctx->chip_class >= EVERGREEN) {
 263                 evergreen_polygon_offset_update(rctx);
 264         } else {
 265                 r600_polygon_offset_update(rctx);
 266         }
 267 }
 268
 269 void r600_delete_rs_state(struct pipe_context *ctx, void *state)
 270 {
 271         struct r600_context *rctx = (struct r600_context *)ctx;
 272         struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
 273
 274         if (rctx->rasterizer == rs) {
 275                 rctx->rasterizer = NULL;
 276         }
 277         if (rctx->states[rs->rstate.id] == &rs->rstate) {
 278                 rctx->states[rs->rstate.id] = NULL;
 279         }
 280         free(rs);
 281 }
 282
 283 void r600_sampler_view_destroy(struct pipe_context *ctx,
 284                                struct pipe_sampler_view *state)
 285 {
 286         struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
 287
 288         pipe_resource_reference(&state->texture, NULL);
 289         FREE(resource);
 290 }
 291
 292 void r600_delete_state(struct pipe_context *ctx, void *state)
 293 {
 294         struct r600_context *rctx = (struct r600_context *)ctx;
 295         struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
 296
 297         if (rctx->states[rstate->id] == rstate) {
 298                 rctx->states[rstate->id] = NULL;
 299         }
 300         for (int i = 0; i < rstate->nregs; i++) {
 301                 pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL);
 302         }
 303         free(rstate);
 304 }
 305
 306 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
 307 {
 308         struct r600_context *rctx = (struct r600_context *)ctx;
 309         struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 310
 311         rctx->vertex_elements = v;
 312         if (v) {
 313                 r600_inval_shader_cache(rctx);
 314                 u_vbuf_bind_vertex_elements(rctx->vbuf_mgr, state,
 315                                                 v->vmgr_elements);
 316
 317                 rctx->states[v->rstate.id] = &v->rstate;
 318                 r600_context_pipe_state_set(rctx, &v->rstate);
 319         }
 320 }
 321
 322 void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
 323 {
 324         struct r600_context *rctx = (struct r600_context *)ctx;
 325         struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 326
 327         if (rctx->states[v->rstate.id] == &v->rstate) {
 328                 rctx->states[v->rstate.id] = NULL;
 329         }
 330         if (rctx->vertex_elements == state)
 331                 rctx->vertex_elements = NULL;
 332
 333         pipe_resource_reference((struct pipe_resource**)&v->fetch_shader, NULL);
 334         u_vbuf_destroy_vertex_elements(rctx->vbuf_mgr, v->vmgr_elements);
 335         FREE(state);
 336 }
 337
 338
 339 void r600_set_index_buffer(struct pipe_context *ctx,
 340                            const struct pipe_index_buffer *ib)
 341 {
 342         struct r600_context *rctx = (struct r600_context *)ctx;
 343
 344         u_vbuf_set_index_buffer(rctx->vbuf_mgr, ib);
 345 }
 346
 347 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
 348                              const struct pipe_vertex_buffer *buffers)
 349 {
 350         struct r600_context *rctx = (struct r600_context *)ctx;
 351         int i;
 352
 353         /* Zero states. */
 354         for (i = 0; i < count; i++) {
 355                 if (!buffers[i].buffer) {
 356                         if (rctx->chip_class >= EVERGREEN) {
 357                                 evergreen_context_pipe_state_set_fs_resource(rctx, NULL, i);
 358                         } else {
 359                                 r600_context_pipe_state_set_fs_resource(rctx, NULL, i);
 360                         }
 361                 }
 362         }
 363         for (; i < rctx->vbuf_mgr->nr_real_vertex_buffers; i++) {
 364                 if (rctx->chip_class >= EVERGREEN) {
 365                         evergreen_context_pipe_state_set_fs_resource(rctx, NULL, i);
 366                 } else {
 367                         r600_context_pipe_state_set_fs_resource(rctx, NULL, i);
 368                 }
 369         }
 370
 371         u_vbuf_set_vertex_buffers(rctx->vbuf_mgr, count, buffers);
 372 }
 373
 374 void *r600_create_vertex_elements(struct pipe_context *ctx,
 375                                   unsigned count,
 376                                   const struct pipe_vertex_element *elements)
 377 {
 378         struct r600_context *rctx = (struct r600_context *)ctx;
 379         struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
 380
 381         assert(count < 32);
 382         if (!v)
 383                 return NULL;
 384
 385         v->count = count;
 386         v->vmgr_elements =
 387                 u_vbuf_create_vertex_elements(rctx->vbuf_mgr, count,
 388                                                   elements, v->elements);
 389
 390         if (r600_vertex_elements_build_fetch_shader(rctx, v)) {
 391                 FREE(v);
 392                 return NULL;
 393         }
 394
 395         return v;
 396 }
 397
 398 void *r600_create_shader_state(struct pipe_context *ctx,
 399                                const struct pipe_shader_state *state)
 400 {
 401         struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader);
 402         int r;
 403
 404         shader->tokens = tgsi_dup_tokens(state->tokens);
 405         shader->so = state->stream_output;
 406
 407         r =  r600_pipe_shader_create(ctx, shader);
 408         if (r) {
 409                 return NULL;
 410         }
 411         return shader;
 412 }
 413
 414 void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
 415 {
 416         struct r600_context *rctx = (struct r600_context *)ctx;
 417
 418         /* TODO delete old shader */
 419         rctx->ps_shader = (struct r600_pipe_shader *)state;
 420         if (state) {
 421                 r600_inval_shader_cache(rctx);
 422                 r600_context_pipe_state_set(rctx, &rctx->ps_shader->rstate);
 423
 424                 rctx->cb_color_control &= C_028808_MULTIWRITE_ENABLE;
 425                 rctx->cb_color_control |= S_028808_MULTIWRITE_ENABLE(!!rctx->ps_shader->shader.fs_write_all);
 426         }
 427         if (rctx->ps_shader && rctx->vs_shader) {
 428                 r600_adjust_gprs(rctx);
 429         }
 430 }
 431
 432 void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
 433 {
 434         struct r600_context *rctx = (struct r600_context *)ctx;
 435
 436         /* TODO delete old shader */
 437         rctx->vs_shader = (struct r600_pipe_shader *)state;
 438         if (state) {
 439                 r600_inval_shader_cache(rctx);
 440                 r600_context_pipe_state_set(rctx, &rctx->vs_shader->rstate);
 441         }
 442         if (rctx->ps_shader && rctx->vs_shader) {
 443                 r600_adjust_gprs(rctx);
 444         }
 445 }
 446
 447 void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
 448 {
 449         struct r600_context *rctx = (struct r600_context *)ctx;
 450         struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
 451
 452         if (rctx->ps_shader == shader) {
 453                 rctx->ps_shader = NULL;
 454         }
 455
 456         free(shader->tokens);
 457         r600_pipe_shader_destroy(ctx, shader);
 458         free(shader);
 459 }
 460
 461 void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
 462 {
 463         struct r600_context *rctx = (struct r600_context *)ctx;
 464         struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
 465
 466         if (rctx->vs_shader == shader) {
 467                 rctx->vs_shader = NULL;
 468         }
 469
 470         free(shader->tokens);
 471         r600_pipe_shader_destroy(ctx, shader);
 472         free(shader);
 473 }
 474
 475 static void r600_update_alpha_ref(struct r600_context *rctx)
 476 {
 477         unsigned alpha_ref;
 478         struct r600_pipe_state rstate;
 479
 480         alpha_ref = rctx->alpha_ref;
 481         rstate.nregs = 0;
 482         if (rctx->export_16bpc)
 483                 alpha_ref &= ~0x1FFF;
 484         r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref, NULL, 0);
 485
 486         r600_context_pipe_state_set(rctx, &rstate);
 487         rctx->alpha_ref_dirty = false;
 488 }
 489
 490 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 491                               struct pipe_resource *buffer)
 492 {
 493         struct r600_context *rctx = (struct r600_context *)ctx;
 494         struct r600_resource *rbuffer = r600_resource(buffer);
 495         struct r600_pipe_resource_state *rstate;
 496         uint64_t va_offset;
 497         uint32_t offset;
 498
 499         /* Note that the state tracker can unbind constant buffers by
 500          * passing NULL here.
 501          */
 502         if (buffer == NULL) {
 503                 return;
 504         }
 505
 506         r600_inval_shader_cache(rctx);
 507
 508         r600_upload_const_buffer(rctx, &rbuffer, &offset);
 509         va_offset = r600_resource_va(ctx->screen, (void*)rbuffer);
 510         va_offset += offset;
 511         va_offset >>= 8;
 512
 513         switch (shader) {
 514         case PIPE_SHADER_VERTEX:
 515                 rctx->vs_const_buffer.nregs = 0;
 516                 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
 517                                         R_028180_ALU_CONST_BUFFER_SIZE_VS_0 + index * 4,
 518                                         ALIGN_DIVUP(buffer->width0 >> 4, 16),
 519                                         NULL, 0);
 520                 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
 521                                         R_028980_ALU_CONST_CACHE_VS_0 + index * 4,
 522                                         va_offset, rbuffer, RADEON_USAGE_READ);
 523                 r600_context_pipe_state_set(rctx, &rctx->vs_const_buffer);
 524
 525                 rstate = &rctx->vs_const_buffer_resource[index];
 526                 if (!rstate->id) {
 527                         if (rctx->chip_class >= EVERGREEN) {
 528                                 evergreen_pipe_init_buffer_resource(rctx, rstate);
 529                         } else {
 530                                 r600_pipe_init_buffer_resource(rctx, rstate);
 531                         }
 532                 }
 533
 534                 if (rctx->chip_class >= EVERGREEN) {
 535                         evergreen_pipe_mod_buffer_resource(ctx, rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 536                         evergreen_context_pipe_state_set_vs_resource(rctx, rstate, index);
 537                 } else {
 538                         r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 539                         r600_context_pipe_state_set_vs_resource(rctx, rstate, index);
 540                 }
 541                 break;
 542         case PIPE_SHADER_FRAGMENT:
 543                 rctx->ps_const_buffer.nregs = 0;
 544                 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
 545                                         R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
 546                                         ALIGN_DIVUP(buffer->width0 >> 4, 16),
 547                                         NULL, 0);
 548                 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
 549                                         R_028940_ALU_CONST_CACHE_PS_0,
 550                                         va_offset, rbuffer, RADEON_USAGE_READ);
 551                 r600_context_pipe_state_set(rctx, &rctx->ps_const_buffer);
 552
 553                 rstate = &rctx->ps_const_buffer_resource[index];
 554                 if (!rstate->id) {
 555                         if (rctx->chip_class >= EVERGREEN) {
 556                                 evergreen_pipe_init_buffer_resource(rctx, rstate);
 557                         } else {
 558                                 r600_pipe_init_buffer_resource(rctx, rstate);
 559                         }
 560                 }
 561                 if (rctx->chip_class >= EVERGREEN) {
 562                         evergreen_pipe_mod_buffer_resource(ctx, rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 563                         evergreen_context_pipe_state_set_ps_resource(rctx, rstate, index);
 564                 } else {
 565                         r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 566                         r600_context_pipe_state_set_ps_resource(rctx, rstate, index);
 567                 }
 568                 break;
 569         default:
 570                 R600_ERR("unsupported %d\n", shader);
 571                 return;
 572         }
 573
 574         if (buffer != &rbuffer->b.b.b)
 575                 pipe_resource_reference((struct pipe_resource**)&rbuffer, NULL);
 576 }
 577
 578 struct pipe_stream_output_target *
 579 r600_create_so_target(struct pipe_context *ctx,
 580                       struct pipe_resource *buffer,
 581                       unsigned buffer_offset,
 582                       unsigned buffer_size)
 583 {
 584         struct r600_context *rctx = (struct r600_context *)ctx;
 585         struct r600_so_target *t;
 586         void *ptr;
 587
 588         t = CALLOC_STRUCT(r600_so_target);
 589         if (!t) {
 590                 return NULL;
 591         }
 592
 593         t->b.reference.count = 1;
 594         t->b.context = ctx;
 595         pipe_resource_reference(&t->b.buffer, buffer);
 596         t->b.buffer_offset = buffer_offset;
 597         t->b.buffer_size = buffer_size;
 598
 599         t->filled_size = (struct r600_resource*)
 600                 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4);
 601         ptr = rctx->ws->buffer_map(t->filled_size->buf, rctx->cs, PIPE_TRANSFER_WRITE);
 602         memset(ptr, 0, t->filled_size->buf->size);
 603         rctx->ws->buffer_unmap(t->filled_size->buf);
 604
 605         return &t->b;
 606 }
 607
 608 void r600_so_target_destroy(struct pipe_context *ctx,
 609                             struct pipe_stream_output_target *target)
 610 {
 611         struct r600_so_target *t = (struct r600_so_target*)target;
 612         pipe_resource_reference(&t->b.buffer, NULL);
 613         pipe_resource_reference((struct pipe_resource**)&t->filled_size, NULL);
 614         FREE(t);
 615 }
 616
 617 void r600_set_so_targets(struct pipe_context *ctx,
 618                          unsigned num_targets,
 619                          struct pipe_stream_output_target **targets,
 620                          unsigned append_bitmask)
 621 {
 622         struct r600_context *rctx = (struct r600_context *)ctx;
 623         unsigned i;
 624
 625         /* Stop streamout. */
 626         if (rctx->num_so_targets) {
 627                 r600_context_streamout_end(rctx);
 628         }
 629
 630         /* Set the new targets. */
 631         for (i = 0; i < num_targets; i++) {
 632                 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]);
 633         }
 634         for (; i < rctx->num_so_targets; i++) {
 635                 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL);
 636         }
 637
 638         rctx->num_so_targets = num_targets;
 639         rctx->streamout_start = num_targets != 0;
 640         rctx->streamout_append_bitmask = append_bitmask;
 641 }
 642
 643 static void r600_vertex_buffer_update(struct r600_context *rctx)
 644 {
 645         struct r600_pipe_resource_state *rstate;
 646         struct r600_resource *rbuffer;
 647         struct pipe_vertex_buffer *vertex_buffer;
 648         unsigned i, count, offset;
 649
 650         r600_inval_vertex_cache(rctx);
 651
 652         if (rctx->vertex_elements->vbuffer_need_offset) {
 653                 /* one resource per vertex elements */
 654                 count = rctx->vertex_elements->count;
 655         } else {
 656                 /* bind vertex buffer once */
 657                 count = rctx->vbuf_mgr->nr_real_vertex_buffers;
 658         }
 659
 660         for (i = 0 ; i < count; i++) {
 661                 rstate = &rctx->fs_resource[i];
 662
 663                 if (rctx->vertex_elements->vbuffer_need_offset) {
 664                         /* one resource per vertex elements */
 665                         unsigned vbuffer_index;
 666                         vbuffer_index = rctx->vertex_elements->elements[i].vertex_buffer_index;
 667                         vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[vbuffer_index];
 668                         rbuffer = (struct r600_resource*)vertex_buffer->buffer;
 669                         offset = rctx->vertex_elements->vbuffer_offset[i];
 670                 } else {
 671                         /* bind vertex buffer once */
 672                         vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[i];
 673                         rbuffer = (struct r600_resource*)vertex_buffer->buffer;
 674                         offset = 0;
 675                 }
 676                 if (vertex_buffer == NULL || rbuffer == NULL)
 677                         continue;
 678                 offset += vertex_buffer->buffer_offset;
 679
 680                 if (!rstate->id) {
 681                         if (rctx->chip_class >= EVERGREEN) {
 682                                 evergreen_pipe_init_buffer_resource(rctx, rstate);
 683                         } else {
 684                                 r600_pipe_init_buffer_resource(rctx, rstate);
 685                         }
 686                 }
 687
 688                 if (rctx->chip_class >= EVERGREEN) {
 689                         evergreen_pipe_mod_buffer_resource(&rctx->context, rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ);
 690                         evergreen_context_pipe_state_set_fs_resource(rctx, rstate, i);
 691                 } else {
 692                         r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ);
 693                         r600_context_pipe_state_set_fs_resource(rctx, rstate, i);
 694                 }
 695         }
 696 }
 697
 698 static int r600_shader_rebuild(struct pipe_context * ctx, struct r600_pipe_shader * shader)
 699 {
 700         struct r600_context *rctx = (struct r600_context *)ctx;
 701         int r;
 702
 703         r600_pipe_shader_destroy(ctx, shader);
 704         r = r600_pipe_shader_create(ctx, shader);
 705         if (r) {
 706                 return r;
 707         }
 708         r600_context_pipe_state_set(rctx, &shader->rstate);
 709
 710         return 0;
 711 }
 712
 713 static void r600_update_derived_state(struct r600_context *rctx)
 714 {
 715         struct pipe_context * ctx = (struct pipe_context*)rctx;
 716         struct r600_pipe_state rstate;
 717
 718         rstate.nregs = 0;
 719
 720         if (rstate.nregs)
 721                 r600_context_pipe_state_set(rctx, &rstate);
 722
 723         if (!rctx->blitter->running) {
 724                 if (rctx->have_depth_fb || rctx->have_depth_texture)
 725                         r600_flush_depth_textures(rctx);
 726         }
 727
 728         if (rctx->chip_class < EVERGREEN) {
 729                 r600_update_sampler_states(rctx);
 730         }
 731
 732         if ((rctx->ps_shader->shader.two_side != rctx->two_side) ||
 733             ((rctx->chip_class >= EVERGREEN) && rctx->ps_shader->shader.fs_write_all &&
 734              (rctx->ps_shader->shader.nr_cbufs != rctx->nr_cbufs))) {
 735                 r600_shader_rebuild(&rctx->context, rctx->ps_shader);
 736         }
 737
 738         if (rctx->alpha_ref_dirty) {
 739                 r600_update_alpha_ref(rctx);
 740         }
 741
 742         if (rctx->ps_shader && ((rctx->sprite_coord_enable &&
 743                 (rctx->ps_shader->sprite_coord_enable != rctx->sprite_coord_enable)) ||
 744                 (rctx->rasterizer && rctx->rasterizer->flatshade != rctx->ps_shader->flatshade))) {
 745
 746                 if (rctx->chip_class >= EVERGREEN)
 747                         evergreen_pipe_shader_ps(ctx, rctx->ps_shader);
 748                 else
 749                         r600_pipe_shader_ps(ctx, rctx->ps_shader);
 750
 751                 r600_context_pipe_state_set(rctx, &rctx->ps_shader->rstate);
 752         }
 753
 754 }
 755
 756 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
 757 {
 758         struct r600_context *rctx = (struct r600_context *)ctx;
 759         struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA];
 760         struct pipe_draw_info info = *dinfo;
 761         struct r600_draw rdraw = {};
 762         struct pipe_index_buffer ib = {};
 763         unsigned prim, mask, ls_mask = 0;
 764         struct r600_block *dirty_block = NULL, *next_block = NULL;
 765         struct r600_atom *state = NULL, *next_state = NULL;
 766
 767         if ((!info.count && (info.indexed || !info.count_from_stream_output)) ||
 768             (info.indexed && !rctx->vbuf_mgr->index_buffer.buffer) ||
 769             !r600_conv_pipe_prim(info.mode, &prim)) {
 770                 return;
 771         }
 772
 773         if (!rctx->ps_shader || !rctx->vs_shader)
 774                 return;
 775
 776         r600_update_derived_state(rctx);
 777
 778         u_vbuf_draw_begin(rctx->vbuf_mgr, &info);
 779         r600_vertex_buffer_update(rctx);
 780
 781         rdraw.vgt_num_indices = info.count;
 782         rdraw.vgt_num_instances = info.instance_count;
 783
 784         if (info.indexed) {
 785                 /* Initialize the index buffer struct. */
 786                 pipe_resource_reference(&ib.buffer, rctx->vbuf_mgr->index_buffer.buffer);
 787                 ib.index_size = rctx->vbuf_mgr->index_buffer.index_size;
 788                 ib.offset = rctx->vbuf_mgr->index_buffer.offset + info.start * ib.index_size;
 789
 790                 /* Translate or upload, if needed. */
 791                 r600_translate_index_buffer(rctx, &ib, info.count);
 792
 793                 if (u_vbuf_resource(ib.buffer)->user_ptr) {
 794                         r600_upload_index_buffer(rctx, &ib, info.count);
 795                 }
 796
 797                 /* Initialize the r600_draw struct with index buffer info. */
 798                 if (ib.index_size == 4) {
 799                         rdraw.vgt_index_type = VGT_INDEX_32 |
 800                                 (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0);
 801                 } else {
 802                         rdraw.vgt_index_type = VGT_INDEX_16 |
 803                                 (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0);
 804                 }
 805                 rdraw.indices = (struct r600_resource*)ib.buffer;
 806                 rdraw.indices_bo_offset = ib.offset;
 807                 rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_DMA;
 808         } else {
 809                 info.index_bias = info.start;
 810                 rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_AUTO_INDEX;
 811                 if (info.count_from_stream_output) {
 812                         rdraw.vgt_draw_initiator |= S_0287F0_USE_OPAQUE(1);
 813
 814                         r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info.count_from_stream_output);
 815                 }
 816         }
 817
 818         mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
 819
 820         if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
 821                 rctx->vgt.id = R600_PIPE_STATE_VGT;
 822                 rctx->vgt.nregs = 0;
 823                 r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, NULL, 0);
 824                 r600_pipe_state_add_reg(&rctx->vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, NULL, 0);
 825                 r600_pipe_state_add_reg(&rctx->vgt, R_028400_VGT_MAX_VTX_INDX, ~0, NULL, 0);
 826                 r600_pipe_state_add_reg(&rctx->vgt, R_028404_VGT_MIN_VTX_INDX, 0, NULL, 0);
 827                 r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias, NULL, 0);
 828                 r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index, NULL, 0);
 829                 r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart, NULL, 0);
 830                 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, NULL, 0);
 831                 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance, NULL, 0);
 832                 r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0, NULL, 0);
 833                 r600_pipe_state_add_reg(&rctx->vgt, R_028814_PA_SU_SC_MODE_CNTL, 0, NULL, 0);
 834                 if (rctx->chip_class <= R700)
 835                         r600_pipe_state_add_reg(&rctx->vgt, R_028808_CB_COLOR_CONTROL, rctx->cb_color_control, NULL, 0);
 836                 r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0, NULL, 0);
 837                 r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0, NULL, 0);
 838         }
 839
 840         rctx->vgt.nregs = 0;
 841         r600_pipe_state_mod_reg(&rctx->vgt, prim);
 842         r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_target_mask & mask);
 843         r600_pipe_state_mod_reg(&rctx->vgt, ~0);
 844         r600_pipe_state_mod_reg(&rctx->vgt, 0);
 845         r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
 846         r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
 847         r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart);
 848         r600_pipe_state_mod_reg(&rctx->vgt, 0);
 849         r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance);
 850
 851         if (prim == V_008958_DI_PT_LINELIST)
 852                 ls_mask = 1;
 853         else if (prim == V_008958_DI_PT_LINESTRIP)
 854                 ls_mask = 2;
 855         r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask) | rctx->pa_sc_line_stipple);
 856
 857         if (info.mode == PIPE_PRIM_QUADS || info.mode == PIPE_PRIM_QUAD_STRIP || info.mode == PIPE_PRIM_POLYGON) {
 858                 r600_pipe_state_mod_reg(&rctx->vgt, S_028814_PROVOKING_VTX_LAST(1) | rctx->pa_su_sc_mode_cntl);
 859         } else {
 860                 r600_pipe_state_mod_reg(&rctx->vgt, rctx->pa_su_sc_mode_cntl);
 861         }
 862         if (rctx->chip_class <= R700)
 863                 r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_color_control);
 864         r600_pipe_state_mod_reg(&rctx->vgt,
 865                                 rctx->vs_shader->pa_cl_vs_out_cntl |
 866                                 (rctx->rasterizer->clip_plane_enable & rctx->vs_shader->shader.clip_dist_write));
 867         r600_pipe_state_mod_reg(&rctx->vgt,
 868                                 rctx->pa_cl_clip_cntl |
 869                                 (rctx->vs_shader->shader.clip_dist_write ||
 870                                  rctx->vs_shader->shader.vs_prohibit_ucps ?
 871                                  0 : rctx->rasterizer->clip_plane_enable & 0x3F));
 872
 873         r600_context_pipe_state_set(rctx, &rctx->vgt);
 874
 875         rdraw.db_render_override = dsa->db_render_override;
 876         rdraw.db_render_control = dsa->db_render_control;
 877
 878         /* Emit states. */
 879         r600_need_cs_space(rctx, 0, TRUE);
 880
 881         LIST_FOR_EACH_ENTRY_SAFE(state, next_state, &rctx->dirty_states, head) {
 882                 r600_emit_atom(rctx, state);
 883         }
 884         LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) {
 885                 r600_context_block_emit_dirty(rctx, dirty_block);
 886         }
 887         LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->resource_dirty,list) {
 888                 r600_context_block_resource_emit_dirty(rctx, dirty_block);
 889         }
 890         rctx->pm4_dirty_cdwords = 0;
 891
 892         /* Enable stream out if needed. */
 893         if (rctx->streamout_start) {
 894                 r600_context_streamout_begin(rctx);
 895                 rctx->streamout_start = FALSE;
 896         }
 897
 898         if (rctx->chip_class >= EVERGREEN) {
 899                 evergreen_context_draw(rctx, &rdraw);
 900         } else {
 901                 r600_context_draw(rctx, &rdraw);
 902         }
 903
 904         rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING;
 905
 906         if (rctx->framebuffer.zsbuf)
 907         {
 908                 struct pipe_resource *tex = rctx->framebuffer.zsbuf->texture;
 909                 ((struct r600_resource_texture *)tex)->dirty_db = TRUE;
 910         }
 911
 912         pipe_resource_reference(&ib.buffer, NULL);
 913         u_vbuf_draw_end(rctx->vbuf_mgr);
 914 }
 915
 916 void _r600_pipe_state_add_reg(struct r600_context *ctx,
 917                               struct r600_pipe_state *state,
 918                               uint32_t offset, uint32_t value,
 919                               uint32_t range_id, uint32_t block_id,
 920                               struct r600_resource *bo,
 921                               enum radeon_bo_usage usage)
 922 {
 923         struct r600_range *range;
 924         struct r600_block *block;
 925
 926         if (bo) assert(usage);
 927
 928         range = &ctx->range[range_id];
 929         block = range->blocks[block_id];
 930         state->regs[state->nregs].block = block;
 931         state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
 932
 933         state->regs[state->nregs].value = value;
 934         state->regs[state->nregs].bo = bo;
 935         state->regs[state->nregs].bo_usage = usage;
 936
 937         state->nregs++;
 938         assert(state->nregs < R600_BLOCK_MAX_REG);
 939 }
 940
 941 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
 942                                      uint32_t offset, uint32_t value,
 943                                      struct r600_resource *bo,
 944                                      enum radeon_bo_usage usage)
 945 {
 946         if (bo) assert(usage);
 947
 948         state->regs[state->nregs].id = offset;
 949         state->regs[state->nregs].block = NULL;
 950         state->regs[state->nregs].value = value;
 951         state->regs[state->nregs].bo = bo;
 952         state->regs[state->nregs].bo_usage = usage;
 953
 954         state->nregs++;
 955         assert(state->nregs < R600_BLOCK_MAX_REG);
 956 }
 957
 958 uint32_t r600_translate_stencil_op(int s_op)
 959 {
 960         switch (s_op) {
 961         case PIPE_STENCIL_OP_KEEP:
 962                 return V_028800_STENCIL_KEEP;
 963         case PIPE_STENCIL_OP_ZERO:
 964                 return V_028800_STENCIL_ZERO;
 965         case PIPE_STENCIL_OP_REPLACE:
 966                 return V_028800_STENCIL_REPLACE;
 967         case PIPE_STENCIL_OP_INCR:
 968                 return V_028800_STENCIL_INCR;
 969         case PIPE_STENCIL_OP_DECR:
 970                 return V_028800_STENCIL_DECR;
 971         case PIPE_STENCIL_OP_INCR_WRAP:
 972                 return V_028800_STENCIL_INCR_WRAP;
 973         case PIPE_STENCIL_OP_DECR_WRAP:
 974                 return V_028800_STENCIL_DECR_WRAP;
 975         case PIPE_STENCIL_OP_INVERT:
 976                 return V_028800_STENCIL_INVERT;
 977         default:
 978                 R600_ERR("Unknown stencil op %d", s_op);
 979                 assert(0);
 980                 break;
 981         }
 982         return 0;
 983 }
 984
 985 uint32_t r600_translate_fill(uint32_t func)
 986 {
 987         switch(func) {
 988         case PIPE_POLYGON_MODE_FILL:
 989                 return 2;
 990         case PIPE_POLYGON_MODE_LINE:
 991                 return 1;
 992         case PIPE_POLYGON_MODE_POINT:
 993                 return 0;
 994         default:
 995                 assert(0);
 996                 return 0;
 997         }
 998 }
 999
1000 unsigned r600_tex_wrap(unsigned wrap)
1001 {
1002         switch (wrap) {
1003         default:
1004         case PIPE_TEX_WRAP_REPEAT:
1005                 return V_03C000_SQ_TEX_WRAP;
1006         case PIPE_TEX_WRAP_CLAMP:
1007                 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1008         case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1009                 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1010         case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1011                 return V_03C000_SQ_TEX_CLAMP_BORDER;
1012         case PIPE_TEX_WRAP_MIRROR_REPEAT:
1013                 return V_03C000_SQ_TEX_MIRROR;
1014         case PIPE_TEX_WRAP_MIRROR_CLAMP:
1015                 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1016         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1017                 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1018         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1019                 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1020         }
1021 }
1022
1023 unsigned r600_tex_filter(unsigned filter)
1024 {
1025         switch (filter) {
1026         default:
1027         case PIPE_TEX_FILTER_NEAREST:
1028                 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1029         case PIPE_TEX_FILTER_LINEAR:
1030                 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1031         }
1032 }
1033
1034 unsigned r600_tex_mipfilter(unsigned filter)
1035 {
1036         switch (filter) {
1037         case PIPE_TEX_MIPFILTER_NEAREST:
1038                 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1039         case PIPE_TEX_MIPFILTER_LINEAR:
1040                 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1041         default:
1042         case PIPE_TEX_MIPFILTER_NONE:
1043                 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1044         }
1045 }
1046
1047 unsigned r600_tex_compare(unsigned compare)
1048 {
1049         switch (compare) {
1050         default:
1051         case PIPE_FUNC_NEVER:
1052                 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1053         case PIPE_FUNC_LESS:
1054                 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1055         case PIPE_FUNC_EQUAL:
1056                 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1057         case PIPE_FUNC_LEQUAL:
1058                 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1059         case PIPE_FUNC_GREATER:
1060                 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1061         case PIPE_FUNC_NOTEQUAL:
1062                 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1063         case PIPE_FUNC_GEQUAL:
1064                 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1065         case PIPE_FUNC_ALWAYS:
1066                 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1067         }
1068 }