projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
r600g: clarify const buffer numbering and handling
[mesa.git] / src / gallium / drivers / r600 / r600_state_common.c
1 /*
2 * Copyright 2010 Red Hat Inc.
3 * 2010 Jerome Glisse
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
26 */
27 #include "r600_formats.h"
28 #include "r600_shader.h"
29 #include "r600d.h"
30
31 #include "util/u_draw_quad.h"
32 #include "util/u_index_modify.h"
33 #include "util/u_upload_mgr.h"
34 #include "tgsi/tgsi_parse.h"
35 #include <byteswap.h>
36
37 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
38
39 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw)
40 {
41 cb->buf = CALLOC(1, 4 * num_dw);
42 cb->max_num_dw = num_dw;
43 }
44
45 void r600_release_command_buffer(struct r600_command_buffer *cb)
46 {
47 FREE(cb->buf);
48 }
49
50 void r600_init_atom(struct r600_context *rctx,
51 struct r600_atom *atom,
52 unsigned id,
53 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
54 unsigned num_dw)
55 {
56 assert(id < R600_NUM_ATOMS);
57 assert(rctx->atoms[id] == NULL);
58 rctx->atoms[id] = atom;
59 atom->id = id;
60 atom->emit = emit;
61 atom->num_dw = num_dw;
62 atom->dirty = false;
63 }
64
65 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom)
66 {
67 r600_emit_command_buffer(rctx->cs, ((struct r600_cso_state*)atom)->cb);
68 }
69
70 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom)
71 {
72 struct radeon_winsys_cs *cs = rctx->cs;
73 struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom;
74 unsigned alpha_ref = a->sx_alpha_ref;
75
76 if (rctx->chip_class >= EVERGREEN && a->cb0_export_16bpc) {
77 alpha_ref &= ~0x1FFF;
78 }
79
80 r600_write_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL,
81 a->sx_alpha_test_control |
82 S_028410_ALPHA_TEST_BYPASS(a->bypass));
83 r600_write_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref);
84 }
85
86 static void r600_texture_barrier(struct pipe_context *ctx)
87 {
88 struct r600_context *rctx = (struct r600_context *)ctx;
89
90 rctx->flags |= R600_CONTEXT_CB_FLUSH | R600_CONTEXT_TEX_FLUSH;
91
92 /* R6xx errata */
93 if (rctx->chip_class == R600) {
94 rctx->flags |= R600_CONTEXT_FLUSH_AND_INV;
95 }
96 }
97
98 static unsigned r600_conv_pipe_prim(unsigned prim)
99 {
100 static const unsigned prim_conv[] = {
101 V_008958_DI_PT_POINTLIST,
102 V_008958_DI_PT_LINELIST,
103 V_008958_DI_PT_LINELOOP,
104 V_008958_DI_PT_LINESTRIP,
105 V_008958_DI_PT_TRILIST,
106 V_008958_DI_PT_TRISTRIP,
107 V_008958_DI_PT_TRIFAN,
108 V_008958_DI_PT_QUADLIST,
109 V_008958_DI_PT_QUADSTRIP,
110 V_008958_DI_PT_POLYGON,
111 V_008958_DI_PT_LINELIST_ADJ,
112 V_008958_DI_PT_LINESTRIP_ADJ,
113 V_008958_DI_PT_TRILIST_ADJ,
114 V_008958_DI_PT_TRISTRIP_ADJ,
115 V_008958_DI_PT_RECTLIST
116 };
117 return prim_conv[prim];
118 }
119
120 /* common state between evergreen and r600 */
121
122 static void r600_bind_blend_state_internal(struct r600_context *rctx,
123 struct r600_blend_state *blend, bool blend_disable)
124 {
125 unsigned color_control;
126 bool update_cb = false;
127
128 rctx->alpha_to_one = blend->alpha_to_one;
129 rctx->dual_src_blend = blend->dual_src_blend;
130
131 if (!blend_disable) {
132 r600_set_cso_state_with_cb(&rctx->blend_state, blend, &blend->buffer);
133 color_control = blend->cb_color_control;
134 } else {
135 /* Blending is disabled. */
136 r600_set_cso_state_with_cb(&rctx->blend_state, blend, &blend->buffer_no_blend);
137 color_control = blend->cb_color_control_no_blend;
138 }
139
140 /* Update derived states. */
141 if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) {
142 rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
143 update_cb = true;
144 }
145 if (rctx->chip_class <= R700 &&
146 rctx->cb_misc_state.cb_color_control != color_control) {
147 rctx->cb_misc_state.cb_color_control = color_control;
148 update_cb = true;
149 }
150 if (rctx->cb_misc_state.dual_src_blend != blend->dual_src_blend) {
151 rctx->cb_misc_state.dual_src_blend = blend->dual_src_blend;
152 update_cb = true;
153 }
154 if (update_cb) {
155 rctx->cb_misc_state.atom.dirty = true;
156 }
157 }
158
159 static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
160 {
161 struct r600_context *rctx = (struct r600_context *)ctx;
162 struct r600_blend_state *blend = (struct r600_blend_state *)state;
163
164 if (blend == NULL)
165 return;
166
167 r600_bind_blend_state_internal(rctx, blend, rctx->force_blend_disable);
168 }
169
170 static void r600_set_blend_color(struct pipe_context *ctx,
171 const struct pipe_blend_color *state)
172 {
173 struct r600_context *rctx = (struct r600_context *)ctx;
174
175 rctx->blend_color.state = *state;
176 rctx->blend_color.atom.dirty = true;
177 }
178
179 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom)
180 {
181 struct radeon_winsys_cs *cs = rctx->cs;
182 struct pipe_blend_color *state = &rctx->blend_color.state;
183
184 r600_write_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
185 r600_write_value(cs, fui(state->color[0])); /* R_028414_CB_BLEND_RED */
186 r600_write_value(cs, fui(state->color[1])); /* R_028418_CB_BLEND_GREEN */
187 r600_write_value(cs, fui(state->color[2])); /* R_02841C_CB_BLEND_BLUE */
188 r600_write_value(cs, fui(state->color[3])); /* R_028420_CB_BLEND_ALPHA */
189 }
190
191 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom)
192 {
193 struct radeon_winsys_cs *cs = rctx->cs;
194 struct r600_vgt_state *a = (struct r600_vgt_state *)atom;
195
196 r600_write_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, a->vgt_multi_prim_ib_reset_en);
197 r600_write_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, a->vgt_multi_prim_ib_reset_indx);
198 }
199
200 void r600_emit_vgt2_state(struct r600_context *rctx, struct r600_atom *atom)
201 {
202 struct radeon_winsys_cs *cs = rctx->cs;
203 struct r600_vgt2_state *a = (struct r600_vgt2_state *)atom;
204
205 r600_write_context_reg(cs, R_028408_VGT_INDX_OFFSET, a->vgt_indx_offset);
206 }
207
208 static void r600_set_clip_state(struct pipe_context *ctx,
209 const struct pipe_clip_state *state)
210 {
211 struct r600_context *rctx = (struct r600_context *)ctx;
212 struct pipe_constant_buffer cb;
213
214 rctx->clip_state.state = *state;
215 rctx->clip_state.atom.dirty = true;
216
217 cb.buffer = NULL;
218 cb.user_buffer = state->ucp;
219 cb.buffer_offset = 0;
220 cb.buffer_size = 4*4*8;
221 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, R600_UCP_CONST_BUFFER, &cb);
222 pipe_resource_reference(&cb.buffer, NULL);
223 }
224
225 static void r600_set_stencil_ref(struct pipe_context *ctx,
226 const struct r600_stencil_ref *state)
227 {
228 struct r600_context *rctx = (struct r600_context *)ctx;
229
230 rctx->stencil_ref.state = *state;
231 rctx->stencil_ref.atom.dirty = true;
232 }
233
234 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom)
235 {
236 struct radeon_winsys_cs *cs = rctx->cs;
237 struct r600_stencil_ref_state *a = (struct r600_stencil_ref_state*)atom;
238
239 r600_write_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
240 r600_write_value(cs, /* R_028430_DB_STENCILREFMASK */
241 S_028430_STENCILREF(a->state.ref_value[0]) |
242 S_028430_STENCILMASK(a->state.valuemask[0]) |
243 S_028430_STENCILWRITEMASK(a->state.writemask[0]));
244 r600_write_value(cs, /* R_028434_DB_STENCILREFMASK_BF */
245 S_028434_STENCILREF_BF(a->state.ref_value[1]) |
246 S_028434_STENCILMASK_BF(a->state.valuemask[1]) |
247 S_028434_STENCILWRITEMASK_BF(a->state.writemask[1]));
248 }
249
250 static void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
251 const struct pipe_stencil_ref *state)
252 {
253 struct r600_context *rctx = (struct r600_context *)ctx;
254 struct r600_dsa_state *dsa = (struct r600_dsa_state*)rctx->dsa_state.cso;
255 struct r600_stencil_ref ref;
256
257 rctx->stencil_ref.pipe_state = *state;
258
259 if (!dsa)
260 return;
261
262 ref.ref_value[0] = state->ref_value[0];
263 ref.ref_value[1] = state->ref_value[1];
264 ref.valuemask[0] = dsa->valuemask[0];
265 ref.valuemask[1] = dsa->valuemask[1];
266 ref.writemask[0] = dsa->writemask[0];
267 ref.writemask[1] = dsa->writemask[1];
268
269 r600_set_stencil_ref(ctx, &ref);
270 }
271
272 static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
273 {
274 struct r600_context *rctx = (struct r600_context *)ctx;
275 struct r600_dsa_state *dsa = state;
276 struct r600_stencil_ref ref;
277
278 if (state == NULL)
279 return;
280
281 r600_set_cso_state_with_cb(&rctx->dsa_state, dsa, &dsa->buffer);
282
283 ref.ref_value[0] = rctx->stencil_ref.pipe_state.ref_value[0];
284 ref.ref_value[1] = rctx->stencil_ref.pipe_state.ref_value[1];
285 ref.valuemask[0] = dsa->valuemask[0];
286 ref.valuemask[1] = dsa->valuemask[1];
287 ref.writemask[0] = dsa->writemask[0];
288 ref.writemask[1] = dsa->writemask[1];
289
290 r600_set_stencil_ref(ctx, &ref);
291
292 /* Update alphatest state. */
293 if (rctx->alphatest_state.sx_alpha_test_control != dsa->sx_alpha_test_control ||
294 rctx->alphatest_state.sx_alpha_ref != dsa->alpha_ref) {
295 rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control;
296 rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref;
297 rctx->alphatest_state.atom.dirty = true;
298 }
299 }
300
301 static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
302 {
303 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
304 struct r600_context *rctx = (struct r600_context *)ctx;
305
306 if (state == NULL)
307 return;
308
309 rctx->rasterizer = rs;
310
311 r600_set_cso_state_with_cb(&rctx->rasterizer_state, rs, &rs->buffer);
312
313 if (rs->offset_enable &&
314 (rs->offset_units != rctx->poly_offset_state.offset_units ||
315 rs->offset_scale != rctx->poly_offset_state.offset_scale)) {
316 rctx->poly_offset_state.offset_units = rs->offset_units;
317 rctx->poly_offset_state.offset_scale = rs->offset_scale;
318 rctx->poly_offset_state.atom.dirty = true;
319 }
320
321 /* Update clip_misc_state. */
322 if (rctx->clip_misc_state.pa_cl_clip_cntl != rs->pa_cl_clip_cntl ||
323 rctx->clip_misc_state.clip_plane_enable != rs->clip_plane_enable) {
324 rctx->clip_misc_state.pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
325 rctx->clip_misc_state.clip_plane_enable = rs->clip_plane_enable;
326 rctx->clip_misc_state.atom.dirty = true;
327 }
328
329 /* Workaround for a missing scissor enable on r600. */
330 if (rctx->chip_class == R600 &&
331 rs->scissor_enable != rctx->scissor.enable) {
332 rctx->scissor.enable = rs->scissor_enable;
333 rctx->scissor.atom.dirty = true;
334 }
335
336 /* Re-emit PA_SC_LINE_STIPPLE. */
337 rctx->last_primitive_type = -1;
338 }
339
340 static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
341 {
342 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
343
344 r600_release_command_buffer(&rs->buffer);
345 FREE(rs);
346 }
347
348 static void r600_sampler_view_destroy(struct pipe_context *ctx,
349 struct pipe_sampler_view *state)
350 {
351 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
352
353 pipe_resource_reference(&state->texture, NULL);
354 FREE(resource);
355 }
356
357 void r600_sampler_states_dirty(struct r600_context *rctx,
358 struct r600_sampler_states *state)
359 {
360 if (state->dirty_mask) {
361 if (state->dirty_mask & state->has_bordercolor_mask) {
362 rctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
363 }
364 state->atom.num_dw =
365 util_bitcount(state->dirty_mask & state->has_bordercolor_mask) * 11 +
366 util_bitcount(state->dirty_mask & ~state->has_bordercolor_mask) * 5;
367 state->atom.dirty = true;
368 }
369 }
370
371 static void r600_bind_sampler_states(struct pipe_context *pipe,
372 unsigned shader,
373 unsigned start,
374 unsigned count, void **states)
375 {
376 struct r600_context *rctx = (struct r600_context *)pipe;
377 struct r600_textures_info *dst = &rctx->samplers[shader];
378 struct r600_pipe_sampler_state **rstates = (struct r600_pipe_sampler_state**)states;
379 int seamless_cube_map = -1;
380 unsigned i;
381 /* This sets 1-bit for states with index >= count. */
382 uint32_t disable_mask = ~((1ull << count) - 1);
383 /* These are the new states set by this function. */
384 uint32_t new_mask = 0;
385
386 assert(start == 0); /* XXX fix below */
387
388 for (i = 0; i < count; i++) {
389 struct r600_pipe_sampler_state *rstate = rstates[i];
390
391 if (rstate == dst->states.states[i]) {
392 continue;
393 }
394
395 if (rstate) {
396 if (rstate->border_color_use) {
397 dst->states.has_bordercolor_mask |= 1 << i;
398 } else {
399 dst->states.has_bordercolor_mask &= ~(1 << i);
400 }
401 seamless_cube_map = rstate->seamless_cube_map;
402
403 new_mask |= 1 << i;
404 } else {
405 disable_mask |= 1 << i;
406 }
407 }
408
409 memcpy(dst->states.states, rstates, sizeof(void*) * count);
410 memset(dst->states.states + count, 0, sizeof(void*) * (NUM_TEX_UNITS - count));
411
412 dst->states.enabled_mask &= ~disable_mask;
413 dst->states.dirty_mask &= dst->states.enabled_mask;
414 dst->states.enabled_mask |= new_mask;
415 dst->states.dirty_mask |= new_mask;
416 dst->states.has_bordercolor_mask &= dst->states.enabled_mask;
417
418 r600_sampler_states_dirty(rctx, &dst->states);
419
420 /* Seamless cubemap state. */
421 if (rctx->chip_class <= R700 &&
422 seamless_cube_map != -1 &&
423 seamless_cube_map != rctx->seamless_cube_map.enabled) {
424 /* change in TA_CNTL_AUX need a pipeline flush */
425 rctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
426 rctx->seamless_cube_map.enabled = seamless_cube_map;
427 rctx->seamless_cube_map.atom.dirty = true;
428 }
429 }
430
431 static void r600_bind_vs_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
432 {
433 r600_bind_sampler_states(ctx, PIPE_SHADER_VERTEX, 0, count, states);
434 }
435
436 static void r600_bind_ps_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
437 {
438 r600_bind_sampler_states(ctx, PIPE_SHADER_FRAGMENT, 0, count, states);
439 }
440
441 static void r600_delete_sampler_state(struct pipe_context *ctx, void *state)
442 {
443 free(state);
444 }
445
446 static void r600_delete_blend_state(struct pipe_context *ctx, void *state)
447 {
448 struct r600_blend_state *blend = (struct r600_blend_state*)state;
449
450 r600_release_command_buffer(&blend->buffer);
451 r600_release_command_buffer(&blend->buffer_no_blend);
452 FREE(blend);
453 }
454
455 static void r600_delete_dsa_state(struct pipe_context *ctx, void *state)
456 {
457 struct r600_dsa_state *dsa = (struct r600_dsa_state *)state;
458
459 r600_release_command_buffer(&dsa->buffer);
460 free(dsa);
461 }
462
463 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
464 {
465 struct r600_context *rctx = (struct r600_context *)ctx;
466
467 r600_set_cso_state(&rctx->vertex_fetch_shader, state);
468 }
469
470 static void r600_delete_vertex_elements(struct pipe_context *ctx, void *state)
471 {
472 pipe_resource_reference((struct pipe_resource**)&state, NULL);
473 }
474
475 static void r600_set_index_buffer(struct pipe_context *ctx,
476 const struct pipe_index_buffer *ib)
477 {
478 struct r600_context *rctx = (struct r600_context *)ctx;
479
480 if (ib) {
481 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
482 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
483 } else {
484 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
485 }
486 }
487
488 void r600_vertex_buffers_dirty(struct r600_context *rctx)
489 {
490 if (rctx->vertex_buffer_state.dirty_mask) {
491 rctx->flags |= rctx->has_vertex_cache ? R600_CONTEXT_VTX_FLUSH : R600_CONTEXT_TEX_FLUSH;
492 rctx->vertex_buffer_state.atom.num_dw = (rctx->chip_class >= EVERGREEN ? 12 : 11) *
493 util_bitcount(rctx->vertex_buffer_state.dirty_mask);
494 rctx->vertex_buffer_state.atom.dirty = true;
495 }
496 }
497
498 static void r600_set_vertex_buffers(struct pipe_context *ctx,
499 unsigned start_slot, unsigned count,
500 const struct pipe_vertex_buffer *input)
501 {
502 struct r600_context *rctx = (struct r600_context *)ctx;
503 struct r600_vertexbuf_state *state = &rctx->vertex_buffer_state;
504 struct pipe_vertex_buffer *vb = state->vb + start_slot;
505 unsigned i;
506 uint32_t disable_mask = 0;
507 /* These are the new buffers set by this function. */
508 uint32_t new_buffer_mask = 0;
509
510 /* Set vertex buffers. */
511 if (input) {
512 for (i = 0; i < count; i++) {
513 if (memcmp(&input[i], &vb[i], sizeof(struct pipe_vertex_buffer))) {
514 if (input[i].buffer) {
515 vb[i].stride = input[i].stride;
516 vb[i].buffer_offset = input[i].buffer_offset;
517 pipe_resource_reference(&vb[i].buffer, input[i].buffer);
518 new_buffer_mask |= 1 << i;
519 } else {
520 pipe_resource_reference(&vb[i].buffer, NULL);
521 disable_mask |= 1 << i;
522 }
523 }
524 }
525 } else {
526 for (i = 0; i < count; i++) {
527 pipe_resource_reference(&vb[i].buffer, NULL);
528 }
529 disable_mask = ((1ull << count) - 1);
530 }
531
532 disable_mask <<= start_slot;
533 new_buffer_mask <<= start_slot;
534
535 rctx->vertex_buffer_state.enabled_mask &= ~disable_mask;
536 rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask;
537 rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask;
538 rctx->vertex_buffer_state.dirty_mask |= new_buffer_mask;
539
540 r600_vertex_buffers_dirty(rctx);
541 }
542
543 void r600_sampler_views_dirty(struct r600_context *rctx,
544 struct r600_samplerview_state *state)
545 {
546 if (state->dirty_mask) {
547 rctx->flags |= R600_CONTEXT_TEX_FLUSH;
548 state->atom.num_dw = (rctx->chip_class >= EVERGREEN ? 14 : 13) *
549 util_bitcount(state->dirty_mask);
550 state->atom.dirty = true;
551 }
552 }
553
554 static void r600_set_sampler_views(struct pipe_context *pipe, unsigned shader,
555 unsigned start, unsigned count,
556 struct pipe_sampler_view **views)
557 {
558 struct r600_context *rctx = (struct r600_context *) pipe;
559 struct r600_textures_info *dst = &rctx->samplers[shader];
560 struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
561 uint32_t dirty_sampler_states_mask = 0;
562 unsigned i;
563 /* This sets 1-bit for textures with index >= count. */
564 uint32_t disable_mask = ~((1ull << count) - 1);
565 /* These are the new textures set by this function. */
566 uint32_t new_mask = 0;
567
568 /* Set textures with index >= count to NULL. */
569 uint32_t remaining_mask;
570
571 assert(start == 0); /* XXX fix below */
572
573 remaining_mask = dst->views.enabled_mask & disable_mask;
574
575 while (remaining_mask) {
576 i = u_bit_scan(&remaining_mask);
577 assert(dst->views.views[i]);
578
579 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
580 }
581
582 for (i = 0; i < count; i++) {
583 if (rviews[i] == dst->views.views[i]) {
584 continue;
585 }
586
587 if (rviews[i]) {
588 struct r600_texture *rtex =
589 (struct r600_texture*)rviews[i]->base.texture;
590
591 if (rtex->is_depth && !rtex->is_flushing_texture) {
592 dst->views.compressed_depthtex_mask |= 1 << i;
593 } else {
594 dst->views.compressed_depthtex_mask &= ~(1 << i);
595 }
596
597 /* Track compressed colorbuffers. */
598 if (rtex->cmask_size && rtex->fmask_size) {
599 dst->views.compressed_colortex_mask |= 1 << i;
600 } else {
601 dst->views.compressed_colortex_mask &= ~(1 << i);
602 }
603
604 /* Changing from array to non-arrays textures and vice versa requires
605 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
606 if (rctx->chip_class <= R700 &&
607 (dst->states.enabled_mask & (1 << i)) &&
608 (rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
609 rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) {
610 dirty_sampler_states_mask |= 1 << i;
611 }
612
613 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]);
614 new_mask |= 1 << i;
615 } else {
616 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
617 disable_mask |= 1 << i;
618 }
619 }
620
621 dst->views.enabled_mask &= ~disable_mask;
622 dst->views.dirty_mask &= dst->views.enabled_mask;
623 dst->views.enabled_mask |= new_mask;
624 dst->views.dirty_mask |= new_mask;
625 dst->views.compressed_depthtex_mask &= dst->views.enabled_mask;
626 dst->views.compressed_colortex_mask &= dst->views.enabled_mask;
627
628 r600_sampler_views_dirty(rctx, &dst->views);
629
630 if (dirty_sampler_states_mask) {
631 dst->states.dirty_mask |= dirty_sampler_states_mask;
632 r600_sampler_states_dirty(rctx, &dst->states);
633 }
634 }
635
636 static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
637 struct pipe_sampler_view **views)
638 {
639 r600_set_sampler_views(ctx, PIPE_SHADER_VERTEX, 0, count, views);
640 }
641
642 static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
643 struct pipe_sampler_view **views)
644 {
645 r600_set_sampler_views(ctx, PIPE_SHADER_FRAGMENT, 0, count, views);
646 }
647
648 static void r600_set_viewport_state(struct pipe_context *ctx,
649 const struct pipe_viewport_state *state)
650 {
651 struct r600_context *rctx = (struct r600_context *)ctx;
652
653 rctx->viewport.state = *state;
654 rctx->viewport.atom.dirty = true;
655 }
656
657 void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom)
658 {
659 struct radeon_winsys_cs *cs = rctx->cs;
660 struct pipe_viewport_state *state = &rctx->viewport.state;
661
662 r600_write_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE_0, 6);
663 r600_write_value(cs, fui(state->scale[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
664 r600_write_value(cs, fui(state->translate[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
665 r600_write_value(cs, fui(state->scale[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
666 r600_write_value(cs, fui(state->translate[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
667 r600_write_value(cs, fui(state->scale[2])); /* R_02844C_PA_CL_VPORT_ZSCALE_0 */
668 r600_write_value(cs, fui(state->translate[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
669 }
670
671 /* Compute the key for the hw shader variant */
672 static INLINE struct r600_shader_key r600_shader_selector_key(struct pipe_context * ctx,
673 struct r600_pipe_shader_selector * sel)
674 {
675 struct r600_context *rctx = (struct r600_context *)ctx;
676 struct r600_shader_key key;
677 memset(&key, 0, sizeof(key));
678
679 if (sel->type == PIPE_SHADER_FRAGMENT) {
680 key.color_two_side = rctx->rasterizer && rctx->rasterizer->two_side;
681 key.alpha_to_one = rctx->alpha_to_one &&
682 rctx->rasterizer && rctx->rasterizer->multisample_enable &&
683 !rctx->framebuffer.cb0_is_integer;
684 key.nr_cbufs = rctx->framebuffer.state.nr_cbufs;
685 /* Dual-source blending only makes sense with nr_cbufs == 1. */
686 if (key.nr_cbufs == 1 && rctx->dual_src_blend)
687 key.nr_cbufs = 2;
688 }
689 return key;
690 }
691
692 /* Select the hw shader variant depending on the current state.
693 * (*dirty) is set to 1 if current variant was changed */
694 static int r600_shader_select(struct pipe_context *ctx,
695 struct r600_pipe_shader_selector* sel,
696 unsigned *dirty)
697 {
698 struct r600_shader_key key;
699 struct r600_context *rctx = (struct r600_context *)ctx;
700 struct r600_pipe_shader * shader = NULL;
701 int r;
702
703 key = r600_shader_selector_key(ctx, sel);
704
705 /* Check if we don't need to change anything.
706 * This path is also used for most shaders that don't need multiple
707 * variants, it will cost just a computation of the key and this
708 * test. */
709 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
710 return 0;
711 }
712
713 /* lookup if we have other variants in the list */
714 if (sel->num_shaders > 1) {
715 struct r600_pipe_shader *p = sel->current, *c = p->next_variant;
716
717 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
718 p = c;
719 c = c->next_variant;
720 }
721
722 if (c) {
723 p->next_variant = c->next_variant;
724 shader = c;
725 }
726 }
727
728 if (unlikely(!shader)) {
729 shader = CALLOC(1, sizeof(struct r600_pipe_shader));
730 shader->selector = sel;
731
732 r = r600_pipe_shader_create(ctx, shader, key);
733 if (unlikely(r)) {
734 R600_ERR("Failed to build shader variant (type=%u) %d\n",
735 sel->type, r);
736 sel->current = NULL;
737 return r;
738 }
739
740 /* We don't know the value of nr_ps_max_color_exports until we built
741 * at least one variant, so we may need to recompute the key after
742 * building first variant. */
743 if (sel->type == PIPE_SHADER_FRAGMENT &&
744 sel->num_shaders == 0) {
745 sel->nr_ps_max_color_exports = shader->shader.nr_ps_max_color_exports;
746 key = r600_shader_selector_key(ctx, sel);
747 }
748
749 shader->key = key;
750 sel->num_shaders++;
751 }
752
753 if (dirty)
754 *dirty = 1;
755
756 shader->next_variant = sel->current;
757 sel->current = shader;
758
759 if (rctx->ps_shader &&
760 rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
761 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
762 rctx->cb_misc_state.atom.dirty = true;
763 }
764 return 0;
765 }
766
767 static void *r600_create_shader_state(struct pipe_context *ctx,
768 const struct pipe_shader_state *state,
769 unsigned pipe_shader_type)
770 {
771 struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector);
772 int r;
773
774 sel->type = pipe_shader_type;
775 sel->tokens = tgsi_dup_tokens(state->tokens);
776 sel->so = state->stream_output;
777
778 r = r600_shader_select(ctx, sel, NULL);
779 if (r)
780 return NULL;
781
782 return sel;
783 }
784
785 static void *r600_create_ps_state(struct pipe_context *ctx,
786 const struct pipe_shader_state *state)
787 {
788 return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
789 }
790
791 static void *r600_create_vs_state(struct pipe_context *ctx,
792 const struct pipe_shader_state *state)
793 {
794 return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
795 }
796
797 static void r600_bind_ps_state(struct pipe_context *ctx, void *state)
798 {
799 struct r600_context *rctx = (struct r600_context *)ctx;
800
801 if (!state)
802 state = rctx->dummy_pixel_shader;
803
804 rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
805 r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
806
807 if (rctx->chip_class <= R700) {
808 bool multiwrite = rctx->ps_shader->current->shader.fs_write_all;
809
810 if (rctx->cb_misc_state.multiwrite != multiwrite) {
811 rctx->cb_misc_state.multiwrite = multiwrite;
812 rctx->cb_misc_state.atom.dirty = true;
813 }
814 }
815
816 if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
817 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
818 rctx->cb_misc_state.atom.dirty = true;
819 }
820
821 if (rctx->chip_class >= EVERGREEN) {
822 evergreen_update_db_shader_control(rctx);
823 } else {
824 r600_update_db_shader_control(rctx);
825 }
826 }
827
828 static void r600_bind_vs_state(struct pipe_context *ctx, void *state)
829 {
830 struct r600_context *rctx = (struct r600_context *)ctx;
831
832 rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
833 if (state) {
834 r600_context_pipe_state_set(rctx, &rctx->vs_shader->current->rstate);
835
836 /* Update clip misc state. */
837 if (rctx->vs_shader->current->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
838 rctx->vs_shader->current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write) {
839 rctx->clip_misc_state.pa_cl_vs_out_cntl = rctx->vs_shader->current->pa_cl_vs_out_cntl;
840 rctx->clip_misc_state.clip_dist_write = rctx->vs_shader->current->shader.clip_dist_write;
841 rctx->clip_misc_state.atom.dirty = true;
842 }
843 }
844 }
845
846 static void r600_delete_shader_selector(struct pipe_context *ctx,
847 struct r600_pipe_shader_selector *sel)
848 {
849 struct r600_pipe_shader *p = sel->current, *c;
850 while (p) {
851 c = p->next_variant;
852 r600_pipe_shader_destroy(ctx, p);
853 free(p);
854 p = c;
855 }
856
857 free(sel->tokens);
858 free(sel);
859 }
860
861
862 static void r600_delete_ps_state(struct pipe_context *ctx, void *state)
863 {
864 struct r600_context *rctx = (struct r600_context *)ctx;
865 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
866
867 if (rctx->ps_shader == sel) {
868 rctx->ps_shader = NULL;
869 }
870
871 r600_delete_shader_selector(ctx, sel);
872 }
873
874 static void r600_delete_vs_state(struct pipe_context *ctx, void *state)
875 {
876 struct r600_context *rctx = (struct r600_context *)ctx;
877 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
878
879 if (rctx->vs_shader == sel) {
880 rctx->vs_shader = NULL;
881 }
882
883 r600_delete_shader_selector(ctx, sel);
884 }
885
886 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
887 {
888 if (state->dirty_mask) {
889 rctx->flags |= R600_CONTEXT_SHADERCONST_FLUSH;
890 state->atom.num_dw = rctx->chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
891 : util_bitcount(state->dirty_mask)*19;
892 state->atom.dirty = true;
893 }
894 }
895
896 static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
897 struct pipe_constant_buffer *input)
898 {
899 struct r600_context *rctx = (struct r600_context *)ctx;
900 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
901 struct pipe_constant_buffer *cb;
902 const uint8_t *ptr;
903
904 /* Note that the state tracker can unbind constant buffers by
905 * passing NULL here.
906 */
907 if (unlikely(!input)) {
908 state->enabled_mask &= ~(1 << index);
909 state->dirty_mask &= ~(1 << index);
910 pipe_resource_reference(&state->cb[index].buffer, NULL);
911 return;
912 }
913
914 cb = &state->cb[index];
915 cb->buffer_size = input->buffer_size;
916
917 ptr = input->user_buffer;
918
919 if (ptr) {
920 /* Upload the user buffer. */
921 if (R600_BIG_ENDIAN) {
922 uint32_t *tmpPtr;
923 unsigned i, size = input->buffer_size;
924
925 if (!(tmpPtr = malloc(size))) {
926 R600_ERR("Failed to allocate BE swap buffer.\n");
927 return;
928 }
929
930 for (i = 0; i < size / 4; ++i) {
931 tmpPtr[i] = bswap_32(((uint32_t *)ptr)[i]);
932 }
933
934 u_upload_data(rctx->uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer);
935 free(tmpPtr);
936 } else {
937 u_upload_data(rctx->uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer);
938 }
939 } else {
940 /* Setup the hw buffer. */
941 cb->buffer_offset = input->buffer_offset;
942 pipe_resource_reference(&cb->buffer, input->buffer);
943 }
944
945 state->enabled_mask |= 1 << index;
946 state->dirty_mask |= 1 << index;
947 r600_constant_buffers_dirty(rctx, state);
948 }
949
950 static struct pipe_stream_output_target *
951 r600_create_so_target(struct pipe_context *ctx,
952 struct pipe_resource *buffer,
953 unsigned buffer_offset,
954 unsigned buffer_size)
955 {
956 struct r600_context *rctx = (struct r600_context *)ctx;
957 struct r600_so_target *t;
958 void *ptr;
959
960 t = CALLOC_STRUCT(r600_so_target);
961 if (!t) {
962 return NULL;
963 }
964
965 t->b.reference.count = 1;
966 t->b.context = ctx;
967 pipe_resource_reference(&t->b.buffer, buffer);
968 t->b.buffer_offset = buffer_offset;
969 t->b.buffer_size = buffer_size;
970
971 t->filled_size = (struct r600_resource*)
972 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4);
973 ptr = rctx->ws->buffer_map(t->filled_size->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
974 memset(ptr, 0, t->filled_size->buf->size);
975 rctx->ws->buffer_unmap(t->filled_size->cs_buf);
976
977 return &t->b;
978 }
979
980 static void r600_so_target_destroy(struct pipe_context *ctx,
981 struct pipe_stream_output_target *target)
982 {
983 struct r600_so_target *t = (struct r600_so_target*)target;
984 pipe_resource_reference(&t->b.buffer, NULL);
985 pipe_resource_reference((struct pipe_resource**)&t->filled_size, NULL);
986 FREE(t);
987 }
988
989 static void r600_set_so_targets(struct pipe_context *ctx,
990 unsigned num_targets,
991 struct pipe_stream_output_target **targets,
992 unsigned append_bitmask)
993 {
994 struct r600_context *rctx = (struct r600_context *)ctx;
995 unsigned i;
996
997 /* Stop streamout. */
998 if (rctx->num_so_targets && !rctx->streamout_start) {
999 r600_context_streamout_end(rctx);
1000 }
1001
1002 /* Set the new targets. */
1003 for (i = 0; i < num_targets; i++) {
1004 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]);
1005 }
1006 for (; i < rctx->num_so_targets; i++) {
1007 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL);
1008 }
1009
1010 rctx->num_so_targets = num_targets;
1011 rctx->streamout_start = num_targets != 0;
1012 rctx->streamout_append_bitmask = append_bitmask;
1013 }
1014
1015 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1016 {
1017 struct r600_context *rctx = (struct r600_context*)pipe;
1018
1019 if (rctx->sample_mask.sample_mask == (uint16_t)sample_mask)
1020 return;
1021
1022 rctx->sample_mask.sample_mask = sample_mask;
1023 rctx->sample_mask.atom.dirty = true;
1024 }
1025
1026 static bool r600_update_derived_state(struct r600_context *rctx)
1027 {
1028 struct pipe_context * ctx = (struct pipe_context*)rctx;
1029 unsigned ps_dirty = 0;
1030 bool blend_disable;
1031
1032 if (!rctx->blitter->running) {
1033 unsigned i;
1034
1035 /* Decompress textures if needed. */
1036 for (i = 0; i < PIPE_SHADER_TYPES; i++) {
1037 struct r600_samplerview_state *views = &rctx->samplers[i].views;
1038 if (views->compressed_depthtex_mask) {
1039 r600_decompress_depth_textures(rctx, views);
1040 }
1041 if (views->compressed_colortex_mask) {
1042 r600_decompress_color_textures(rctx, views);
1043 }
1044 }
1045 }
1046
1047 r600_shader_select(ctx, rctx->ps_shader, &ps_dirty);
1048
1049 if (rctx->ps_shader && rctx->rasterizer &&
1050 ((rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable) ||
1051 (rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade))) {
1052
1053 if (rctx->chip_class >= EVERGREEN)
1054 evergreen_pipe_shader_ps(ctx, rctx->ps_shader->current);
1055 else
1056 r600_pipe_shader_ps(ctx, rctx->ps_shader->current);
1057
1058 ps_dirty = 1;
1059 }
1060
1061 if (ps_dirty)
1062 r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
1063
1064 if (rctx->chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
1065 if (!r600_adjust_gprs(rctx)) {
1066 /* discard rendering */
1067 return false;
1068 }
1069 }
1070
1071 blend_disable = (rctx->dual_src_blend &&
1072 rctx->ps_shader->current->nr_ps_color_outputs < 2);
1073
1074 if (blend_disable != rctx->force_blend_disable) {
1075 rctx->force_blend_disable = blend_disable;
1076 r600_bind_blend_state_internal(rctx,
1077 rctx->blend_state.cso,
1078 blend_disable);
1079 }
1080 return true;
1081 }
1082
1083 static unsigned r600_conv_prim_to_gs_out(unsigned mode)
1084 {
1085 static const int prim_conv[] = {
1086 V_028A6C_OUTPRIM_TYPE_POINTLIST,
1087 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1088 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1089 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1090 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1091 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1092 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1093 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1094 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1095 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1096 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1097 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1098 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1099 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1100 V_028A6C_OUTPRIM_TYPE_TRISTRIP
1101 };
1102 assert(mode < Elements(prim_conv));
1103
1104 return prim_conv[mode];
1105 }
1106
1107 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1108 {
1109 struct radeon_winsys_cs *cs = rctx->cs;
1110 struct r600_clip_misc_state *state = &rctx->clip_misc_state;
1111
1112 r600_write_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
1113 state->pa_cl_clip_cntl |
1114 (state->clip_dist_write ? 0 : state->clip_plane_enable & 0x3F));
1115 r600_write_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
1116 state->pa_cl_vs_out_cntl |
1117 (state->clip_plane_enable & state->clip_dist_write));
1118 }
1119
1120 static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
1121 {
1122 struct r600_context *rctx = (struct r600_context *)ctx;
1123 struct pipe_draw_info info = *dinfo;
1124 struct pipe_index_buffer ib = {};
1125 unsigned i;
1126 struct r600_block *dirty_block = NULL, *next_block = NULL;
1127 struct radeon_winsys_cs *cs = rctx->cs;
1128
1129 if (!info.count && (info.indexed || !info.count_from_stream_output)) {
1130 assert(0);
1131 return;
1132 }
1133
1134 if (!rctx->vs_shader) {
1135 assert(0);
1136 return;
1137 }
1138
1139 if (!r600_update_derived_state(rctx)) {
1140 /* useless to render because current rendering command
1141 * can't be achieved
1142 */
1143 return;
1144 }
1145
1146 if (info.indexed) {
1147 /* Initialize the index buffer struct. */
1148 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
1149 ib.user_buffer = rctx->index_buffer.user_buffer;
1150 ib.index_size = rctx->index_buffer.index_size;
1151 ib.offset = rctx->index_buffer.offset + info.start * ib.index_size;
1152
1153 /* Translate 8-bit indices to 16-bit. */
1154 if (ib.index_size == 1) {
1155 struct pipe_resource *out_buffer = NULL;
1156 unsigned out_offset;
1157 void *ptr;
1158
1159 u_upload_alloc(rctx->uploader, 0, info.count * 2,
1160 &out_offset, &out_buffer, &ptr);
1161
1162 util_shorten_ubyte_elts_to_userptr(
1163 &rctx->context, &ib, 0, ib.offset, info.count, ptr);
1164
1165 pipe_resource_reference(&ib.buffer, NULL);
1166 ib.user_buffer = NULL;
1167 ib.buffer = out_buffer;
1168 ib.offset = out_offset;
1169 ib.index_size = 2;
1170 }
1171
1172 /* Upload the index buffer.
1173 * The upload is skipped for small index counts on little-endian machines
1174 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
1175 * Note: Instanced rendering in combination with immediate indices hangs. */
1176 if (ib.user_buffer && (R600_BIG_ENDIAN || info.instance_count > 1 ||
1177 info.count*ib.index_size > 20)) {
1178 u_upload_data(rctx->uploader, 0, info.count * ib.index_size,
1179 ib.user_buffer, &ib.offset, &ib.buffer);
1180 ib.user_buffer = NULL;
1181 }
1182 } else {
1183 info.index_bias = info.start;
1184 }
1185
1186 /* Enable stream out if needed. */
1187 if (rctx->streamout_start) {
1188 r600_context_streamout_begin(rctx);
1189 rctx->streamout_start = FALSE;
1190 }
1191
1192 /* Set the index offset and multi primitive */
1193 if (rctx->vgt2_state.vgt_indx_offset != info.index_bias) {
1194 rctx->vgt2_state.vgt_indx_offset = info.index_bias;
1195 rctx->vgt2_state.atom.dirty = true;
1196 }
1197 if (rctx->vgt_state.vgt_multi_prim_ib_reset_en != info.primitive_restart ||
1198 rctx->vgt_state.vgt_multi_prim_ib_reset_indx != info.restart_index) {
1199 rctx->vgt_state.vgt_multi_prim_ib_reset_en = info.primitive_restart;
1200 rctx->vgt_state.vgt_multi_prim_ib_reset_indx = info.restart_index;
1201 rctx->vgt_state.atom.dirty = true;
1202 }
1203
1204 /* Emit states. */
1205 r600_need_cs_space(rctx, ib.user_buffer ? 5 : 0, TRUE);
1206 r600_flush_emit(rctx);
1207
1208 for (i = 0; i < R600_NUM_ATOMS; i++) {
1209 if (rctx->atoms[i] == NULL || !rctx->atoms[i]->dirty) {
1210 continue;
1211 }
1212 r600_emit_atom(rctx, rctx->atoms[i]);
1213 }
1214 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) {
1215 r600_context_block_emit_dirty(rctx, dirty_block, 0 /* pkt_flags */);
1216 }
1217 rctx->pm4_dirty_cdwords = 0;
1218
1219 /* Update start instance. */
1220 if (rctx->last_start_instance != info.start_instance) {
1221 r600_write_ctl_const(cs, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
1222 rctx->last_start_instance = info.start_instance;
1223 }
1224
1225 /* Update the primitive type. */
1226 if (rctx->last_primitive_type != info.mode) {
1227 unsigned ls_mask = 0;
1228
1229 if (info.mode == PIPE_PRIM_LINES)
1230 ls_mask = 1;
1231 else if (info.mode == PIPE_PRIM_LINE_STRIP ||
1232 info.mode == PIPE_PRIM_LINE_LOOP)
1233 ls_mask = 2;
1234
1235 r600_write_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
1236 S_028A0C_AUTO_RESET_CNTL(ls_mask) |
1237 (rctx->rasterizer ? rctx->rasterizer->pa_sc_line_stipple : 0));
1238 r600_write_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
1239 r600_conv_prim_to_gs_out(info.mode));
1240 r600_write_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE,
1241 r600_conv_pipe_prim(info.mode));
1242
1243 rctx->last_primitive_type = info.mode;
1244 }
1245
1246 /* Draw packets. */
1247 cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->predicate_drawing);
1248 cs->buf[cs->cdw++] = info.instance_count;
1249 if (info.indexed) {
1250 cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->predicate_drawing);
1251 cs->buf[cs->cdw++] = ib.index_size == 4 ?
1252 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
1253 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
1254
1255 if (ib.user_buffer) {
1256 unsigned size_bytes = info.count*ib.index_size;
1257 unsigned size_dw = align(size_bytes, 4) / 4;
1258 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_IMMD, 1 + size_dw, rctx->predicate_drawing);
1259 cs->buf[cs->cdw++] = info.count;
1260 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_IMMEDIATE;
1261 memcpy(cs->buf+cs->cdw, ib.user_buffer, size_bytes);
1262 cs->cdw += size_dw;
1263 } else {
1264 uint64_t va = r600_resource_va(ctx->screen, ib.buffer) + ib.offset;
1265 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->predicate_drawing);
1266 cs->buf[cs->cdw++] = va;
1267 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
1268 cs->buf[cs->cdw++] = info.count;
1269 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
1270 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->predicate_drawing);
1271 cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
1272 }
1273 } else {
1274 if (info.count_from_stream_output) {
1275 struct r600_so_target *t = (struct r600_so_target*)info.count_from_stream_output;
1276 uint64_t va = r600_resource_va(&rctx->screen->screen, (void*)t->filled_size);
1277
1278 r600_write_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
1279
1280 cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0);
1281 cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG;
1282 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */
1283 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
1284 cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */
1285 cs->buf[cs->cdw++] = 0; /* unused */
1286
1287 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1288 cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, t->filled_size, RADEON_USAGE_READ);
1289 }
1290
1291 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->predicate_drawing);
1292 cs->buf[cs->cdw++] = info.count;
1293 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
1294 (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
1295 }
1296
1297 /* Set the depth buffer as dirty. */
1298 if (rctx->framebuffer.state.zsbuf) {
1299 struct pipe_surface *surf = rctx->framebuffer.state.zsbuf;
1300 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
1301
1302 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1303 }
1304 if (rctx->framebuffer.compressed_cb_mask) {
1305 struct pipe_surface *surf;
1306 struct r600_texture *rtex;
1307 unsigned mask = rctx->framebuffer.compressed_cb_mask;
1308
1309 do {
1310 unsigned i = u_bit_scan(&mask);
1311 surf = rctx->framebuffer.state.cbufs[i];
1312 rtex = (struct r600_texture*)surf->texture;
1313
1314 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1315
1316 } while (mask);
1317 }
1318
1319 pipe_resource_reference(&ib.buffer, NULL);
1320 }
1321
1322 void r600_draw_rectangle(struct blitter_context *blitter,
1323 int x1, int y1, int x2, int y2, float depth,
1324 enum blitter_attrib_type type, const union pipe_color_union *attrib)
1325 {
1326 struct r600_context *rctx = (struct r600_context*)util_blitter_get_pipe(blitter);
1327 struct pipe_viewport_state viewport;
1328 struct pipe_resource *buf = NULL;
1329 unsigned offset = 0;
1330 float *vb;
1331
1332 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
1333 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
1334 return;
1335 }
1336
1337 /* Some operations (like color resolve on r6xx) don't work
1338 * with the conventional primitive types.
1339 * One that works is PT_RECTLIST, which we use here. */
1340
1341 /* setup viewport */
1342 viewport.scale[0] = 1.0f;
1343 viewport.scale[1] = 1.0f;
1344 viewport.scale[2] = 1.0f;
1345 viewport.scale[3] = 1.0f;
1346 viewport.translate[0] = 0.0f;
1347 viewport.translate[1] = 0.0f;
1348 viewport.translate[2] = 0.0f;
1349 viewport.translate[3] = 0.0f;
1350 rctx->context.set_viewport_state(&rctx->context, &viewport);
1351
1352 /* Upload vertices. The hw rectangle has only 3 vertices,
1353 * I guess the 4th one is derived from the first 3.
1354 * The vertex specification should match u_blitter's vertex element state. */
1355 u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, &offset, &buf, (void**)&vb);
1356 vb[0] = x1;
1357 vb[1] = y1;
1358 vb[2] = depth;
1359 vb[3] = 1;
1360
1361 vb[8] = x1;
1362 vb[9] = y2;
1363 vb[10] = depth;
1364 vb[11] = 1;
1365
1366 vb[16] = x2;
1367 vb[17] = y1;
1368 vb[18] = depth;
1369 vb[19] = 1;
1370
1371 if (attrib) {
1372 memcpy(vb+4, attrib->f, sizeof(float)*4);
1373 memcpy(vb+12, attrib->f, sizeof(float)*4);
1374 memcpy(vb+20, attrib->f, sizeof(float)*4);
1375 }
1376
1377 /* draw */
1378 util_draw_vertex_buffer(&rctx->context, NULL, buf, rctx->blitter->vb_slot, offset,
1379 R600_PRIM_RECTANGLE_LIST, 3, 2);
1380 pipe_resource_reference(&buf, NULL);
1381 }
1382
1383 void _r600_pipe_state_add_reg_bo(struct r600_context *ctx,
1384 struct r600_pipe_state *state,
1385 uint32_t offset, uint32_t value,
1386 uint32_t range_id, uint32_t block_id,
1387 struct r600_resource *bo,
1388 enum radeon_bo_usage usage)
1389
1390 {
1391 struct r600_range *range;
1392 struct r600_block *block;
1393
1394 if (bo) assert(usage);
1395
1396 range = &ctx->range[range_id];
1397 block = range->blocks[block_id];
1398 state->regs[state->nregs].block = block;
1399 state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
1400
1401 state->regs[state->nregs].value = value;
1402 state->regs[state->nregs].bo = bo;
1403 state->regs[state->nregs].bo_usage = usage;
1404
1405 state->nregs++;
1406 assert(state->nregs < R600_BLOCK_MAX_REG);
1407 }
1408
1409 void _r600_pipe_state_add_reg(struct r600_context *ctx,
1410 struct r600_pipe_state *state,
1411 uint32_t offset, uint32_t value,
1412 uint32_t range_id, uint32_t block_id)
1413 {
1414 _r600_pipe_state_add_reg_bo(ctx, state, offset, value,
1415 range_id, block_id, NULL, 0);
1416 }
1417
1418 uint32_t r600_translate_stencil_op(int s_op)
1419 {
1420 switch (s_op) {
1421 case PIPE_STENCIL_OP_KEEP:
1422 return V_028800_STENCIL_KEEP;
1423 case PIPE_STENCIL_OP_ZERO:
1424 return V_028800_STENCIL_ZERO;
1425 case PIPE_STENCIL_OP_REPLACE:
1426 return V_028800_STENCIL_REPLACE;
1427 case PIPE_STENCIL_OP_INCR:
1428 return V_028800_STENCIL_INCR;
1429 case PIPE_STENCIL_OP_DECR:
1430 return V_028800_STENCIL_DECR;
1431 case PIPE_STENCIL_OP_INCR_WRAP:
1432 return V_028800_STENCIL_INCR_WRAP;
1433 case PIPE_STENCIL_OP_DECR_WRAP:
1434 return V_028800_STENCIL_DECR_WRAP;
1435 case PIPE_STENCIL_OP_INVERT:
1436 return V_028800_STENCIL_INVERT;
1437 default:
1438 R600_ERR("Unknown stencil op %d", s_op);
1439 assert(0);
1440 break;
1441 }
1442 return 0;
1443 }
1444
1445 uint32_t r600_translate_fill(uint32_t func)
1446 {
1447 switch(func) {
1448 case PIPE_POLYGON_MODE_FILL:
1449 return 2;
1450 case PIPE_POLYGON_MODE_LINE:
1451 return 1;
1452 case PIPE_POLYGON_MODE_POINT:
1453 return 0;
1454 default:
1455 assert(0);
1456 return 0;
1457 }
1458 }
1459
1460 unsigned r600_tex_wrap(unsigned wrap)
1461 {
1462 switch (wrap) {
1463 default:
1464 case PIPE_TEX_WRAP_REPEAT:
1465 return V_03C000_SQ_TEX_WRAP;
1466 case PIPE_TEX_WRAP_CLAMP:
1467 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1468 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1469 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1470 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1471 return V_03C000_SQ_TEX_CLAMP_BORDER;
1472 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1473 return V_03C000_SQ_TEX_MIRROR;
1474 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1475 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1476 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1477 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1478 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1479 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1480 }
1481 }
1482
1483 unsigned r600_tex_filter(unsigned filter)
1484 {
1485 switch (filter) {
1486 default:
1487 case PIPE_TEX_FILTER_NEAREST:
1488 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1489 case PIPE_TEX_FILTER_LINEAR:
1490 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1491 }
1492 }
1493
1494 unsigned r600_tex_mipfilter(unsigned filter)
1495 {
1496 switch (filter) {
1497 case PIPE_TEX_MIPFILTER_NEAREST:
1498 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1499 case PIPE_TEX_MIPFILTER_LINEAR:
1500 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1501 default:
1502 case PIPE_TEX_MIPFILTER_NONE:
1503 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1504 }
1505 }
1506
1507 unsigned r600_tex_compare(unsigned compare)
1508 {
1509 switch (compare) {
1510 default:
1511 case PIPE_FUNC_NEVER:
1512 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1513 case PIPE_FUNC_LESS:
1514 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1515 case PIPE_FUNC_EQUAL:
1516 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1517 case PIPE_FUNC_LEQUAL:
1518 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1519 case PIPE_FUNC_GREATER:
1520 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1521 case PIPE_FUNC_NOTEQUAL:
1522 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1523 case PIPE_FUNC_GEQUAL:
1524 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1525 case PIPE_FUNC_ALWAYS:
1526 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1527 }
1528 }
1529
1530 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
1531 {
1532 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
1533 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
1534 (linear_filter &&
1535 (wrap == PIPE_TEX_WRAP_CLAMP ||
1536 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
1537 }
1538
1539 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
1540 {
1541 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
1542 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
1543
1544 return (state->border_color.ui[0] || state->border_color.ui[1] ||
1545 state->border_color.ui[2] || state->border_color.ui[3]) &&
1546 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
1547 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
1548 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
1549 }
1550
1551 /* keep this at the end of this file, please */
1552 void r600_init_common_state_functions(struct r600_context *rctx)
1553 {
1554 rctx->context.create_fs_state = r600_create_ps_state;
1555 rctx->context.create_vs_state = r600_create_vs_state;
1556 rctx->context.create_vertex_elements_state = r600_create_vertex_fetch_shader;
1557 rctx->context.bind_blend_state = r600_bind_blend_state;
1558 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1559 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler_states;
1560 rctx->context.bind_fs_state = r600_bind_ps_state;
1561 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1562 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1563 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler_states;
1564 rctx->context.bind_vs_state = r600_bind_vs_state;
1565 rctx->context.delete_blend_state = r600_delete_blend_state;
1566 rctx->context.delete_depth_stencil_alpha_state = r600_delete_dsa_state;
1567 rctx->context.delete_fs_state = r600_delete_ps_state;
1568 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1569 rctx->context.delete_sampler_state = r600_delete_sampler_state;
1570 rctx->context.delete_vertex_elements_state = r600_delete_vertex_elements;
1571 rctx->context.delete_vs_state = r600_delete_vs_state;
1572 rctx->context.set_blend_color = r600_set_blend_color;
1573 rctx->context.set_clip_state = r600_set_clip_state;
1574 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1575 rctx->context.set_sample_mask = r600_set_sample_mask;
1576 rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1577 rctx->context.set_viewport_state = r600_set_viewport_state;
1578 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1579 rctx->context.set_index_buffer = r600_set_index_buffer;
1580 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views;
1581 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views;
1582 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1583 rctx->context.texture_barrier = r600_texture_barrier;
1584 rctx->context.create_stream_output_target = r600_create_so_target;
1585 rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1586 rctx->context.set_stream_output_targets = r600_set_so_targets;
1587 rctx->context.draw_vbo = r600_draw_vbo;
1588 }