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r600g: port the layered surface rendering patch from radeonsi
[mesa.git] / src / gallium / drivers / r600 / r600_state_common.c
1 /*
2 * Copyright 2010 Red Hat Inc.
3 * 2010 Jerome Glisse
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
26 */
27 #include "r600_formats.h"
28 #include "r600_shader.h"
29 #include "r600d.h"
30
31 #include "util/u_draw_quad.h"
32 #include "util/u_format_s3tc.h"
33 #include "util/u_index_modify.h"
34 #include "util/u_memory.h"
35 #include "util/u_upload_mgr.h"
36 #include "util/u_math.h"
37 #include "tgsi/tgsi_parse.h"
38
39 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
40
41 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw)
42 {
43 assert(!cb->buf);
44 cb->buf = CALLOC(1, 4 * num_dw);
45 cb->max_num_dw = num_dw;
46 }
47
48 void r600_release_command_buffer(struct r600_command_buffer *cb)
49 {
50 FREE(cb->buf);
51 }
52
53 void r600_init_atom(struct r600_context *rctx,
54 struct r600_atom *atom,
55 unsigned id,
56 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
57 unsigned num_dw)
58 {
59 assert(id < R600_NUM_ATOMS);
60 assert(rctx->atoms[id] == NULL);
61 rctx->atoms[id] = atom;
62 atom->emit = (void*)emit;
63 atom->num_dw = num_dw;
64 atom->dirty = false;
65 }
66
67 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom)
68 {
69 r600_emit_command_buffer(rctx->b.rings.gfx.cs, ((struct r600_cso_state*)atom)->cb);
70 }
71
72 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom)
73 {
74 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
75 struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom;
76 unsigned alpha_ref = a->sx_alpha_ref;
77
78 if (rctx->b.chip_class >= EVERGREEN && a->cb0_export_16bpc) {
79 alpha_ref &= ~0x1FFF;
80 }
81
82 r600_write_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL,
83 a->sx_alpha_test_control |
84 S_028410_ALPHA_TEST_BYPASS(a->bypass));
85 r600_write_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref);
86 }
87
88 static void r600_texture_barrier(struct pipe_context *ctx)
89 {
90 struct r600_context *rctx = (struct r600_context *)ctx;
91
92 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
93 R600_CONTEXT_FLUSH_AND_INV_CB |
94 R600_CONTEXT_FLUSH_AND_INV |
95 R600_CONTEXT_WAIT_3D_IDLE;
96 }
97
98 static unsigned r600_conv_pipe_prim(unsigned prim)
99 {
100 static const unsigned prim_conv[] = {
101 V_008958_DI_PT_POINTLIST,
102 V_008958_DI_PT_LINELIST,
103 V_008958_DI_PT_LINELOOP,
104 V_008958_DI_PT_LINESTRIP,
105 V_008958_DI_PT_TRILIST,
106 V_008958_DI_PT_TRISTRIP,
107 V_008958_DI_PT_TRIFAN,
108 V_008958_DI_PT_QUADLIST,
109 V_008958_DI_PT_QUADSTRIP,
110 V_008958_DI_PT_POLYGON,
111 V_008958_DI_PT_LINELIST_ADJ,
112 V_008958_DI_PT_LINESTRIP_ADJ,
113 V_008958_DI_PT_TRILIST_ADJ,
114 V_008958_DI_PT_TRISTRIP_ADJ,
115 V_008958_DI_PT_RECTLIST
116 };
117 return prim_conv[prim];
118 }
119
120 /* common state between evergreen and r600 */
121
122 static void r600_bind_blend_state_internal(struct r600_context *rctx,
123 struct r600_blend_state *blend, bool blend_disable)
124 {
125 unsigned color_control;
126 bool update_cb = false;
127
128 rctx->alpha_to_one = blend->alpha_to_one;
129 rctx->dual_src_blend = blend->dual_src_blend;
130
131 if (!blend_disable) {
132 r600_set_cso_state_with_cb(&rctx->blend_state, blend, &blend->buffer);
133 color_control = blend->cb_color_control;
134 } else {
135 /* Blending is disabled. */
136 r600_set_cso_state_with_cb(&rctx->blend_state, blend, &blend->buffer_no_blend);
137 color_control = blend->cb_color_control_no_blend;
138 }
139
140 /* Update derived states. */
141 if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) {
142 rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
143 update_cb = true;
144 }
145 if (rctx->b.chip_class <= R700 &&
146 rctx->cb_misc_state.cb_color_control != color_control) {
147 rctx->cb_misc_state.cb_color_control = color_control;
148 update_cb = true;
149 }
150 if (rctx->cb_misc_state.dual_src_blend != blend->dual_src_blend) {
151 rctx->cb_misc_state.dual_src_blend = blend->dual_src_blend;
152 update_cb = true;
153 }
154 if (update_cb) {
155 rctx->cb_misc_state.atom.dirty = true;
156 }
157 }
158
159 static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
160 {
161 struct r600_context *rctx = (struct r600_context *)ctx;
162 struct r600_blend_state *blend = (struct r600_blend_state *)state;
163
164 if (blend == NULL)
165 return;
166
167 r600_bind_blend_state_internal(rctx, blend, rctx->force_blend_disable);
168 }
169
170 static void r600_set_blend_color(struct pipe_context *ctx,
171 const struct pipe_blend_color *state)
172 {
173 struct r600_context *rctx = (struct r600_context *)ctx;
174
175 rctx->blend_color.state = *state;
176 rctx->blend_color.atom.dirty = true;
177 }
178
179 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom)
180 {
181 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
182 struct pipe_blend_color *state = &rctx->blend_color.state;
183
184 r600_write_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
185 radeon_emit(cs, fui(state->color[0])); /* R_028414_CB_BLEND_RED */
186 radeon_emit(cs, fui(state->color[1])); /* R_028418_CB_BLEND_GREEN */
187 radeon_emit(cs, fui(state->color[2])); /* R_02841C_CB_BLEND_BLUE */
188 radeon_emit(cs, fui(state->color[3])); /* R_028420_CB_BLEND_ALPHA */
189 }
190
191 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom)
192 {
193 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
194 struct r600_vgt_state *a = (struct r600_vgt_state *)atom;
195
196 r600_write_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, a->vgt_multi_prim_ib_reset_en);
197 r600_write_context_reg_seq(cs, R_028408_VGT_INDX_OFFSET, 2);
198 radeon_emit(cs, a->vgt_indx_offset); /* R_028408_VGT_INDX_OFFSET */
199 radeon_emit(cs, a->vgt_multi_prim_ib_reset_indx); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
200 }
201
202 static void r600_set_clip_state(struct pipe_context *ctx,
203 const struct pipe_clip_state *state)
204 {
205 struct r600_context *rctx = (struct r600_context *)ctx;
206 struct pipe_constant_buffer cb;
207
208 rctx->clip_state.state = *state;
209 rctx->clip_state.atom.dirty = true;
210
211 cb.buffer = NULL;
212 cb.user_buffer = state->ucp;
213 cb.buffer_offset = 0;
214 cb.buffer_size = 4*4*8;
215 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, R600_UCP_CONST_BUFFER, &cb);
216 pipe_resource_reference(&cb.buffer, NULL);
217 }
218
219 static void r600_set_stencil_ref(struct pipe_context *ctx,
220 const struct r600_stencil_ref *state)
221 {
222 struct r600_context *rctx = (struct r600_context *)ctx;
223
224 rctx->stencil_ref.state = *state;
225 rctx->stencil_ref.atom.dirty = true;
226 }
227
228 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom)
229 {
230 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
231 struct r600_stencil_ref_state *a = (struct r600_stencil_ref_state*)atom;
232
233 r600_write_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
234 radeon_emit(cs, /* R_028430_DB_STENCILREFMASK */
235 S_028430_STENCILREF(a->state.ref_value[0]) |
236 S_028430_STENCILMASK(a->state.valuemask[0]) |
237 S_028430_STENCILWRITEMASK(a->state.writemask[0]));
238 radeon_emit(cs, /* R_028434_DB_STENCILREFMASK_BF */
239 S_028434_STENCILREF_BF(a->state.ref_value[1]) |
240 S_028434_STENCILMASK_BF(a->state.valuemask[1]) |
241 S_028434_STENCILWRITEMASK_BF(a->state.writemask[1]));
242 }
243
244 static void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
245 const struct pipe_stencil_ref *state)
246 {
247 struct r600_context *rctx = (struct r600_context *)ctx;
248 struct r600_dsa_state *dsa = (struct r600_dsa_state*)rctx->dsa_state.cso;
249 struct r600_stencil_ref ref;
250
251 rctx->stencil_ref.pipe_state = *state;
252
253 if (!dsa)
254 return;
255
256 ref.ref_value[0] = state->ref_value[0];
257 ref.ref_value[1] = state->ref_value[1];
258 ref.valuemask[0] = dsa->valuemask[0];
259 ref.valuemask[1] = dsa->valuemask[1];
260 ref.writemask[0] = dsa->writemask[0];
261 ref.writemask[1] = dsa->writemask[1];
262
263 r600_set_stencil_ref(ctx, &ref);
264 }
265
266 static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
267 {
268 struct r600_context *rctx = (struct r600_context *)ctx;
269 struct r600_dsa_state *dsa = state;
270 struct r600_stencil_ref ref;
271
272 if (state == NULL) {
273 r600_set_cso_state_with_cb(&rctx->dsa_state, NULL, NULL);
274 return;
275 }
276
277 r600_set_cso_state_with_cb(&rctx->dsa_state, dsa, &dsa->buffer);
278
279 ref.ref_value[0] = rctx->stencil_ref.pipe_state.ref_value[0];
280 ref.ref_value[1] = rctx->stencil_ref.pipe_state.ref_value[1];
281 ref.valuemask[0] = dsa->valuemask[0];
282 ref.valuemask[1] = dsa->valuemask[1];
283 ref.writemask[0] = dsa->writemask[0];
284 ref.writemask[1] = dsa->writemask[1];
285 if (rctx->zwritemask != dsa->zwritemask) {
286 rctx->zwritemask = dsa->zwritemask;
287 if (rctx->b.chip_class >= EVERGREEN) {
288 /* work around some issue when not writting to zbuffer
289 * we are having lockup on evergreen so do not enable
290 * hyperz when not writting zbuffer
291 */
292 rctx->db_misc_state.atom.dirty = true;
293 }
294 }
295
296 r600_set_stencil_ref(ctx, &ref);
297
298 /* Update alphatest state. */
299 if (rctx->alphatest_state.sx_alpha_test_control != dsa->sx_alpha_test_control ||
300 rctx->alphatest_state.sx_alpha_ref != dsa->alpha_ref) {
301 rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control;
302 rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref;
303 rctx->alphatest_state.atom.dirty = true;
304 }
305 }
306
307 static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
308 {
309 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
310 struct r600_context *rctx = (struct r600_context *)ctx;
311
312 if (state == NULL)
313 return;
314
315 rctx->rasterizer = rs;
316
317 r600_set_cso_state_with_cb(&rctx->rasterizer_state, rs, &rs->buffer);
318
319 if (rs->offset_enable &&
320 (rs->offset_units != rctx->poly_offset_state.offset_units ||
321 rs->offset_scale != rctx->poly_offset_state.offset_scale)) {
322 rctx->poly_offset_state.offset_units = rs->offset_units;
323 rctx->poly_offset_state.offset_scale = rs->offset_scale;
324 rctx->poly_offset_state.atom.dirty = true;
325 }
326
327 /* Update clip_misc_state. */
328 if (rctx->clip_misc_state.pa_cl_clip_cntl != rs->pa_cl_clip_cntl ||
329 rctx->clip_misc_state.clip_plane_enable != rs->clip_plane_enable) {
330 rctx->clip_misc_state.pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
331 rctx->clip_misc_state.clip_plane_enable = rs->clip_plane_enable;
332 rctx->clip_misc_state.atom.dirty = true;
333 }
334
335 /* Workaround for a missing scissor enable on r600. */
336 if (rctx->b.chip_class == R600 &&
337 rs->scissor_enable != rctx->scissor.enable) {
338 rctx->scissor.enable = rs->scissor_enable;
339 rctx->scissor.atom.dirty = true;
340 }
341
342 /* Re-emit PA_SC_LINE_STIPPLE. */
343 rctx->last_primitive_type = -1;
344 }
345
346 static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
347 {
348 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
349
350 r600_release_command_buffer(&rs->buffer);
351 FREE(rs);
352 }
353
354 static void r600_sampler_view_destroy(struct pipe_context *ctx,
355 struct pipe_sampler_view *state)
356 {
357 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
358
359 pipe_resource_reference(&state->texture, NULL);
360 FREE(resource);
361 }
362
363 void r600_sampler_states_dirty(struct r600_context *rctx,
364 struct r600_sampler_states *state)
365 {
366 if (state->dirty_mask) {
367 if (state->dirty_mask & state->has_bordercolor_mask) {
368 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
369 }
370 state->atom.num_dw =
371 util_bitcount(state->dirty_mask & state->has_bordercolor_mask) * 11 +
372 util_bitcount(state->dirty_mask & ~state->has_bordercolor_mask) * 5;
373 state->atom.dirty = true;
374 }
375 }
376
377 static void r600_bind_sampler_states(struct pipe_context *pipe,
378 unsigned shader,
379 unsigned start,
380 unsigned count, void **states)
381 {
382 struct r600_context *rctx = (struct r600_context *)pipe;
383 struct r600_textures_info *dst = &rctx->samplers[shader];
384 struct r600_pipe_sampler_state **rstates = (struct r600_pipe_sampler_state**)states;
385 int seamless_cube_map = -1;
386 unsigned i;
387 /* This sets 1-bit for states with index >= count. */
388 uint32_t disable_mask = ~((1ull << count) - 1);
389 /* These are the new states set by this function. */
390 uint32_t new_mask = 0;
391
392 assert(start == 0); /* XXX fix below */
393
394 if (shader != PIPE_SHADER_VERTEX &&
395 shader != PIPE_SHADER_FRAGMENT) {
396 return;
397 }
398
399 for (i = 0; i < count; i++) {
400 struct r600_pipe_sampler_state *rstate = rstates[i];
401
402 if (rstate == dst->states.states[i]) {
403 continue;
404 }
405
406 if (rstate) {
407 if (rstate->border_color_use) {
408 dst->states.has_bordercolor_mask |= 1 << i;
409 } else {
410 dst->states.has_bordercolor_mask &= ~(1 << i);
411 }
412 seamless_cube_map = rstate->seamless_cube_map;
413
414 new_mask |= 1 << i;
415 } else {
416 disable_mask |= 1 << i;
417 }
418 }
419
420 memcpy(dst->states.states, rstates, sizeof(void*) * count);
421 memset(dst->states.states + count, 0, sizeof(void*) * (NUM_TEX_UNITS - count));
422
423 dst->states.enabled_mask &= ~disable_mask;
424 dst->states.dirty_mask &= dst->states.enabled_mask;
425 dst->states.enabled_mask |= new_mask;
426 dst->states.dirty_mask |= new_mask;
427 dst->states.has_bordercolor_mask &= dst->states.enabled_mask;
428
429 r600_sampler_states_dirty(rctx, &dst->states);
430
431 /* Seamless cubemap state. */
432 if (rctx->b.chip_class <= R700 &&
433 seamless_cube_map != -1 &&
434 seamless_cube_map != rctx->seamless_cube_map.enabled) {
435 /* change in TA_CNTL_AUX need a pipeline flush */
436 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
437 rctx->seamless_cube_map.enabled = seamless_cube_map;
438 rctx->seamless_cube_map.atom.dirty = true;
439 }
440 }
441
442 static void r600_delete_sampler_state(struct pipe_context *ctx, void *state)
443 {
444 free(state);
445 }
446
447 static void r600_delete_blend_state(struct pipe_context *ctx, void *state)
448 {
449 struct r600_blend_state *blend = (struct r600_blend_state*)state;
450
451 r600_release_command_buffer(&blend->buffer);
452 r600_release_command_buffer(&blend->buffer_no_blend);
453 FREE(blend);
454 }
455
456 static void r600_delete_dsa_state(struct pipe_context *ctx, void *state)
457 {
458 struct r600_context *rctx = (struct r600_context *)ctx;
459 struct r600_dsa_state *dsa = (struct r600_dsa_state *)state;
460
461 if (rctx->dsa_state.cso == state) {
462 ctx->bind_depth_stencil_alpha_state(ctx, NULL);
463 }
464
465 r600_release_command_buffer(&dsa->buffer);
466 free(dsa);
467 }
468
469 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
470 {
471 struct r600_context *rctx = (struct r600_context *)ctx;
472
473 r600_set_cso_state(&rctx->vertex_fetch_shader, state);
474 }
475
476 static void r600_delete_vertex_elements(struct pipe_context *ctx, void *state)
477 {
478 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state;
479 pipe_resource_reference((struct pipe_resource**)&shader->buffer, NULL);
480 FREE(shader);
481 }
482
483 static void r600_set_index_buffer(struct pipe_context *ctx,
484 const struct pipe_index_buffer *ib)
485 {
486 struct r600_context *rctx = (struct r600_context *)ctx;
487
488 if (ib) {
489 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
490 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
491 r600_context_add_resource_size(ctx, ib->buffer);
492 } else {
493 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
494 }
495 }
496
497 void r600_vertex_buffers_dirty(struct r600_context *rctx)
498 {
499 if (rctx->vertex_buffer_state.dirty_mask) {
500 rctx->b.flags |= R600_CONTEXT_INV_VERTEX_CACHE;
501 rctx->vertex_buffer_state.atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 12 : 11) *
502 util_bitcount(rctx->vertex_buffer_state.dirty_mask);
503 rctx->vertex_buffer_state.atom.dirty = true;
504 }
505 }
506
507 static void r600_set_vertex_buffers(struct pipe_context *ctx,
508 unsigned start_slot, unsigned count,
509 const struct pipe_vertex_buffer *input)
510 {
511 struct r600_context *rctx = (struct r600_context *)ctx;
512 struct r600_vertexbuf_state *state = &rctx->vertex_buffer_state;
513 struct pipe_vertex_buffer *vb = state->vb + start_slot;
514 unsigned i;
515 uint32_t disable_mask = 0;
516 /* These are the new buffers set by this function. */
517 uint32_t new_buffer_mask = 0;
518
519 /* Set vertex buffers. */
520 if (input) {
521 for (i = 0; i < count; i++) {
522 if (memcmp(&input[i], &vb[i], sizeof(struct pipe_vertex_buffer))) {
523 if (input[i].buffer) {
524 vb[i].stride = input[i].stride;
525 vb[i].buffer_offset = input[i].buffer_offset;
526 pipe_resource_reference(&vb[i].buffer, input[i].buffer);
527 new_buffer_mask |= 1 << i;
528 r600_context_add_resource_size(ctx, input[i].buffer);
529 } else {
530 pipe_resource_reference(&vb[i].buffer, NULL);
531 disable_mask |= 1 << i;
532 }
533 }
534 }
535 } else {
536 for (i = 0; i < count; i++) {
537 pipe_resource_reference(&vb[i].buffer, NULL);
538 }
539 disable_mask = ((1ull << count) - 1);
540 }
541
542 disable_mask <<= start_slot;
543 new_buffer_mask <<= start_slot;
544
545 rctx->vertex_buffer_state.enabled_mask &= ~disable_mask;
546 rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask;
547 rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask;
548 rctx->vertex_buffer_state.dirty_mask |= new_buffer_mask;
549
550 r600_vertex_buffers_dirty(rctx);
551 }
552
553 void r600_sampler_views_dirty(struct r600_context *rctx,
554 struct r600_samplerview_state *state)
555 {
556 if (state->dirty_mask) {
557 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
558 state->atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 14 : 13) *
559 util_bitcount(state->dirty_mask);
560 state->atom.dirty = true;
561 }
562 }
563
564 static void r600_set_sampler_views(struct pipe_context *pipe, unsigned shader,
565 unsigned start, unsigned count,
566 struct pipe_sampler_view **views)
567 {
568 struct r600_context *rctx = (struct r600_context *) pipe;
569 struct r600_textures_info *dst = &rctx->samplers[shader];
570 struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
571 uint32_t dirty_sampler_states_mask = 0;
572 unsigned i;
573 /* This sets 1-bit for textures with index >= count. */
574 uint32_t disable_mask = ~((1ull << count) - 1);
575 /* These are the new textures set by this function. */
576 uint32_t new_mask = 0;
577
578 /* Set textures with index >= count to NULL. */
579 uint32_t remaining_mask;
580
581 assert(start == 0); /* XXX fix below */
582
583 if (shader == PIPE_SHADER_COMPUTE) {
584 evergreen_set_cs_sampler_view(pipe, start, count, views);
585 return;
586 }
587
588 remaining_mask = dst->views.enabled_mask & disable_mask;
589
590 while (remaining_mask) {
591 i = u_bit_scan(&remaining_mask);
592 assert(dst->views.views[i]);
593
594 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
595 }
596
597 for (i = 0; i < count; i++) {
598 if (rviews[i] == dst->views.views[i]) {
599 continue;
600 }
601
602 if (rviews[i]) {
603 struct r600_texture *rtex =
604 (struct r600_texture*)rviews[i]->base.texture;
605
606 if (rviews[i]->base.texture->target != PIPE_BUFFER) {
607 if (rtex->is_depth && !rtex->is_flushing_texture) {
608 dst->views.compressed_depthtex_mask |= 1 << i;
609 } else {
610 dst->views.compressed_depthtex_mask &= ~(1 << i);
611 }
612
613 /* Track compressed colorbuffers. */
614 if (rtex->cmask.size) {
615 dst->views.compressed_colortex_mask |= 1 << i;
616 } else {
617 dst->views.compressed_colortex_mask &= ~(1 << i);
618 }
619 }
620 /* Changing from array to non-arrays textures and vice versa requires
621 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
622 if (rctx->b.chip_class <= R700 &&
623 (dst->states.enabled_mask & (1 << i)) &&
624 (rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
625 rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) {
626 dirty_sampler_states_mask |= 1 << i;
627 }
628
629 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]);
630 new_mask |= 1 << i;
631 r600_context_add_resource_size(pipe, views[i]->texture);
632 } else {
633 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
634 disable_mask |= 1 << i;
635 }
636 }
637
638 dst->views.enabled_mask &= ~disable_mask;
639 dst->views.dirty_mask &= dst->views.enabled_mask;
640 dst->views.enabled_mask |= new_mask;
641 dst->views.dirty_mask |= new_mask;
642 dst->views.compressed_depthtex_mask &= dst->views.enabled_mask;
643 dst->views.compressed_colortex_mask &= dst->views.enabled_mask;
644 dst->views.dirty_txq_constants = TRUE;
645 dst->views.dirty_buffer_constants = TRUE;
646 r600_sampler_views_dirty(rctx, &dst->views);
647
648 if (dirty_sampler_states_mask) {
649 dst->states.dirty_mask |= dirty_sampler_states_mask;
650 r600_sampler_states_dirty(rctx, &dst->states);
651 }
652 }
653
654 static void r600_set_viewport_states(struct pipe_context *ctx,
655 unsigned start_slot,
656 unsigned num_viewports,
657 const struct pipe_viewport_state *state)
658 {
659 struct r600_context *rctx = (struct r600_context *)ctx;
660
661 rctx->viewport.state = *state;
662 rctx->viewport.atom.dirty = true;
663 }
664
665 void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom)
666 {
667 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
668 struct pipe_viewport_state *state = &rctx->viewport.state;
669
670 r600_write_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE_0, 6);
671 radeon_emit(cs, fui(state->scale[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
672 radeon_emit(cs, fui(state->translate[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
673 radeon_emit(cs, fui(state->scale[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
674 radeon_emit(cs, fui(state->translate[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
675 radeon_emit(cs, fui(state->scale[2])); /* R_02844C_PA_CL_VPORT_ZSCALE_0 */
676 radeon_emit(cs, fui(state->translate[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
677 }
678
679 /* Compute the key for the hw shader variant */
680 static INLINE struct r600_shader_key r600_shader_selector_key(struct pipe_context * ctx,
681 struct r600_pipe_shader_selector * sel)
682 {
683 struct r600_context *rctx = (struct r600_context *)ctx;
684 struct r600_shader_key key;
685 memset(&key, 0, sizeof(key));
686
687 if (sel->type == PIPE_SHADER_FRAGMENT) {
688 key.color_two_side = rctx->rasterizer && rctx->rasterizer->two_side;
689 key.alpha_to_one = rctx->alpha_to_one &&
690 rctx->rasterizer && rctx->rasterizer->multisample_enable &&
691 !rctx->framebuffer.cb0_is_integer;
692 key.nr_cbufs = rctx->framebuffer.state.nr_cbufs;
693 /* Dual-source blending only makes sense with nr_cbufs == 1. */
694 if (key.nr_cbufs == 1 && rctx->dual_src_blend)
695 key.nr_cbufs = 2;
696 } else if (sel->type == PIPE_SHADER_VERTEX) {
697 key.vs_as_es = (rctx->gs_shader != NULL);
698 }
699 return key;
700 }
701
702 /* Select the hw shader variant depending on the current state.
703 * (*dirty) is set to 1 if current variant was changed */
704 static int r600_shader_select(struct pipe_context *ctx,
705 struct r600_pipe_shader_selector* sel,
706 bool *dirty)
707 {
708 struct r600_shader_key key;
709 struct r600_pipe_shader * shader = NULL;
710 int r;
711
712 memset(&key, 0, sizeof(key));
713 key = r600_shader_selector_key(ctx, sel);
714
715 /* Check if we don't need to change anything.
716 * This path is also used for most shaders that don't need multiple
717 * variants, it will cost just a computation of the key and this
718 * test. */
719 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
720 return 0;
721 }
722
723 /* lookup if we have other variants in the list */
724 if (sel->num_shaders > 1) {
725 struct r600_pipe_shader *p = sel->current, *c = p->next_variant;
726
727 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
728 p = c;
729 c = c->next_variant;
730 }
731
732 if (c) {
733 p->next_variant = c->next_variant;
734 shader = c;
735 }
736 }
737
738 if (unlikely(!shader)) {
739 shader = CALLOC(1, sizeof(struct r600_pipe_shader));
740 shader->selector = sel;
741
742 r = r600_pipe_shader_create(ctx, shader, key);
743 if (unlikely(r)) {
744 R600_ERR("Failed to build shader variant (type=%u) %d\n",
745 sel->type, r);
746 sel->current = NULL;
747 FREE(shader);
748 return r;
749 }
750
751 /* We don't know the value of nr_ps_max_color_exports until we built
752 * at least one variant, so we may need to recompute the key after
753 * building first variant. */
754 if (sel->type == PIPE_SHADER_FRAGMENT &&
755 sel->num_shaders == 0) {
756 sel->nr_ps_max_color_exports = shader->shader.nr_ps_max_color_exports;
757 key = r600_shader_selector_key(ctx, sel);
758 }
759
760 memcpy(&shader->key, &key, sizeof(key));
761 sel->num_shaders++;
762 }
763
764 if (dirty)
765 *dirty = true;
766
767 shader->next_variant = sel->current;
768 sel->current = shader;
769
770 return 0;
771 }
772
773 static void *r600_create_shader_state(struct pipe_context *ctx,
774 const struct pipe_shader_state *state,
775 unsigned pipe_shader_type)
776 {
777 struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector);
778
779 sel->type = pipe_shader_type;
780 sel->tokens = tgsi_dup_tokens(state->tokens);
781 sel->so = state->stream_output;
782 return sel;
783 }
784
785 static void *r600_create_ps_state(struct pipe_context *ctx,
786 const struct pipe_shader_state *state)
787 {
788 return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
789 }
790
791 static void *r600_create_vs_state(struct pipe_context *ctx,
792 const struct pipe_shader_state *state)
793 {
794 return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
795 }
796
797 static void *r600_create_gs_state(struct pipe_context *ctx,
798 const struct pipe_shader_state *state)
799 {
800 return r600_create_shader_state(ctx, state, PIPE_SHADER_GEOMETRY);
801 }
802
803 static void r600_bind_ps_state(struct pipe_context *ctx, void *state)
804 {
805 struct r600_context *rctx = (struct r600_context *)ctx;
806
807 if (!state)
808 state = rctx->dummy_pixel_shader;
809
810 rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
811 }
812
813 static void r600_bind_vs_state(struct pipe_context *ctx, void *state)
814 {
815 struct r600_context *rctx = (struct r600_context *)ctx;
816
817 if (!state)
818 return;
819
820 rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
821 rctx->b.streamout.stride_in_dw = rctx->vs_shader->so.stride;
822 }
823
824 static void r600_bind_gs_state(struct pipe_context *ctx, void *state)
825 {
826 struct r600_context *rctx = (struct r600_context *)ctx;
827
828 rctx->gs_shader = (struct r600_pipe_shader_selector *)state;
829
830 if (!state)
831 return;
832 rctx->b.streamout.stride_in_dw = rctx->gs_shader->so.stride;
833 }
834
835 static void r600_delete_shader_selector(struct pipe_context *ctx,
836 struct r600_pipe_shader_selector *sel)
837 {
838 struct r600_pipe_shader *p = sel->current, *c;
839 while (p) {
840 c = p->next_variant;
841 r600_pipe_shader_destroy(ctx, p);
842 free(p);
843 p = c;
844 }
845
846 free(sel->tokens);
847 free(sel);
848 }
849
850
851 static void r600_delete_ps_state(struct pipe_context *ctx, void *state)
852 {
853 struct r600_context *rctx = (struct r600_context *)ctx;
854 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
855
856 if (rctx->ps_shader == sel) {
857 rctx->ps_shader = NULL;
858 }
859
860 r600_delete_shader_selector(ctx, sel);
861 }
862
863 static void r600_delete_vs_state(struct pipe_context *ctx, void *state)
864 {
865 struct r600_context *rctx = (struct r600_context *)ctx;
866 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
867
868 if (rctx->vs_shader == sel) {
869 rctx->vs_shader = NULL;
870 }
871
872 r600_delete_shader_selector(ctx, sel);
873 }
874
875
876 static void r600_delete_gs_state(struct pipe_context *ctx, void *state)
877 {
878 struct r600_context *rctx = (struct r600_context *)ctx;
879 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
880
881 if (rctx->gs_shader == sel) {
882 rctx->gs_shader = NULL;
883 }
884
885 r600_delete_shader_selector(ctx, sel);
886 }
887
888
889 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
890 {
891 if (state->dirty_mask) {
892 rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE;
893 state->atom.num_dw = rctx->b.chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
894 : util_bitcount(state->dirty_mask)*19;
895 state->atom.dirty = true;
896 }
897 }
898
899 static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
900 struct pipe_constant_buffer *input)
901 {
902 struct r600_context *rctx = (struct r600_context *)ctx;
903 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
904 struct pipe_constant_buffer *cb;
905 const uint8_t *ptr;
906
907 /* Note that the state tracker can unbind constant buffers by
908 * passing NULL here.
909 */
910 if (unlikely(!input || (!input->buffer && !input->user_buffer))) {
911 state->enabled_mask &= ~(1 << index);
912 state->dirty_mask &= ~(1 << index);
913 pipe_resource_reference(&state->cb[index].buffer, NULL);
914 return;
915 }
916
917 cb = &state->cb[index];
918 cb->buffer_size = input->buffer_size;
919
920 ptr = input->user_buffer;
921
922 if (ptr) {
923 /* Upload the user buffer. */
924 if (R600_BIG_ENDIAN) {
925 uint32_t *tmpPtr;
926 unsigned i, size = input->buffer_size;
927
928 if (!(tmpPtr = malloc(size))) {
929 R600_ERR("Failed to allocate BE swap buffer.\n");
930 return;
931 }
932
933 for (i = 0; i < size / 4; ++i) {
934 tmpPtr[i] = util_bswap32(((uint32_t *)ptr)[i]);
935 }
936
937 u_upload_data(rctx->b.uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer);
938 free(tmpPtr);
939 } else {
940 u_upload_data(rctx->b.uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer);
941 }
942 /* account it in gtt */
943 rctx->b.gtt += input->buffer_size;
944 } else {
945 /* Setup the hw buffer. */
946 cb->buffer_offset = input->buffer_offset;
947 pipe_resource_reference(&cb->buffer, input->buffer);
948 r600_context_add_resource_size(ctx, input->buffer);
949 }
950
951 state->enabled_mask |= 1 << index;
952 state->dirty_mask |= 1 << index;
953 r600_constant_buffers_dirty(rctx, state);
954 }
955
956 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
957 {
958 struct r600_context *rctx = (struct r600_context*)pipe;
959
960 if (rctx->sample_mask.sample_mask == (uint16_t)sample_mask)
961 return;
962
963 rctx->sample_mask.sample_mask = sample_mask;
964 rctx->sample_mask.atom.dirty = true;
965 }
966
967 /*
968 * On r600/700 hw we don't have vertex fetch swizzle, though TBO
969 * doesn't require full swizzles it does need masking and setting alpha
970 * to one, so we setup a set of 5 constants with the masks + alpha value
971 * then in the shader, we AND the 4 components with 0xffffffff or 0,
972 * then OR the alpha with the value given here.
973 * We use a 6th constant to store the txq buffer size in
974 */
975 static void r600_setup_buffer_constants(struct r600_context *rctx, int shader_type)
976 {
977 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
978 int bits;
979 uint32_t array_size;
980 struct pipe_constant_buffer cb;
981 int i, j;
982
983 if (!samplers->views.dirty_buffer_constants)
984 return;
985
986 samplers->views.dirty_buffer_constants = FALSE;
987
988 bits = util_last_bit(samplers->views.enabled_mask);
989 array_size = bits * 8 * sizeof(uint32_t) * 4;
990 samplers->buffer_constants = realloc(samplers->buffer_constants, array_size);
991 memset(samplers->buffer_constants, 0, array_size);
992 for (i = 0; i < bits; i++) {
993 if (samplers->views.enabled_mask & (1 << i)) {
994 int offset = i * 8;
995 const struct util_format_description *desc;
996 desc = util_format_description(samplers->views.views[i]->base.format);
997
998 for (j = 0; j < 4; j++)
999 if (j < desc->nr_channels)
1000 samplers->buffer_constants[offset+j] = 0xffffffff;
1001 else
1002 samplers->buffer_constants[offset+j] = 0x0;
1003 if (desc->nr_channels < 4) {
1004 if (desc->channel[0].pure_integer)
1005 samplers->buffer_constants[offset+4] = 1;
1006 else
1007 samplers->buffer_constants[offset+4] = 0x3f800000;
1008 } else
1009 samplers->buffer_constants[offset + 4] = 0;
1010
1011 samplers->buffer_constants[offset + 5] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
1012 }
1013 }
1014
1015 cb.buffer = NULL;
1016 cb.user_buffer = samplers->buffer_constants;
1017 cb.buffer_offset = 0;
1018 cb.buffer_size = array_size;
1019 rctx->b.b.set_constant_buffer(&rctx->b.b, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
1020 pipe_resource_reference(&cb.buffer, NULL);
1021 }
1022
1023 /* On evergreen we only need to store the buffer size for TXQ */
1024 static void eg_setup_buffer_constants(struct r600_context *rctx, int shader_type)
1025 {
1026 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1027 int bits;
1028 uint32_t array_size;
1029 struct pipe_constant_buffer cb;
1030 int i;
1031
1032 if (!samplers->views.dirty_buffer_constants)
1033 return;
1034
1035 samplers->views.dirty_buffer_constants = FALSE;
1036
1037 bits = util_last_bit(samplers->views.enabled_mask);
1038 array_size = bits * sizeof(uint32_t) * 4;
1039 samplers->buffer_constants = realloc(samplers->buffer_constants, array_size);
1040 memset(samplers->buffer_constants, 0, array_size);
1041 for (i = 0; i < bits; i++)
1042 if (samplers->views.enabled_mask & (1 << i))
1043 samplers->buffer_constants[i] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
1044
1045 cb.buffer = NULL;
1046 cb.user_buffer = samplers->buffer_constants;
1047 cb.buffer_offset = 0;
1048 cb.buffer_size = array_size;
1049 rctx->b.b.set_constant_buffer(&rctx->b.b, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
1050 pipe_resource_reference(&cb.buffer, NULL);
1051 }
1052
1053 static void r600_setup_txq_cube_array_constants(struct r600_context *rctx, int shader_type)
1054 {
1055 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1056 int bits;
1057 uint32_t array_size;
1058 struct pipe_constant_buffer cb;
1059 int i;
1060
1061 if (!samplers->views.dirty_txq_constants)
1062 return;
1063
1064 samplers->views.dirty_txq_constants = FALSE;
1065
1066 bits = util_last_bit(samplers->views.enabled_mask);
1067 array_size = bits * sizeof(uint32_t) * 4;
1068 samplers->txq_constants = realloc(samplers->txq_constants, array_size);
1069 memset(samplers->txq_constants, 0, array_size);
1070 for (i = 0; i < bits; i++)
1071 if (samplers->views.enabled_mask & (1 << i))
1072 samplers->txq_constants[i] = samplers->views.views[i]->base.texture->array_size / 6;
1073
1074 cb.buffer = NULL;
1075 cb.user_buffer = samplers->txq_constants;
1076 cb.buffer_offset = 0;
1077 cb.buffer_size = array_size;
1078 rctx->b.b.set_constant_buffer(&rctx->b.b, shader_type, R600_TXQ_CONST_BUFFER, &cb);
1079 pipe_resource_reference(&cb.buffer, NULL);
1080 }
1081
1082 static void update_shader_atom(struct pipe_context *ctx,
1083 struct r600_shader_state *state,
1084 struct r600_pipe_shader *shader)
1085 {
1086 state->shader = shader;
1087 if (shader) {
1088 state->atom.num_dw = shader->command_buffer.num_dw;
1089 state->atom.dirty = true;
1090 r600_context_add_resource_size(ctx, (struct pipe_resource *)shader->bo);
1091 } else {
1092 state->atom.num_dw = 0;
1093 state->atom.dirty = false;
1094 }
1095 }
1096
1097 static void update_gs_block_state(struct r600_context *rctx, unsigned enable)
1098 {
1099 if (rctx->shader_stages.geom_enable != enable) {
1100 rctx->shader_stages.geom_enable = enable;
1101 rctx->shader_stages.atom.dirty = true;
1102 }
1103
1104 if (rctx->gs_rings.enable != enable) {
1105 rctx->gs_rings.enable = enable;
1106 rctx->gs_rings.atom.dirty = true;
1107
1108 if (enable && !rctx->gs_rings.esgs_ring.buffer) {
1109 unsigned size = 0x1C000;
1110 rctx->gs_rings.esgs_ring.buffer =
1111 pipe_buffer_create(rctx->b.b.screen, PIPE_BIND_CUSTOM,
1112 PIPE_USAGE_STATIC, size);
1113 rctx->gs_rings.esgs_ring.buffer_size = size;
1114
1115 size = 0x4000000;
1116
1117 rctx->gs_rings.gsvs_ring.buffer =
1118 pipe_buffer_create(rctx->b.b.screen, PIPE_BIND_CUSTOM,
1119 PIPE_USAGE_STATIC, size);
1120 rctx->gs_rings.gsvs_ring.buffer_size = size;
1121 }
1122
1123 if (enable) {
1124 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_GEOMETRY,
1125 R600_GS_RING_CONST_BUFFER, &rctx->gs_rings.esgs_ring);
1126 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
1127 R600_GS_RING_CONST_BUFFER, &rctx->gs_rings.gsvs_ring);
1128 } else {
1129 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_GEOMETRY,
1130 R600_GS_RING_CONST_BUFFER, NULL);
1131 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
1132 R600_GS_RING_CONST_BUFFER, NULL);
1133 }
1134 }
1135 }
1136
1137 static bool r600_update_derived_state(struct r600_context *rctx)
1138 {
1139 struct pipe_context * ctx = (struct pipe_context*)rctx;
1140 bool ps_dirty = false, vs_dirty = false, gs_dirty = false;
1141 bool blend_disable;
1142
1143 if (!rctx->blitter->running) {
1144 unsigned i;
1145
1146 /* Decompress textures if needed. */
1147 for (i = 0; i < PIPE_SHADER_TYPES; i++) {
1148 struct r600_samplerview_state *views = &rctx->samplers[i].views;
1149 if (views->compressed_depthtex_mask) {
1150 r600_decompress_depth_textures(rctx, views);
1151 }
1152 if (views->compressed_colortex_mask) {
1153 r600_decompress_color_textures(rctx, views);
1154 }
1155 }
1156 }
1157
1158 update_gs_block_state(rctx, rctx->gs_shader != NULL);
1159
1160 if (rctx->gs_shader) {
1161 r600_shader_select(ctx, rctx->gs_shader, &gs_dirty);
1162 if (unlikely(!rctx->gs_shader->current))
1163 return false;
1164
1165 if (rctx->b.chip_class >= EVERGREEN && !rctx->shader_stages.geom_enable) {
1166 rctx->shader_stages.geom_enable = true;
1167 rctx->shader_stages.atom.dirty = true;
1168 }
1169
1170 /* gs_shader provides GS and VS (copy shader) */
1171 if (unlikely(rctx->geometry_shader.shader != rctx->gs_shader->current)) {
1172 update_shader_atom(ctx, &rctx->geometry_shader, rctx->gs_shader->current);
1173 update_shader_atom(ctx, &rctx->vertex_shader, rctx->gs_shader->current->gs_copy_shader);
1174 }
1175
1176 r600_shader_select(ctx, rctx->vs_shader, &vs_dirty);
1177 if (unlikely(!rctx->vs_shader->current))
1178 return false;
1179
1180 /* vs_shader is used as ES */
1181 if (unlikely(vs_dirty || rctx->export_shader.shader != rctx->vs_shader->current)) {
1182 update_shader_atom(ctx, &rctx->export_shader, rctx->vs_shader->current);
1183 }
1184 } else {
1185 if (unlikely(rctx->geometry_shader.shader)) {
1186 update_shader_atom(ctx, &rctx->geometry_shader, NULL);
1187 update_shader_atom(ctx, &rctx->export_shader, NULL);
1188 rctx->shader_stages.geom_enable = false;
1189 rctx->shader_stages.atom.dirty = true;
1190 }
1191
1192 r600_shader_select(ctx, rctx->vs_shader, &vs_dirty);
1193 if (unlikely(!rctx->vs_shader->current))
1194 return false;
1195
1196 if (unlikely(vs_dirty || rctx->vertex_shader.shader != rctx->vs_shader->current)) {
1197 update_shader_atom(ctx, &rctx->vertex_shader, rctx->vs_shader->current);
1198
1199 /* Update clip misc state. */
1200 if (rctx->vs_shader->current->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
1201 rctx->vs_shader->current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write) {
1202 rctx->clip_misc_state.pa_cl_vs_out_cntl = rctx->vs_shader->current->pa_cl_vs_out_cntl;
1203 rctx->clip_misc_state.clip_dist_write = rctx->vs_shader->current->shader.clip_dist_write;
1204 rctx->clip_misc_state.atom.dirty = true;
1205 }
1206 }
1207 }
1208
1209 r600_shader_select(ctx, rctx->ps_shader, &ps_dirty);
1210 if (unlikely(!rctx->ps_shader->current))
1211 return false;
1212
1213 if (unlikely(ps_dirty || rctx->pixel_shader.shader != rctx->ps_shader->current)) {
1214
1215 if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
1216 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
1217 rctx->cb_misc_state.atom.dirty = true;
1218 }
1219
1220 if (rctx->b.chip_class <= R700) {
1221 bool multiwrite = rctx->ps_shader->current->shader.fs_write_all;
1222
1223 if (rctx->cb_misc_state.multiwrite != multiwrite) {
1224 rctx->cb_misc_state.multiwrite = multiwrite;
1225 rctx->cb_misc_state.atom.dirty = true;
1226 }
1227 }
1228
1229 if (rctx->b.chip_class >= EVERGREEN) {
1230 evergreen_update_db_shader_control(rctx);
1231 } else {
1232 r600_update_db_shader_control(rctx);
1233 }
1234
1235 if (unlikely(!ps_dirty && rctx->ps_shader && rctx->rasterizer &&
1236 ((rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable) ||
1237 (rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade)))) {
1238
1239 if (rctx->b.chip_class >= EVERGREEN)
1240 evergreen_update_ps_state(ctx, rctx->ps_shader->current);
1241 else
1242 r600_update_ps_state(ctx, rctx->ps_shader->current);
1243 }
1244
1245 update_shader_atom(ctx, &rctx->pixel_shader, rctx->ps_shader->current);
1246 }
1247
1248 /* on R600 we stuff masks + txq info into one constant buffer */
1249 /* on evergreen we only need a txq info one */
1250 if (rctx->b.chip_class < EVERGREEN) {
1251 if (rctx->ps_shader && rctx->ps_shader->current->shader.uses_tex_buffers)
1252 r600_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
1253 if (rctx->vs_shader && rctx->vs_shader->current->shader.uses_tex_buffers)
1254 r600_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
1255 if (rctx->gs_shader && rctx->gs_shader->current->shader.uses_tex_buffers)
1256 r600_setup_buffer_constants(rctx, PIPE_SHADER_GEOMETRY);
1257 } else {
1258 if (rctx->ps_shader && rctx->ps_shader->current->shader.uses_tex_buffers)
1259 eg_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
1260 if (rctx->vs_shader && rctx->vs_shader->current->shader.uses_tex_buffers)
1261 eg_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
1262 if (rctx->gs_shader && rctx->gs_shader->current->shader.uses_tex_buffers)
1263 eg_setup_buffer_constants(rctx, PIPE_SHADER_GEOMETRY);
1264 }
1265
1266
1267 if (rctx->ps_shader && rctx->ps_shader->current->shader.has_txq_cube_array_z_comp)
1268 r600_setup_txq_cube_array_constants(rctx, PIPE_SHADER_FRAGMENT);
1269 if (rctx->vs_shader && rctx->vs_shader->current->shader.has_txq_cube_array_z_comp)
1270 r600_setup_txq_cube_array_constants(rctx, PIPE_SHADER_VERTEX);
1271 if (rctx->gs_shader && rctx->gs_shader->current->shader.has_txq_cube_array_z_comp)
1272 r600_setup_txq_cube_array_constants(rctx, PIPE_SHADER_GEOMETRY);
1273
1274 if (rctx->b.chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
1275 if (!r600_adjust_gprs(rctx)) {
1276 /* discard rendering */
1277 return false;
1278 }
1279 }
1280
1281 blend_disable = (rctx->dual_src_blend &&
1282 rctx->ps_shader->current->nr_ps_color_outputs < 2);
1283
1284 if (blend_disable != rctx->force_blend_disable) {
1285 rctx->force_blend_disable = blend_disable;
1286 r600_bind_blend_state_internal(rctx,
1287 rctx->blend_state.cso,
1288 blend_disable);
1289 }
1290
1291 return true;
1292 }
1293
1294 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1295 {
1296 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1297 struct r600_clip_misc_state *state = &rctx->clip_misc_state;
1298
1299 r600_write_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
1300 state->pa_cl_clip_cntl |
1301 (state->clip_dist_write ? 0 : state->clip_plane_enable & 0x3F));
1302 r600_write_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
1303 state->pa_cl_vs_out_cntl |
1304 (state->clip_plane_enable & state->clip_dist_write));
1305 }
1306
1307 static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
1308 {
1309 struct r600_context *rctx = (struct r600_context *)ctx;
1310 struct pipe_draw_info info = *dinfo;
1311 struct pipe_index_buffer ib = {};
1312 unsigned i;
1313 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1314
1315 if (!info.count && (info.indexed || !info.count_from_stream_output)) {
1316 assert(0);
1317 return;
1318 }
1319
1320 if (!rctx->vs_shader || !rctx->ps_shader) {
1321 assert(0);
1322 return;
1323 }
1324
1325 /* make sure that the gfx ring is only one active */
1326 if (rctx->b.rings.dma.cs) {
1327 rctx->b.rings.dma.flush(rctx, RADEON_FLUSH_ASYNC);
1328 }
1329
1330 if (!r600_update_derived_state(rctx)) {
1331 /* useless to render because current rendering command
1332 * can't be achieved
1333 */
1334 return;
1335 }
1336
1337 if (info.indexed) {
1338 /* Initialize the index buffer struct. */
1339 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
1340 ib.user_buffer = rctx->index_buffer.user_buffer;
1341 ib.index_size = rctx->index_buffer.index_size;
1342 ib.offset = rctx->index_buffer.offset + info.start * ib.index_size;
1343
1344 /* Translate 8-bit indices to 16-bit. */
1345 if (ib.index_size == 1) {
1346 struct pipe_resource *out_buffer = NULL;
1347 unsigned out_offset;
1348 void *ptr;
1349
1350 u_upload_alloc(rctx->b.uploader, 0, info.count * 2,
1351 &out_offset, &out_buffer, &ptr);
1352
1353 util_shorten_ubyte_elts_to_userptr(
1354 &rctx->b.b, &ib, 0, ib.offset, info.count, ptr);
1355
1356 pipe_resource_reference(&ib.buffer, NULL);
1357 ib.user_buffer = NULL;
1358 ib.buffer = out_buffer;
1359 ib.offset = out_offset;
1360 ib.index_size = 2;
1361 }
1362
1363 /* Upload the index buffer.
1364 * The upload is skipped for small index counts on little-endian machines
1365 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
1366 * Note: Instanced rendering in combination with immediate indices hangs. */
1367 if (ib.user_buffer && (R600_BIG_ENDIAN || info.instance_count > 1 ||
1368 info.count*ib.index_size > 20)) {
1369 u_upload_data(rctx->b.uploader, 0, info.count * ib.index_size,
1370 ib.user_buffer, &ib.offset, &ib.buffer);
1371 ib.user_buffer = NULL;
1372 }
1373 } else {
1374 info.index_bias = info.start;
1375 }
1376
1377 /* Set the index offset and primitive restart. */
1378 if (rctx->vgt_state.vgt_multi_prim_ib_reset_en != info.primitive_restart ||
1379 rctx->vgt_state.vgt_multi_prim_ib_reset_indx != info.restart_index ||
1380 rctx->vgt_state.vgt_indx_offset != info.index_bias) {
1381 rctx->vgt_state.vgt_multi_prim_ib_reset_en = info.primitive_restart;
1382 rctx->vgt_state.vgt_multi_prim_ib_reset_indx = info.restart_index;
1383 rctx->vgt_state.vgt_indx_offset = info.index_bias;
1384 rctx->vgt_state.atom.dirty = true;
1385 }
1386
1387 /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
1388 if (rctx->b.chip_class == R600) {
1389 rctx->b.flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
1390 rctx->cb_misc_state.atom.dirty = true;
1391 }
1392
1393 /* Emit states. */
1394 r600_need_cs_space(rctx, ib.user_buffer ? 5 : 0, TRUE);
1395 r600_flush_emit(rctx);
1396
1397 for (i = 0; i < R600_NUM_ATOMS; i++) {
1398 if (rctx->atoms[i] == NULL || !rctx->atoms[i]->dirty) {
1399 continue;
1400 }
1401 r600_emit_atom(rctx, rctx->atoms[i]);
1402 }
1403
1404 /* Update start instance. */
1405 if (rctx->last_start_instance != info.start_instance) {
1406 r600_write_ctl_const(cs, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
1407 rctx->last_start_instance = info.start_instance;
1408 }
1409
1410 /* Update the primitive type. */
1411 if (rctx->last_primitive_type != info.mode) {
1412 unsigned ls_mask = 0;
1413
1414 if (info.mode == PIPE_PRIM_LINES)
1415 ls_mask = 1;
1416 else if (info.mode == PIPE_PRIM_LINE_STRIP ||
1417 info.mode == PIPE_PRIM_LINE_LOOP)
1418 ls_mask = 2;
1419
1420 r600_write_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
1421 S_028A0C_AUTO_RESET_CNTL(ls_mask) |
1422 (rctx->rasterizer ? rctx->rasterizer->pa_sc_line_stipple : 0));
1423 r600_write_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE,
1424 r600_conv_pipe_prim(info.mode));
1425
1426 rctx->last_primitive_type = info.mode;
1427 }
1428
1429 /* Draw packets. */
1430 cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->b.predicate_drawing);
1431 cs->buf[cs->cdw++] = info.instance_count;
1432 if (info.indexed) {
1433 cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->b.predicate_drawing);
1434 cs->buf[cs->cdw++] = ib.index_size == 4 ?
1435 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
1436 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
1437
1438 if (ib.user_buffer) {
1439 unsigned size_bytes = info.count*ib.index_size;
1440 unsigned size_dw = align(size_bytes, 4) / 4;
1441 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_IMMD, 1 + size_dw, rctx->b.predicate_drawing);
1442 cs->buf[cs->cdw++] = info.count;
1443 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_IMMEDIATE;
1444 memcpy(cs->buf+cs->cdw, ib.user_buffer, size_bytes);
1445 cs->cdw += size_dw;
1446 } else {
1447 uint64_t va = r600_resource_va(ctx->screen, ib.buffer) + ib.offset;
1448 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->b.predicate_drawing);
1449 cs->buf[cs->cdw++] = va;
1450 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
1451 cs->buf[cs->cdw++] = info.count;
1452 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
1453 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->b.predicate_drawing);
1454 cs->buf[cs->cdw++] = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
1455 }
1456 } else {
1457 if (info.count_from_stream_output) {
1458 struct r600_so_target *t = (struct r600_so_target*)info.count_from_stream_output;
1459 uint64_t va = r600_resource_va(&rctx->screen->b.b, (void*)t->buf_filled_size) + t->buf_filled_size_offset;
1460
1461 r600_write_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
1462
1463 cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0);
1464 cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG;
1465 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */
1466 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
1467 cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */
1468 cs->buf[cs->cdw++] = 0; /* unused */
1469
1470 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1471 cs->buf[cs->cdw++] = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, t->buf_filled_size, RADEON_USAGE_READ);
1472 }
1473
1474 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->b.predicate_drawing);
1475 cs->buf[cs->cdw++] = info.count;
1476 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
1477 (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
1478 }
1479
1480 if (rctx->screen->b.trace_bo) {
1481 r600_trace_emit(rctx);
1482 }
1483
1484 /* Set the depth buffer as dirty. */
1485 if (rctx->framebuffer.state.zsbuf) {
1486 struct pipe_surface *surf = rctx->framebuffer.state.zsbuf;
1487 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
1488
1489 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1490 }
1491 if (rctx->framebuffer.compressed_cb_mask) {
1492 struct pipe_surface *surf;
1493 struct r600_texture *rtex;
1494 unsigned mask = rctx->framebuffer.compressed_cb_mask;
1495
1496 do {
1497 unsigned i = u_bit_scan(&mask);
1498 surf = rctx->framebuffer.state.cbufs[i];
1499 rtex = (struct r600_texture*)surf->texture;
1500
1501 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1502
1503 } while (mask);
1504 }
1505
1506 pipe_resource_reference(&ib.buffer, NULL);
1507 rctx->b.num_draw_calls++;
1508 }
1509
1510 void r600_draw_rectangle(struct blitter_context *blitter,
1511 int x1, int y1, int x2, int y2, float depth,
1512 enum blitter_attrib_type type, const union pipe_color_union *attrib)
1513 {
1514 struct r600_context *rctx = (struct r600_context*)util_blitter_get_pipe(blitter);
1515 struct pipe_viewport_state viewport;
1516 struct pipe_resource *buf = NULL;
1517 unsigned offset = 0;
1518 float *vb;
1519
1520 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
1521 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
1522 return;
1523 }
1524
1525 /* Some operations (like color resolve on r6xx) don't work
1526 * with the conventional primitive types.
1527 * One that works is PT_RECTLIST, which we use here. */
1528
1529 /* setup viewport */
1530 viewport.scale[0] = 1.0f;
1531 viewport.scale[1] = 1.0f;
1532 viewport.scale[2] = 1.0f;
1533 viewport.scale[3] = 1.0f;
1534 viewport.translate[0] = 0.0f;
1535 viewport.translate[1] = 0.0f;
1536 viewport.translate[2] = 0.0f;
1537 viewport.translate[3] = 0.0f;
1538 rctx->b.b.set_viewport_states(&rctx->b.b, 0, 1, &viewport);
1539
1540 /* Upload vertices. The hw rectangle has only 3 vertices,
1541 * I guess the 4th one is derived from the first 3.
1542 * The vertex specification should match u_blitter's vertex element state. */
1543 u_upload_alloc(rctx->b.uploader, 0, sizeof(float) * 24, &offset, &buf, (void**)&vb);
1544 vb[0] = x1;
1545 vb[1] = y1;
1546 vb[2] = depth;
1547 vb[3] = 1;
1548
1549 vb[8] = x1;
1550 vb[9] = y2;
1551 vb[10] = depth;
1552 vb[11] = 1;
1553
1554 vb[16] = x2;
1555 vb[17] = y1;
1556 vb[18] = depth;
1557 vb[19] = 1;
1558
1559 if (attrib) {
1560 memcpy(vb+4, attrib->f, sizeof(float)*4);
1561 memcpy(vb+12, attrib->f, sizeof(float)*4);
1562 memcpy(vb+20, attrib->f, sizeof(float)*4);
1563 }
1564
1565 /* draw */
1566 util_draw_vertex_buffer(&rctx->b.b, NULL, buf, rctx->blitter->vb_slot, offset,
1567 R600_PRIM_RECTANGLE_LIST, 3, 2);
1568 pipe_resource_reference(&buf, NULL);
1569 }
1570
1571 uint32_t r600_translate_stencil_op(int s_op)
1572 {
1573 switch (s_op) {
1574 case PIPE_STENCIL_OP_KEEP:
1575 return V_028800_STENCIL_KEEP;
1576 case PIPE_STENCIL_OP_ZERO:
1577 return V_028800_STENCIL_ZERO;
1578 case PIPE_STENCIL_OP_REPLACE:
1579 return V_028800_STENCIL_REPLACE;
1580 case PIPE_STENCIL_OP_INCR:
1581 return V_028800_STENCIL_INCR;
1582 case PIPE_STENCIL_OP_DECR:
1583 return V_028800_STENCIL_DECR;
1584 case PIPE_STENCIL_OP_INCR_WRAP:
1585 return V_028800_STENCIL_INCR_WRAP;
1586 case PIPE_STENCIL_OP_DECR_WRAP:
1587 return V_028800_STENCIL_DECR_WRAP;
1588 case PIPE_STENCIL_OP_INVERT:
1589 return V_028800_STENCIL_INVERT;
1590 default:
1591 R600_ERR("Unknown stencil op %d", s_op);
1592 assert(0);
1593 break;
1594 }
1595 return 0;
1596 }
1597
1598 uint32_t r600_translate_fill(uint32_t func)
1599 {
1600 switch(func) {
1601 case PIPE_POLYGON_MODE_FILL:
1602 return 2;
1603 case PIPE_POLYGON_MODE_LINE:
1604 return 1;
1605 case PIPE_POLYGON_MODE_POINT:
1606 return 0;
1607 default:
1608 assert(0);
1609 return 0;
1610 }
1611 }
1612
1613 unsigned r600_tex_wrap(unsigned wrap)
1614 {
1615 switch (wrap) {
1616 default:
1617 case PIPE_TEX_WRAP_REPEAT:
1618 return V_03C000_SQ_TEX_WRAP;
1619 case PIPE_TEX_WRAP_CLAMP:
1620 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1621 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1622 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1623 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1624 return V_03C000_SQ_TEX_CLAMP_BORDER;
1625 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1626 return V_03C000_SQ_TEX_MIRROR;
1627 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1628 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1629 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1630 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1631 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1632 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1633 }
1634 }
1635
1636 unsigned r600_tex_filter(unsigned filter)
1637 {
1638 switch (filter) {
1639 default:
1640 case PIPE_TEX_FILTER_NEAREST:
1641 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1642 case PIPE_TEX_FILTER_LINEAR:
1643 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1644 }
1645 }
1646
1647 unsigned r600_tex_mipfilter(unsigned filter)
1648 {
1649 switch (filter) {
1650 case PIPE_TEX_MIPFILTER_NEAREST:
1651 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1652 case PIPE_TEX_MIPFILTER_LINEAR:
1653 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1654 default:
1655 case PIPE_TEX_MIPFILTER_NONE:
1656 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1657 }
1658 }
1659
1660 unsigned r600_tex_compare(unsigned compare)
1661 {
1662 switch (compare) {
1663 default:
1664 case PIPE_FUNC_NEVER:
1665 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1666 case PIPE_FUNC_LESS:
1667 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1668 case PIPE_FUNC_EQUAL:
1669 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1670 case PIPE_FUNC_LEQUAL:
1671 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1672 case PIPE_FUNC_GREATER:
1673 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1674 case PIPE_FUNC_NOTEQUAL:
1675 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1676 case PIPE_FUNC_GEQUAL:
1677 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1678 case PIPE_FUNC_ALWAYS:
1679 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1680 }
1681 }
1682
1683 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
1684 {
1685 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
1686 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
1687 (linear_filter &&
1688 (wrap == PIPE_TEX_WRAP_CLAMP ||
1689 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
1690 }
1691
1692 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
1693 {
1694 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
1695 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
1696
1697 return (state->border_color.ui[0] || state->border_color.ui[1] ||
1698 state->border_color.ui[2] || state->border_color.ui[3]) &&
1699 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
1700 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
1701 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
1702 }
1703
1704 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a)
1705 {
1706
1707 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1708 struct r600_pipe_shader *shader = ((struct r600_shader_state*)a)->shader;
1709
1710 if (!shader)
1711 return;
1712
1713 r600_emit_command_buffer(cs, &shader->command_buffer);
1714 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1715 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, shader->bo, RADEON_USAGE_READ));
1716 }
1717
1718 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
1719 struct pipe_resource *texture,
1720 const struct pipe_surface *templ,
1721 unsigned width, unsigned height)
1722 {
1723 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
1724
1725 assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level));
1726 assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level));
1727 if (surface == NULL)
1728 return NULL;
1729 pipe_reference_init(&surface->base.reference, 1);
1730 pipe_resource_reference(&surface->base.texture, texture);
1731 surface->base.context = pipe;
1732 surface->base.format = templ->format;
1733 surface->base.width = width;
1734 surface->base.height = height;
1735 surface->base.u = templ->u;
1736 return &surface->base;
1737 }
1738
1739 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
1740 struct pipe_resource *tex,
1741 const struct pipe_surface *templ)
1742 {
1743 unsigned level = templ->u.tex.level;
1744
1745 return r600_create_surface_custom(pipe, tex, templ,
1746 u_minify(tex->width0, level),
1747 u_minify(tex->height0, level));
1748 }
1749
1750 static void r600_surface_destroy(struct pipe_context *pipe,
1751 struct pipe_surface *surface)
1752 {
1753 struct r600_surface *surf = (struct r600_surface*)surface;
1754 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, NULL);
1755 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, NULL);
1756 pipe_resource_reference(&surface->texture, NULL);
1757 FREE(surface);
1758 }
1759
1760 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
1761 const unsigned char *swizzle_view,
1762 boolean vtx)
1763 {
1764 unsigned i;
1765 unsigned char swizzle[4];
1766 unsigned result = 0;
1767 const uint32_t tex_swizzle_shift[4] = {
1768 16, 19, 22, 25,
1769 };
1770 const uint32_t vtx_swizzle_shift[4] = {
1771 3, 6, 9, 12,
1772 };
1773 const uint32_t swizzle_bit[4] = {
1774 0, 1, 2, 3,
1775 };
1776 const uint32_t *swizzle_shift = tex_swizzle_shift;
1777
1778 if (vtx)
1779 swizzle_shift = vtx_swizzle_shift;
1780
1781 if (swizzle_view) {
1782 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
1783 } else {
1784 memcpy(swizzle, swizzle_format, 4);
1785 }
1786
1787 /* Get swizzle. */
1788 for (i = 0; i < 4; i++) {
1789 switch (swizzle[i]) {
1790 case UTIL_FORMAT_SWIZZLE_Y:
1791 result |= swizzle_bit[1] << swizzle_shift[i];
1792 break;
1793 case UTIL_FORMAT_SWIZZLE_Z:
1794 result |= swizzle_bit[2] << swizzle_shift[i];
1795 break;
1796 case UTIL_FORMAT_SWIZZLE_W:
1797 result |= swizzle_bit[3] << swizzle_shift[i];
1798 break;
1799 case UTIL_FORMAT_SWIZZLE_0:
1800 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
1801 break;
1802 case UTIL_FORMAT_SWIZZLE_1:
1803 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
1804 break;
1805 default: /* UTIL_FORMAT_SWIZZLE_X */
1806 result |= swizzle_bit[0] << swizzle_shift[i];
1807 }
1808 }
1809 return result;
1810 }
1811
1812 /* texture format translate */
1813 uint32_t r600_translate_texformat(struct pipe_screen *screen,
1814 enum pipe_format format,
1815 const unsigned char *swizzle_view,
1816 uint32_t *word4_p, uint32_t *yuv_format_p)
1817 {
1818 struct r600_screen *rscreen = (struct r600_screen *)screen;
1819 uint32_t result = 0, word4 = 0, yuv_format = 0;
1820 const struct util_format_description *desc;
1821 boolean uniform = TRUE;
1822 bool enable_s3tc = rscreen->b.info.drm_minor >= 9;
1823 bool is_srgb_valid = FALSE;
1824 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
1825 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
1826
1827 int i;
1828 const uint32_t sign_bit[4] = {
1829 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
1830 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
1831 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
1832 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
1833 };
1834 desc = util_format_description(format);
1835
1836 /* Depth and stencil swizzling is handled separately. */
1837 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS) {
1838 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view, FALSE);
1839 }
1840
1841 /* Colorspace (return non-RGB formats directly). */
1842 switch (desc->colorspace) {
1843 /* Depth stencil formats */
1844 case UTIL_FORMAT_COLORSPACE_ZS:
1845 switch (format) {
1846 /* Depth sampler formats. */
1847 case PIPE_FORMAT_Z16_UNORM:
1848 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1849 result = FMT_16;
1850 goto out_word4;
1851 case PIPE_FORMAT_Z24X8_UNORM:
1852 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1853 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1854 result = FMT_8_24;
1855 goto out_word4;
1856 case PIPE_FORMAT_X8Z24_UNORM:
1857 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1858 if (rscreen->b.chip_class < EVERGREEN)
1859 goto out_unknown;
1860 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
1861 result = FMT_24_8;
1862 goto out_word4;
1863 case PIPE_FORMAT_Z32_FLOAT:
1864 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1865 result = FMT_32_FLOAT;
1866 goto out_word4;
1867 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1868 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1869 result = FMT_X24_8_32_FLOAT;
1870 goto out_word4;
1871 /* Stencil sampler formats. */
1872 case PIPE_FORMAT_S8_UINT:
1873 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1874 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1875 result = FMT_8;
1876 goto out_word4;
1877 case PIPE_FORMAT_X24S8_UINT:
1878 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1879 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
1880 result = FMT_8_24;
1881 goto out_word4;
1882 case PIPE_FORMAT_S8X24_UINT:
1883 if (rscreen->b.chip_class < EVERGREEN)
1884 goto out_unknown;
1885 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1886 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1887 result = FMT_24_8;
1888 goto out_word4;
1889 case PIPE_FORMAT_X32_S8X24_UINT:
1890 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1891 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
1892 result = FMT_X24_8_32_FLOAT;
1893 goto out_word4;
1894 default:
1895 goto out_unknown;
1896 }
1897
1898 case UTIL_FORMAT_COLORSPACE_YUV:
1899 yuv_format |= (1 << 30);
1900 switch (format) {
1901 case PIPE_FORMAT_UYVY:
1902 case PIPE_FORMAT_YUYV:
1903 default:
1904 break;
1905 }
1906 goto out_unknown; /* XXX */
1907
1908 case UTIL_FORMAT_COLORSPACE_SRGB:
1909 word4 |= S_038010_FORCE_DEGAMMA(1);
1910 break;
1911
1912 default:
1913 break;
1914 }
1915
1916 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1917 if (!enable_s3tc)
1918 goto out_unknown;
1919
1920 switch (format) {
1921 case PIPE_FORMAT_RGTC1_SNORM:
1922 case PIPE_FORMAT_LATC1_SNORM:
1923 word4 |= sign_bit[0];
1924 case PIPE_FORMAT_RGTC1_UNORM:
1925 case PIPE_FORMAT_LATC1_UNORM:
1926 result = FMT_BC4;
1927 goto out_word4;
1928 case PIPE_FORMAT_RGTC2_SNORM:
1929 case PIPE_FORMAT_LATC2_SNORM:
1930 word4 |= sign_bit[0] | sign_bit[1];
1931 case PIPE_FORMAT_RGTC2_UNORM:
1932 case PIPE_FORMAT_LATC2_UNORM:
1933 result = FMT_BC5;
1934 goto out_word4;
1935 default:
1936 goto out_unknown;
1937 }
1938 }
1939
1940 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1941
1942 if (!enable_s3tc)
1943 goto out_unknown;
1944
1945 if (!util_format_s3tc_enabled) {
1946 goto out_unknown;
1947 }
1948
1949 switch (format) {
1950 case PIPE_FORMAT_DXT1_RGB:
1951 case PIPE_FORMAT_DXT1_RGBA:
1952 case PIPE_FORMAT_DXT1_SRGB:
1953 case PIPE_FORMAT_DXT1_SRGBA:
1954 result = FMT_BC1;
1955 is_srgb_valid = TRUE;
1956 goto out_word4;
1957 case PIPE_FORMAT_DXT3_RGBA:
1958 case PIPE_FORMAT_DXT3_SRGBA:
1959 result = FMT_BC2;
1960 is_srgb_valid = TRUE;
1961 goto out_word4;
1962 case PIPE_FORMAT_DXT5_RGBA:
1963 case PIPE_FORMAT_DXT5_SRGBA:
1964 result = FMT_BC3;
1965 is_srgb_valid = TRUE;
1966 goto out_word4;
1967 default:
1968 goto out_unknown;
1969 }
1970 }
1971
1972 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1973 switch (format) {
1974 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1975 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1976 result = FMT_GB_GR;
1977 goto out_word4;
1978 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1979 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1980 result = FMT_BG_RG;
1981 goto out_word4;
1982 default:
1983 goto out_unknown;
1984 }
1985 }
1986
1987 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1988 result = FMT_5_9_9_9_SHAREDEXP;
1989 goto out_word4;
1990 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1991 result = FMT_10_11_11_FLOAT;
1992 goto out_word4;
1993 }
1994
1995
1996 for (i = 0; i < desc->nr_channels; i++) {
1997 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1998 word4 |= sign_bit[i];
1999 }
2000 }
2001
2002 /* R8G8Bx_SNORM - XXX CxV8U8 */
2003
2004 /* See whether the components are of the same size. */
2005 for (i = 1; i < desc->nr_channels; i++) {
2006 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
2007 }
2008
2009 /* Non-uniform formats. */
2010 if (!uniform) {
2011 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
2012 desc->channel[0].pure_integer)
2013 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2014 switch(desc->nr_channels) {
2015 case 3:
2016 if (desc->channel[0].size == 5 &&
2017 desc->channel[1].size == 6 &&
2018 desc->channel[2].size == 5) {
2019 result = FMT_5_6_5;
2020 goto out_word4;
2021 }
2022 goto out_unknown;
2023 case 4:
2024 if (desc->channel[0].size == 5 &&
2025 desc->channel[1].size == 5 &&
2026 desc->channel[2].size == 5 &&
2027 desc->channel[3].size == 1) {
2028 result = FMT_1_5_5_5;
2029 goto out_word4;
2030 }
2031 if (desc->channel[0].size == 10 &&
2032 desc->channel[1].size == 10 &&
2033 desc->channel[2].size == 10 &&
2034 desc->channel[3].size == 2) {
2035 result = FMT_2_10_10_10;
2036 goto out_word4;
2037 }
2038 goto out_unknown;
2039 }
2040 goto out_unknown;
2041 }
2042
2043 /* Find the first non-VOID channel. */
2044 for (i = 0; i < 4; i++) {
2045 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2046 break;
2047 }
2048 }
2049
2050 if (i == 4)
2051 goto out_unknown;
2052
2053 /* uniform formats */
2054 switch (desc->channel[i].type) {
2055 case UTIL_FORMAT_TYPE_UNSIGNED:
2056 case UTIL_FORMAT_TYPE_SIGNED:
2057 #if 0
2058 if (!desc->channel[i].normalized &&
2059 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
2060 goto out_unknown;
2061 }
2062 #endif
2063 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
2064 desc->channel[i].pure_integer)
2065 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2066
2067 switch (desc->channel[i].size) {
2068 case 4:
2069 switch (desc->nr_channels) {
2070 case 2:
2071 result = FMT_4_4;
2072 goto out_word4;
2073 case 4:
2074 result = FMT_4_4_4_4;
2075 goto out_word4;
2076 }
2077 goto out_unknown;
2078 case 8:
2079 switch (desc->nr_channels) {
2080 case 1:
2081 result = FMT_8;
2082 goto out_word4;
2083 case 2:
2084 result = FMT_8_8;
2085 goto out_word4;
2086 case 4:
2087 result = FMT_8_8_8_8;
2088 is_srgb_valid = TRUE;
2089 goto out_word4;
2090 }
2091 goto out_unknown;
2092 case 16:
2093 switch (desc->nr_channels) {
2094 case 1:
2095 result = FMT_16;
2096 goto out_word4;
2097 case 2:
2098 result = FMT_16_16;
2099 goto out_word4;
2100 case 4:
2101 result = FMT_16_16_16_16;
2102 goto out_word4;
2103 }
2104 goto out_unknown;
2105 case 32:
2106 switch (desc->nr_channels) {
2107 case 1:
2108 result = FMT_32;
2109 goto out_word4;
2110 case 2:
2111 result = FMT_32_32;
2112 goto out_word4;
2113 case 4:
2114 result = FMT_32_32_32_32;
2115 goto out_word4;
2116 }
2117 }
2118 goto out_unknown;
2119
2120 case UTIL_FORMAT_TYPE_FLOAT:
2121 switch (desc->channel[i].size) {
2122 case 16:
2123 switch (desc->nr_channels) {
2124 case 1:
2125 result = FMT_16_FLOAT;
2126 goto out_word4;
2127 case 2:
2128 result = FMT_16_16_FLOAT;
2129 goto out_word4;
2130 case 4:
2131 result = FMT_16_16_16_16_FLOAT;
2132 goto out_word4;
2133 }
2134 goto out_unknown;
2135 case 32:
2136 switch (desc->nr_channels) {
2137 case 1:
2138 result = FMT_32_FLOAT;
2139 goto out_word4;
2140 case 2:
2141 result = FMT_32_32_FLOAT;
2142 goto out_word4;
2143 case 4:
2144 result = FMT_32_32_32_32_FLOAT;
2145 goto out_word4;
2146 }
2147 }
2148 goto out_unknown;
2149 }
2150
2151 out_word4:
2152
2153 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid)
2154 return ~0;
2155 if (word4_p)
2156 *word4_p = word4;
2157 if (yuv_format_p)
2158 *yuv_format_p = yuv_format;
2159 return result;
2160 out_unknown:
2161 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
2162 return ~0;
2163 }
2164
2165 static void r600_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource *buf)
2166 {
2167 struct r600_context *rctx = (struct r600_context*)ctx;
2168 struct r600_resource *rbuffer = r600_resource(buf);
2169 unsigned i, shader, mask, alignment = rbuffer->buf->alignment;
2170
2171 /* Discard the buffer. */
2172 pb_reference(&rbuffer->buf, NULL);
2173
2174 /* Create a new one in the same pipe_resource. */
2175 r600_init_resource(&rctx->screen->b, rbuffer, rbuffer->b.b.width0, alignment,
2176 TRUE, rbuffer->b.b.usage);
2177
2178 /* We changed the buffer, now we need to bind it where the old one was bound. */
2179 /* Vertex buffers. */
2180 mask = rctx->vertex_buffer_state.enabled_mask;
2181 while (mask) {
2182 i = u_bit_scan(&mask);
2183 if (rctx->vertex_buffer_state.vb[i].buffer == &rbuffer->b.b) {
2184 rctx->vertex_buffer_state.dirty_mask |= 1 << i;
2185 r600_vertex_buffers_dirty(rctx);
2186 }
2187 }
2188 /* Streamout buffers. */
2189 for (i = 0; i < rctx->b.streamout.num_targets; i++) {
2190 if (rctx->b.streamout.targets[i]->b.buffer == &rbuffer->b.b) {
2191 if (rctx->b.streamout.begin_emitted) {
2192 r600_emit_streamout_end(&rctx->b);
2193 }
2194 rctx->b.streamout.append_bitmask = rctx->b.streamout.enabled_mask;
2195 r600_streamout_buffers_dirty(&rctx->b);
2196 }
2197 }
2198
2199 /* Constant buffers. */
2200 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
2201 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
2202 bool found = false;
2203 uint32_t mask = state->enabled_mask;
2204
2205 while (mask) {
2206 unsigned i = u_bit_scan(&mask);
2207 if (state->cb[i].buffer == &rbuffer->b.b) {
2208 found = true;
2209 state->dirty_mask |= 1 << i;
2210 }
2211 }
2212 if (found) {
2213 r600_constant_buffers_dirty(rctx, state);
2214 }
2215 }
2216
2217 /* XXX TODO: texture buffer objects */
2218 }
2219
2220 static void r600_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
2221 {
2222 struct r600_context *rctx = (struct r600_context*)ctx;
2223
2224 if (rctx->db_misc_state.occlusion_query_enabled != enable) {
2225 rctx->db_misc_state.occlusion_query_enabled = enable;
2226 rctx->db_misc_state.atom.dirty = true;
2227 }
2228 }
2229
2230 static void r600_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
2231 bool include_draw_vbo)
2232 {
2233 r600_need_cs_space((struct r600_context*)ctx, num_dw, include_draw_vbo);
2234 }
2235
2236 /* keep this at the end of this file, please */
2237 void r600_init_common_state_functions(struct r600_context *rctx)
2238 {
2239 rctx->b.b.create_fs_state = r600_create_ps_state;
2240 rctx->b.b.create_vs_state = r600_create_vs_state;
2241 rctx->b.b.create_gs_state = r600_create_gs_state;
2242 rctx->b.b.create_vertex_elements_state = r600_create_vertex_fetch_shader;
2243 rctx->b.b.bind_blend_state = r600_bind_blend_state;
2244 rctx->b.b.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
2245 rctx->b.b.bind_sampler_states = r600_bind_sampler_states;
2246 rctx->b.b.bind_fs_state = r600_bind_ps_state;
2247 rctx->b.b.bind_rasterizer_state = r600_bind_rs_state;
2248 rctx->b.b.bind_vertex_elements_state = r600_bind_vertex_elements;
2249 rctx->b.b.bind_vs_state = r600_bind_vs_state;
2250 rctx->b.b.bind_gs_state = r600_bind_gs_state;
2251 rctx->b.b.delete_blend_state = r600_delete_blend_state;
2252 rctx->b.b.delete_depth_stencil_alpha_state = r600_delete_dsa_state;
2253 rctx->b.b.delete_fs_state = r600_delete_ps_state;
2254 rctx->b.b.delete_rasterizer_state = r600_delete_rs_state;
2255 rctx->b.b.delete_sampler_state = r600_delete_sampler_state;
2256 rctx->b.b.delete_vertex_elements_state = r600_delete_vertex_elements;
2257 rctx->b.b.delete_vs_state = r600_delete_vs_state;
2258 rctx->b.b.delete_gs_state = r600_delete_gs_state;
2259 rctx->b.b.set_blend_color = r600_set_blend_color;
2260 rctx->b.b.set_clip_state = r600_set_clip_state;
2261 rctx->b.b.set_constant_buffer = r600_set_constant_buffer;
2262 rctx->b.b.set_sample_mask = r600_set_sample_mask;
2263 rctx->b.b.set_stencil_ref = r600_set_pipe_stencil_ref;
2264 rctx->b.b.set_viewport_states = r600_set_viewport_states;
2265 rctx->b.b.set_vertex_buffers = r600_set_vertex_buffers;
2266 rctx->b.b.set_index_buffer = r600_set_index_buffer;
2267 rctx->b.b.set_sampler_views = r600_set_sampler_views;
2268 rctx->b.b.sampler_view_destroy = r600_sampler_view_destroy;
2269 rctx->b.b.texture_barrier = r600_texture_barrier;
2270 rctx->b.b.set_stream_output_targets = r600_set_streamout_targets;
2271 rctx->b.b.create_surface = r600_create_surface;
2272 rctx->b.b.surface_destroy = r600_surface_destroy;
2273 rctx->b.b.draw_vbo = r600_draw_vbo;
2274 rctx->b.invalidate_buffer = r600_invalidate_buffer;
2275 rctx->b.set_occlusion_query_state = r600_set_occlusion_query_state;
2276 rctx->b.need_gfx_cs_space = r600_need_gfx_cs_space;
2277 }
2278
2279 void r600_trace_emit(struct r600_context *rctx)
2280 {
2281 struct r600_screen *rscreen = rctx->screen;
2282 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2283 uint64_t va;
2284 uint32_t reloc;
2285
2286 va = r600_resource_va(&rscreen->b.b, (void*)rscreen->b.trace_bo);
2287 reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rscreen->b.trace_bo, RADEON_USAGE_READWRITE);
2288 radeon_emit(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
2289 radeon_emit(cs, va & 0xFFFFFFFFUL);
2290 radeon_emit(cs, (va >> 32UL) & 0xFFUL);
2291 radeon_emit(cs, cs->cdw);
2292 radeon_emit(cs, rscreen->b.cs_count);
2293 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2294 radeon_emit(cs, reloc);
2295 }