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radeon: implement pipe_context::bind_sampler_states()
[mesa.git] / src / gallium / drivers / r600 / r600_state_common.c
1 /*
2 * Copyright 2010 Red Hat Inc.
3 * 2010 Jerome Glisse
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
26 */
27 #include "r600_formats.h"
28 #include "r600_shader.h"
29 #include "r600d.h"
30
31 #include "util/u_draw_quad.h"
32 #include "util/u_format_s3tc.h"
33 #include "util/u_index_modify.h"
34 #include "util/u_memory.h"
35 #include "util/u_upload_mgr.h"
36 #include "util/u_math.h"
37 #include "tgsi/tgsi_parse.h"
38
39 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
40
41 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw)
42 {
43 assert(!cb->buf);
44 cb->buf = CALLOC(1, 4 * num_dw);
45 cb->max_num_dw = num_dw;
46 }
47
48 void r600_release_command_buffer(struct r600_command_buffer *cb)
49 {
50 FREE(cb->buf);
51 }
52
53 void r600_init_atom(struct r600_context *rctx,
54 struct r600_atom *atom,
55 unsigned id,
56 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
57 unsigned num_dw)
58 {
59 assert(id < R600_NUM_ATOMS);
60 assert(rctx->atoms[id] == NULL);
61 rctx->atoms[id] = atom;
62 atom->emit = (void*)emit;
63 atom->num_dw = num_dw;
64 atom->dirty = false;
65 }
66
67 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom)
68 {
69 r600_emit_command_buffer(rctx->b.rings.gfx.cs, ((struct r600_cso_state*)atom)->cb);
70 }
71
72 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom)
73 {
74 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
75 struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom;
76 unsigned alpha_ref = a->sx_alpha_ref;
77
78 if (rctx->b.chip_class >= EVERGREEN && a->cb0_export_16bpc) {
79 alpha_ref &= ~0x1FFF;
80 }
81
82 r600_write_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL,
83 a->sx_alpha_test_control |
84 S_028410_ALPHA_TEST_BYPASS(a->bypass));
85 r600_write_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref);
86 }
87
88 static void r600_texture_barrier(struct pipe_context *ctx)
89 {
90 struct r600_context *rctx = (struct r600_context *)ctx;
91
92 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
93 R600_CONTEXT_FLUSH_AND_INV_CB |
94 R600_CONTEXT_FLUSH_AND_INV |
95 R600_CONTEXT_WAIT_3D_IDLE;
96 }
97
98 static unsigned r600_conv_pipe_prim(unsigned prim)
99 {
100 static const unsigned prim_conv[] = {
101 V_008958_DI_PT_POINTLIST,
102 V_008958_DI_PT_LINELIST,
103 V_008958_DI_PT_LINELOOP,
104 V_008958_DI_PT_LINESTRIP,
105 V_008958_DI_PT_TRILIST,
106 V_008958_DI_PT_TRISTRIP,
107 V_008958_DI_PT_TRIFAN,
108 V_008958_DI_PT_QUADLIST,
109 V_008958_DI_PT_QUADSTRIP,
110 V_008958_DI_PT_POLYGON,
111 V_008958_DI_PT_LINELIST_ADJ,
112 V_008958_DI_PT_LINESTRIP_ADJ,
113 V_008958_DI_PT_TRILIST_ADJ,
114 V_008958_DI_PT_TRISTRIP_ADJ,
115 V_008958_DI_PT_RECTLIST
116 };
117 return prim_conv[prim];
118 }
119
120 /* common state between evergreen and r600 */
121
122 static void r600_bind_blend_state_internal(struct r600_context *rctx,
123 struct r600_blend_state *blend, bool blend_disable)
124 {
125 unsigned color_control;
126 bool update_cb = false;
127
128 rctx->alpha_to_one = blend->alpha_to_one;
129 rctx->dual_src_blend = blend->dual_src_blend;
130
131 if (!blend_disable) {
132 r600_set_cso_state_with_cb(&rctx->blend_state, blend, &blend->buffer);
133 color_control = blend->cb_color_control;
134 } else {
135 /* Blending is disabled. */
136 r600_set_cso_state_with_cb(&rctx->blend_state, blend, &blend->buffer_no_blend);
137 color_control = blend->cb_color_control_no_blend;
138 }
139
140 /* Update derived states. */
141 if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) {
142 rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
143 update_cb = true;
144 }
145 if (rctx->b.chip_class <= R700 &&
146 rctx->cb_misc_state.cb_color_control != color_control) {
147 rctx->cb_misc_state.cb_color_control = color_control;
148 update_cb = true;
149 }
150 if (rctx->cb_misc_state.dual_src_blend != blend->dual_src_blend) {
151 rctx->cb_misc_state.dual_src_blend = blend->dual_src_blend;
152 update_cb = true;
153 }
154 if (update_cb) {
155 rctx->cb_misc_state.atom.dirty = true;
156 }
157 }
158
159 static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
160 {
161 struct r600_context *rctx = (struct r600_context *)ctx;
162 struct r600_blend_state *blend = (struct r600_blend_state *)state;
163
164 if (blend == NULL)
165 return;
166
167 r600_bind_blend_state_internal(rctx, blend, rctx->force_blend_disable);
168 }
169
170 static void r600_set_blend_color(struct pipe_context *ctx,
171 const struct pipe_blend_color *state)
172 {
173 struct r600_context *rctx = (struct r600_context *)ctx;
174
175 rctx->blend_color.state = *state;
176 rctx->blend_color.atom.dirty = true;
177 }
178
179 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom)
180 {
181 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
182 struct pipe_blend_color *state = &rctx->blend_color.state;
183
184 r600_write_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
185 radeon_emit(cs, fui(state->color[0])); /* R_028414_CB_BLEND_RED */
186 radeon_emit(cs, fui(state->color[1])); /* R_028418_CB_BLEND_GREEN */
187 radeon_emit(cs, fui(state->color[2])); /* R_02841C_CB_BLEND_BLUE */
188 radeon_emit(cs, fui(state->color[3])); /* R_028420_CB_BLEND_ALPHA */
189 }
190
191 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom)
192 {
193 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
194 struct r600_vgt_state *a = (struct r600_vgt_state *)atom;
195
196 r600_write_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, a->vgt_multi_prim_ib_reset_en);
197 r600_write_context_reg_seq(cs, R_028408_VGT_INDX_OFFSET, 2);
198 radeon_emit(cs, a->vgt_indx_offset); /* R_028408_VGT_INDX_OFFSET */
199 radeon_emit(cs, a->vgt_multi_prim_ib_reset_indx); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
200 }
201
202 static void r600_set_clip_state(struct pipe_context *ctx,
203 const struct pipe_clip_state *state)
204 {
205 struct r600_context *rctx = (struct r600_context *)ctx;
206 struct pipe_constant_buffer cb;
207
208 rctx->clip_state.state = *state;
209 rctx->clip_state.atom.dirty = true;
210
211 cb.buffer = NULL;
212 cb.user_buffer = state->ucp;
213 cb.buffer_offset = 0;
214 cb.buffer_size = 4*4*8;
215 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, R600_UCP_CONST_BUFFER, &cb);
216 pipe_resource_reference(&cb.buffer, NULL);
217 }
218
219 static void r600_set_stencil_ref(struct pipe_context *ctx,
220 const struct r600_stencil_ref *state)
221 {
222 struct r600_context *rctx = (struct r600_context *)ctx;
223
224 rctx->stencil_ref.state = *state;
225 rctx->stencil_ref.atom.dirty = true;
226 }
227
228 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom)
229 {
230 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
231 struct r600_stencil_ref_state *a = (struct r600_stencil_ref_state*)atom;
232
233 r600_write_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
234 radeon_emit(cs, /* R_028430_DB_STENCILREFMASK */
235 S_028430_STENCILREF(a->state.ref_value[0]) |
236 S_028430_STENCILMASK(a->state.valuemask[0]) |
237 S_028430_STENCILWRITEMASK(a->state.writemask[0]));
238 radeon_emit(cs, /* R_028434_DB_STENCILREFMASK_BF */
239 S_028434_STENCILREF_BF(a->state.ref_value[1]) |
240 S_028434_STENCILMASK_BF(a->state.valuemask[1]) |
241 S_028434_STENCILWRITEMASK_BF(a->state.writemask[1]));
242 }
243
244 static void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
245 const struct pipe_stencil_ref *state)
246 {
247 struct r600_context *rctx = (struct r600_context *)ctx;
248 struct r600_dsa_state *dsa = (struct r600_dsa_state*)rctx->dsa_state.cso;
249 struct r600_stencil_ref ref;
250
251 rctx->stencil_ref.pipe_state = *state;
252
253 if (!dsa)
254 return;
255
256 ref.ref_value[0] = state->ref_value[0];
257 ref.ref_value[1] = state->ref_value[1];
258 ref.valuemask[0] = dsa->valuemask[0];
259 ref.valuemask[1] = dsa->valuemask[1];
260 ref.writemask[0] = dsa->writemask[0];
261 ref.writemask[1] = dsa->writemask[1];
262
263 r600_set_stencil_ref(ctx, &ref);
264 }
265
266 static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
267 {
268 struct r600_context *rctx = (struct r600_context *)ctx;
269 struct r600_dsa_state *dsa = state;
270 struct r600_stencil_ref ref;
271
272 if (state == NULL)
273 return;
274
275 r600_set_cso_state_with_cb(&rctx->dsa_state, dsa, &dsa->buffer);
276
277 ref.ref_value[0] = rctx->stencil_ref.pipe_state.ref_value[0];
278 ref.ref_value[1] = rctx->stencil_ref.pipe_state.ref_value[1];
279 ref.valuemask[0] = dsa->valuemask[0];
280 ref.valuemask[1] = dsa->valuemask[1];
281 ref.writemask[0] = dsa->writemask[0];
282 ref.writemask[1] = dsa->writemask[1];
283 if (rctx->zwritemask != dsa->zwritemask) {
284 rctx->zwritemask = dsa->zwritemask;
285 if (rctx->b.chip_class >= EVERGREEN) {
286 /* work around some issue when not writting to zbuffer
287 * we are having lockup on evergreen so do not enable
288 * hyperz when not writting zbuffer
289 */
290 rctx->db_misc_state.atom.dirty = true;
291 }
292 }
293
294 r600_set_stencil_ref(ctx, &ref);
295
296 /* Update alphatest state. */
297 if (rctx->alphatest_state.sx_alpha_test_control != dsa->sx_alpha_test_control ||
298 rctx->alphatest_state.sx_alpha_ref != dsa->alpha_ref) {
299 rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control;
300 rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref;
301 rctx->alphatest_state.atom.dirty = true;
302 if (rctx->b.chip_class >= EVERGREEN) {
303 evergreen_update_db_shader_control(rctx);
304 } else {
305 r600_update_db_shader_control(rctx);
306 }
307 }
308 }
309
310 static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
311 {
312 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
313 struct r600_context *rctx = (struct r600_context *)ctx;
314
315 if (state == NULL)
316 return;
317
318 rctx->rasterizer = rs;
319
320 r600_set_cso_state_with_cb(&rctx->rasterizer_state, rs, &rs->buffer);
321
322 if (rs->offset_enable &&
323 (rs->offset_units != rctx->poly_offset_state.offset_units ||
324 rs->offset_scale != rctx->poly_offset_state.offset_scale)) {
325 rctx->poly_offset_state.offset_units = rs->offset_units;
326 rctx->poly_offset_state.offset_scale = rs->offset_scale;
327 rctx->poly_offset_state.atom.dirty = true;
328 }
329
330 /* Update clip_misc_state. */
331 if (rctx->clip_misc_state.pa_cl_clip_cntl != rs->pa_cl_clip_cntl ||
332 rctx->clip_misc_state.clip_plane_enable != rs->clip_plane_enable) {
333 rctx->clip_misc_state.pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
334 rctx->clip_misc_state.clip_plane_enable = rs->clip_plane_enable;
335 rctx->clip_misc_state.atom.dirty = true;
336 }
337
338 /* Workaround for a missing scissor enable on r600. */
339 if (rctx->b.chip_class == R600 &&
340 rs->scissor_enable != rctx->scissor.enable) {
341 rctx->scissor.enable = rs->scissor_enable;
342 rctx->scissor.atom.dirty = true;
343 }
344
345 /* Re-emit PA_SC_LINE_STIPPLE. */
346 rctx->last_primitive_type = -1;
347 }
348
349 static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
350 {
351 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
352
353 r600_release_command_buffer(&rs->buffer);
354 FREE(rs);
355 }
356
357 static void r600_sampler_view_destroy(struct pipe_context *ctx,
358 struct pipe_sampler_view *state)
359 {
360 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
361
362 pipe_resource_reference(&state->texture, NULL);
363 FREE(resource);
364 }
365
366 void r600_sampler_states_dirty(struct r600_context *rctx,
367 struct r600_sampler_states *state)
368 {
369 if (state->dirty_mask) {
370 if (state->dirty_mask & state->has_bordercolor_mask) {
371 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
372 }
373 state->atom.num_dw =
374 util_bitcount(state->dirty_mask & state->has_bordercolor_mask) * 11 +
375 util_bitcount(state->dirty_mask & ~state->has_bordercolor_mask) * 5;
376 state->atom.dirty = true;
377 }
378 }
379
380 static void r600_bind_sampler_states(struct pipe_context *pipe,
381 unsigned shader,
382 unsigned start,
383 unsigned count, void **states)
384 {
385 struct r600_context *rctx = (struct r600_context *)pipe;
386 struct r600_textures_info *dst = &rctx->samplers[shader];
387 struct r600_pipe_sampler_state **rstates = (struct r600_pipe_sampler_state**)states;
388 int seamless_cube_map = -1;
389 unsigned i;
390 /* This sets 1-bit for states with index >= count. */
391 uint32_t disable_mask = ~((1ull << count) - 1);
392 /* These are the new states set by this function. */
393 uint32_t new_mask = 0;
394
395 assert(start == 0); /* XXX fix below */
396
397 for (i = 0; i < count; i++) {
398 struct r600_pipe_sampler_state *rstate = rstates[i];
399
400 if (rstate == dst->states.states[i]) {
401 continue;
402 }
403
404 if (rstate) {
405 if (rstate->border_color_use) {
406 dst->states.has_bordercolor_mask |= 1 << i;
407 } else {
408 dst->states.has_bordercolor_mask &= ~(1 << i);
409 }
410 seamless_cube_map = rstate->seamless_cube_map;
411
412 new_mask |= 1 << i;
413 } else {
414 disable_mask |= 1 << i;
415 }
416 }
417
418 memcpy(dst->states.states, rstates, sizeof(void*) * count);
419 memset(dst->states.states + count, 0, sizeof(void*) * (NUM_TEX_UNITS - count));
420
421 dst->states.enabled_mask &= ~disable_mask;
422 dst->states.dirty_mask &= dst->states.enabled_mask;
423 dst->states.enabled_mask |= new_mask;
424 dst->states.dirty_mask |= new_mask;
425 dst->states.has_bordercolor_mask &= dst->states.enabled_mask;
426
427 r600_sampler_states_dirty(rctx, &dst->states);
428
429 /* Seamless cubemap state. */
430 if (rctx->b.chip_class <= R700 &&
431 seamless_cube_map != -1 &&
432 seamless_cube_map != rctx->seamless_cube_map.enabled) {
433 /* change in TA_CNTL_AUX need a pipeline flush */
434 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
435 rctx->seamless_cube_map.enabled = seamless_cube_map;
436 rctx->seamless_cube_map.atom.dirty = true;
437 }
438 }
439
440 static void r600_bind_vs_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
441 {
442 r600_bind_sampler_states(ctx, PIPE_SHADER_VERTEX, 0, count, states);
443 }
444
445 static void r600_bind_ps_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
446 {
447 r600_bind_sampler_states(ctx, PIPE_SHADER_FRAGMENT, 0, count, states);
448 }
449
450 static void r600_delete_sampler_state(struct pipe_context *ctx, void *state)
451 {
452 free(state);
453 }
454
455 static void r600_delete_blend_state(struct pipe_context *ctx, void *state)
456 {
457 struct r600_blend_state *blend = (struct r600_blend_state*)state;
458
459 r600_release_command_buffer(&blend->buffer);
460 r600_release_command_buffer(&blend->buffer_no_blend);
461 FREE(blend);
462 }
463
464 static void r600_delete_dsa_state(struct pipe_context *ctx, void *state)
465 {
466 struct r600_dsa_state *dsa = (struct r600_dsa_state *)state;
467
468 r600_release_command_buffer(&dsa->buffer);
469 free(dsa);
470 }
471
472 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
473 {
474 struct r600_context *rctx = (struct r600_context *)ctx;
475
476 r600_set_cso_state(&rctx->vertex_fetch_shader, state);
477 }
478
479 static void r600_delete_vertex_elements(struct pipe_context *ctx, void *state)
480 {
481 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state;
482 pipe_resource_reference((struct pipe_resource**)&shader->buffer, NULL);
483 FREE(shader);
484 }
485
486 static void r600_set_index_buffer(struct pipe_context *ctx,
487 const struct pipe_index_buffer *ib)
488 {
489 struct r600_context *rctx = (struct r600_context *)ctx;
490
491 if (ib) {
492 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
493 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
494 r600_context_add_resource_size(ctx, ib->buffer);
495 } else {
496 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
497 }
498 }
499
500 void r600_vertex_buffers_dirty(struct r600_context *rctx)
501 {
502 if (rctx->vertex_buffer_state.dirty_mask) {
503 rctx->b.flags |= R600_CONTEXT_INV_VERTEX_CACHE;
504 rctx->vertex_buffer_state.atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 12 : 11) *
505 util_bitcount(rctx->vertex_buffer_state.dirty_mask);
506 rctx->vertex_buffer_state.atom.dirty = true;
507 }
508 }
509
510 static void r600_set_vertex_buffers(struct pipe_context *ctx,
511 unsigned start_slot, unsigned count,
512 const struct pipe_vertex_buffer *input)
513 {
514 struct r600_context *rctx = (struct r600_context *)ctx;
515 struct r600_vertexbuf_state *state = &rctx->vertex_buffer_state;
516 struct pipe_vertex_buffer *vb = state->vb + start_slot;
517 unsigned i;
518 uint32_t disable_mask = 0;
519 /* These are the new buffers set by this function. */
520 uint32_t new_buffer_mask = 0;
521
522 /* Set vertex buffers. */
523 if (input) {
524 for (i = 0; i < count; i++) {
525 if (memcmp(&input[i], &vb[i], sizeof(struct pipe_vertex_buffer))) {
526 if (input[i].buffer) {
527 vb[i].stride = input[i].stride;
528 vb[i].buffer_offset = input[i].buffer_offset;
529 pipe_resource_reference(&vb[i].buffer, input[i].buffer);
530 new_buffer_mask |= 1 << i;
531 r600_context_add_resource_size(ctx, input[i].buffer);
532 } else {
533 pipe_resource_reference(&vb[i].buffer, NULL);
534 disable_mask |= 1 << i;
535 }
536 }
537 }
538 } else {
539 for (i = 0; i < count; i++) {
540 pipe_resource_reference(&vb[i].buffer, NULL);
541 }
542 disable_mask = ((1ull << count) - 1);
543 }
544
545 disable_mask <<= start_slot;
546 new_buffer_mask <<= start_slot;
547
548 rctx->vertex_buffer_state.enabled_mask &= ~disable_mask;
549 rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask;
550 rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask;
551 rctx->vertex_buffer_state.dirty_mask |= new_buffer_mask;
552
553 r600_vertex_buffers_dirty(rctx);
554 }
555
556 void r600_sampler_views_dirty(struct r600_context *rctx,
557 struct r600_samplerview_state *state)
558 {
559 if (state->dirty_mask) {
560 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
561 state->atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 14 : 13) *
562 util_bitcount(state->dirty_mask);
563 state->atom.dirty = true;
564 }
565 }
566
567 static void r600_set_sampler_views(struct pipe_context *pipe, unsigned shader,
568 unsigned start, unsigned count,
569 struct pipe_sampler_view **views)
570 {
571 struct r600_context *rctx = (struct r600_context *) pipe;
572 struct r600_textures_info *dst = &rctx->samplers[shader];
573 struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
574 uint32_t dirty_sampler_states_mask = 0;
575 unsigned i;
576 /* This sets 1-bit for textures with index >= count. */
577 uint32_t disable_mask = ~((1ull << count) - 1);
578 /* These are the new textures set by this function. */
579 uint32_t new_mask = 0;
580
581 /* Set textures with index >= count to NULL. */
582 uint32_t remaining_mask;
583
584 assert(start == 0); /* XXX fix below */
585
586 remaining_mask = dst->views.enabled_mask & disable_mask;
587
588 while (remaining_mask) {
589 i = u_bit_scan(&remaining_mask);
590 assert(dst->views.views[i]);
591
592 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
593 }
594
595 for (i = 0; i < count; i++) {
596 if (rviews[i] == dst->views.views[i]) {
597 continue;
598 }
599
600 if (rviews[i]) {
601 struct r600_texture *rtex =
602 (struct r600_texture*)rviews[i]->base.texture;
603
604 if (rviews[i]->base.texture->target != PIPE_BUFFER) {
605 if (rtex->is_depth && !rtex->is_flushing_texture) {
606 dst->views.compressed_depthtex_mask |= 1 << i;
607 } else {
608 dst->views.compressed_depthtex_mask &= ~(1 << i);
609 }
610
611 /* Track compressed colorbuffers. */
612 if (rtex->cmask.size) {
613 dst->views.compressed_colortex_mask |= 1 << i;
614 } else {
615 dst->views.compressed_colortex_mask &= ~(1 << i);
616 }
617 }
618 /* Changing from array to non-arrays textures and vice versa requires
619 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
620 if (rctx->b.chip_class <= R700 &&
621 (dst->states.enabled_mask & (1 << i)) &&
622 (rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
623 rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) {
624 dirty_sampler_states_mask |= 1 << i;
625 }
626
627 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]);
628 new_mask |= 1 << i;
629 r600_context_add_resource_size(pipe, views[i]->texture);
630 } else {
631 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
632 disable_mask |= 1 << i;
633 }
634 }
635
636 dst->views.enabled_mask &= ~disable_mask;
637 dst->views.dirty_mask &= dst->views.enabled_mask;
638 dst->views.enabled_mask |= new_mask;
639 dst->views.dirty_mask |= new_mask;
640 dst->views.compressed_depthtex_mask &= dst->views.enabled_mask;
641 dst->views.compressed_colortex_mask &= dst->views.enabled_mask;
642 dst->views.dirty_txq_constants = TRUE;
643 dst->views.dirty_buffer_constants = TRUE;
644 r600_sampler_views_dirty(rctx, &dst->views);
645
646 if (dirty_sampler_states_mask) {
647 dst->states.dirty_mask |= dirty_sampler_states_mask;
648 r600_sampler_states_dirty(rctx, &dst->states);
649 }
650 }
651
652 static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
653 struct pipe_sampler_view **views)
654 {
655 r600_set_sampler_views(ctx, PIPE_SHADER_VERTEX, 0, count, views);
656 }
657
658 static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
659 struct pipe_sampler_view **views)
660 {
661 r600_set_sampler_views(ctx, PIPE_SHADER_FRAGMENT, 0, count, views);
662 }
663
664 static void r600_set_viewport_states(struct pipe_context *ctx,
665 unsigned start_slot,
666 unsigned num_viewports,
667 const struct pipe_viewport_state *state)
668 {
669 struct r600_context *rctx = (struct r600_context *)ctx;
670
671 rctx->viewport.state = *state;
672 rctx->viewport.atom.dirty = true;
673 }
674
675 void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom)
676 {
677 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
678 struct pipe_viewport_state *state = &rctx->viewport.state;
679
680 r600_write_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE_0, 6);
681 radeon_emit(cs, fui(state->scale[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
682 radeon_emit(cs, fui(state->translate[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
683 radeon_emit(cs, fui(state->scale[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
684 radeon_emit(cs, fui(state->translate[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
685 radeon_emit(cs, fui(state->scale[2])); /* R_02844C_PA_CL_VPORT_ZSCALE_0 */
686 radeon_emit(cs, fui(state->translate[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
687 }
688
689 /* Compute the key for the hw shader variant */
690 static INLINE struct r600_shader_key r600_shader_selector_key(struct pipe_context * ctx,
691 struct r600_pipe_shader_selector * sel)
692 {
693 struct r600_context *rctx = (struct r600_context *)ctx;
694 struct r600_shader_key key;
695 memset(&key, 0, sizeof(key));
696
697 if (sel->type == PIPE_SHADER_FRAGMENT) {
698 key.color_two_side = rctx->rasterizer && rctx->rasterizer->two_side;
699 key.alpha_to_one = rctx->alpha_to_one &&
700 rctx->rasterizer && rctx->rasterizer->multisample_enable &&
701 !rctx->framebuffer.cb0_is_integer;
702 key.nr_cbufs = rctx->framebuffer.state.nr_cbufs;
703 /* Dual-source blending only makes sense with nr_cbufs == 1. */
704 if (key.nr_cbufs == 1 && rctx->dual_src_blend)
705 key.nr_cbufs = 2;
706 }
707 return key;
708 }
709
710 /* Select the hw shader variant depending on the current state.
711 * (*dirty) is set to 1 if current variant was changed */
712 static int r600_shader_select(struct pipe_context *ctx,
713 struct r600_pipe_shader_selector* sel,
714 bool *dirty)
715 {
716 struct r600_shader_key key;
717 struct r600_context *rctx = (struct r600_context *)ctx;
718 struct r600_pipe_shader * shader = NULL;
719 int r;
720
721 memset(&key, 0, sizeof(key));
722 key = r600_shader_selector_key(ctx, sel);
723
724 /* Check if we don't need to change anything.
725 * This path is also used for most shaders that don't need multiple
726 * variants, it will cost just a computation of the key and this
727 * test. */
728 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
729 return 0;
730 }
731
732 /* lookup if we have other variants in the list */
733 if (sel->num_shaders > 1) {
734 struct r600_pipe_shader *p = sel->current, *c = p->next_variant;
735
736 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
737 p = c;
738 c = c->next_variant;
739 }
740
741 if (c) {
742 p->next_variant = c->next_variant;
743 shader = c;
744 }
745 }
746
747 if (unlikely(!shader)) {
748 shader = CALLOC(1, sizeof(struct r600_pipe_shader));
749 shader->selector = sel;
750
751 r = r600_pipe_shader_create(ctx, shader, key);
752 if (unlikely(r)) {
753 R600_ERR("Failed to build shader variant (type=%u) %d\n",
754 sel->type, r);
755 sel->current = NULL;
756 FREE(shader);
757 return r;
758 }
759
760 /* We don't know the value of nr_ps_max_color_exports until we built
761 * at least one variant, so we may need to recompute the key after
762 * building first variant. */
763 if (sel->type == PIPE_SHADER_FRAGMENT &&
764 sel->num_shaders == 0) {
765 sel->nr_ps_max_color_exports = shader->shader.nr_ps_max_color_exports;
766 key = r600_shader_selector_key(ctx, sel);
767 }
768
769 memcpy(&shader->key, &key, sizeof(key));
770 sel->num_shaders++;
771 }
772
773 if (dirty)
774 *dirty = true;
775
776 shader->next_variant = sel->current;
777 sel->current = shader;
778
779 if (rctx->ps_shader &&
780 rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
781 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
782 rctx->cb_misc_state.atom.dirty = true;
783 }
784 return 0;
785 }
786
787 static void *r600_create_shader_state(struct pipe_context *ctx,
788 const struct pipe_shader_state *state,
789 unsigned pipe_shader_type)
790 {
791 struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector);
792 int r;
793
794 sel->type = pipe_shader_type;
795 sel->tokens = tgsi_dup_tokens(state->tokens);
796 sel->so = state->stream_output;
797
798 r = r600_shader_select(ctx, sel, NULL);
799 if (r)
800 return NULL;
801
802 return sel;
803 }
804
805 static void *r600_create_ps_state(struct pipe_context *ctx,
806 const struct pipe_shader_state *state)
807 {
808 return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
809 }
810
811 static void *r600_create_vs_state(struct pipe_context *ctx,
812 const struct pipe_shader_state *state)
813 {
814 return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
815 }
816
817 static void r600_bind_ps_state(struct pipe_context *ctx, void *state)
818 {
819 struct r600_context *rctx = (struct r600_context *)ctx;
820
821 if (!state)
822 state = rctx->dummy_pixel_shader;
823
824 rctx->pixel_shader.shader = rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
825 rctx->pixel_shader.atom.num_dw = rctx->ps_shader->current->command_buffer.num_dw;
826 rctx->pixel_shader.atom.dirty = true;
827
828 r600_context_add_resource_size(ctx, (struct pipe_resource *)rctx->ps_shader->current->bo);
829
830 if (rctx->b.chip_class <= R700) {
831 bool multiwrite = rctx->ps_shader->current->shader.fs_write_all;
832
833 if (rctx->cb_misc_state.multiwrite != multiwrite) {
834 rctx->cb_misc_state.multiwrite = multiwrite;
835 rctx->cb_misc_state.atom.dirty = true;
836 }
837 }
838
839 if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
840 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
841 rctx->cb_misc_state.atom.dirty = true;
842 }
843
844 if (rctx->b.chip_class >= EVERGREEN) {
845 evergreen_update_db_shader_control(rctx);
846 } else {
847 r600_update_db_shader_control(rctx);
848 }
849 }
850
851 static void r600_bind_vs_state(struct pipe_context *ctx, void *state)
852 {
853 struct r600_context *rctx = (struct r600_context *)ctx;
854
855 if (!state)
856 return;
857
858 rctx->vertex_shader.shader = rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
859 rctx->vertex_shader.atom.dirty = true;
860 rctx->b.streamout.stride_in_dw = rctx->vs_shader->so.stride;
861
862 r600_context_add_resource_size(ctx, (struct pipe_resource *)rctx->vs_shader->current->bo);
863
864 /* Update clip misc state. */
865 if (rctx->vs_shader->current->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
866 rctx->vs_shader->current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write) {
867 rctx->clip_misc_state.pa_cl_vs_out_cntl = rctx->vs_shader->current->pa_cl_vs_out_cntl;
868 rctx->clip_misc_state.clip_dist_write = rctx->vs_shader->current->shader.clip_dist_write;
869 rctx->clip_misc_state.atom.dirty = true;
870 }
871 }
872
873 static void r600_delete_shader_selector(struct pipe_context *ctx,
874 struct r600_pipe_shader_selector *sel)
875 {
876 struct r600_pipe_shader *p = sel->current, *c;
877 while (p) {
878 c = p->next_variant;
879 r600_pipe_shader_destroy(ctx, p);
880 free(p);
881 p = c;
882 }
883
884 free(sel->tokens);
885 free(sel);
886 }
887
888
889 static void r600_delete_ps_state(struct pipe_context *ctx, void *state)
890 {
891 struct r600_context *rctx = (struct r600_context *)ctx;
892 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
893
894 if (rctx->ps_shader == sel) {
895 rctx->ps_shader = NULL;
896 }
897
898 r600_delete_shader_selector(ctx, sel);
899 }
900
901 static void r600_delete_vs_state(struct pipe_context *ctx, void *state)
902 {
903 struct r600_context *rctx = (struct r600_context *)ctx;
904 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
905
906 if (rctx->vs_shader == sel) {
907 rctx->vs_shader = NULL;
908 }
909
910 r600_delete_shader_selector(ctx, sel);
911 }
912
913 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
914 {
915 if (state->dirty_mask) {
916 rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE;
917 state->atom.num_dw = rctx->b.chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
918 : util_bitcount(state->dirty_mask)*19;
919 state->atom.dirty = true;
920 }
921 }
922
923 static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
924 struct pipe_constant_buffer *input)
925 {
926 struct r600_context *rctx = (struct r600_context *)ctx;
927 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
928 struct pipe_constant_buffer *cb;
929 const uint8_t *ptr;
930
931 /* Note that the state tracker can unbind constant buffers by
932 * passing NULL here.
933 */
934 if (unlikely(!input || (!input->buffer && !input->user_buffer))) {
935 state->enabled_mask &= ~(1 << index);
936 state->dirty_mask &= ~(1 << index);
937 pipe_resource_reference(&state->cb[index].buffer, NULL);
938 return;
939 }
940
941 cb = &state->cb[index];
942 cb->buffer_size = input->buffer_size;
943
944 ptr = input->user_buffer;
945
946 if (ptr) {
947 /* Upload the user buffer. */
948 if (R600_BIG_ENDIAN) {
949 uint32_t *tmpPtr;
950 unsigned i, size = input->buffer_size;
951
952 if (!(tmpPtr = malloc(size))) {
953 R600_ERR("Failed to allocate BE swap buffer.\n");
954 return;
955 }
956
957 for (i = 0; i < size / 4; ++i) {
958 tmpPtr[i] = util_bswap32(((uint32_t *)ptr)[i]);
959 }
960
961 u_upload_data(rctx->uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer);
962 free(tmpPtr);
963 } else {
964 u_upload_data(rctx->uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer);
965 }
966 /* account it in gtt */
967 rctx->b.gtt += input->buffer_size;
968 } else {
969 /* Setup the hw buffer. */
970 cb->buffer_offset = input->buffer_offset;
971 pipe_resource_reference(&cb->buffer, input->buffer);
972 r600_context_add_resource_size(ctx, input->buffer);
973 }
974
975 state->enabled_mask |= 1 << index;
976 state->dirty_mask |= 1 << index;
977 r600_constant_buffers_dirty(rctx, state);
978 }
979
980 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
981 {
982 struct r600_context *rctx = (struct r600_context*)pipe;
983
984 if (rctx->sample_mask.sample_mask == (uint16_t)sample_mask)
985 return;
986
987 rctx->sample_mask.sample_mask = sample_mask;
988 rctx->sample_mask.atom.dirty = true;
989 }
990
991 /*
992 * On r600/700 hw we don't have vertex fetch swizzle, though TBO
993 * doesn't require full swizzles it does need masking and setting alpha
994 * to one, so we setup a set of 5 constants with the masks + alpha value
995 * then in the shader, we AND the 4 components with 0xffffffff or 0,
996 * then OR the alpha with the value given here.
997 * We use a 6th constant to store the txq buffer size in
998 */
999 static void r600_setup_buffer_constants(struct r600_context *rctx, int shader_type)
1000 {
1001 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1002 int bits;
1003 uint32_t array_size;
1004 struct pipe_constant_buffer cb;
1005 int i, j;
1006
1007 if (!samplers->views.dirty_buffer_constants)
1008 return;
1009
1010 samplers->views.dirty_buffer_constants = FALSE;
1011
1012 bits = util_last_bit(samplers->views.enabled_mask);
1013 array_size = bits * 8 * sizeof(uint32_t) * 4;
1014 samplers->buffer_constants = realloc(samplers->buffer_constants, array_size);
1015 memset(samplers->buffer_constants, 0, array_size);
1016 for (i = 0; i < bits; i++) {
1017 if (samplers->views.enabled_mask & (1 << i)) {
1018 int offset = i * 8;
1019 const struct util_format_description *desc;
1020 desc = util_format_description(samplers->views.views[i]->base.format);
1021
1022 for (j = 0; j < 4; j++)
1023 if (j < desc->nr_channels)
1024 samplers->buffer_constants[offset+j] = 0xffffffff;
1025 else
1026 samplers->buffer_constants[offset+j] = 0x0;
1027 if (desc->nr_channels < 4) {
1028 if (desc->channel[0].pure_integer)
1029 samplers->buffer_constants[offset+4] = 1;
1030 else
1031 samplers->buffer_constants[offset+4] = 0x3f800000;
1032 } else
1033 samplers->buffer_constants[offset + 4] = 0;
1034
1035 samplers->buffer_constants[offset + 5] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
1036 }
1037 }
1038
1039 cb.buffer = NULL;
1040 cb.user_buffer = samplers->buffer_constants;
1041 cb.buffer_offset = 0;
1042 cb.buffer_size = array_size;
1043 rctx->b.b.set_constant_buffer(&rctx->b.b, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
1044 pipe_resource_reference(&cb.buffer, NULL);
1045 }
1046
1047 /* On evergreen we only need to store the buffer size for TXQ */
1048 static void eg_setup_buffer_constants(struct r600_context *rctx, int shader_type)
1049 {
1050 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1051 int bits;
1052 uint32_t array_size;
1053 struct pipe_constant_buffer cb;
1054 int i;
1055
1056 if (!samplers->views.dirty_buffer_constants)
1057 return;
1058
1059 samplers->views.dirty_buffer_constants = FALSE;
1060
1061 bits = util_last_bit(samplers->views.enabled_mask);
1062 array_size = bits * sizeof(uint32_t) * 4;
1063 samplers->buffer_constants = realloc(samplers->buffer_constants, array_size);
1064 memset(samplers->buffer_constants, 0, array_size);
1065 for (i = 0; i < bits; i++)
1066 if (samplers->views.enabled_mask & (1 << i))
1067 samplers->buffer_constants[i] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
1068
1069 cb.buffer = NULL;
1070 cb.user_buffer = samplers->buffer_constants;
1071 cb.buffer_offset = 0;
1072 cb.buffer_size = array_size;
1073 rctx->b.b.set_constant_buffer(&rctx->b.b, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
1074 pipe_resource_reference(&cb.buffer, NULL);
1075 }
1076
1077 static void r600_setup_txq_cube_array_constants(struct r600_context *rctx, int shader_type)
1078 {
1079 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1080 int bits;
1081 uint32_t array_size;
1082 struct pipe_constant_buffer cb;
1083 int i;
1084
1085 if (!samplers->views.dirty_txq_constants)
1086 return;
1087
1088 samplers->views.dirty_txq_constants = FALSE;
1089
1090 bits = util_last_bit(samplers->views.enabled_mask);
1091 array_size = bits * sizeof(uint32_t) * 4;
1092 samplers->txq_constants = realloc(samplers->txq_constants, array_size);
1093 memset(samplers->txq_constants, 0, array_size);
1094 for (i = 0; i < bits; i++)
1095 if (samplers->views.enabled_mask & (1 << i))
1096 samplers->txq_constants[i] = samplers->views.views[i]->base.texture->array_size / 6;
1097
1098 cb.buffer = NULL;
1099 cb.user_buffer = samplers->txq_constants;
1100 cb.buffer_offset = 0;
1101 cb.buffer_size = array_size;
1102 rctx->b.b.set_constant_buffer(&rctx->b.b, shader_type, R600_TXQ_CONST_BUFFER, &cb);
1103 pipe_resource_reference(&cb.buffer, NULL);
1104 }
1105
1106 static bool r600_update_derived_state(struct r600_context *rctx)
1107 {
1108 struct pipe_context * ctx = (struct pipe_context*)rctx;
1109 bool ps_dirty = false;
1110 bool blend_disable;
1111
1112 if (!rctx->blitter->running) {
1113 unsigned i;
1114
1115 /* Decompress textures if needed. */
1116 for (i = 0; i < PIPE_SHADER_TYPES; i++) {
1117 struct r600_samplerview_state *views = &rctx->samplers[i].views;
1118 if (views->compressed_depthtex_mask) {
1119 r600_decompress_depth_textures(rctx, views);
1120 }
1121 if (views->compressed_colortex_mask) {
1122 r600_decompress_color_textures(rctx, views);
1123 }
1124 }
1125 }
1126
1127 r600_shader_select(ctx, rctx->ps_shader, &ps_dirty);
1128
1129 if (rctx->ps_shader && rctx->rasterizer &&
1130 ((rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable) ||
1131 (rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade))) {
1132
1133 if (rctx->b.chip_class >= EVERGREEN)
1134 evergreen_update_ps_state(ctx, rctx->ps_shader->current);
1135 else
1136 r600_update_ps_state(ctx, rctx->ps_shader->current);
1137
1138 ps_dirty = true;
1139 }
1140
1141 if (ps_dirty) {
1142 rctx->pixel_shader.atom.num_dw = rctx->ps_shader->current->command_buffer.num_dw;
1143 rctx->pixel_shader.atom.dirty = true;
1144 }
1145
1146 /* on R600 we stuff masks + txq info into one constant buffer */
1147 /* on evergreen we only need a txq info one */
1148 if (rctx->b.chip_class < EVERGREEN) {
1149 if (rctx->ps_shader && rctx->ps_shader->current->shader.uses_tex_buffers)
1150 r600_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
1151 if (rctx->vs_shader && rctx->vs_shader->current->shader.uses_tex_buffers)
1152 r600_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
1153 } else {
1154 if (rctx->ps_shader && rctx->ps_shader->current->shader.uses_tex_buffers)
1155 eg_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
1156 if (rctx->vs_shader && rctx->vs_shader->current->shader.uses_tex_buffers)
1157 eg_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
1158 }
1159
1160
1161 if (rctx->ps_shader && rctx->ps_shader->current->shader.has_txq_cube_array_z_comp)
1162 r600_setup_txq_cube_array_constants(rctx, PIPE_SHADER_FRAGMENT);
1163 if (rctx->vs_shader && rctx->vs_shader->current->shader.has_txq_cube_array_z_comp)
1164 r600_setup_txq_cube_array_constants(rctx, PIPE_SHADER_VERTEX);
1165
1166 if (rctx->b.chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
1167 if (!r600_adjust_gprs(rctx)) {
1168 /* discard rendering */
1169 return false;
1170 }
1171 }
1172
1173 blend_disable = (rctx->dual_src_blend &&
1174 rctx->ps_shader->current->nr_ps_color_outputs < 2);
1175
1176 if (blend_disable != rctx->force_blend_disable) {
1177 rctx->force_blend_disable = blend_disable;
1178 r600_bind_blend_state_internal(rctx,
1179 rctx->blend_state.cso,
1180 blend_disable);
1181 }
1182 return true;
1183 }
1184
1185 static unsigned r600_conv_prim_to_gs_out(unsigned mode)
1186 {
1187 static const int prim_conv[] = {
1188 V_028A6C_OUTPRIM_TYPE_POINTLIST,
1189 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1190 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1191 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1192 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1193 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1194 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1195 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1196 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1197 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1198 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1199 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1200 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1201 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1202 V_028A6C_OUTPRIM_TYPE_TRISTRIP
1203 };
1204 assert(mode < Elements(prim_conv));
1205
1206 return prim_conv[mode];
1207 }
1208
1209 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1210 {
1211 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1212 struct r600_clip_misc_state *state = &rctx->clip_misc_state;
1213
1214 r600_write_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
1215 state->pa_cl_clip_cntl |
1216 (state->clip_dist_write ? 0 : state->clip_plane_enable & 0x3F));
1217 r600_write_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
1218 state->pa_cl_vs_out_cntl |
1219 (state->clip_plane_enable & state->clip_dist_write));
1220 }
1221
1222 static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
1223 {
1224 struct r600_context *rctx = (struct r600_context *)ctx;
1225 struct pipe_draw_info info = *dinfo;
1226 struct pipe_index_buffer ib = {};
1227 unsigned i;
1228 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1229
1230 if (!info.count && (info.indexed || !info.count_from_stream_output)) {
1231 assert(0);
1232 return;
1233 }
1234
1235 if (!rctx->vs_shader) {
1236 assert(0);
1237 return;
1238 }
1239
1240 /* make sure that the gfx ring is only one active */
1241 if (rctx->b.rings.dma.cs) {
1242 rctx->b.rings.dma.flush(rctx, RADEON_FLUSH_ASYNC);
1243 }
1244
1245 if (!r600_update_derived_state(rctx)) {
1246 /* useless to render because current rendering command
1247 * can't be achieved
1248 */
1249 return;
1250 }
1251
1252 if (info.indexed) {
1253 /* Initialize the index buffer struct. */
1254 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
1255 ib.user_buffer = rctx->index_buffer.user_buffer;
1256 ib.index_size = rctx->index_buffer.index_size;
1257 ib.offset = rctx->index_buffer.offset + info.start * ib.index_size;
1258
1259 /* Translate 8-bit indices to 16-bit. */
1260 if (ib.index_size == 1) {
1261 struct pipe_resource *out_buffer = NULL;
1262 unsigned out_offset;
1263 void *ptr;
1264
1265 u_upload_alloc(rctx->uploader, 0, info.count * 2,
1266 &out_offset, &out_buffer, &ptr);
1267
1268 util_shorten_ubyte_elts_to_userptr(
1269 &rctx->b.b, &ib, 0, ib.offset, info.count, ptr);
1270
1271 pipe_resource_reference(&ib.buffer, NULL);
1272 ib.user_buffer = NULL;
1273 ib.buffer = out_buffer;
1274 ib.offset = out_offset;
1275 ib.index_size = 2;
1276 }
1277
1278 /* Upload the index buffer.
1279 * The upload is skipped for small index counts on little-endian machines
1280 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
1281 * Note: Instanced rendering in combination with immediate indices hangs. */
1282 if (ib.user_buffer && (R600_BIG_ENDIAN || info.instance_count > 1 ||
1283 info.count*ib.index_size > 20)) {
1284 u_upload_data(rctx->uploader, 0, info.count * ib.index_size,
1285 ib.user_buffer, &ib.offset, &ib.buffer);
1286 ib.user_buffer = NULL;
1287 }
1288 } else {
1289 info.index_bias = info.start;
1290 }
1291
1292 /* Set the index offset and primitive restart. */
1293 if (rctx->vgt_state.vgt_multi_prim_ib_reset_en != info.primitive_restart ||
1294 rctx->vgt_state.vgt_multi_prim_ib_reset_indx != info.restart_index ||
1295 rctx->vgt_state.vgt_indx_offset != info.index_bias) {
1296 rctx->vgt_state.vgt_multi_prim_ib_reset_en = info.primitive_restart;
1297 rctx->vgt_state.vgt_multi_prim_ib_reset_indx = info.restart_index;
1298 rctx->vgt_state.vgt_indx_offset = info.index_bias;
1299 rctx->vgt_state.atom.dirty = true;
1300 }
1301
1302 /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
1303 if (rctx->b.chip_class == R600) {
1304 rctx->b.flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
1305 rctx->cb_misc_state.atom.dirty = true;
1306 }
1307
1308 /* Emit states. */
1309 r600_need_cs_space(rctx, ib.user_buffer ? 5 : 0, TRUE);
1310 r600_flush_emit(rctx);
1311
1312 for (i = 0; i < R600_NUM_ATOMS; i++) {
1313 if (rctx->atoms[i] == NULL || !rctx->atoms[i]->dirty) {
1314 continue;
1315 }
1316 r600_emit_atom(rctx, rctx->atoms[i]);
1317 }
1318
1319 /* Update start instance. */
1320 if (rctx->last_start_instance != info.start_instance) {
1321 r600_write_ctl_const(cs, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
1322 rctx->last_start_instance = info.start_instance;
1323 }
1324
1325 /* Update the primitive type. */
1326 if (rctx->last_primitive_type != info.mode) {
1327 unsigned ls_mask = 0;
1328
1329 if (info.mode == PIPE_PRIM_LINES)
1330 ls_mask = 1;
1331 else if (info.mode == PIPE_PRIM_LINE_STRIP ||
1332 info.mode == PIPE_PRIM_LINE_LOOP)
1333 ls_mask = 2;
1334
1335 r600_write_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
1336 S_028A0C_AUTO_RESET_CNTL(ls_mask) |
1337 (rctx->rasterizer ? rctx->rasterizer->pa_sc_line_stipple : 0));
1338 r600_write_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
1339 r600_conv_prim_to_gs_out(info.mode));
1340 r600_write_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE,
1341 r600_conv_pipe_prim(info.mode));
1342
1343 rctx->last_primitive_type = info.mode;
1344 }
1345
1346 /* Draw packets. */
1347 cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->predicate_drawing);
1348 cs->buf[cs->cdw++] = info.instance_count;
1349 if (info.indexed) {
1350 cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->predicate_drawing);
1351 cs->buf[cs->cdw++] = ib.index_size == 4 ?
1352 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
1353 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
1354
1355 if (ib.user_buffer) {
1356 unsigned size_bytes = info.count*ib.index_size;
1357 unsigned size_dw = align(size_bytes, 4) / 4;
1358 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_IMMD, 1 + size_dw, rctx->predicate_drawing);
1359 cs->buf[cs->cdw++] = info.count;
1360 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_IMMEDIATE;
1361 memcpy(cs->buf+cs->cdw, ib.user_buffer, size_bytes);
1362 cs->cdw += size_dw;
1363 } else {
1364 uint64_t va = r600_resource_va(ctx->screen, ib.buffer) + ib.offset;
1365 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->predicate_drawing);
1366 cs->buf[cs->cdw++] = va;
1367 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
1368 cs->buf[cs->cdw++] = info.count;
1369 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
1370 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->predicate_drawing);
1371 cs->buf[cs->cdw++] = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
1372 }
1373 } else {
1374 if (info.count_from_stream_output) {
1375 struct r600_so_target *t = (struct r600_so_target*)info.count_from_stream_output;
1376 uint64_t va = r600_resource_va(&rctx->screen->b.b, (void*)t->buf_filled_size) + t->buf_filled_size_offset;
1377
1378 r600_write_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
1379
1380 cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0);
1381 cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG;
1382 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */
1383 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
1384 cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */
1385 cs->buf[cs->cdw++] = 0; /* unused */
1386
1387 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1388 cs->buf[cs->cdw++] = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, t->buf_filled_size, RADEON_USAGE_READ);
1389 }
1390
1391 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->predicate_drawing);
1392 cs->buf[cs->cdw++] = info.count;
1393 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
1394 (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
1395 }
1396
1397 if (rctx->screen->trace_bo) {
1398 r600_trace_emit(rctx);
1399 }
1400
1401 /* Set the depth buffer as dirty. */
1402 if (rctx->framebuffer.state.zsbuf) {
1403 struct pipe_surface *surf = rctx->framebuffer.state.zsbuf;
1404 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
1405
1406 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1407 }
1408 if (rctx->framebuffer.compressed_cb_mask) {
1409 struct pipe_surface *surf;
1410 struct r600_texture *rtex;
1411 unsigned mask = rctx->framebuffer.compressed_cb_mask;
1412
1413 do {
1414 unsigned i = u_bit_scan(&mask);
1415 surf = rctx->framebuffer.state.cbufs[i];
1416 rtex = (struct r600_texture*)surf->texture;
1417
1418 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1419
1420 } while (mask);
1421 }
1422
1423 pipe_resource_reference(&ib.buffer, NULL);
1424 rctx->num_draw_calls++;
1425 }
1426
1427 void r600_draw_rectangle(struct blitter_context *blitter,
1428 int x1, int y1, int x2, int y2, float depth,
1429 enum blitter_attrib_type type, const union pipe_color_union *attrib)
1430 {
1431 struct r600_context *rctx = (struct r600_context*)util_blitter_get_pipe(blitter);
1432 struct pipe_viewport_state viewport;
1433 struct pipe_resource *buf = NULL;
1434 unsigned offset = 0;
1435 float *vb;
1436
1437 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
1438 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
1439 return;
1440 }
1441
1442 /* Some operations (like color resolve on r6xx) don't work
1443 * with the conventional primitive types.
1444 * One that works is PT_RECTLIST, which we use here. */
1445
1446 /* setup viewport */
1447 viewport.scale[0] = 1.0f;
1448 viewport.scale[1] = 1.0f;
1449 viewport.scale[2] = 1.0f;
1450 viewport.scale[3] = 1.0f;
1451 viewport.translate[0] = 0.0f;
1452 viewport.translate[1] = 0.0f;
1453 viewport.translate[2] = 0.0f;
1454 viewport.translate[3] = 0.0f;
1455 rctx->b.b.set_viewport_states(&rctx->b.b, 0, 1, &viewport);
1456
1457 /* Upload vertices. The hw rectangle has only 3 vertices,
1458 * I guess the 4th one is derived from the first 3.
1459 * The vertex specification should match u_blitter's vertex element state. */
1460 u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, &offset, &buf, (void**)&vb);
1461 vb[0] = x1;
1462 vb[1] = y1;
1463 vb[2] = depth;
1464 vb[3] = 1;
1465
1466 vb[8] = x1;
1467 vb[9] = y2;
1468 vb[10] = depth;
1469 vb[11] = 1;
1470
1471 vb[16] = x2;
1472 vb[17] = y1;
1473 vb[18] = depth;
1474 vb[19] = 1;
1475
1476 if (attrib) {
1477 memcpy(vb+4, attrib->f, sizeof(float)*4);
1478 memcpy(vb+12, attrib->f, sizeof(float)*4);
1479 memcpy(vb+20, attrib->f, sizeof(float)*4);
1480 }
1481
1482 /* draw */
1483 util_draw_vertex_buffer(&rctx->b.b, NULL, buf, rctx->blitter->vb_slot, offset,
1484 R600_PRIM_RECTANGLE_LIST, 3, 2);
1485 pipe_resource_reference(&buf, NULL);
1486 }
1487
1488 uint32_t r600_translate_stencil_op(int s_op)
1489 {
1490 switch (s_op) {
1491 case PIPE_STENCIL_OP_KEEP:
1492 return V_028800_STENCIL_KEEP;
1493 case PIPE_STENCIL_OP_ZERO:
1494 return V_028800_STENCIL_ZERO;
1495 case PIPE_STENCIL_OP_REPLACE:
1496 return V_028800_STENCIL_REPLACE;
1497 case PIPE_STENCIL_OP_INCR:
1498 return V_028800_STENCIL_INCR;
1499 case PIPE_STENCIL_OP_DECR:
1500 return V_028800_STENCIL_DECR;
1501 case PIPE_STENCIL_OP_INCR_WRAP:
1502 return V_028800_STENCIL_INCR_WRAP;
1503 case PIPE_STENCIL_OP_DECR_WRAP:
1504 return V_028800_STENCIL_DECR_WRAP;
1505 case PIPE_STENCIL_OP_INVERT:
1506 return V_028800_STENCIL_INVERT;
1507 default:
1508 R600_ERR("Unknown stencil op %d", s_op);
1509 assert(0);
1510 break;
1511 }
1512 return 0;
1513 }
1514
1515 uint32_t r600_translate_fill(uint32_t func)
1516 {
1517 switch(func) {
1518 case PIPE_POLYGON_MODE_FILL:
1519 return 2;
1520 case PIPE_POLYGON_MODE_LINE:
1521 return 1;
1522 case PIPE_POLYGON_MODE_POINT:
1523 return 0;
1524 default:
1525 assert(0);
1526 return 0;
1527 }
1528 }
1529
1530 unsigned r600_tex_wrap(unsigned wrap)
1531 {
1532 switch (wrap) {
1533 default:
1534 case PIPE_TEX_WRAP_REPEAT:
1535 return V_03C000_SQ_TEX_WRAP;
1536 case PIPE_TEX_WRAP_CLAMP:
1537 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1538 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1539 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1540 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1541 return V_03C000_SQ_TEX_CLAMP_BORDER;
1542 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1543 return V_03C000_SQ_TEX_MIRROR;
1544 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1545 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1546 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1547 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1548 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1549 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1550 }
1551 }
1552
1553 unsigned r600_tex_filter(unsigned filter)
1554 {
1555 switch (filter) {
1556 default:
1557 case PIPE_TEX_FILTER_NEAREST:
1558 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1559 case PIPE_TEX_FILTER_LINEAR:
1560 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1561 }
1562 }
1563
1564 unsigned r600_tex_mipfilter(unsigned filter)
1565 {
1566 switch (filter) {
1567 case PIPE_TEX_MIPFILTER_NEAREST:
1568 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1569 case PIPE_TEX_MIPFILTER_LINEAR:
1570 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1571 default:
1572 case PIPE_TEX_MIPFILTER_NONE:
1573 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1574 }
1575 }
1576
1577 unsigned r600_tex_compare(unsigned compare)
1578 {
1579 switch (compare) {
1580 default:
1581 case PIPE_FUNC_NEVER:
1582 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1583 case PIPE_FUNC_LESS:
1584 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1585 case PIPE_FUNC_EQUAL:
1586 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1587 case PIPE_FUNC_LEQUAL:
1588 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1589 case PIPE_FUNC_GREATER:
1590 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1591 case PIPE_FUNC_NOTEQUAL:
1592 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1593 case PIPE_FUNC_GEQUAL:
1594 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1595 case PIPE_FUNC_ALWAYS:
1596 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1597 }
1598 }
1599
1600 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
1601 {
1602 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
1603 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
1604 (linear_filter &&
1605 (wrap == PIPE_TEX_WRAP_CLAMP ||
1606 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
1607 }
1608
1609 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
1610 {
1611 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
1612 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
1613
1614 return (state->border_color.ui[0] || state->border_color.ui[1] ||
1615 state->border_color.ui[2] || state->border_color.ui[3]) &&
1616 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
1617 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
1618 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
1619 }
1620
1621 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a)
1622 {
1623 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1624 struct r600_pipe_shader *shader = ((struct r600_shader_state*)a)->shader->current;
1625
1626 r600_emit_command_buffer(cs, &shader->command_buffer);
1627
1628 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1629 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, shader->bo, RADEON_USAGE_READ));
1630 }
1631
1632 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
1633 struct pipe_resource *texture,
1634 const struct pipe_surface *templ,
1635 unsigned width, unsigned height)
1636 {
1637 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
1638
1639 assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level));
1640 assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level));
1641 assert(templ->u.tex.first_layer == templ->u.tex.last_layer);
1642 if (surface == NULL)
1643 return NULL;
1644 pipe_reference_init(&surface->base.reference, 1);
1645 pipe_resource_reference(&surface->base.texture, texture);
1646 surface->base.context = pipe;
1647 surface->base.format = templ->format;
1648 surface->base.width = width;
1649 surface->base.height = height;
1650 surface->base.u = templ->u;
1651 return &surface->base;
1652 }
1653
1654 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
1655 struct pipe_resource *tex,
1656 const struct pipe_surface *templ)
1657 {
1658 unsigned level = templ->u.tex.level;
1659
1660 return r600_create_surface_custom(pipe, tex, templ,
1661 u_minify(tex->width0, level),
1662 u_minify(tex->height0, level));
1663 }
1664
1665 static void r600_surface_destroy(struct pipe_context *pipe,
1666 struct pipe_surface *surface)
1667 {
1668 struct r600_surface *surf = (struct r600_surface*)surface;
1669 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, NULL);
1670 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, NULL);
1671 pipe_resource_reference(&surface->texture, NULL);
1672 FREE(surface);
1673 }
1674
1675 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
1676 const unsigned char *swizzle_view,
1677 boolean vtx)
1678 {
1679 unsigned i;
1680 unsigned char swizzle[4];
1681 unsigned result = 0;
1682 const uint32_t tex_swizzle_shift[4] = {
1683 16, 19, 22, 25,
1684 };
1685 const uint32_t vtx_swizzle_shift[4] = {
1686 3, 6, 9, 12,
1687 };
1688 const uint32_t swizzle_bit[4] = {
1689 0, 1, 2, 3,
1690 };
1691 const uint32_t *swizzle_shift = tex_swizzle_shift;
1692
1693 if (vtx)
1694 swizzle_shift = vtx_swizzle_shift;
1695
1696 if (swizzle_view) {
1697 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
1698 } else {
1699 memcpy(swizzle, swizzle_format, 4);
1700 }
1701
1702 /* Get swizzle. */
1703 for (i = 0; i < 4; i++) {
1704 switch (swizzle[i]) {
1705 case UTIL_FORMAT_SWIZZLE_Y:
1706 result |= swizzle_bit[1] << swizzle_shift[i];
1707 break;
1708 case UTIL_FORMAT_SWIZZLE_Z:
1709 result |= swizzle_bit[2] << swizzle_shift[i];
1710 break;
1711 case UTIL_FORMAT_SWIZZLE_W:
1712 result |= swizzle_bit[3] << swizzle_shift[i];
1713 break;
1714 case UTIL_FORMAT_SWIZZLE_0:
1715 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
1716 break;
1717 case UTIL_FORMAT_SWIZZLE_1:
1718 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
1719 break;
1720 default: /* UTIL_FORMAT_SWIZZLE_X */
1721 result |= swizzle_bit[0] << swizzle_shift[i];
1722 }
1723 }
1724 return result;
1725 }
1726
1727 /* texture format translate */
1728 uint32_t r600_translate_texformat(struct pipe_screen *screen,
1729 enum pipe_format format,
1730 const unsigned char *swizzle_view,
1731 uint32_t *word4_p, uint32_t *yuv_format_p)
1732 {
1733 struct r600_screen *rscreen = (struct r600_screen *)screen;
1734 uint32_t result = 0, word4 = 0, yuv_format = 0;
1735 const struct util_format_description *desc;
1736 boolean uniform = TRUE;
1737 bool enable_s3tc = rscreen->b.info.drm_minor >= 9;
1738 bool is_srgb_valid = FALSE;
1739 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
1740 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
1741
1742 int i;
1743 const uint32_t sign_bit[4] = {
1744 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
1745 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
1746 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
1747 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
1748 };
1749 desc = util_format_description(format);
1750
1751 /* Depth and stencil swizzling is handled separately. */
1752 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS) {
1753 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view, FALSE);
1754 }
1755
1756 /* Colorspace (return non-RGB formats directly). */
1757 switch (desc->colorspace) {
1758 /* Depth stencil formats */
1759 case UTIL_FORMAT_COLORSPACE_ZS:
1760 switch (format) {
1761 /* Depth sampler formats. */
1762 case PIPE_FORMAT_Z16_UNORM:
1763 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1764 result = FMT_16;
1765 goto out_word4;
1766 case PIPE_FORMAT_Z24X8_UNORM:
1767 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1768 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1769 result = FMT_8_24;
1770 goto out_word4;
1771 case PIPE_FORMAT_X8Z24_UNORM:
1772 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1773 if (rscreen->b.chip_class < EVERGREEN)
1774 goto out_unknown;
1775 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
1776 result = FMT_24_8;
1777 goto out_word4;
1778 case PIPE_FORMAT_Z32_FLOAT:
1779 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1780 result = FMT_32_FLOAT;
1781 goto out_word4;
1782 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1783 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1784 result = FMT_X24_8_32_FLOAT;
1785 goto out_word4;
1786 /* Stencil sampler formats. */
1787 case PIPE_FORMAT_S8_UINT:
1788 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1789 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1790 result = FMT_8;
1791 goto out_word4;
1792 case PIPE_FORMAT_X24S8_UINT:
1793 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1794 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
1795 result = FMT_8_24;
1796 goto out_word4;
1797 case PIPE_FORMAT_S8X24_UINT:
1798 if (rscreen->b.chip_class < EVERGREEN)
1799 goto out_unknown;
1800 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1801 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1802 result = FMT_24_8;
1803 goto out_word4;
1804 case PIPE_FORMAT_X32_S8X24_UINT:
1805 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1806 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
1807 result = FMT_X24_8_32_FLOAT;
1808 goto out_word4;
1809 default:
1810 goto out_unknown;
1811 }
1812
1813 case UTIL_FORMAT_COLORSPACE_YUV:
1814 yuv_format |= (1 << 30);
1815 switch (format) {
1816 case PIPE_FORMAT_UYVY:
1817 case PIPE_FORMAT_YUYV:
1818 default:
1819 break;
1820 }
1821 goto out_unknown; /* XXX */
1822
1823 case UTIL_FORMAT_COLORSPACE_SRGB:
1824 word4 |= S_038010_FORCE_DEGAMMA(1);
1825 break;
1826
1827 default:
1828 break;
1829 }
1830
1831 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1832 if (!enable_s3tc)
1833 goto out_unknown;
1834
1835 switch (format) {
1836 case PIPE_FORMAT_RGTC1_SNORM:
1837 case PIPE_FORMAT_LATC1_SNORM:
1838 word4 |= sign_bit[0];
1839 case PIPE_FORMAT_RGTC1_UNORM:
1840 case PIPE_FORMAT_LATC1_UNORM:
1841 result = FMT_BC4;
1842 goto out_word4;
1843 case PIPE_FORMAT_RGTC2_SNORM:
1844 case PIPE_FORMAT_LATC2_SNORM:
1845 word4 |= sign_bit[0] | sign_bit[1];
1846 case PIPE_FORMAT_RGTC2_UNORM:
1847 case PIPE_FORMAT_LATC2_UNORM:
1848 result = FMT_BC5;
1849 goto out_word4;
1850 default:
1851 goto out_unknown;
1852 }
1853 }
1854
1855 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1856
1857 if (!enable_s3tc)
1858 goto out_unknown;
1859
1860 if (!util_format_s3tc_enabled) {
1861 goto out_unknown;
1862 }
1863
1864 switch (format) {
1865 case PIPE_FORMAT_DXT1_RGB:
1866 case PIPE_FORMAT_DXT1_RGBA:
1867 case PIPE_FORMAT_DXT1_SRGB:
1868 case PIPE_FORMAT_DXT1_SRGBA:
1869 result = FMT_BC1;
1870 is_srgb_valid = TRUE;
1871 goto out_word4;
1872 case PIPE_FORMAT_DXT3_RGBA:
1873 case PIPE_FORMAT_DXT3_SRGBA:
1874 result = FMT_BC2;
1875 is_srgb_valid = TRUE;
1876 goto out_word4;
1877 case PIPE_FORMAT_DXT5_RGBA:
1878 case PIPE_FORMAT_DXT5_SRGBA:
1879 result = FMT_BC3;
1880 is_srgb_valid = TRUE;
1881 goto out_word4;
1882 default:
1883 goto out_unknown;
1884 }
1885 }
1886
1887 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1888 switch (format) {
1889 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1890 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1891 result = FMT_GB_GR;
1892 goto out_word4;
1893 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1894 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1895 result = FMT_BG_RG;
1896 goto out_word4;
1897 default:
1898 goto out_unknown;
1899 }
1900 }
1901
1902 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1903 result = FMT_5_9_9_9_SHAREDEXP;
1904 goto out_word4;
1905 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1906 result = FMT_10_11_11_FLOAT;
1907 goto out_word4;
1908 }
1909
1910
1911 for (i = 0; i < desc->nr_channels; i++) {
1912 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1913 word4 |= sign_bit[i];
1914 }
1915 }
1916
1917 /* R8G8Bx_SNORM - XXX CxV8U8 */
1918
1919 /* See whether the components are of the same size. */
1920 for (i = 1; i < desc->nr_channels; i++) {
1921 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1922 }
1923
1924 /* Non-uniform formats. */
1925 if (!uniform) {
1926 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1927 desc->channel[0].pure_integer)
1928 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1929 switch(desc->nr_channels) {
1930 case 3:
1931 if (desc->channel[0].size == 5 &&
1932 desc->channel[1].size == 6 &&
1933 desc->channel[2].size == 5) {
1934 result = FMT_5_6_5;
1935 goto out_word4;
1936 }
1937 goto out_unknown;
1938 case 4:
1939 if (desc->channel[0].size == 5 &&
1940 desc->channel[1].size == 5 &&
1941 desc->channel[2].size == 5 &&
1942 desc->channel[3].size == 1) {
1943 result = FMT_1_5_5_5;
1944 goto out_word4;
1945 }
1946 if (desc->channel[0].size == 10 &&
1947 desc->channel[1].size == 10 &&
1948 desc->channel[2].size == 10 &&
1949 desc->channel[3].size == 2) {
1950 result = FMT_2_10_10_10;
1951 goto out_word4;
1952 }
1953 goto out_unknown;
1954 }
1955 goto out_unknown;
1956 }
1957
1958 /* Find the first non-VOID channel. */
1959 for (i = 0; i < 4; i++) {
1960 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1961 break;
1962 }
1963 }
1964
1965 if (i == 4)
1966 goto out_unknown;
1967
1968 /* uniform formats */
1969 switch (desc->channel[i].type) {
1970 case UTIL_FORMAT_TYPE_UNSIGNED:
1971 case UTIL_FORMAT_TYPE_SIGNED:
1972 #if 0
1973 if (!desc->channel[i].normalized &&
1974 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
1975 goto out_unknown;
1976 }
1977 #endif
1978 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1979 desc->channel[i].pure_integer)
1980 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1981
1982 switch (desc->channel[i].size) {
1983 case 4:
1984 switch (desc->nr_channels) {
1985 case 2:
1986 result = FMT_4_4;
1987 goto out_word4;
1988 case 4:
1989 result = FMT_4_4_4_4;
1990 goto out_word4;
1991 }
1992 goto out_unknown;
1993 case 8:
1994 switch (desc->nr_channels) {
1995 case 1:
1996 result = FMT_8;
1997 goto out_word4;
1998 case 2:
1999 result = FMT_8_8;
2000 goto out_word4;
2001 case 4:
2002 result = FMT_8_8_8_8;
2003 is_srgb_valid = TRUE;
2004 goto out_word4;
2005 }
2006 goto out_unknown;
2007 case 16:
2008 switch (desc->nr_channels) {
2009 case 1:
2010 result = FMT_16;
2011 goto out_word4;
2012 case 2:
2013 result = FMT_16_16;
2014 goto out_word4;
2015 case 4:
2016 result = FMT_16_16_16_16;
2017 goto out_word4;
2018 }
2019 goto out_unknown;
2020 case 32:
2021 switch (desc->nr_channels) {
2022 case 1:
2023 result = FMT_32;
2024 goto out_word4;
2025 case 2:
2026 result = FMT_32_32;
2027 goto out_word4;
2028 case 4:
2029 result = FMT_32_32_32_32;
2030 goto out_word4;
2031 }
2032 }
2033 goto out_unknown;
2034
2035 case UTIL_FORMAT_TYPE_FLOAT:
2036 switch (desc->channel[i].size) {
2037 case 16:
2038 switch (desc->nr_channels) {
2039 case 1:
2040 result = FMT_16_FLOAT;
2041 goto out_word4;
2042 case 2:
2043 result = FMT_16_16_FLOAT;
2044 goto out_word4;
2045 case 4:
2046 result = FMT_16_16_16_16_FLOAT;
2047 goto out_word4;
2048 }
2049 goto out_unknown;
2050 case 32:
2051 switch (desc->nr_channels) {
2052 case 1:
2053 result = FMT_32_FLOAT;
2054 goto out_word4;
2055 case 2:
2056 result = FMT_32_32_FLOAT;
2057 goto out_word4;
2058 case 4:
2059 result = FMT_32_32_32_32_FLOAT;
2060 goto out_word4;
2061 }
2062 }
2063 goto out_unknown;
2064 }
2065
2066 out_word4:
2067
2068 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid)
2069 return ~0;
2070 if (word4_p)
2071 *word4_p = word4;
2072 if (yuv_format_p)
2073 *yuv_format_p = yuv_format;
2074 return result;
2075 out_unknown:
2076 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
2077 return ~0;
2078 }
2079
2080 /* keep this at the end of this file, please */
2081 void r600_init_common_state_functions(struct r600_context *rctx)
2082 {
2083 rctx->b.b.create_fs_state = r600_create_ps_state;
2084 rctx->b.b.create_vs_state = r600_create_vs_state;
2085 rctx->b.b.create_vertex_elements_state = r600_create_vertex_fetch_shader;
2086 rctx->b.b.bind_blend_state = r600_bind_blend_state;
2087 rctx->b.b.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
2088 rctx->b.b.bind_sampler_states = r600_bind_sampler_states;
2089 rctx->b.b.bind_fragment_sampler_states = r600_bind_ps_sampler_states;
2090 rctx->b.b.bind_fs_state = r600_bind_ps_state;
2091 rctx->b.b.bind_rasterizer_state = r600_bind_rs_state;
2092 rctx->b.b.bind_vertex_elements_state = r600_bind_vertex_elements;
2093 rctx->b.b.bind_vertex_sampler_states = r600_bind_vs_sampler_states;
2094 rctx->b.b.bind_vs_state = r600_bind_vs_state;
2095 rctx->b.b.delete_blend_state = r600_delete_blend_state;
2096 rctx->b.b.delete_depth_stencil_alpha_state = r600_delete_dsa_state;
2097 rctx->b.b.delete_fs_state = r600_delete_ps_state;
2098 rctx->b.b.delete_rasterizer_state = r600_delete_rs_state;
2099 rctx->b.b.delete_sampler_state = r600_delete_sampler_state;
2100 rctx->b.b.delete_vertex_elements_state = r600_delete_vertex_elements;
2101 rctx->b.b.delete_vs_state = r600_delete_vs_state;
2102 rctx->b.b.set_blend_color = r600_set_blend_color;
2103 rctx->b.b.set_clip_state = r600_set_clip_state;
2104 rctx->b.b.set_constant_buffer = r600_set_constant_buffer;
2105 rctx->b.b.set_sample_mask = r600_set_sample_mask;
2106 rctx->b.b.set_stencil_ref = r600_set_pipe_stencil_ref;
2107 rctx->b.b.set_viewport_states = r600_set_viewport_states;
2108 rctx->b.b.set_vertex_buffers = r600_set_vertex_buffers;
2109 rctx->b.b.set_index_buffer = r600_set_index_buffer;
2110 rctx->b.b.set_fragment_sampler_views = r600_set_ps_sampler_views;
2111 rctx->b.b.set_vertex_sampler_views = r600_set_vs_sampler_views;
2112 rctx->b.b.sampler_view_destroy = r600_sampler_view_destroy;
2113 rctx->b.b.texture_barrier = r600_texture_barrier;
2114 rctx->b.b.set_stream_output_targets = r600_set_streamout_targets;
2115 rctx->b.b.create_surface = r600_create_surface;
2116 rctx->b.b.surface_destroy = r600_surface_destroy;
2117 rctx->b.b.draw_vbo = r600_draw_vbo;
2118 }
2119
2120 void r600_trace_emit(struct r600_context *rctx)
2121 {
2122 struct r600_screen *rscreen = rctx->screen;
2123 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2124 uint64_t va;
2125 uint32_t reloc;
2126
2127 va = r600_resource_va(&rscreen->b.b, (void*)rscreen->trace_bo);
2128 reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rscreen->trace_bo, RADEON_USAGE_READWRITE);
2129 radeon_emit(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
2130 radeon_emit(cs, va & 0xFFFFFFFFUL);
2131 radeon_emit(cs, (va >> 32UL) & 0xFFUL);
2132 radeon_emit(cs, cs->cdw);
2133 radeon_emit(cs, rscreen->cs_count);
2134 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2135 radeon_emit(cs, reloc);
2136 }