projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
r600g: remove unused function
[mesa.git] / src / gallium / drivers / r600 / r600_state_common.c
1 /*
2 * Copyright 2010 Red Hat Inc.
3 * 2010 Jerome Glisse
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
26 */
27 #include "r600_formats.h"
28 #include "r600d.h"
29
30 #include "util/u_draw_quad.h"
31 #include "util/u_upload_mgr.h"
32 #include "tgsi/tgsi_parse.h"
33 #include <byteswap.h>
34
35 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
36
37 static void r600_emit_command_buffer(struct r600_context *rctx, struct r600_atom *atom)
38 {
39 struct radeon_winsys_cs *cs = rctx->cs;
40 struct r600_command_buffer *cb = (struct r600_command_buffer*)atom;
41
42 assert(cs->cdw + cb->atom.num_dw <= RADEON_MAX_CMDBUF_DWORDS);
43 memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->atom.num_dw);
44 cs->cdw += cb->atom.num_dw;
45 }
46
47 void r600_init_command_buffer(struct r600_context *rctx, struct r600_command_buffer *cb, unsigned id, unsigned num_dw)
48 {
49 r600_init_atom(rctx, &cb->atom, id, r600_emit_command_buffer, 0);
50 cb->buf = CALLOC(1, 4 * num_dw);
51 cb->max_num_dw = num_dw;
52 }
53
54 void r600_release_command_buffer(struct r600_command_buffer *cb)
55 {
56 FREE(cb->buf);
57 }
58
59 static void r600_emit_surface_sync(struct r600_context *rctx, struct r600_atom *atom)
60 {
61 struct radeon_winsys_cs *cs = rctx->cs;
62 struct r600_surface_sync_cmd *a = (struct r600_surface_sync_cmd*)atom;
63
64 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
65 cs->buf[cs->cdw++] = a->flush_flags; /* CP_COHER_CNTL */
66 cs->buf[cs->cdw++] = 0xffffffff; /* CP_COHER_SIZE */
67 cs->buf[cs->cdw++] = 0; /* CP_COHER_BASE */
68 cs->buf[cs->cdw++] = 0x0000000A; /* POLL_INTERVAL */
69
70 a->flush_flags = 0;
71 }
72
73 static void r600_emit_r6xx_flush_and_inv(struct r600_context *rctx, struct r600_atom *atom)
74 {
75 struct radeon_winsys_cs *cs = rctx->cs;
76 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
77 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
78 }
79
80 void r600_init_atom(struct r600_context *rctx,
81 struct r600_atom *atom,
82 unsigned id,
83 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
84 unsigned num_dw)
85 {
86 assert(id < R600_MAX_ATOM);
87 assert(rctx->atoms[id] == NULL);
88 rctx->atoms[id] = atom;
89 atom->id = id;
90 atom->emit = emit;
91 atom->num_dw = num_dw;
92 atom->dirty = false;
93 }
94
95 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom)
96 {
97 struct radeon_winsys_cs *cs = rctx->cs;
98 struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom;
99 unsigned alpha_ref = a->sx_alpha_ref;
100
101 if (rctx->chip_class >= EVERGREEN && a->cb0_export_16bpc) {
102 alpha_ref &= ~0x1FFF;
103 }
104
105 r600_write_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL,
106 a->sx_alpha_test_control |
107 S_028410_ALPHA_TEST_BYPASS(a->bypass));
108 r600_write_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref);
109 }
110
111 void r600_init_common_atoms(struct r600_context *rctx)
112 {
113 r600_init_atom(rctx, &rctx->r6xx_flush_and_inv_cmd, 2, r600_emit_r6xx_flush_and_inv, 2);
114 r600_init_atom(rctx, &rctx->surface_sync_cmd.atom, 3, r600_emit_surface_sync, 5);
115 }
116
117 unsigned r600_get_cb_flush_flags(struct r600_context *rctx)
118 {
119 unsigned flags = 0;
120
121 if (rctx->framebuffer.nr_cbufs) {
122 flags |= S_0085F0_CB_ACTION_ENA(1) |
123 (((1 << rctx->framebuffer.nr_cbufs) - 1) << S_0085F0_CB0_DEST_BASE_ENA_SHIFT);
124 }
125
126 /* Workaround for broken flushing on some R6xx chipsets. */
127 if (rctx->family == CHIP_RV670 ||
128 rctx->family == CHIP_RS780 ||
129 rctx->family == CHIP_RS880) {
130 flags |= S_0085F0_CB1_DEST_BASE_ENA(1) |
131 S_0085F0_DEST_BASE_0_ENA(1);
132 }
133 return flags;
134 }
135
136 void r600_texture_barrier(struct pipe_context *ctx)
137 {
138 struct r600_context *rctx = (struct r600_context *)ctx;
139
140 rctx->surface_sync_cmd.flush_flags |= S_0085F0_TC_ACTION_ENA(1) | r600_get_cb_flush_flags(rctx);
141 r600_atom_dirty(rctx, &rctx->surface_sync_cmd.atom);
142 }
143
144 static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
145 {
146 static const int prim_conv[] = {
147 V_008958_DI_PT_POINTLIST,
148 V_008958_DI_PT_LINELIST,
149 V_008958_DI_PT_LINELOOP,
150 V_008958_DI_PT_LINESTRIP,
151 V_008958_DI_PT_TRILIST,
152 V_008958_DI_PT_TRISTRIP,
153 V_008958_DI_PT_TRIFAN,
154 V_008958_DI_PT_QUADLIST,
155 V_008958_DI_PT_QUADSTRIP,
156 V_008958_DI_PT_POLYGON,
157 -1,
158 -1,
159 -1,
160 -1,
161 V_008958_DI_PT_RECTLIST
162 };
163
164 *prim = prim_conv[pprim];
165 if (*prim == -1) {
166 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim);
167 return false;
168 }
169 return true;
170 }
171
172 /* common state between evergreen and r600 */
173
174 static void r600_bind_blend_state_internal(struct r600_context *rctx,
175 struct r600_pipe_blend *blend)
176 {
177 struct r600_pipe_state *rstate;
178 bool update_cb = false;
179
180 rstate = &blend->rstate;
181 rctx->states[rstate->id] = rstate;
182 r600_context_pipe_state_set(rctx, rstate);
183
184 if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) {
185 rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
186 update_cb = true;
187 }
188 if (rctx->chip_class <= R700 &&
189 rctx->cb_misc_state.cb_color_control != blend->cb_color_control) {
190 rctx->cb_misc_state.cb_color_control = blend->cb_color_control;
191 update_cb = true;
192 }
193 if (rctx->cb_misc_state.dual_src_blend != blend->dual_src_blend) {
194 rctx->cb_misc_state.dual_src_blend = blend->dual_src_blend;
195 update_cb = true;
196 }
197 if (update_cb) {
198 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
199 }
200 }
201
202 void r600_bind_blend_state(struct pipe_context *ctx, void *state)
203 {
204 struct r600_context *rctx = (struct r600_context *)ctx;
205 struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
206
207 if (blend == NULL)
208 return;
209
210 rctx->blend = blend;
211 rctx->alpha_to_one = blend->alpha_to_one;
212 rctx->dual_src_blend = blend->dual_src_blend;
213
214 if (!rctx->blend_override)
215 r600_bind_blend_state_internal(rctx, blend);
216 }
217
218 void r600_set_blend_color(struct pipe_context *ctx,
219 const struct pipe_blend_color *state)
220 {
221 struct r600_context *rctx = (struct r600_context *)ctx;
222 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
223
224 if (rstate == NULL)
225 return;
226
227 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
228 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]));
229 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
230 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
231 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
232
233 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
234 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
235 r600_context_pipe_state_set(rctx, rstate);
236 }
237
238 static void r600_set_stencil_ref(struct pipe_context *ctx,
239 const struct r600_stencil_ref *state)
240 {
241 struct r600_context *rctx = (struct r600_context *)ctx;
242 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
243
244 if (rstate == NULL)
245 return;
246
247 rstate->id = R600_PIPE_STATE_STENCIL_REF;
248 r600_pipe_state_add_reg(rstate,
249 R_028430_DB_STENCILREFMASK,
250 S_028430_STENCILREF(state->ref_value[0]) |
251 S_028430_STENCILMASK(state->valuemask[0]) |
252 S_028430_STENCILWRITEMASK(state->writemask[0]));
253 r600_pipe_state_add_reg(rstate,
254 R_028434_DB_STENCILREFMASK_BF,
255 S_028434_STENCILREF_BF(state->ref_value[1]) |
256 S_028434_STENCILMASK_BF(state->valuemask[1]) |
257 S_028434_STENCILWRITEMASK_BF(state->writemask[1]));
258
259 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
260 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
261 r600_context_pipe_state_set(rctx, rstate);
262 }
263
264 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
265 const struct pipe_stencil_ref *state)
266 {
267 struct r600_context *rctx = (struct r600_context *)ctx;
268 struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA];
269 struct r600_stencil_ref ref;
270
271 rctx->stencil_ref = *state;
272
273 if (!dsa)
274 return;
275
276 ref.ref_value[0] = state->ref_value[0];
277 ref.ref_value[1] = state->ref_value[1];
278 ref.valuemask[0] = dsa->valuemask[0];
279 ref.valuemask[1] = dsa->valuemask[1];
280 ref.writemask[0] = dsa->writemask[0];
281 ref.writemask[1] = dsa->writemask[1];
282
283 r600_set_stencil_ref(ctx, &ref);
284 }
285
286 void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
287 {
288 struct r600_context *rctx = (struct r600_context *)ctx;
289 struct r600_pipe_dsa *dsa = state;
290 struct r600_pipe_state *rstate;
291 struct r600_stencil_ref ref;
292
293 if (state == NULL)
294 return;
295 rstate = &dsa->rstate;
296 rctx->states[rstate->id] = rstate;
297 r600_context_pipe_state_set(rctx, rstate);
298
299 ref.ref_value[0] = rctx->stencil_ref.ref_value[0];
300 ref.ref_value[1] = rctx->stencil_ref.ref_value[1];
301 ref.valuemask[0] = dsa->valuemask[0];
302 ref.valuemask[1] = dsa->valuemask[1];
303 ref.writemask[0] = dsa->writemask[0];
304 ref.writemask[1] = dsa->writemask[1];
305
306 r600_set_stencil_ref(ctx, &ref);
307
308 /* Update alphatest state. */
309 if (rctx->alphatest_state.sx_alpha_test_control != dsa->sx_alpha_test_control ||
310 rctx->alphatest_state.sx_alpha_ref != dsa->alpha_ref) {
311 rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control;
312 rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref;
313 r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
314 }
315 }
316
317 void r600_set_max_scissor(struct r600_context *rctx)
318 {
319 /* Set a scissor state such that it doesn't do anything. */
320 struct pipe_scissor_state scissor;
321 scissor.minx = 0;
322 scissor.miny = 0;
323 scissor.maxx = 8192;
324 scissor.maxy = 8192;
325
326 r600_set_scissor_state(rctx, &scissor);
327 }
328
329 void r600_bind_rs_state(struct pipe_context *ctx, void *state)
330 {
331 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
332 struct r600_context *rctx = (struct r600_context *)ctx;
333
334 if (state == NULL)
335 return;
336
337 rctx->sprite_coord_enable = rs->sprite_coord_enable;
338 rctx->two_side = rs->two_side;
339 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
340 rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
341 rctx->multisample_enable = rs->multisample_enable;
342
343 rctx->rasterizer = rs;
344
345 rctx->states[rs->rstate.id] = &rs->rstate;
346 r600_context_pipe_state_set(rctx, &rs->rstate);
347
348 if (rctx->chip_class >= EVERGREEN) {
349 evergreen_polygon_offset_update(rctx);
350 } else {
351 r600_polygon_offset_update(rctx);
352 }
353
354 /* Workaround for a missing scissor enable on r600. */
355 if (rctx->chip_class == R600) {
356 if (rs->scissor_enable != rctx->scissor_enable) {
357 rctx->scissor_enable = rs->scissor_enable;
358
359 if (rs->scissor_enable) {
360 r600_set_scissor_state(rctx, &rctx->scissor_state);
361 } else {
362 r600_set_max_scissor(rctx);
363 }
364 }
365 }
366 }
367
368 void r600_delete_rs_state(struct pipe_context *ctx, void *state)
369 {
370 struct r600_context *rctx = (struct r600_context *)ctx;
371 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
372
373 if (rctx->rasterizer == rs) {
374 rctx->rasterizer = NULL;
375 }
376 if (rctx->states[rs->rstate.id] == &rs->rstate) {
377 rctx->states[rs->rstate.id] = NULL;
378 }
379 free(rs);
380 }
381
382 void r600_sampler_view_destroy(struct pipe_context *ctx,
383 struct pipe_sampler_view *state)
384 {
385 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
386
387 pipe_resource_reference(&state->texture, NULL);
388 FREE(resource);
389 }
390
391 static void r600_bind_samplers(struct pipe_context *pipe,
392 unsigned shader,
393 unsigned start,
394 unsigned count, void **states)
395 {
396 struct r600_context *rctx = (struct r600_context *)pipe;
397 struct r600_textures_info *dst;
398 int seamless_cube_map = -1;
399 unsigned i;
400
401 assert(start == 0); /* XXX fix below */
402
403 switch (shader) {
404 case PIPE_SHADER_VERTEX:
405 dst = &rctx->vs_samplers;
406 break;
407 case PIPE_SHADER_FRAGMENT:
408 dst = &rctx->ps_samplers;
409 break;
410 default:
411 debug_error("bad shader in r600_bind_samplers()");
412 return;
413 }
414
415 memcpy(dst->samplers, states, sizeof(void*) * count);
416 dst->n_samplers = count;
417 dst->atom_sampler.num_dw = 0;
418
419 for (i = 0; i < count; i++) {
420 struct r600_pipe_sampler_state *sampler = states[i];
421
422 if (sampler == NULL) {
423 continue;
424 }
425 if (sampler->border_color_use) {
426 dst->atom_sampler.num_dw += 11;
427 rctx->flags |= R600_PARTIAL_FLUSH;
428 } else {
429 dst->atom_sampler.num_dw += 5;
430 }
431 seamless_cube_map = sampler->seamless_cube_map;
432 }
433 if (rctx->chip_class <= R700 && seamless_cube_map != -1 && seamless_cube_map != rctx->seamless_cube_map.enabled) {
434 /* change in TA_CNTL_AUX need a pipeline flush */
435 rctx->flags |= R600_PARTIAL_FLUSH;
436 rctx->seamless_cube_map.enabled = seamless_cube_map;
437 r600_atom_dirty(rctx, &rctx->seamless_cube_map.atom);
438 }
439 if (dst->atom_sampler.num_dw) {
440 r600_atom_dirty(rctx, &dst->atom_sampler);
441 }
442 }
443
444 void r600_bind_vs_samplers(struct pipe_context *ctx, unsigned count, void **states)
445 {
446 r600_bind_samplers(ctx, PIPE_SHADER_VERTEX, 0, count, states);
447 }
448
449 void r600_bind_ps_samplers(struct pipe_context *ctx, unsigned count, void **states)
450 {
451 r600_bind_samplers(ctx, PIPE_SHADER_FRAGMENT, 0, count, states);
452 }
453
454 void r600_delete_sampler(struct pipe_context *ctx, void *state)
455 {
456 free(state);
457 }
458
459 void r600_delete_state(struct pipe_context *ctx, void *state)
460 {
461 struct r600_context *rctx = (struct r600_context *)ctx;
462 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
463
464 if (rctx->states[rstate->id] == rstate) {
465 rctx->states[rstate->id] = NULL;
466 }
467 for (int i = 0; i < rstate->nregs; i++) {
468 pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL);
469 }
470 free(rstate);
471 }
472
473 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
474 {
475 struct r600_context *rctx = (struct r600_context *)ctx;
476 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
477
478 rctx->vertex_elements = v;
479 if (v) {
480 r600_inval_shader_cache(rctx);
481
482 rctx->states[v->rstate.id] = &v->rstate;
483 r600_context_pipe_state_set(rctx, &v->rstate);
484 }
485 }
486
487 void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
488 {
489 struct r600_context *rctx = (struct r600_context *)ctx;
490 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
491
492 if (rctx->states[v->rstate.id] == &v->rstate) {
493 rctx->states[v->rstate.id] = NULL;
494 }
495 if (rctx->vertex_elements == state)
496 rctx->vertex_elements = NULL;
497
498 pipe_resource_reference((struct pipe_resource**)&v->fetch_shader, NULL);
499 FREE(state);
500 }
501
502 void r600_set_index_buffer(struct pipe_context *ctx,
503 const struct pipe_index_buffer *ib)
504 {
505 struct r600_context *rctx = (struct r600_context *)ctx;
506
507 if (ib) {
508 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
509 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
510 } else {
511 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
512 }
513 }
514
515 void r600_vertex_buffers_dirty(struct r600_context *rctx)
516 {
517 if (rctx->vertex_buffer_state.dirty_mask) {
518 r600_inval_vertex_cache(rctx);
519 rctx->vertex_buffer_state.atom.num_dw = (rctx->chip_class >= EVERGREEN ? 12 : 11) *
520 util_bitcount(rctx->vertex_buffer_state.dirty_mask);
521 r600_atom_dirty(rctx, &rctx->vertex_buffer_state.atom);
522 }
523 }
524
525 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
526 const struct pipe_vertex_buffer *input)
527 {
528 struct r600_context *rctx = (struct r600_context *)ctx;
529 struct r600_vertexbuf_state *state = &rctx->vertex_buffer_state;
530 struct pipe_vertex_buffer *vb = state->vb;
531 unsigned i;
532 /* This sets 1-bit for buffers with index >= count. */
533 uint32_t disable_mask = ~((1ull << count) - 1);
534 /* These are the new buffers set by this function. */
535 uint32_t new_buffer_mask = 0;
536
537 /* Set buffers with index >= count to NULL. */
538 uint32_t remaining_buffers_mask =
539 rctx->vertex_buffer_state.enabled_mask & disable_mask;
540
541 while (remaining_buffers_mask) {
542 i = u_bit_scan(&remaining_buffers_mask);
543 pipe_resource_reference(&vb[i].buffer, NULL);
544 }
545
546 /* Set vertex buffers. */
547 for (i = 0; i < count; i++) {
548 if (memcmp(&input[i], &vb[i], sizeof(struct pipe_vertex_buffer))) {
549 if (input[i].buffer) {
550 vb[i].stride = input[i].stride;
551 vb[i].buffer_offset = input[i].buffer_offset;
552 pipe_resource_reference(&vb[i].buffer, input[i].buffer);
553 new_buffer_mask |= 1 << i;
554 } else {
555 pipe_resource_reference(&vb[i].buffer, NULL);
556 disable_mask |= 1 << i;
557 }
558 }
559 }
560
561 rctx->vertex_buffer_state.enabled_mask &= ~disable_mask;
562 rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask;
563 rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask;
564 rctx->vertex_buffer_state.dirty_mask |= new_buffer_mask;
565
566 r600_vertex_buffers_dirty(rctx);
567 }
568
569 void r600_sampler_views_dirty(struct r600_context *rctx,
570 struct r600_samplerview_state *state)
571 {
572 if (state->dirty_mask) {
573 r600_inval_texture_cache(rctx);
574 state->atom.num_dw = (rctx->chip_class >= EVERGREEN ? 14 : 13) *
575 util_bitcount(state->dirty_mask);
576 r600_atom_dirty(rctx, &state->atom);
577 }
578 }
579
580 void r600_set_sampler_views(struct pipe_context *pipe,
581 unsigned shader,
582 unsigned start,
583 unsigned count,
584 struct pipe_sampler_view **views)
585 {
586 struct r600_context *rctx = (struct r600_context *) pipe;
587 struct r600_textures_info *dst;
588 struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
589 unsigned i;
590 /* This sets 1-bit for textures with index >= count. */
591 uint32_t disable_mask = ~((1ull << count) - 1);
592 /* These are the new textures set by this function. */
593 uint32_t new_mask = 0;
594
595 /* Set textures with index >= count to NULL. */
596 uint32_t remaining_mask;
597
598 assert(start == 0); /* XXX fix below */
599
600 switch (shader) {
601 case PIPE_SHADER_VERTEX:
602 dst = &rctx->vs_samplers;
603 break;
604 case PIPE_SHADER_FRAGMENT:
605 dst = &rctx->ps_samplers;
606 break;
607 default:
608 debug_error("bad shader in r600_set_sampler_views()");
609 return;
610 }
611
612 remaining_mask = dst->views.enabled_mask & disable_mask;
613
614 while (remaining_mask) {
615 i = u_bit_scan(&remaining_mask);
616 assert(dst->views.views[i]);
617
618 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
619 }
620
621 for (i = 0; i < count; i++) {
622 if (rviews[i] == dst->views.views[i]) {
623 continue;
624 }
625
626 if (rviews[i]) {
627 struct r600_texture *rtex =
628 (struct r600_texture*)rviews[i]->base.texture;
629
630 if (rtex->is_depth && !rtex->is_flushing_texture) {
631 dst->views.compressed_depthtex_mask |= 1 << i;
632 } else {
633 dst->views.compressed_depthtex_mask &= ~(1 << i);
634 }
635
636 /* Track compressed colorbuffers for Evergreen (Cayman doesn't need this). */
637 if (rctx->chip_class != CAYMAN && rtex->cmask_size && rtex->fmask_size) {
638 dst->views.compressed_colortex_mask |= 1 << i;
639 } else {
640 dst->views.compressed_colortex_mask &= ~(1 << i);
641 }
642
643 /* Changing from array to non-arrays textures and vice
644 * versa requires updating TEX_ARRAY_OVERRIDE on R6xx-R7xx. */
645 if (rctx->chip_class <= R700 &&
646 (rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
647 rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) {
648 r600_atom_dirty(rctx, &dst->atom_sampler);
649 }
650
651 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]);
652 new_mask |= 1 << i;
653 } else {
654 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
655 disable_mask |= 1 << i;
656 }
657 }
658
659 dst->views.enabled_mask &= ~disable_mask;
660 dst->views.dirty_mask &= dst->views.enabled_mask;
661 dst->views.enabled_mask |= new_mask;
662 dst->views.dirty_mask |= new_mask;
663 dst->views.compressed_depthtex_mask &= dst->views.enabled_mask;
664 dst->views.compressed_colortex_mask &= dst->views.enabled_mask;
665
666 r600_sampler_views_dirty(rctx, &dst->views);
667 }
668
669 void *r600_create_vertex_elements(struct pipe_context *ctx,
670 unsigned count,
671 const struct pipe_vertex_element *elements)
672 {
673 struct r600_context *rctx = (struct r600_context *)ctx;
674 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
675
676 assert(count < 32);
677 if (!v)
678 return NULL;
679
680 v->count = count;
681 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
682
683 if (r600_vertex_elements_build_fetch_shader(rctx, v)) {
684 FREE(v);
685 return NULL;
686 }
687
688 return v;
689 }
690
691 /* Compute the key for the hw shader variant */
692 static INLINE unsigned r600_shader_selector_key(struct pipe_context * ctx,
693 struct r600_pipe_shader_selector * sel)
694 {
695 struct r600_context *rctx = (struct r600_context *)ctx;
696 unsigned key;
697
698 if (sel->type == PIPE_SHADER_FRAGMENT) {
699 key = rctx->two_side |
700 ((rctx->alpha_to_one && rctx->multisample_enable && !rctx->cb0_is_integer) << 1) |
701 (MIN2(sel->nr_ps_max_color_exports, rctx->nr_cbufs + rctx->dual_src_blend) << 2);
702 } else
703 key = 0;
704
705 return key;
706 }
707
708 /* Select the hw shader variant depending on the current state.
709 * (*dirty) is set to 1 if current variant was changed */
710 static int r600_shader_select(struct pipe_context *ctx,
711 struct r600_pipe_shader_selector* sel,
712 unsigned *dirty)
713 {
714 unsigned key;
715 struct r600_context *rctx = (struct r600_context *)ctx;
716 struct r600_pipe_shader * shader = NULL;
717 int r;
718
719 key = r600_shader_selector_key(ctx, sel);
720
721 /* Check if we don't need to change anything.
722 * This path is also used for most shaders that don't need multiple
723 * variants, it will cost just a computation of the key and this
724 * test. */
725 if (likely(sel->current && sel->current->key == key)) {
726 return 0;
727 }
728
729 /* lookup if we have other variants in the list */
730 if (sel->num_shaders > 1) {
731 struct r600_pipe_shader *p = sel->current, *c = p->next_variant;
732
733 while (c && c->key != key) {
734 p = c;
735 c = c->next_variant;
736 }
737
738 if (c) {
739 p->next_variant = c->next_variant;
740 shader = c;
741 }
742 }
743
744 if (unlikely(!shader)) {
745 shader = CALLOC(1, sizeof(struct r600_pipe_shader));
746 shader->selector = sel;
747
748 r = r600_pipe_shader_create(ctx, shader);
749 if (unlikely(r)) {
750 R600_ERR("Failed to build shader variant (type=%u, key=%u) %d\n",
751 sel->type, key, r);
752 sel->current = NULL;
753 return r;
754 }
755
756 /* We don't know the value of nr_ps_max_color_exports until we built
757 * at least one variant, so we may need to recompute the key after
758 * building first variant. */
759 if (sel->type == PIPE_SHADER_FRAGMENT &&
760 sel->num_shaders == 0) {
761 sel->nr_ps_max_color_exports = shader->shader.nr_ps_max_color_exports;
762 key = r600_shader_selector_key(ctx, sel);
763 }
764
765 shader->key = key;
766 sel->num_shaders++;
767 }
768
769 if (dirty)
770 *dirty = 1;
771
772 shader->next_variant = sel->current;
773 sel->current = shader;
774
775 if (rctx->chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
776 r600_adjust_gprs(rctx);
777 }
778
779 if (rctx->ps_shader &&
780 rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
781 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
782 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
783 }
784 return 0;
785 }
786
787 static void *r600_create_shader_state(struct pipe_context *ctx,
788 const struct pipe_shader_state *state,
789 unsigned pipe_shader_type)
790 {
791 struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector);
792 int r;
793
794 sel->type = pipe_shader_type;
795 sel->tokens = tgsi_dup_tokens(state->tokens);
796 sel->so = state->stream_output;
797
798 r = r600_shader_select(ctx, sel, NULL);
799 if (r)
800 return NULL;
801
802 return sel;
803 }
804
805 void *r600_create_shader_state_ps(struct pipe_context *ctx,
806 const struct pipe_shader_state *state)
807 {
808 return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
809 }
810
811 void *r600_create_shader_state_vs(struct pipe_context *ctx,
812 const struct pipe_shader_state *state)
813 {
814 return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
815 }
816
817 void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
818 {
819 struct r600_context *rctx = (struct r600_context *)ctx;
820
821 if (!state)
822 state = rctx->dummy_pixel_shader;
823
824 rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
825 r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
826
827 if (rctx->chip_class <= R700) {
828 bool multiwrite = rctx->ps_shader->current->shader.fs_write_all;
829
830 if (rctx->cb_misc_state.multiwrite != multiwrite) {
831 rctx->cb_misc_state.multiwrite = multiwrite;
832 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
833 }
834
835 if (rctx->vs_shader)
836 r600_adjust_gprs(rctx);
837 }
838
839 if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
840 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
841 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
842 }
843 }
844
845 void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
846 {
847 struct r600_context *rctx = (struct r600_context *)ctx;
848
849 rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
850 if (state) {
851 r600_context_pipe_state_set(rctx, &rctx->vs_shader->current->rstate);
852
853 if (rctx->chip_class < EVERGREEN && rctx->ps_shader)
854 r600_adjust_gprs(rctx);
855 }
856 }
857
858 static void r600_delete_shader_selector(struct pipe_context *ctx,
859 struct r600_pipe_shader_selector *sel)
860 {
861 struct r600_pipe_shader *p = sel->current, *c;
862 while (p) {
863 c = p->next_variant;
864 r600_pipe_shader_destroy(ctx, p);
865 free(p);
866 p = c;
867 }
868
869 free(sel->tokens);
870 free(sel);
871 }
872
873
874 void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
875 {
876 struct r600_context *rctx = (struct r600_context *)ctx;
877 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
878
879 if (rctx->ps_shader == sel) {
880 rctx->ps_shader = NULL;
881 }
882
883 r600_delete_shader_selector(ctx, sel);
884 }
885
886 void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
887 {
888 struct r600_context *rctx = (struct r600_context *)ctx;
889 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
890
891 if (rctx->vs_shader == sel) {
892 rctx->vs_shader = NULL;
893 }
894
895 r600_delete_shader_selector(ctx, sel);
896 }
897
898 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
899 {
900 if (state->dirty_mask) {
901 r600_inval_shader_cache(rctx);
902 state->atom.num_dw = rctx->chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
903 : util_bitcount(state->dirty_mask)*19;
904 r600_atom_dirty(rctx, &state->atom);
905 }
906 }
907
908 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
909 struct pipe_constant_buffer *input)
910 {
911 struct r600_context *rctx = (struct r600_context *)ctx;
912 struct r600_constbuf_state *state;
913 struct pipe_constant_buffer *cb;
914 const uint8_t *ptr;
915
916 switch (shader) {
917 case PIPE_SHADER_VERTEX:
918 state = &rctx->vs_constbuf_state;
919 break;
920 case PIPE_SHADER_FRAGMENT:
921 state = &rctx->ps_constbuf_state;
922 break;
923 default:
924 return;
925 }
926
927 /* Note that the state tracker can unbind constant buffers by
928 * passing NULL here.
929 */
930 if (unlikely(!input)) {
931 state->enabled_mask &= ~(1 << index);
932 state->dirty_mask &= ~(1 << index);
933 pipe_resource_reference(&state->cb[index].buffer, NULL);
934 return;
935 }
936
937 cb = &state->cb[index];
938 cb->buffer_size = input->buffer_size;
939
940 ptr = input->user_buffer;
941
942 if (ptr) {
943 /* Upload the user buffer. */
944 if (R600_BIG_ENDIAN) {
945 uint32_t *tmpPtr;
946 unsigned i, size = input->buffer_size;
947
948 if (!(tmpPtr = malloc(size))) {
949 R600_ERR("Failed to allocate BE swap buffer.\n");
950 return;
951 }
952
953 for (i = 0; i < size / 4; ++i) {
954 tmpPtr[i] = bswap_32(((uint32_t *)ptr)[i]);
955 }
956
957 u_upload_data(rctx->uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer);
958 free(tmpPtr);
959 } else {
960 u_upload_data(rctx->uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer);
961 }
962 } else {
963 /* Setup the hw buffer. */
964 cb->buffer_offset = input->buffer_offset;
965 pipe_resource_reference(&cb->buffer, input->buffer);
966 }
967
968 state->enabled_mask |= 1 << index;
969 state->dirty_mask |= 1 << index;
970 r600_constant_buffers_dirty(rctx, state);
971 }
972
973 struct pipe_stream_output_target *
974 r600_create_so_target(struct pipe_context *ctx,
975 struct pipe_resource *buffer,
976 unsigned buffer_offset,
977 unsigned buffer_size)
978 {
979 struct r600_context *rctx = (struct r600_context *)ctx;
980 struct r600_so_target *t;
981 void *ptr;
982
983 t = CALLOC_STRUCT(r600_so_target);
984 if (!t) {
985 return NULL;
986 }
987
988 t->b.reference.count = 1;
989 t->b.context = ctx;
990 pipe_resource_reference(&t->b.buffer, buffer);
991 t->b.buffer_offset = buffer_offset;
992 t->b.buffer_size = buffer_size;
993
994 t->filled_size = (struct r600_resource*)
995 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4);
996 ptr = rctx->ws->buffer_map(t->filled_size->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
997 memset(ptr, 0, t->filled_size->buf->size);
998 rctx->ws->buffer_unmap(t->filled_size->cs_buf);
999
1000 return &t->b;
1001 }
1002
1003 void r600_so_target_destroy(struct pipe_context *ctx,
1004 struct pipe_stream_output_target *target)
1005 {
1006 struct r600_so_target *t = (struct r600_so_target*)target;
1007 pipe_resource_reference(&t->b.buffer, NULL);
1008 pipe_resource_reference((struct pipe_resource**)&t->filled_size, NULL);
1009 FREE(t);
1010 }
1011
1012 void r600_set_so_targets(struct pipe_context *ctx,
1013 unsigned num_targets,
1014 struct pipe_stream_output_target **targets,
1015 unsigned append_bitmask)
1016 {
1017 struct r600_context *rctx = (struct r600_context *)ctx;
1018 unsigned i;
1019
1020 /* Stop streamout. */
1021 if (rctx->num_so_targets && !rctx->streamout_start) {
1022 r600_context_streamout_end(rctx);
1023 }
1024
1025 /* Set the new targets. */
1026 for (i = 0; i < num_targets; i++) {
1027 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]);
1028 }
1029 for (; i < rctx->num_so_targets; i++) {
1030 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL);
1031 }
1032
1033 rctx->num_so_targets = num_targets;
1034 rctx->streamout_start = num_targets != 0;
1035 rctx->streamout_append_bitmask = append_bitmask;
1036 }
1037
1038 void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1039 {
1040 struct r600_context *rctx = (struct r600_context*)pipe;
1041
1042 if (rctx->sample_mask.sample_mask == (uint16_t)sample_mask)
1043 return;
1044
1045 rctx->sample_mask.sample_mask = sample_mask;
1046 r600_atom_dirty(rctx, &rctx->sample_mask.atom);
1047 }
1048
1049 static void r600_update_derived_state(struct r600_context *rctx)
1050 {
1051 struct pipe_context * ctx = (struct pipe_context*)rctx;
1052 unsigned ps_dirty = 0, blend_override;
1053
1054 if (!rctx->blitter->running) {
1055 /* Decompress textures if needed. */
1056 if (rctx->vs_samplers.views.compressed_depthtex_mask) {
1057 r600_decompress_depth_textures(rctx, &rctx->vs_samplers.views);
1058 }
1059 if (rctx->ps_samplers.views.compressed_depthtex_mask) {
1060 r600_decompress_depth_textures(rctx, &rctx->ps_samplers.views);
1061 }
1062 if (rctx->vs_samplers.views.compressed_colortex_mask) {
1063 r600_decompress_color_textures(rctx, &rctx->vs_samplers.views);
1064 }
1065 if (rctx->ps_samplers.views.compressed_colortex_mask) {
1066 r600_decompress_color_textures(rctx, &rctx->ps_samplers.views);
1067 }
1068 }
1069
1070 r600_shader_select(ctx, rctx->ps_shader, &ps_dirty);
1071
1072 if (rctx->ps_shader && ((rctx->sprite_coord_enable &&
1073 (rctx->ps_shader->current->sprite_coord_enable != rctx->sprite_coord_enable)) ||
1074 (rctx->rasterizer && rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade))) {
1075
1076 if (rctx->chip_class >= EVERGREEN)
1077 evergreen_pipe_shader_ps(ctx, rctx->ps_shader->current);
1078 else
1079 r600_pipe_shader_ps(ctx, rctx->ps_shader->current);
1080
1081 ps_dirty = 1;
1082 }
1083
1084 if (ps_dirty)
1085 r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
1086
1087 blend_override = (rctx->dual_src_blend &&
1088 rctx->ps_shader->current->nr_ps_color_outputs < 2);
1089
1090 if (blend_override != rctx->blend_override) {
1091 rctx->blend_override = blend_override;
1092 r600_bind_blend_state_internal(rctx,
1093 blend_override ? rctx->no_blend : rctx->blend);
1094 }
1095
1096 if (rctx->chip_class >= EVERGREEN) {
1097 evergreen_update_dual_export_state(rctx);
1098 } else {
1099 r600_update_dual_export_state(rctx);
1100 }
1101 }
1102
1103 static unsigned r600_conv_prim_to_gs_out(unsigned mode)
1104 {
1105 static const int prim_conv[] = {
1106 V_028A6C_OUTPRIM_TYPE_POINTLIST,
1107 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1108 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1109 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1110 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1111 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1112 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1113 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1114 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1115 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1116 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1117 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1118 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1119 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1120 V_028A6C_OUTPRIM_TYPE_TRISTRIP
1121 };
1122 assert(mode < Elements(prim_conv));
1123
1124 return prim_conv[mode];
1125 }
1126
1127 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
1128 {
1129 struct r600_context *rctx = (struct r600_context *)ctx;
1130 struct pipe_draw_info info = *dinfo;
1131 struct pipe_index_buffer ib = {};
1132 unsigned prim, ls_mask = 0, i;
1133 struct r600_block *dirty_block = NULL, *next_block = NULL;
1134 struct radeon_winsys_cs *cs = rctx->cs;
1135 uint64_t va;
1136 uint8_t *ptr;
1137
1138 if ((!info.count && (info.indexed || !info.count_from_stream_output)) ||
1139 !r600_conv_pipe_prim(info.mode, &prim)) {
1140 assert(0);
1141 return;
1142 }
1143
1144 if (!rctx->vs_shader) {
1145 assert(0);
1146 return;
1147 }
1148
1149 r600_update_derived_state(rctx);
1150
1151 /* partial flush triggered by border color change */
1152 if (rctx->flags & R600_PARTIAL_FLUSH) {
1153 rctx->flags &= ~R600_PARTIAL_FLUSH;
1154 r600_write_value(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1155 r600_write_value(cs, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1156 }
1157
1158 if (info.indexed) {
1159 /* Initialize the index buffer struct. */
1160 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
1161 ib.user_buffer = rctx->index_buffer.user_buffer;
1162 ib.index_size = rctx->index_buffer.index_size;
1163 ib.offset = rctx->index_buffer.offset + info.start * ib.index_size;
1164
1165 /* Translate or upload, if needed. */
1166 r600_translate_index_buffer(rctx, &ib, info.count);
1167
1168 ptr = (uint8_t*)ib.user_buffer;
1169 if (!ib.buffer && ptr) {
1170 u_upload_data(rctx->uploader, 0, info.count * ib.index_size,
1171 ptr, &ib.offset, &ib.buffer);
1172 }
1173 } else {
1174 info.index_bias = info.start;
1175 }
1176
1177 if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
1178 rctx->vgt.id = R600_PIPE_STATE_VGT;
1179 rctx->vgt.nregs = 0;
1180 r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim);
1181 r600_pipe_state_add_reg(&rctx->vgt, R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0);
1182 r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias);
1183 r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index);
1184 r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart);
1185 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
1186 r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0);
1187 r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0);
1188 r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0);
1189 }
1190
1191 rctx->vgt.nregs = 0;
1192 r600_pipe_state_mod_reg(&rctx->vgt, prim);
1193 r600_pipe_state_mod_reg(&rctx->vgt, r600_conv_prim_to_gs_out(info.mode));
1194 r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
1195 r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
1196 r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart);
1197 r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance);
1198
1199 if (prim == V_008958_DI_PT_LINELIST)
1200 ls_mask = 1;
1201 else if (prim == V_008958_DI_PT_LINESTRIP ||
1202 prim == V_008958_DI_PT_LINELOOP)
1203 ls_mask = 2;
1204 r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask) | rctx->pa_sc_line_stipple);
1205 r600_pipe_state_mod_reg(&rctx->vgt,
1206 rctx->vs_shader->current->pa_cl_vs_out_cntl |
1207 (rctx->rasterizer->clip_plane_enable & rctx->vs_shader->current->shader.clip_dist_write));
1208 r600_pipe_state_mod_reg(&rctx->vgt,
1209 rctx->pa_cl_clip_cntl |
1210 (rctx->vs_shader->current->shader.clip_dist_write ||
1211 rctx->vs_shader->current->shader.vs_prohibit_ucps ?
1212 0 : rctx->rasterizer->clip_plane_enable & 0x3F));
1213
1214 r600_context_pipe_state_set(rctx, &rctx->vgt);
1215
1216 /* Enable stream out if needed. */
1217 if (rctx->streamout_start) {
1218 r600_context_streamout_begin(rctx);
1219 rctx->streamout_start = FALSE;
1220 }
1221
1222 /* Emit states (the function expects that we emit at most 17 dwords here). */
1223 r600_need_cs_space(rctx, 0, TRUE);
1224
1225 for (i = 0; i < R600_MAX_ATOM; i++) {
1226 if (rctx->atoms[i] == NULL || !rctx->atoms[i]->dirty) {
1227 continue;
1228 }
1229 r600_emit_atom(rctx, rctx->atoms[i]);
1230 }
1231 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) {
1232 r600_context_block_emit_dirty(rctx, dirty_block, 0 /* pkt_flags */);
1233 }
1234 rctx->pm4_dirty_cdwords = 0;
1235
1236 /* draw packet */
1237 cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->predicate_drawing);
1238 cs->buf[cs->cdw++] = info.instance_count;
1239 if (info.indexed) {
1240 cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->predicate_drawing);
1241 cs->buf[cs->cdw++] = ib.index_size == 4 ?
1242 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
1243 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
1244
1245 va = r600_resource_va(ctx->screen, ib.buffer);
1246 va += ib.offset;
1247 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->predicate_drawing);
1248 cs->buf[cs->cdw++] = va;
1249 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
1250 cs->buf[cs->cdw++] = info.count;
1251 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
1252 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->predicate_drawing);
1253 cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
1254 } else {
1255 if (info.count_from_stream_output) {
1256 struct r600_so_target *t = (struct r600_so_target*)info.count_from_stream_output;
1257 uint64_t va = r600_resource_va(&rctx->screen->screen, (void*)t->filled_size);
1258
1259 r600_write_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
1260
1261 cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0);
1262 cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG;
1263 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */
1264 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
1265 cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */
1266 cs->buf[cs->cdw++] = 0; /* unused */
1267
1268 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1269 cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, t->filled_size, RADEON_USAGE_READ);
1270 }
1271
1272 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->predicate_drawing);
1273 cs->buf[cs->cdw++] = info.count;
1274 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
1275 (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
1276 }
1277
1278 rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING;
1279
1280 /* Set the depth buffer as dirty. */
1281 if (rctx->framebuffer.zsbuf) {
1282 struct pipe_surface *surf = rctx->framebuffer.zsbuf;
1283 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
1284
1285 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1286 }
1287 if (rctx->compressed_cb_mask) {
1288 struct pipe_surface *surf;
1289 struct r600_texture *rtex;
1290 unsigned mask = rctx->compressed_cb_mask;
1291
1292 do {
1293 unsigned i = u_bit_scan(&mask);
1294 surf = rctx->framebuffer.cbufs[i];
1295 rtex = (struct r600_texture*)surf->texture;
1296
1297 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1298
1299 } while (mask);
1300 }
1301
1302 pipe_resource_reference(&ib.buffer, NULL);
1303 }
1304
1305 void r600_draw_rectangle(struct blitter_context *blitter,
1306 unsigned x1, unsigned y1, unsigned x2, unsigned y2, float depth,
1307 enum blitter_attrib_type type, const union pipe_color_union *attrib)
1308 {
1309 struct r600_context *rctx = (struct r600_context*)util_blitter_get_pipe(blitter);
1310 struct pipe_viewport_state viewport;
1311 struct pipe_resource *buf = NULL;
1312 unsigned offset = 0;
1313 float *vb;
1314
1315 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
1316 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
1317 return;
1318 }
1319
1320 /* Some operations (like color resolve on r6xx) don't work
1321 * with the conventional primitive types.
1322 * One that works is PT_RECTLIST, which we use here. */
1323
1324 /* setup viewport */
1325 viewport.scale[0] = 1.0f;
1326 viewport.scale[1] = 1.0f;
1327 viewport.scale[2] = 1.0f;
1328 viewport.scale[3] = 1.0f;
1329 viewport.translate[0] = 0.0f;
1330 viewport.translate[1] = 0.0f;
1331 viewport.translate[2] = 0.0f;
1332 viewport.translate[3] = 0.0f;
1333 rctx->context.set_viewport_state(&rctx->context, &viewport);
1334
1335 /* Upload vertices. The hw rectangle has only 3 vertices,
1336 * I guess the 4th one is derived from the first 3.
1337 * The vertex specification should match u_blitter's vertex element state. */
1338 u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, &offset, &buf, (void**)&vb);
1339 vb[0] = x1;
1340 vb[1] = y1;
1341 vb[2] = depth;
1342 vb[3] = 1;
1343
1344 vb[8] = x1;
1345 vb[9] = y2;
1346 vb[10] = depth;
1347 vb[11] = 1;
1348
1349 vb[16] = x2;
1350 vb[17] = y1;
1351 vb[18] = depth;
1352 vb[19] = 1;
1353
1354 if (attrib) {
1355 memcpy(vb+4, attrib->f, sizeof(float)*4);
1356 memcpy(vb+12, attrib->f, sizeof(float)*4);
1357 memcpy(vb+20, attrib->f, sizeof(float)*4);
1358 }
1359
1360 /* draw */
1361 util_draw_vertex_buffer(&rctx->context, NULL, buf, offset,
1362 R600_PRIM_RECTANGLE_LIST, 3, 2);
1363 pipe_resource_reference(&buf, NULL);
1364 }
1365
1366 void _r600_pipe_state_add_reg_bo(struct r600_context *ctx,
1367 struct r600_pipe_state *state,
1368 uint32_t offset, uint32_t value,
1369 uint32_t range_id, uint32_t block_id,
1370 struct r600_resource *bo,
1371 enum radeon_bo_usage usage)
1372
1373 {
1374 struct r600_range *range;
1375 struct r600_block *block;
1376
1377 if (bo) assert(usage);
1378
1379 range = &ctx->range[range_id];
1380 block = range->blocks[block_id];
1381 state->regs[state->nregs].block = block;
1382 state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
1383
1384 state->regs[state->nregs].value = value;
1385 state->regs[state->nregs].bo = bo;
1386 state->regs[state->nregs].bo_usage = usage;
1387
1388 state->nregs++;
1389 assert(state->nregs < R600_BLOCK_MAX_REG);
1390 }
1391
1392 void _r600_pipe_state_add_reg(struct r600_context *ctx,
1393 struct r600_pipe_state *state,
1394 uint32_t offset, uint32_t value,
1395 uint32_t range_id, uint32_t block_id)
1396 {
1397 _r600_pipe_state_add_reg_bo(ctx, state, offset, value,
1398 range_id, block_id, NULL, 0);
1399 }
1400
1401 uint32_t r600_translate_stencil_op(int s_op)
1402 {
1403 switch (s_op) {
1404 case PIPE_STENCIL_OP_KEEP:
1405 return V_028800_STENCIL_KEEP;
1406 case PIPE_STENCIL_OP_ZERO:
1407 return V_028800_STENCIL_ZERO;
1408 case PIPE_STENCIL_OP_REPLACE:
1409 return V_028800_STENCIL_REPLACE;
1410 case PIPE_STENCIL_OP_INCR:
1411 return V_028800_STENCIL_INCR;
1412 case PIPE_STENCIL_OP_DECR:
1413 return V_028800_STENCIL_DECR;
1414 case PIPE_STENCIL_OP_INCR_WRAP:
1415 return V_028800_STENCIL_INCR_WRAP;
1416 case PIPE_STENCIL_OP_DECR_WRAP:
1417 return V_028800_STENCIL_DECR_WRAP;
1418 case PIPE_STENCIL_OP_INVERT:
1419 return V_028800_STENCIL_INVERT;
1420 default:
1421 R600_ERR("Unknown stencil op %d", s_op);
1422 assert(0);
1423 break;
1424 }
1425 return 0;
1426 }
1427
1428 uint32_t r600_translate_fill(uint32_t func)
1429 {
1430 switch(func) {
1431 case PIPE_POLYGON_MODE_FILL:
1432 return 2;
1433 case PIPE_POLYGON_MODE_LINE:
1434 return 1;
1435 case PIPE_POLYGON_MODE_POINT:
1436 return 0;
1437 default:
1438 assert(0);
1439 return 0;
1440 }
1441 }
1442
1443 unsigned r600_tex_wrap(unsigned wrap)
1444 {
1445 switch (wrap) {
1446 default:
1447 case PIPE_TEX_WRAP_REPEAT:
1448 return V_03C000_SQ_TEX_WRAP;
1449 case PIPE_TEX_WRAP_CLAMP:
1450 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1451 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1452 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1453 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1454 return V_03C000_SQ_TEX_CLAMP_BORDER;
1455 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1456 return V_03C000_SQ_TEX_MIRROR;
1457 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1458 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1459 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1460 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1461 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1462 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1463 }
1464 }
1465
1466 unsigned r600_tex_filter(unsigned filter)
1467 {
1468 switch (filter) {
1469 default:
1470 case PIPE_TEX_FILTER_NEAREST:
1471 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1472 case PIPE_TEX_FILTER_LINEAR:
1473 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1474 }
1475 }
1476
1477 unsigned r600_tex_mipfilter(unsigned filter)
1478 {
1479 switch (filter) {
1480 case PIPE_TEX_MIPFILTER_NEAREST:
1481 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1482 case PIPE_TEX_MIPFILTER_LINEAR:
1483 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1484 default:
1485 case PIPE_TEX_MIPFILTER_NONE:
1486 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1487 }
1488 }
1489
1490 unsigned r600_tex_compare(unsigned compare)
1491 {
1492 switch (compare) {
1493 default:
1494 case PIPE_FUNC_NEVER:
1495 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1496 case PIPE_FUNC_LESS:
1497 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1498 case PIPE_FUNC_EQUAL:
1499 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1500 case PIPE_FUNC_LEQUAL:
1501 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1502 case PIPE_FUNC_GREATER:
1503 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1504 case PIPE_FUNC_NOTEQUAL:
1505 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1506 case PIPE_FUNC_GEQUAL:
1507 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1508 case PIPE_FUNC_ALWAYS:
1509 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1510 }
1511 }