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r600g: fix alpha-test with HyperZ enabled, fixing L4D2 tree corruption
[mesa.git] / src / gallium / drivers / r600 / r600_state_common.c
1 /*
2 * Copyright 2010 Red Hat Inc.
3 * 2010 Jerome Glisse
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
26 */
27 #include "r600_formats.h"
28 #include "r600_shader.h"
29 #include "r600d.h"
30
31 #include "util/u_format_s3tc.h"
32 #include "util/u_index_modify.h"
33 #include "util/u_memory.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_math.h"
36 #include "tgsi/tgsi_parse.h"
37
38 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw)
39 {
40 assert(!cb->buf);
41 cb->buf = CALLOC(1, 4 * num_dw);
42 cb->max_num_dw = num_dw;
43 }
44
45 void r600_release_command_buffer(struct r600_command_buffer *cb)
46 {
47 FREE(cb->buf);
48 }
49
50 void r600_init_atom(struct r600_context *rctx,
51 struct r600_atom *atom,
52 unsigned id,
53 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
54 unsigned num_dw)
55 {
56 assert(id < R600_NUM_ATOMS);
57 assert(rctx->atoms[id] == NULL);
58 rctx->atoms[id] = atom;
59 atom->emit = (void*)emit;
60 atom->num_dw = num_dw;
61 atom->dirty = false;
62 }
63
64 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom)
65 {
66 r600_emit_command_buffer(rctx->b.rings.gfx.cs, ((struct r600_cso_state*)atom)->cb);
67 }
68
69 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom)
70 {
71 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
72 struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom;
73 unsigned alpha_ref = a->sx_alpha_ref;
74
75 if (rctx->b.chip_class >= EVERGREEN && a->cb0_export_16bpc) {
76 alpha_ref &= ~0x1FFF;
77 }
78
79 r600_write_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL,
80 a->sx_alpha_test_control |
81 S_028410_ALPHA_TEST_BYPASS(a->bypass));
82 r600_write_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref);
83 }
84
85 static void r600_texture_barrier(struct pipe_context *ctx)
86 {
87 struct r600_context *rctx = (struct r600_context *)ctx;
88
89 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
90 R600_CONTEXT_FLUSH_AND_INV_CB |
91 R600_CONTEXT_FLUSH_AND_INV |
92 R600_CONTEXT_WAIT_3D_IDLE;
93 }
94
95 static unsigned r600_conv_pipe_prim(unsigned prim)
96 {
97 static const unsigned prim_conv[] = {
98 V_008958_DI_PT_POINTLIST,
99 V_008958_DI_PT_LINELIST,
100 V_008958_DI_PT_LINELOOP,
101 V_008958_DI_PT_LINESTRIP,
102 V_008958_DI_PT_TRILIST,
103 V_008958_DI_PT_TRISTRIP,
104 V_008958_DI_PT_TRIFAN,
105 V_008958_DI_PT_QUADLIST,
106 V_008958_DI_PT_QUADSTRIP,
107 V_008958_DI_PT_POLYGON,
108 V_008958_DI_PT_LINELIST_ADJ,
109 V_008958_DI_PT_LINESTRIP_ADJ,
110 V_008958_DI_PT_TRILIST_ADJ,
111 V_008958_DI_PT_TRISTRIP_ADJ,
112 V_008958_DI_PT_RECTLIST
113 };
114 return prim_conv[prim];
115 }
116
117 /* common state between evergreen and r600 */
118
119 static void r600_bind_blend_state_internal(struct r600_context *rctx,
120 struct r600_blend_state *blend, bool blend_disable)
121 {
122 unsigned color_control;
123 bool update_cb = false;
124
125 rctx->alpha_to_one = blend->alpha_to_one;
126 rctx->dual_src_blend = blend->dual_src_blend;
127
128 if (!blend_disable) {
129 r600_set_cso_state_with_cb(&rctx->blend_state, blend, &blend->buffer);
130 color_control = blend->cb_color_control;
131 } else {
132 /* Blending is disabled. */
133 r600_set_cso_state_with_cb(&rctx->blend_state, blend, &blend->buffer_no_blend);
134 color_control = blend->cb_color_control_no_blend;
135 }
136
137 /* Update derived states. */
138 if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) {
139 rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
140 update_cb = true;
141 }
142 if (rctx->b.chip_class <= R700 &&
143 rctx->cb_misc_state.cb_color_control != color_control) {
144 rctx->cb_misc_state.cb_color_control = color_control;
145 update_cb = true;
146 }
147 if (rctx->cb_misc_state.dual_src_blend != blend->dual_src_blend) {
148 rctx->cb_misc_state.dual_src_blend = blend->dual_src_blend;
149 update_cb = true;
150 }
151 if (update_cb) {
152 rctx->cb_misc_state.atom.dirty = true;
153 }
154 }
155
156 static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
157 {
158 struct r600_context *rctx = (struct r600_context *)ctx;
159 struct r600_blend_state *blend = (struct r600_blend_state *)state;
160
161 if (blend == NULL)
162 return;
163
164 r600_bind_blend_state_internal(rctx, blend, rctx->force_blend_disable);
165 }
166
167 static void r600_set_blend_color(struct pipe_context *ctx,
168 const struct pipe_blend_color *state)
169 {
170 struct r600_context *rctx = (struct r600_context *)ctx;
171
172 rctx->blend_color.state = *state;
173 rctx->blend_color.atom.dirty = true;
174 }
175
176 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom)
177 {
178 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
179 struct pipe_blend_color *state = &rctx->blend_color.state;
180
181 r600_write_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
182 radeon_emit(cs, fui(state->color[0])); /* R_028414_CB_BLEND_RED */
183 radeon_emit(cs, fui(state->color[1])); /* R_028418_CB_BLEND_GREEN */
184 radeon_emit(cs, fui(state->color[2])); /* R_02841C_CB_BLEND_BLUE */
185 radeon_emit(cs, fui(state->color[3])); /* R_028420_CB_BLEND_ALPHA */
186 }
187
188 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom)
189 {
190 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
191 struct r600_vgt_state *a = (struct r600_vgt_state *)atom;
192
193 r600_write_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, a->vgt_multi_prim_ib_reset_en);
194 r600_write_context_reg_seq(cs, R_028408_VGT_INDX_OFFSET, 2);
195 radeon_emit(cs, a->vgt_indx_offset); /* R_028408_VGT_INDX_OFFSET */
196 radeon_emit(cs, a->vgt_multi_prim_ib_reset_indx); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
197 }
198
199 static void r600_set_clip_state(struct pipe_context *ctx,
200 const struct pipe_clip_state *state)
201 {
202 struct r600_context *rctx = (struct r600_context *)ctx;
203 struct pipe_constant_buffer cb;
204
205 rctx->clip_state.state = *state;
206 rctx->clip_state.atom.dirty = true;
207
208 cb.buffer = NULL;
209 cb.user_buffer = state->ucp;
210 cb.buffer_offset = 0;
211 cb.buffer_size = 4*4*8;
212 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, R600_UCP_CONST_BUFFER, &cb);
213 pipe_resource_reference(&cb.buffer, NULL);
214 }
215
216 static void r600_set_stencil_ref(struct pipe_context *ctx,
217 const struct r600_stencil_ref *state)
218 {
219 struct r600_context *rctx = (struct r600_context *)ctx;
220
221 rctx->stencil_ref.state = *state;
222 rctx->stencil_ref.atom.dirty = true;
223 }
224
225 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom)
226 {
227 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
228 struct r600_stencil_ref_state *a = (struct r600_stencil_ref_state*)atom;
229
230 r600_write_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
231 radeon_emit(cs, /* R_028430_DB_STENCILREFMASK */
232 S_028430_STENCILREF(a->state.ref_value[0]) |
233 S_028430_STENCILMASK(a->state.valuemask[0]) |
234 S_028430_STENCILWRITEMASK(a->state.writemask[0]));
235 radeon_emit(cs, /* R_028434_DB_STENCILREFMASK_BF */
236 S_028434_STENCILREF_BF(a->state.ref_value[1]) |
237 S_028434_STENCILMASK_BF(a->state.valuemask[1]) |
238 S_028434_STENCILWRITEMASK_BF(a->state.writemask[1]));
239 }
240
241 static void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
242 const struct pipe_stencil_ref *state)
243 {
244 struct r600_context *rctx = (struct r600_context *)ctx;
245 struct r600_dsa_state *dsa = (struct r600_dsa_state*)rctx->dsa_state.cso;
246 struct r600_stencil_ref ref;
247
248 rctx->stencil_ref.pipe_state = *state;
249
250 if (!dsa)
251 return;
252
253 ref.ref_value[0] = state->ref_value[0];
254 ref.ref_value[1] = state->ref_value[1];
255 ref.valuemask[0] = dsa->valuemask[0];
256 ref.valuemask[1] = dsa->valuemask[1];
257 ref.writemask[0] = dsa->writemask[0];
258 ref.writemask[1] = dsa->writemask[1];
259
260 r600_set_stencil_ref(ctx, &ref);
261 }
262
263 static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
264 {
265 struct r600_context *rctx = (struct r600_context *)ctx;
266 struct r600_dsa_state *dsa = state;
267 struct r600_stencil_ref ref;
268
269 if (state == NULL) {
270 r600_set_cso_state_with_cb(&rctx->dsa_state, NULL, NULL);
271 return;
272 }
273
274 r600_set_cso_state_with_cb(&rctx->dsa_state, dsa, &dsa->buffer);
275
276 ref.ref_value[0] = rctx->stencil_ref.pipe_state.ref_value[0];
277 ref.ref_value[1] = rctx->stencil_ref.pipe_state.ref_value[1];
278 ref.valuemask[0] = dsa->valuemask[0];
279 ref.valuemask[1] = dsa->valuemask[1];
280 ref.writemask[0] = dsa->writemask[0];
281 ref.writemask[1] = dsa->writemask[1];
282 if (rctx->zwritemask != dsa->zwritemask) {
283 rctx->zwritemask = dsa->zwritemask;
284 if (rctx->b.chip_class >= EVERGREEN) {
285 /* work around some issue when not writting to zbuffer
286 * we are having lockup on evergreen so do not enable
287 * hyperz when not writting zbuffer
288 */
289 rctx->db_misc_state.atom.dirty = true;
290 }
291 }
292
293 r600_set_stencil_ref(ctx, &ref);
294
295 /* Update alphatest state. */
296 if (rctx->alphatest_state.sx_alpha_test_control != dsa->sx_alpha_test_control ||
297 rctx->alphatest_state.sx_alpha_ref != dsa->alpha_ref) {
298 rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control;
299 rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref;
300 rctx->alphatest_state.atom.dirty = true;
301 }
302 }
303
304 static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
305 {
306 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
307 struct r600_context *rctx = (struct r600_context *)ctx;
308
309 if (state == NULL)
310 return;
311
312 rctx->rasterizer = rs;
313
314 r600_set_cso_state_with_cb(&rctx->rasterizer_state, rs, &rs->buffer);
315
316 if (rs->offset_enable &&
317 (rs->offset_units != rctx->poly_offset_state.offset_units ||
318 rs->offset_scale != rctx->poly_offset_state.offset_scale)) {
319 rctx->poly_offset_state.offset_units = rs->offset_units;
320 rctx->poly_offset_state.offset_scale = rs->offset_scale;
321 rctx->poly_offset_state.atom.dirty = true;
322 }
323
324 /* Update clip_misc_state. */
325 if (rctx->clip_misc_state.pa_cl_clip_cntl != rs->pa_cl_clip_cntl ||
326 rctx->clip_misc_state.clip_plane_enable != rs->clip_plane_enable) {
327 rctx->clip_misc_state.pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
328 rctx->clip_misc_state.clip_plane_enable = rs->clip_plane_enable;
329 rctx->clip_misc_state.atom.dirty = true;
330 }
331
332 /* Workaround for a missing scissor enable on r600. */
333 if (rctx->b.chip_class == R600 &&
334 rs->scissor_enable != rctx->scissor[0].enable) {
335 rctx->scissor[0].enable = rs->scissor_enable;
336 rctx->scissor[0].atom.dirty = true;
337 }
338
339 /* Re-emit PA_SC_LINE_STIPPLE. */
340 rctx->last_primitive_type = -1;
341 }
342
343 static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
344 {
345 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
346
347 r600_release_command_buffer(&rs->buffer);
348 FREE(rs);
349 }
350
351 static void r600_sampler_view_destroy(struct pipe_context *ctx,
352 struct pipe_sampler_view *state)
353 {
354 struct r600_pipe_sampler_view *view = (struct r600_pipe_sampler_view *)state;
355
356 if (view->tex_resource->gpu_address &&
357 view->tex_resource->b.b.target == PIPE_BUFFER)
358 LIST_DELINIT(&view->list);
359
360 pipe_resource_reference(&state->texture, NULL);
361 FREE(view);
362 }
363
364 void r600_sampler_states_dirty(struct r600_context *rctx,
365 struct r600_sampler_states *state)
366 {
367 if (state->dirty_mask) {
368 if (state->dirty_mask & state->has_bordercolor_mask) {
369 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
370 }
371 state->atom.num_dw =
372 util_bitcount(state->dirty_mask & state->has_bordercolor_mask) * 11 +
373 util_bitcount(state->dirty_mask & ~state->has_bordercolor_mask) * 5;
374 state->atom.dirty = true;
375 }
376 }
377
378 static void r600_bind_sampler_states(struct pipe_context *pipe,
379 unsigned shader,
380 unsigned start,
381 unsigned count, void **states)
382 {
383 struct r600_context *rctx = (struct r600_context *)pipe;
384 struct r600_textures_info *dst = &rctx->samplers[shader];
385 struct r600_pipe_sampler_state **rstates = (struct r600_pipe_sampler_state**)states;
386 int seamless_cube_map = -1;
387 unsigned i;
388 /* This sets 1-bit for states with index >= count. */
389 uint32_t disable_mask = ~((1ull << count) - 1);
390 /* These are the new states set by this function. */
391 uint32_t new_mask = 0;
392
393 assert(start == 0); /* XXX fix below */
394
395 if (shader != PIPE_SHADER_VERTEX &&
396 shader != PIPE_SHADER_FRAGMENT) {
397 return;
398 }
399
400 for (i = 0; i < count; i++) {
401 struct r600_pipe_sampler_state *rstate = rstates[i];
402
403 if (rstate == dst->states.states[i]) {
404 continue;
405 }
406
407 if (rstate) {
408 if (rstate->border_color_use) {
409 dst->states.has_bordercolor_mask |= 1 << i;
410 } else {
411 dst->states.has_bordercolor_mask &= ~(1 << i);
412 }
413 seamless_cube_map = rstate->seamless_cube_map;
414
415 new_mask |= 1 << i;
416 } else {
417 disable_mask |= 1 << i;
418 }
419 }
420
421 memcpy(dst->states.states, rstates, sizeof(void*) * count);
422 memset(dst->states.states + count, 0, sizeof(void*) * (NUM_TEX_UNITS - count));
423
424 dst->states.enabled_mask &= ~disable_mask;
425 dst->states.dirty_mask &= dst->states.enabled_mask;
426 dst->states.enabled_mask |= new_mask;
427 dst->states.dirty_mask |= new_mask;
428 dst->states.has_bordercolor_mask &= dst->states.enabled_mask;
429
430 r600_sampler_states_dirty(rctx, &dst->states);
431
432 /* Seamless cubemap state. */
433 if (rctx->b.chip_class <= R700 &&
434 seamless_cube_map != -1 &&
435 seamless_cube_map != rctx->seamless_cube_map.enabled) {
436 /* change in TA_CNTL_AUX need a pipeline flush */
437 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
438 rctx->seamless_cube_map.enabled = seamless_cube_map;
439 rctx->seamless_cube_map.atom.dirty = true;
440 }
441 }
442
443 static void r600_delete_sampler_state(struct pipe_context *ctx, void *state)
444 {
445 free(state);
446 }
447
448 static void r600_delete_blend_state(struct pipe_context *ctx, void *state)
449 {
450 struct r600_blend_state *blend = (struct r600_blend_state*)state;
451
452 r600_release_command_buffer(&blend->buffer);
453 r600_release_command_buffer(&blend->buffer_no_blend);
454 FREE(blend);
455 }
456
457 static void r600_delete_dsa_state(struct pipe_context *ctx, void *state)
458 {
459 struct r600_context *rctx = (struct r600_context *)ctx;
460 struct r600_dsa_state *dsa = (struct r600_dsa_state *)state;
461
462 if (rctx->dsa_state.cso == state) {
463 ctx->bind_depth_stencil_alpha_state(ctx, NULL);
464 }
465
466 r600_release_command_buffer(&dsa->buffer);
467 free(dsa);
468 }
469
470 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
471 {
472 struct r600_context *rctx = (struct r600_context *)ctx;
473
474 r600_set_cso_state(&rctx->vertex_fetch_shader, state);
475 }
476
477 static void r600_delete_vertex_elements(struct pipe_context *ctx, void *state)
478 {
479 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state;
480 pipe_resource_reference((struct pipe_resource**)&shader->buffer, NULL);
481 FREE(shader);
482 }
483
484 static void r600_set_index_buffer(struct pipe_context *ctx,
485 const struct pipe_index_buffer *ib)
486 {
487 struct r600_context *rctx = (struct r600_context *)ctx;
488
489 if (ib) {
490 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
491 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
492 r600_context_add_resource_size(ctx, ib->buffer);
493 } else {
494 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
495 }
496 }
497
498 void r600_vertex_buffers_dirty(struct r600_context *rctx)
499 {
500 if (rctx->vertex_buffer_state.dirty_mask) {
501 rctx->b.flags |= R600_CONTEXT_INV_VERTEX_CACHE;
502 rctx->vertex_buffer_state.atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 12 : 11) *
503 util_bitcount(rctx->vertex_buffer_state.dirty_mask);
504 rctx->vertex_buffer_state.atom.dirty = true;
505 }
506 }
507
508 static void r600_set_vertex_buffers(struct pipe_context *ctx,
509 unsigned start_slot, unsigned count,
510 const struct pipe_vertex_buffer *input)
511 {
512 struct r600_context *rctx = (struct r600_context *)ctx;
513 struct r600_vertexbuf_state *state = &rctx->vertex_buffer_state;
514 struct pipe_vertex_buffer *vb = state->vb + start_slot;
515 unsigned i;
516 uint32_t disable_mask = 0;
517 /* These are the new buffers set by this function. */
518 uint32_t new_buffer_mask = 0;
519
520 /* Set vertex buffers. */
521 if (input) {
522 for (i = 0; i < count; i++) {
523 if (memcmp(&input[i], &vb[i], sizeof(struct pipe_vertex_buffer))) {
524 if (input[i].buffer) {
525 vb[i].stride = input[i].stride;
526 vb[i].buffer_offset = input[i].buffer_offset;
527 pipe_resource_reference(&vb[i].buffer, input[i].buffer);
528 new_buffer_mask |= 1 << i;
529 r600_context_add_resource_size(ctx, input[i].buffer);
530 } else {
531 pipe_resource_reference(&vb[i].buffer, NULL);
532 disable_mask |= 1 << i;
533 }
534 }
535 }
536 } else {
537 for (i = 0; i < count; i++) {
538 pipe_resource_reference(&vb[i].buffer, NULL);
539 }
540 disable_mask = ((1ull << count) - 1);
541 }
542
543 disable_mask <<= start_slot;
544 new_buffer_mask <<= start_slot;
545
546 rctx->vertex_buffer_state.enabled_mask &= ~disable_mask;
547 rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask;
548 rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask;
549 rctx->vertex_buffer_state.dirty_mask |= new_buffer_mask;
550
551 r600_vertex_buffers_dirty(rctx);
552 }
553
554 void r600_sampler_views_dirty(struct r600_context *rctx,
555 struct r600_samplerview_state *state)
556 {
557 if (state->dirty_mask) {
558 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
559 state->atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 14 : 13) *
560 util_bitcount(state->dirty_mask);
561 state->atom.dirty = true;
562 }
563 }
564
565 static void r600_set_sampler_views(struct pipe_context *pipe, unsigned shader,
566 unsigned start, unsigned count,
567 struct pipe_sampler_view **views)
568 {
569 struct r600_context *rctx = (struct r600_context *) pipe;
570 struct r600_textures_info *dst = &rctx->samplers[shader];
571 struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
572 uint32_t dirty_sampler_states_mask = 0;
573 unsigned i;
574 /* This sets 1-bit for textures with index >= count. */
575 uint32_t disable_mask = ~((1ull << count) - 1);
576 /* These are the new textures set by this function. */
577 uint32_t new_mask = 0;
578
579 /* Set textures with index >= count to NULL. */
580 uint32_t remaining_mask;
581
582 assert(start == 0); /* XXX fix below */
583
584 if (shader == PIPE_SHADER_COMPUTE) {
585 evergreen_set_cs_sampler_view(pipe, start, count, views);
586 return;
587 }
588
589 remaining_mask = dst->views.enabled_mask & disable_mask;
590
591 while (remaining_mask) {
592 i = u_bit_scan(&remaining_mask);
593 assert(dst->views.views[i]);
594
595 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
596 }
597
598 for (i = 0; i < count; i++) {
599 if (rviews[i] == dst->views.views[i]) {
600 continue;
601 }
602
603 if (rviews[i]) {
604 struct r600_texture *rtex =
605 (struct r600_texture*)rviews[i]->base.texture;
606
607 if (rviews[i]->base.texture->target != PIPE_BUFFER) {
608 if (rtex->is_depth && !rtex->is_flushing_texture) {
609 dst->views.compressed_depthtex_mask |= 1 << i;
610 } else {
611 dst->views.compressed_depthtex_mask &= ~(1 << i);
612 }
613
614 /* Track compressed colorbuffers. */
615 if (rtex->cmask.size) {
616 dst->views.compressed_colortex_mask |= 1 << i;
617 } else {
618 dst->views.compressed_colortex_mask &= ~(1 << i);
619 }
620 }
621 /* Changing from array to non-arrays textures and vice versa requires
622 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
623 if (rctx->b.chip_class <= R700 &&
624 (dst->states.enabled_mask & (1 << i)) &&
625 (rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
626 rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) {
627 dirty_sampler_states_mask |= 1 << i;
628 }
629
630 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]);
631 new_mask |= 1 << i;
632 r600_context_add_resource_size(pipe, views[i]->texture);
633 } else {
634 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
635 disable_mask |= 1 << i;
636 }
637 }
638
639 dst->views.enabled_mask &= ~disable_mask;
640 dst->views.dirty_mask &= dst->views.enabled_mask;
641 dst->views.enabled_mask |= new_mask;
642 dst->views.dirty_mask |= new_mask;
643 dst->views.compressed_depthtex_mask &= dst->views.enabled_mask;
644 dst->views.compressed_colortex_mask &= dst->views.enabled_mask;
645 dst->views.dirty_txq_constants = TRUE;
646 dst->views.dirty_buffer_constants = TRUE;
647 r600_sampler_views_dirty(rctx, &dst->views);
648
649 if (dirty_sampler_states_mask) {
650 dst->states.dirty_mask |= dirty_sampler_states_mask;
651 r600_sampler_states_dirty(rctx, &dst->states);
652 }
653 }
654
655 static void r600_set_viewport_states(struct pipe_context *ctx,
656 unsigned start_slot,
657 unsigned num_viewports,
658 const struct pipe_viewport_state *state)
659 {
660 struct r600_context *rctx = (struct r600_context *)ctx;
661 int i;
662
663 for (i = start_slot; i < start_slot + num_viewports; i++) {
664 rctx->viewport[i].state = state[i - start_slot];
665 rctx->viewport[i].atom.dirty = true;
666 }
667 }
668
669 void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom)
670 {
671 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
672 struct r600_viewport_state *rstate = (struct r600_viewport_state *)atom;
673 struct pipe_viewport_state *state = &rstate->state;
674 int offset = rstate->idx * 6 * 4;
675
676 r600_write_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE_0 + offset, 6);
677 radeon_emit(cs, fui(state->scale[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
678 radeon_emit(cs, fui(state->translate[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
679 radeon_emit(cs, fui(state->scale[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
680 radeon_emit(cs, fui(state->translate[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
681 radeon_emit(cs, fui(state->scale[2])); /* R_02844C_PA_CL_VPORT_ZSCALE_0 */
682 radeon_emit(cs, fui(state->translate[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
683 }
684
685 /* Compute the key for the hw shader variant */
686 static INLINE struct r600_shader_key r600_shader_selector_key(struct pipe_context * ctx,
687 struct r600_pipe_shader_selector * sel)
688 {
689 struct r600_context *rctx = (struct r600_context *)ctx;
690 struct r600_shader_key key;
691 memset(&key, 0, sizeof(key));
692
693 if (sel->type == PIPE_SHADER_FRAGMENT) {
694 key.color_two_side = rctx->rasterizer && rctx->rasterizer->two_side;
695 key.alpha_to_one = rctx->alpha_to_one &&
696 rctx->rasterizer && rctx->rasterizer->multisample_enable &&
697 !rctx->framebuffer.cb0_is_integer;
698 key.nr_cbufs = rctx->framebuffer.state.nr_cbufs;
699 /* Dual-source blending only makes sense with nr_cbufs == 1. */
700 if (key.nr_cbufs == 1 && rctx->dual_src_blend)
701 key.nr_cbufs = 2;
702 } else if (sel->type == PIPE_SHADER_VERTEX) {
703 key.vs_as_es = (rctx->gs_shader != NULL);
704 }
705 return key;
706 }
707
708 /* Select the hw shader variant depending on the current state.
709 * (*dirty) is set to 1 if current variant was changed */
710 static int r600_shader_select(struct pipe_context *ctx,
711 struct r600_pipe_shader_selector* sel,
712 bool *dirty)
713 {
714 struct r600_shader_key key;
715 struct r600_pipe_shader * shader = NULL;
716 int r;
717
718 memset(&key, 0, sizeof(key));
719 key = r600_shader_selector_key(ctx, sel);
720
721 /* Check if we don't need to change anything.
722 * This path is also used for most shaders that don't need multiple
723 * variants, it will cost just a computation of the key and this
724 * test. */
725 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
726 return 0;
727 }
728
729 /* lookup if we have other variants in the list */
730 if (sel->num_shaders > 1) {
731 struct r600_pipe_shader *p = sel->current, *c = p->next_variant;
732
733 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
734 p = c;
735 c = c->next_variant;
736 }
737
738 if (c) {
739 p->next_variant = c->next_variant;
740 shader = c;
741 }
742 }
743
744 if (unlikely(!shader)) {
745 shader = CALLOC(1, sizeof(struct r600_pipe_shader));
746 shader->selector = sel;
747
748 r = r600_pipe_shader_create(ctx, shader, key);
749 if (unlikely(r)) {
750 R600_ERR("Failed to build shader variant (type=%u) %d\n",
751 sel->type, r);
752 sel->current = NULL;
753 FREE(shader);
754 return r;
755 }
756
757 /* We don't know the value of nr_ps_max_color_exports until we built
758 * at least one variant, so we may need to recompute the key after
759 * building first variant. */
760 if (sel->type == PIPE_SHADER_FRAGMENT &&
761 sel->num_shaders == 0) {
762 sel->nr_ps_max_color_exports = shader->shader.nr_ps_max_color_exports;
763 key = r600_shader_selector_key(ctx, sel);
764 }
765
766 memcpy(&shader->key, &key, sizeof(key));
767 sel->num_shaders++;
768 }
769
770 if (dirty)
771 *dirty = true;
772
773 shader->next_variant = sel->current;
774 sel->current = shader;
775
776 return 0;
777 }
778
779 static void *r600_create_shader_state(struct pipe_context *ctx,
780 const struct pipe_shader_state *state,
781 unsigned pipe_shader_type)
782 {
783 struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector);
784
785 sel->type = pipe_shader_type;
786 sel->tokens = tgsi_dup_tokens(state->tokens);
787 sel->so = state->stream_output;
788 return sel;
789 }
790
791 static void *r600_create_ps_state(struct pipe_context *ctx,
792 const struct pipe_shader_state *state)
793 {
794 return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
795 }
796
797 static void *r600_create_vs_state(struct pipe_context *ctx,
798 const struct pipe_shader_state *state)
799 {
800 return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
801 }
802
803 static void *r600_create_gs_state(struct pipe_context *ctx,
804 const struct pipe_shader_state *state)
805 {
806 return r600_create_shader_state(ctx, state, PIPE_SHADER_GEOMETRY);
807 }
808
809 static void r600_bind_ps_state(struct pipe_context *ctx, void *state)
810 {
811 struct r600_context *rctx = (struct r600_context *)ctx;
812
813 if (!state)
814 state = rctx->dummy_pixel_shader;
815
816 rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
817 }
818
819 static void r600_bind_vs_state(struct pipe_context *ctx, void *state)
820 {
821 struct r600_context *rctx = (struct r600_context *)ctx;
822
823 if (!state)
824 return;
825
826 rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
827 rctx->b.streamout.stride_in_dw = rctx->vs_shader->so.stride;
828 }
829
830 static void r600_bind_gs_state(struct pipe_context *ctx, void *state)
831 {
832 struct r600_context *rctx = (struct r600_context *)ctx;
833
834 rctx->gs_shader = (struct r600_pipe_shader_selector *)state;
835
836 if (!state)
837 return;
838 rctx->b.streamout.stride_in_dw = rctx->gs_shader->so.stride;
839 }
840
841 static void r600_delete_shader_selector(struct pipe_context *ctx,
842 struct r600_pipe_shader_selector *sel)
843 {
844 struct r600_pipe_shader *p = sel->current, *c;
845 while (p) {
846 c = p->next_variant;
847 r600_pipe_shader_destroy(ctx, p);
848 free(p);
849 p = c;
850 }
851
852 free(sel->tokens);
853 free(sel);
854 }
855
856
857 static void r600_delete_ps_state(struct pipe_context *ctx, void *state)
858 {
859 struct r600_context *rctx = (struct r600_context *)ctx;
860 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
861
862 if (rctx->ps_shader == sel) {
863 rctx->ps_shader = NULL;
864 }
865
866 r600_delete_shader_selector(ctx, sel);
867 }
868
869 static void r600_delete_vs_state(struct pipe_context *ctx, void *state)
870 {
871 struct r600_context *rctx = (struct r600_context *)ctx;
872 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
873
874 if (rctx->vs_shader == sel) {
875 rctx->vs_shader = NULL;
876 }
877
878 r600_delete_shader_selector(ctx, sel);
879 }
880
881
882 static void r600_delete_gs_state(struct pipe_context *ctx, void *state)
883 {
884 struct r600_context *rctx = (struct r600_context *)ctx;
885 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
886
887 if (rctx->gs_shader == sel) {
888 rctx->gs_shader = NULL;
889 }
890
891 r600_delete_shader_selector(ctx, sel);
892 }
893
894
895 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
896 {
897 if (state->dirty_mask) {
898 rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE;
899 state->atom.num_dw = rctx->b.chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
900 : util_bitcount(state->dirty_mask)*19;
901 state->atom.dirty = true;
902 }
903 }
904
905 static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
906 struct pipe_constant_buffer *input)
907 {
908 struct r600_context *rctx = (struct r600_context *)ctx;
909 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
910 struct pipe_constant_buffer *cb;
911 const uint8_t *ptr;
912
913 /* Note that the state tracker can unbind constant buffers by
914 * passing NULL here.
915 */
916 if (unlikely(!input || (!input->buffer && !input->user_buffer))) {
917 state->enabled_mask &= ~(1 << index);
918 state->dirty_mask &= ~(1 << index);
919 pipe_resource_reference(&state->cb[index].buffer, NULL);
920 return;
921 }
922
923 cb = &state->cb[index];
924 cb->buffer_size = input->buffer_size;
925
926 ptr = input->user_buffer;
927
928 if (ptr) {
929 /* Upload the user buffer. */
930 if (R600_BIG_ENDIAN) {
931 uint32_t *tmpPtr;
932 unsigned i, size = input->buffer_size;
933
934 if (!(tmpPtr = malloc(size))) {
935 R600_ERR("Failed to allocate BE swap buffer.\n");
936 return;
937 }
938
939 for (i = 0; i < size / 4; ++i) {
940 tmpPtr[i] = util_cpu_to_le32(((uint32_t *)ptr)[i]);
941 }
942
943 u_upload_data(rctx->b.uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer);
944 free(tmpPtr);
945 } else {
946 u_upload_data(rctx->b.uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer);
947 }
948 /* account it in gtt */
949 rctx->b.gtt += input->buffer_size;
950 } else {
951 /* Setup the hw buffer. */
952 cb->buffer_offset = input->buffer_offset;
953 pipe_resource_reference(&cb->buffer, input->buffer);
954 r600_context_add_resource_size(ctx, input->buffer);
955 }
956
957 state->enabled_mask |= 1 << index;
958 state->dirty_mask |= 1 << index;
959 r600_constant_buffers_dirty(rctx, state);
960 }
961
962 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
963 {
964 struct r600_context *rctx = (struct r600_context*)pipe;
965
966 if (rctx->sample_mask.sample_mask == (uint16_t)sample_mask)
967 return;
968
969 rctx->sample_mask.sample_mask = sample_mask;
970 rctx->sample_mask.atom.dirty = true;
971 }
972
973 /*
974 * On r600/700 hw we don't have vertex fetch swizzle, though TBO
975 * doesn't require full swizzles it does need masking and setting alpha
976 * to one, so we setup a set of 5 constants with the masks + alpha value
977 * then in the shader, we AND the 4 components with 0xffffffff or 0,
978 * then OR the alpha with the value given here.
979 * We use a 6th constant to store the txq buffer size in
980 */
981 static void r600_setup_buffer_constants(struct r600_context *rctx, int shader_type)
982 {
983 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
984 int bits;
985 uint32_t array_size;
986 struct pipe_constant_buffer cb;
987 int i, j;
988
989 if (!samplers->views.dirty_buffer_constants)
990 return;
991
992 samplers->views.dirty_buffer_constants = FALSE;
993
994 bits = util_last_bit(samplers->views.enabled_mask);
995 array_size = bits * 8 * sizeof(uint32_t) * 4;
996 samplers->buffer_constants = realloc(samplers->buffer_constants, array_size);
997 memset(samplers->buffer_constants, 0, array_size);
998 for (i = 0; i < bits; i++) {
999 if (samplers->views.enabled_mask & (1 << i)) {
1000 int offset = i * 8;
1001 const struct util_format_description *desc;
1002 desc = util_format_description(samplers->views.views[i]->base.format);
1003
1004 for (j = 0; j < 4; j++)
1005 if (j < desc->nr_channels)
1006 samplers->buffer_constants[offset+j] = 0xffffffff;
1007 else
1008 samplers->buffer_constants[offset+j] = 0x0;
1009 if (desc->nr_channels < 4) {
1010 if (desc->channel[0].pure_integer)
1011 samplers->buffer_constants[offset+4] = 1;
1012 else
1013 samplers->buffer_constants[offset+4] = 0x3f800000;
1014 } else
1015 samplers->buffer_constants[offset + 4] = 0;
1016
1017 samplers->buffer_constants[offset + 5] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
1018 }
1019 }
1020
1021 cb.buffer = NULL;
1022 cb.user_buffer = samplers->buffer_constants;
1023 cb.buffer_offset = 0;
1024 cb.buffer_size = array_size;
1025 rctx->b.b.set_constant_buffer(&rctx->b.b, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
1026 pipe_resource_reference(&cb.buffer, NULL);
1027 }
1028
1029 /* On evergreen we only need to store the buffer size for TXQ */
1030 static void eg_setup_buffer_constants(struct r600_context *rctx, int shader_type)
1031 {
1032 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1033 int bits;
1034 uint32_t array_size;
1035 struct pipe_constant_buffer cb;
1036 int i;
1037
1038 if (!samplers->views.dirty_buffer_constants)
1039 return;
1040
1041 samplers->views.dirty_buffer_constants = FALSE;
1042
1043 bits = util_last_bit(samplers->views.enabled_mask);
1044 array_size = bits * sizeof(uint32_t) * 4;
1045 samplers->buffer_constants = realloc(samplers->buffer_constants, array_size);
1046 memset(samplers->buffer_constants, 0, array_size);
1047 for (i = 0; i < bits; i++)
1048 if (samplers->views.enabled_mask & (1 << i))
1049 samplers->buffer_constants[i] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
1050
1051 cb.buffer = NULL;
1052 cb.user_buffer = samplers->buffer_constants;
1053 cb.buffer_offset = 0;
1054 cb.buffer_size = array_size;
1055 rctx->b.b.set_constant_buffer(&rctx->b.b, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
1056 pipe_resource_reference(&cb.buffer, NULL);
1057 }
1058
1059 static void r600_setup_txq_cube_array_constants(struct r600_context *rctx, int shader_type)
1060 {
1061 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1062 int bits;
1063 uint32_t array_size;
1064 struct pipe_constant_buffer cb;
1065 int i;
1066
1067 if (!samplers->views.dirty_txq_constants)
1068 return;
1069
1070 samplers->views.dirty_txq_constants = FALSE;
1071
1072 bits = util_last_bit(samplers->views.enabled_mask);
1073 array_size = bits * sizeof(uint32_t) * 4;
1074 samplers->txq_constants = realloc(samplers->txq_constants, array_size);
1075 memset(samplers->txq_constants, 0, array_size);
1076 for (i = 0; i < bits; i++)
1077 if (samplers->views.enabled_mask & (1 << i))
1078 samplers->txq_constants[i] = samplers->views.views[i]->base.texture->array_size / 6;
1079
1080 cb.buffer = NULL;
1081 cb.user_buffer = samplers->txq_constants;
1082 cb.buffer_offset = 0;
1083 cb.buffer_size = array_size;
1084 rctx->b.b.set_constant_buffer(&rctx->b.b, shader_type, R600_TXQ_CONST_BUFFER, &cb);
1085 pipe_resource_reference(&cb.buffer, NULL);
1086 }
1087
1088 static void update_shader_atom(struct pipe_context *ctx,
1089 struct r600_shader_state *state,
1090 struct r600_pipe_shader *shader)
1091 {
1092 state->shader = shader;
1093 if (shader) {
1094 state->atom.num_dw = shader->command_buffer.num_dw;
1095 state->atom.dirty = true;
1096 r600_context_add_resource_size(ctx, (struct pipe_resource *)shader->bo);
1097 } else {
1098 state->atom.num_dw = 0;
1099 state->atom.dirty = false;
1100 }
1101 }
1102
1103 static void update_gs_block_state(struct r600_context *rctx, unsigned enable)
1104 {
1105 if (rctx->shader_stages.geom_enable != enable) {
1106 rctx->shader_stages.geom_enable = enable;
1107 rctx->shader_stages.atom.dirty = true;
1108 }
1109
1110 if (rctx->gs_rings.enable != enable) {
1111 rctx->gs_rings.enable = enable;
1112 rctx->gs_rings.atom.dirty = true;
1113
1114 if (enable && !rctx->gs_rings.esgs_ring.buffer) {
1115 unsigned size = 0x1C000;
1116 rctx->gs_rings.esgs_ring.buffer =
1117 pipe_buffer_create(rctx->b.b.screen, PIPE_BIND_CUSTOM,
1118 PIPE_USAGE_DEFAULT, size);
1119 rctx->gs_rings.esgs_ring.buffer_size = size;
1120
1121 size = 0x4000000;
1122
1123 rctx->gs_rings.gsvs_ring.buffer =
1124 pipe_buffer_create(rctx->b.b.screen, PIPE_BIND_CUSTOM,
1125 PIPE_USAGE_DEFAULT, size);
1126 rctx->gs_rings.gsvs_ring.buffer_size = size;
1127 }
1128
1129 if (enable) {
1130 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_GEOMETRY,
1131 R600_GS_RING_CONST_BUFFER, &rctx->gs_rings.esgs_ring);
1132 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
1133 R600_GS_RING_CONST_BUFFER, &rctx->gs_rings.gsvs_ring);
1134 } else {
1135 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_GEOMETRY,
1136 R600_GS_RING_CONST_BUFFER, NULL);
1137 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
1138 R600_GS_RING_CONST_BUFFER, NULL);
1139 }
1140 }
1141 }
1142
1143 static bool r600_update_derived_state(struct r600_context *rctx)
1144 {
1145 struct pipe_context * ctx = (struct pipe_context*)rctx;
1146 bool ps_dirty = false, vs_dirty = false, gs_dirty = false;
1147 bool blend_disable;
1148
1149 if (!rctx->blitter->running) {
1150 unsigned i;
1151
1152 /* Decompress textures if needed. */
1153 for (i = 0; i < PIPE_SHADER_TYPES; i++) {
1154 struct r600_samplerview_state *views = &rctx->samplers[i].views;
1155 if (views->compressed_depthtex_mask) {
1156 r600_decompress_depth_textures(rctx, views);
1157 }
1158 if (views->compressed_colortex_mask) {
1159 r600_decompress_color_textures(rctx, views);
1160 }
1161 }
1162 }
1163
1164 update_gs_block_state(rctx, rctx->gs_shader != NULL);
1165
1166 if (rctx->gs_shader) {
1167 r600_shader_select(ctx, rctx->gs_shader, &gs_dirty);
1168 if (unlikely(!rctx->gs_shader->current))
1169 return false;
1170
1171 if (!rctx->shader_stages.geom_enable) {
1172 rctx->shader_stages.geom_enable = true;
1173 rctx->shader_stages.atom.dirty = true;
1174 }
1175
1176 /* gs_shader provides GS and VS (copy shader) */
1177 if (unlikely(rctx->geometry_shader.shader != rctx->gs_shader->current)) {
1178 update_shader_atom(ctx, &rctx->geometry_shader, rctx->gs_shader->current);
1179 update_shader_atom(ctx, &rctx->vertex_shader, rctx->gs_shader->current->gs_copy_shader);
1180 /* Update clip misc state. */
1181 if (rctx->gs_shader->current->gs_copy_shader->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
1182 rctx->gs_shader->current->gs_copy_shader->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write ||
1183 rctx->clip_misc_state.clip_disable != rctx->gs_shader->current->shader.vs_position_window_space) {
1184 rctx->clip_misc_state.pa_cl_vs_out_cntl = rctx->gs_shader->current->gs_copy_shader->pa_cl_vs_out_cntl;
1185 rctx->clip_misc_state.clip_dist_write = rctx->gs_shader->current->gs_copy_shader->shader.clip_dist_write;
1186 rctx->clip_misc_state.clip_disable = rctx->gs_shader->current->shader.vs_position_window_space;
1187 rctx->clip_misc_state.atom.dirty = true;
1188 }
1189 }
1190
1191 r600_shader_select(ctx, rctx->vs_shader, &vs_dirty);
1192 if (unlikely(!rctx->vs_shader->current))
1193 return false;
1194
1195 /* vs_shader is used as ES */
1196 if (unlikely(vs_dirty || rctx->export_shader.shader != rctx->vs_shader->current)) {
1197 update_shader_atom(ctx, &rctx->export_shader, rctx->vs_shader->current);
1198 }
1199 } else {
1200 if (unlikely(rctx->geometry_shader.shader)) {
1201 update_shader_atom(ctx, &rctx->geometry_shader, NULL);
1202 update_shader_atom(ctx, &rctx->export_shader, NULL);
1203 rctx->shader_stages.geom_enable = false;
1204 rctx->shader_stages.atom.dirty = true;
1205 }
1206
1207 r600_shader_select(ctx, rctx->vs_shader, &vs_dirty);
1208 if (unlikely(!rctx->vs_shader->current))
1209 return false;
1210
1211 if (unlikely(vs_dirty || rctx->vertex_shader.shader != rctx->vs_shader->current)) {
1212 update_shader_atom(ctx, &rctx->vertex_shader, rctx->vs_shader->current);
1213
1214 /* Update clip misc state. */
1215 if (rctx->vs_shader->current->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
1216 rctx->vs_shader->current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write ||
1217 rctx->clip_misc_state.clip_disable != rctx->vs_shader->current->shader.vs_position_window_space) {
1218 rctx->clip_misc_state.pa_cl_vs_out_cntl = rctx->vs_shader->current->pa_cl_vs_out_cntl;
1219 rctx->clip_misc_state.clip_dist_write = rctx->vs_shader->current->shader.clip_dist_write;
1220 rctx->clip_misc_state.clip_disable = rctx->vs_shader->current->shader.vs_position_window_space;
1221 rctx->clip_misc_state.atom.dirty = true;
1222 }
1223 }
1224 }
1225
1226 r600_shader_select(ctx, rctx->ps_shader, &ps_dirty);
1227 if (unlikely(!rctx->ps_shader->current))
1228 return false;
1229
1230 if (unlikely(ps_dirty || rctx->pixel_shader.shader != rctx->ps_shader->current ||
1231 rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable ||
1232 rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade)) {
1233
1234 if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
1235 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
1236 rctx->cb_misc_state.atom.dirty = true;
1237 }
1238
1239 if (rctx->b.chip_class <= R700) {
1240 bool multiwrite = rctx->ps_shader->current->shader.fs_write_all;
1241
1242 if (rctx->cb_misc_state.multiwrite != multiwrite) {
1243 rctx->cb_misc_state.multiwrite = multiwrite;
1244 rctx->cb_misc_state.atom.dirty = true;
1245 }
1246 }
1247
1248 if (unlikely(!ps_dirty && rctx->ps_shader && rctx->rasterizer &&
1249 ((rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable) ||
1250 (rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade)))) {
1251
1252 if (rctx->b.chip_class >= EVERGREEN)
1253 evergreen_update_ps_state(ctx, rctx->ps_shader->current);
1254 else
1255 r600_update_ps_state(ctx, rctx->ps_shader->current);
1256 }
1257
1258 update_shader_atom(ctx, &rctx->pixel_shader, rctx->ps_shader->current);
1259 }
1260
1261 if (rctx->b.chip_class >= EVERGREEN) {
1262 evergreen_update_db_shader_control(rctx);
1263 } else {
1264 r600_update_db_shader_control(rctx);
1265 }
1266
1267 /* on R600 we stuff masks + txq info into one constant buffer */
1268 /* on evergreen we only need a txq info one */
1269 if (rctx->b.chip_class < EVERGREEN) {
1270 if (rctx->ps_shader && rctx->ps_shader->current->shader.uses_tex_buffers)
1271 r600_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
1272 if (rctx->vs_shader && rctx->vs_shader->current->shader.uses_tex_buffers)
1273 r600_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
1274 if (rctx->gs_shader && rctx->gs_shader->current->shader.uses_tex_buffers)
1275 r600_setup_buffer_constants(rctx, PIPE_SHADER_GEOMETRY);
1276 } else {
1277 if (rctx->ps_shader && rctx->ps_shader->current->shader.uses_tex_buffers)
1278 eg_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
1279 if (rctx->vs_shader && rctx->vs_shader->current->shader.uses_tex_buffers)
1280 eg_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
1281 if (rctx->gs_shader && rctx->gs_shader->current->shader.uses_tex_buffers)
1282 eg_setup_buffer_constants(rctx, PIPE_SHADER_GEOMETRY);
1283 }
1284
1285
1286 if (rctx->ps_shader && rctx->ps_shader->current->shader.has_txq_cube_array_z_comp)
1287 r600_setup_txq_cube_array_constants(rctx, PIPE_SHADER_FRAGMENT);
1288 if (rctx->vs_shader && rctx->vs_shader->current->shader.has_txq_cube_array_z_comp)
1289 r600_setup_txq_cube_array_constants(rctx, PIPE_SHADER_VERTEX);
1290 if (rctx->gs_shader && rctx->gs_shader->current->shader.has_txq_cube_array_z_comp)
1291 r600_setup_txq_cube_array_constants(rctx, PIPE_SHADER_GEOMETRY);
1292
1293 if (rctx->b.chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
1294 if (!r600_adjust_gprs(rctx)) {
1295 /* discard rendering */
1296 return false;
1297 }
1298 }
1299
1300 blend_disable = (rctx->dual_src_blend &&
1301 rctx->ps_shader->current->nr_ps_color_outputs < 2);
1302
1303 if (blend_disable != rctx->force_blend_disable) {
1304 rctx->force_blend_disable = blend_disable;
1305 r600_bind_blend_state_internal(rctx,
1306 rctx->blend_state.cso,
1307 blend_disable);
1308 }
1309
1310 return true;
1311 }
1312
1313 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1314 {
1315 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1316 struct r600_clip_misc_state *state = &rctx->clip_misc_state;
1317
1318 r600_write_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
1319 state->pa_cl_clip_cntl |
1320 (state->clip_dist_write ? 0 : state->clip_plane_enable & 0x3F) |
1321 S_028810_CLIP_DISABLE(state->clip_disable));
1322 r600_write_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
1323 state->pa_cl_vs_out_cntl |
1324 (state->clip_plane_enable & state->clip_dist_write));
1325 }
1326
1327 static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
1328 {
1329 struct r600_context *rctx = (struct r600_context *)ctx;
1330 struct pipe_draw_info info = *dinfo;
1331 struct pipe_index_buffer ib = {};
1332 unsigned i;
1333 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1334
1335 if (!info.count && (info.indexed || !info.count_from_stream_output)) {
1336 return;
1337 }
1338
1339 if (!rctx->vs_shader || !rctx->ps_shader) {
1340 assert(0);
1341 return;
1342 }
1343
1344 /* make sure that the gfx ring is only one active */
1345 if (rctx->b.rings.dma.cs && rctx->b.rings.dma.cs->cdw) {
1346 rctx->b.rings.dma.flush(rctx, RADEON_FLUSH_ASYNC, NULL);
1347 }
1348
1349 if (!r600_update_derived_state(rctx)) {
1350 /* useless to render because current rendering command
1351 * can't be achieved
1352 */
1353 return;
1354 }
1355
1356 if (info.indexed) {
1357 /* Initialize the index buffer struct. */
1358 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
1359 ib.user_buffer = rctx->index_buffer.user_buffer;
1360 ib.index_size = rctx->index_buffer.index_size;
1361 ib.offset = rctx->index_buffer.offset + info.start * ib.index_size;
1362
1363 /* Translate 8-bit indices to 16-bit. */
1364 if (ib.index_size == 1) {
1365 struct pipe_resource *out_buffer = NULL;
1366 unsigned out_offset;
1367 void *ptr;
1368
1369 u_upload_alloc(rctx->b.uploader, 0, info.count * 2,
1370 &out_offset, &out_buffer, &ptr);
1371
1372 util_shorten_ubyte_elts_to_userptr(
1373 &rctx->b.b, &ib, 0, ib.offset, info.count, ptr);
1374
1375 pipe_resource_reference(&ib.buffer, NULL);
1376 ib.user_buffer = NULL;
1377 ib.buffer = out_buffer;
1378 ib.offset = out_offset;
1379 ib.index_size = 2;
1380 }
1381
1382 /* Upload the index buffer.
1383 * The upload is skipped for small index counts on little-endian machines
1384 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
1385 * Note: Instanced rendering in combination with immediate indices hangs. */
1386 if (ib.user_buffer && (R600_BIG_ENDIAN || info.instance_count > 1 ||
1387 info.count*ib.index_size > 20)) {
1388 u_upload_data(rctx->b.uploader, 0, info.count * ib.index_size,
1389 ib.user_buffer, &ib.offset, &ib.buffer);
1390 ib.user_buffer = NULL;
1391 }
1392 } else {
1393 info.index_bias = info.start;
1394 }
1395
1396 /* Set the index offset and primitive restart. */
1397 if (rctx->vgt_state.vgt_multi_prim_ib_reset_en != info.primitive_restart ||
1398 rctx->vgt_state.vgt_multi_prim_ib_reset_indx != info.restart_index ||
1399 rctx->vgt_state.vgt_indx_offset != info.index_bias) {
1400 rctx->vgt_state.vgt_multi_prim_ib_reset_en = info.primitive_restart;
1401 rctx->vgt_state.vgt_multi_prim_ib_reset_indx = info.restart_index;
1402 rctx->vgt_state.vgt_indx_offset = info.index_bias;
1403 rctx->vgt_state.atom.dirty = true;
1404 }
1405
1406 /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
1407 if (rctx->b.chip_class == R600) {
1408 rctx->b.flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
1409 rctx->cb_misc_state.atom.dirty = true;
1410 }
1411
1412 /* Emit states. */
1413 r600_need_cs_space(rctx, ib.user_buffer ? 5 : 0, TRUE);
1414 r600_flush_emit(rctx);
1415
1416 for (i = 0; i < R600_NUM_ATOMS; i++) {
1417 if (rctx->atoms[i] == NULL || !rctx->atoms[i]->dirty) {
1418 continue;
1419 }
1420 r600_emit_atom(rctx, rctx->atoms[i]);
1421 }
1422
1423 if (rctx->b.chip_class == CAYMAN) {
1424 /* Copied from radeonsi. */
1425 unsigned primgroup_size = 128; /* recommended without a GS */
1426 bool ia_switch_on_eop = false;
1427 bool partial_vs_wave = false;
1428
1429 if (rctx->gs_shader)
1430 primgroup_size = 64; /* recommended with a GS */
1431
1432 if ((rctx->rasterizer && rctx->rasterizer->pa_sc_line_stipple) ||
1433 (rctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) {
1434 ia_switch_on_eop = true;
1435 }
1436
1437 if (rctx->b.streamout.streamout_enabled ||
1438 rctx->b.streamout.prims_gen_query_enabled)
1439 partial_vs_wave = true;
1440
1441 r600_write_context_reg(cs, CM_R_028AA8_IA_MULTI_VGT_PARAM,
1442 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
1443 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
1444 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1));
1445 }
1446
1447 /* On R6xx, CULL_FRONT=1 culls all points, lines, and rectangles,
1448 * even though it should have no effect on those. */
1449 if (rctx->b.chip_class == R600 && rctx->rasterizer) {
1450 unsigned su_sc_mode_cntl = rctx->rasterizer->pa_su_sc_mode_cntl;
1451 unsigned prim = info.mode;
1452
1453 if (rctx->gs_shader) {
1454 prim = rctx->gs_shader->current->shader.gs_output_prim;
1455 }
1456 prim = r600_conv_prim_to_gs_out(prim); /* decrease the number of types to 3 */
1457
1458 if (prim == V_028A6C_OUTPRIM_TYPE_POINTLIST ||
1459 prim == V_028A6C_OUTPRIM_TYPE_LINESTRIP ||
1460 info.mode == R600_PRIM_RECTANGLE_LIST) {
1461 su_sc_mode_cntl &= C_028814_CULL_FRONT;
1462 }
1463 r600_write_context_reg(cs, R_028814_PA_SU_SC_MODE_CNTL, su_sc_mode_cntl);
1464 }
1465
1466 /* Update start instance. */
1467 if (rctx->last_start_instance != info.start_instance) {
1468 r600_write_ctl_const(cs, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
1469 rctx->last_start_instance = info.start_instance;
1470 }
1471
1472 /* Update the primitive type. */
1473 if (rctx->last_primitive_type != info.mode) {
1474 unsigned ls_mask = 0;
1475
1476 if (info.mode == PIPE_PRIM_LINES)
1477 ls_mask = 1;
1478 else if (info.mode == PIPE_PRIM_LINE_STRIP ||
1479 info.mode == PIPE_PRIM_LINE_LOOP)
1480 ls_mask = 2;
1481
1482 r600_write_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
1483 S_028A0C_AUTO_RESET_CNTL(ls_mask) |
1484 (rctx->rasterizer ? rctx->rasterizer->pa_sc_line_stipple : 0));
1485 r600_write_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE,
1486 r600_conv_pipe_prim(info.mode));
1487
1488 rctx->last_primitive_type = info.mode;
1489 }
1490
1491 /* Draw packets. */
1492 cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->b.predicate_drawing);
1493 cs->buf[cs->cdw++] = info.instance_count;
1494 if (info.indexed) {
1495 cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->b.predicate_drawing);
1496 cs->buf[cs->cdw++] = ib.index_size == 4 ?
1497 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
1498 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
1499
1500 if (ib.user_buffer) {
1501 unsigned size_bytes = info.count*ib.index_size;
1502 unsigned size_dw = align(size_bytes, 4) / 4;
1503 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_IMMD, 1 + size_dw, rctx->b.predicate_drawing);
1504 cs->buf[cs->cdw++] = info.count;
1505 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_IMMEDIATE;
1506 memcpy(cs->buf+cs->cdw, ib.user_buffer, size_bytes);
1507 cs->cdw += size_dw;
1508 } else {
1509 uint64_t va = r600_resource(ib.buffer)->gpu_address + ib.offset;
1510 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->b.predicate_drawing);
1511 cs->buf[cs->cdw++] = va;
1512 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
1513 cs->buf[cs->cdw++] = info.count;
1514 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
1515 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->b.predicate_drawing);
1516 cs->buf[cs->cdw++] = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
1517 (struct r600_resource*)ib.buffer,
1518 RADEON_USAGE_READ, RADEON_PRIO_MIN);
1519 }
1520 } else {
1521 if (info.count_from_stream_output) {
1522 struct r600_so_target *t = (struct r600_so_target*)info.count_from_stream_output;
1523 uint64_t va = t->buf_filled_size->gpu_address + t->buf_filled_size_offset;
1524
1525 r600_write_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
1526
1527 cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0);
1528 cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG;
1529 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */
1530 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
1531 cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */
1532 cs->buf[cs->cdw++] = 0; /* unused */
1533
1534 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1535 cs->buf[cs->cdw++] = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
1536 t->buf_filled_size, RADEON_USAGE_READ,
1537 RADEON_PRIO_MIN);
1538 }
1539
1540 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->b.predicate_drawing);
1541 cs->buf[cs->cdw++] = info.count;
1542 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
1543 (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
1544 }
1545
1546 if (rctx->screen->b.trace_bo) {
1547 r600_trace_emit(rctx);
1548 }
1549
1550 /* Set the depth buffer as dirty. */
1551 if (rctx->framebuffer.state.zsbuf) {
1552 struct pipe_surface *surf = rctx->framebuffer.state.zsbuf;
1553 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
1554
1555 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1556 }
1557 if (rctx->framebuffer.compressed_cb_mask) {
1558 struct pipe_surface *surf;
1559 struct r600_texture *rtex;
1560 unsigned mask = rctx->framebuffer.compressed_cb_mask;
1561
1562 do {
1563 unsigned i = u_bit_scan(&mask);
1564 surf = rctx->framebuffer.state.cbufs[i];
1565 rtex = (struct r600_texture*)surf->texture;
1566
1567 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1568
1569 } while (mask);
1570 }
1571
1572 pipe_resource_reference(&ib.buffer, NULL);
1573 rctx->b.num_draw_calls++;
1574 }
1575
1576 uint32_t r600_translate_stencil_op(int s_op)
1577 {
1578 switch (s_op) {
1579 case PIPE_STENCIL_OP_KEEP:
1580 return V_028800_STENCIL_KEEP;
1581 case PIPE_STENCIL_OP_ZERO:
1582 return V_028800_STENCIL_ZERO;
1583 case PIPE_STENCIL_OP_REPLACE:
1584 return V_028800_STENCIL_REPLACE;
1585 case PIPE_STENCIL_OP_INCR:
1586 return V_028800_STENCIL_INCR;
1587 case PIPE_STENCIL_OP_DECR:
1588 return V_028800_STENCIL_DECR;
1589 case PIPE_STENCIL_OP_INCR_WRAP:
1590 return V_028800_STENCIL_INCR_WRAP;
1591 case PIPE_STENCIL_OP_DECR_WRAP:
1592 return V_028800_STENCIL_DECR_WRAP;
1593 case PIPE_STENCIL_OP_INVERT:
1594 return V_028800_STENCIL_INVERT;
1595 default:
1596 R600_ERR("Unknown stencil op %d", s_op);
1597 assert(0);
1598 break;
1599 }
1600 return 0;
1601 }
1602
1603 uint32_t r600_translate_fill(uint32_t func)
1604 {
1605 switch(func) {
1606 case PIPE_POLYGON_MODE_FILL:
1607 return 2;
1608 case PIPE_POLYGON_MODE_LINE:
1609 return 1;
1610 case PIPE_POLYGON_MODE_POINT:
1611 return 0;
1612 default:
1613 assert(0);
1614 return 0;
1615 }
1616 }
1617
1618 unsigned r600_tex_wrap(unsigned wrap)
1619 {
1620 switch (wrap) {
1621 default:
1622 case PIPE_TEX_WRAP_REPEAT:
1623 return V_03C000_SQ_TEX_WRAP;
1624 case PIPE_TEX_WRAP_CLAMP:
1625 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1626 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1627 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1628 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1629 return V_03C000_SQ_TEX_CLAMP_BORDER;
1630 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1631 return V_03C000_SQ_TEX_MIRROR;
1632 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1633 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1634 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1635 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1636 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1637 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1638 }
1639 }
1640
1641 unsigned r600_tex_filter(unsigned filter)
1642 {
1643 switch (filter) {
1644 default:
1645 case PIPE_TEX_FILTER_NEAREST:
1646 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1647 case PIPE_TEX_FILTER_LINEAR:
1648 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1649 }
1650 }
1651
1652 unsigned r600_tex_mipfilter(unsigned filter)
1653 {
1654 switch (filter) {
1655 case PIPE_TEX_MIPFILTER_NEAREST:
1656 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1657 case PIPE_TEX_MIPFILTER_LINEAR:
1658 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1659 default:
1660 case PIPE_TEX_MIPFILTER_NONE:
1661 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1662 }
1663 }
1664
1665 unsigned r600_tex_compare(unsigned compare)
1666 {
1667 switch (compare) {
1668 default:
1669 case PIPE_FUNC_NEVER:
1670 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1671 case PIPE_FUNC_LESS:
1672 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1673 case PIPE_FUNC_EQUAL:
1674 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1675 case PIPE_FUNC_LEQUAL:
1676 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1677 case PIPE_FUNC_GREATER:
1678 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1679 case PIPE_FUNC_NOTEQUAL:
1680 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1681 case PIPE_FUNC_GEQUAL:
1682 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1683 case PIPE_FUNC_ALWAYS:
1684 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1685 }
1686 }
1687
1688 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
1689 {
1690 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
1691 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
1692 (linear_filter &&
1693 (wrap == PIPE_TEX_WRAP_CLAMP ||
1694 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
1695 }
1696
1697 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
1698 {
1699 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
1700 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
1701
1702 return (state->border_color.ui[0] || state->border_color.ui[1] ||
1703 state->border_color.ui[2] || state->border_color.ui[3]) &&
1704 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
1705 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
1706 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
1707 }
1708
1709 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a)
1710 {
1711
1712 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1713 struct r600_pipe_shader *shader = ((struct r600_shader_state*)a)->shader;
1714
1715 if (!shader)
1716 return;
1717
1718 r600_emit_command_buffer(cs, &shader->command_buffer);
1719 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1720 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, shader->bo,
1721 RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA));
1722 }
1723
1724 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
1725 const unsigned char *swizzle_view,
1726 boolean vtx)
1727 {
1728 unsigned i;
1729 unsigned char swizzle[4];
1730 unsigned result = 0;
1731 const uint32_t tex_swizzle_shift[4] = {
1732 16, 19, 22, 25,
1733 };
1734 const uint32_t vtx_swizzle_shift[4] = {
1735 3, 6, 9, 12,
1736 };
1737 const uint32_t swizzle_bit[4] = {
1738 0, 1, 2, 3,
1739 };
1740 const uint32_t *swizzle_shift = tex_swizzle_shift;
1741
1742 if (vtx)
1743 swizzle_shift = vtx_swizzle_shift;
1744
1745 if (swizzle_view) {
1746 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
1747 } else {
1748 memcpy(swizzle, swizzle_format, 4);
1749 }
1750
1751 /* Get swizzle. */
1752 for (i = 0; i < 4; i++) {
1753 switch (swizzle[i]) {
1754 case UTIL_FORMAT_SWIZZLE_Y:
1755 result |= swizzle_bit[1] << swizzle_shift[i];
1756 break;
1757 case UTIL_FORMAT_SWIZZLE_Z:
1758 result |= swizzle_bit[2] << swizzle_shift[i];
1759 break;
1760 case UTIL_FORMAT_SWIZZLE_W:
1761 result |= swizzle_bit[3] << swizzle_shift[i];
1762 break;
1763 case UTIL_FORMAT_SWIZZLE_0:
1764 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
1765 break;
1766 case UTIL_FORMAT_SWIZZLE_1:
1767 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
1768 break;
1769 default: /* UTIL_FORMAT_SWIZZLE_X */
1770 result |= swizzle_bit[0] << swizzle_shift[i];
1771 }
1772 }
1773 return result;
1774 }
1775
1776 /* texture format translate */
1777 uint32_t r600_translate_texformat(struct pipe_screen *screen,
1778 enum pipe_format format,
1779 const unsigned char *swizzle_view,
1780 uint32_t *word4_p, uint32_t *yuv_format_p)
1781 {
1782 struct r600_screen *rscreen = (struct r600_screen *)screen;
1783 uint32_t result = 0, word4 = 0, yuv_format = 0;
1784 const struct util_format_description *desc;
1785 boolean uniform = TRUE;
1786 bool enable_s3tc = rscreen->b.info.drm_minor >= 9;
1787 bool is_srgb_valid = FALSE;
1788 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
1789 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
1790
1791 int i;
1792 const uint32_t sign_bit[4] = {
1793 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
1794 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
1795 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
1796 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
1797 };
1798 desc = util_format_description(format);
1799
1800 /* Depth and stencil swizzling is handled separately. */
1801 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS) {
1802 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view, FALSE);
1803 }
1804
1805 /* Colorspace (return non-RGB formats directly). */
1806 switch (desc->colorspace) {
1807 /* Depth stencil formats */
1808 case UTIL_FORMAT_COLORSPACE_ZS:
1809 switch (format) {
1810 /* Depth sampler formats. */
1811 case PIPE_FORMAT_Z16_UNORM:
1812 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1813 result = FMT_16;
1814 goto out_word4;
1815 case PIPE_FORMAT_Z24X8_UNORM:
1816 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1817 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1818 result = FMT_8_24;
1819 goto out_word4;
1820 case PIPE_FORMAT_X8Z24_UNORM:
1821 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1822 if (rscreen->b.chip_class < EVERGREEN)
1823 goto out_unknown;
1824 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
1825 result = FMT_24_8;
1826 goto out_word4;
1827 case PIPE_FORMAT_Z32_FLOAT:
1828 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1829 result = FMT_32_FLOAT;
1830 goto out_word4;
1831 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1832 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1833 result = FMT_X24_8_32_FLOAT;
1834 goto out_word4;
1835 /* Stencil sampler formats. */
1836 case PIPE_FORMAT_S8_UINT:
1837 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1838 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1839 result = FMT_8;
1840 goto out_word4;
1841 case PIPE_FORMAT_X24S8_UINT:
1842 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1843 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
1844 result = FMT_8_24;
1845 goto out_word4;
1846 case PIPE_FORMAT_S8X24_UINT:
1847 if (rscreen->b.chip_class < EVERGREEN)
1848 goto out_unknown;
1849 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1850 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1851 result = FMT_24_8;
1852 goto out_word4;
1853 case PIPE_FORMAT_X32_S8X24_UINT:
1854 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1855 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
1856 result = FMT_X24_8_32_FLOAT;
1857 goto out_word4;
1858 default:
1859 goto out_unknown;
1860 }
1861
1862 case UTIL_FORMAT_COLORSPACE_YUV:
1863 yuv_format |= (1 << 30);
1864 switch (format) {
1865 case PIPE_FORMAT_UYVY:
1866 case PIPE_FORMAT_YUYV:
1867 default:
1868 break;
1869 }
1870 goto out_unknown; /* XXX */
1871
1872 case UTIL_FORMAT_COLORSPACE_SRGB:
1873 word4 |= S_038010_FORCE_DEGAMMA(1);
1874 break;
1875
1876 default:
1877 break;
1878 }
1879
1880 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1881 if (!enable_s3tc)
1882 goto out_unknown;
1883
1884 switch (format) {
1885 case PIPE_FORMAT_RGTC1_SNORM:
1886 case PIPE_FORMAT_LATC1_SNORM:
1887 word4 |= sign_bit[0];
1888 case PIPE_FORMAT_RGTC1_UNORM:
1889 case PIPE_FORMAT_LATC1_UNORM:
1890 result = FMT_BC4;
1891 goto out_word4;
1892 case PIPE_FORMAT_RGTC2_SNORM:
1893 case PIPE_FORMAT_LATC2_SNORM:
1894 word4 |= sign_bit[0] | sign_bit[1];
1895 case PIPE_FORMAT_RGTC2_UNORM:
1896 case PIPE_FORMAT_LATC2_UNORM:
1897 result = FMT_BC5;
1898 goto out_word4;
1899 default:
1900 goto out_unknown;
1901 }
1902 }
1903
1904 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1905
1906 if (!enable_s3tc)
1907 goto out_unknown;
1908
1909 if (!util_format_s3tc_enabled) {
1910 goto out_unknown;
1911 }
1912
1913 switch (format) {
1914 case PIPE_FORMAT_DXT1_RGB:
1915 case PIPE_FORMAT_DXT1_RGBA:
1916 case PIPE_FORMAT_DXT1_SRGB:
1917 case PIPE_FORMAT_DXT1_SRGBA:
1918 result = FMT_BC1;
1919 is_srgb_valid = TRUE;
1920 goto out_word4;
1921 case PIPE_FORMAT_DXT3_RGBA:
1922 case PIPE_FORMAT_DXT3_SRGBA:
1923 result = FMT_BC2;
1924 is_srgb_valid = TRUE;
1925 goto out_word4;
1926 case PIPE_FORMAT_DXT5_RGBA:
1927 case PIPE_FORMAT_DXT5_SRGBA:
1928 result = FMT_BC3;
1929 is_srgb_valid = TRUE;
1930 goto out_word4;
1931 default:
1932 goto out_unknown;
1933 }
1934 }
1935
1936 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1937 if (!enable_s3tc)
1938 goto out_unknown;
1939
1940 if (rscreen->b.chip_class < EVERGREEN)
1941 goto out_unknown;
1942
1943 switch (format) {
1944 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1945 case PIPE_FORMAT_BPTC_SRGBA:
1946 result = FMT_BC7;
1947 is_srgb_valid = TRUE;
1948 goto out_word4;
1949 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1950 word4 |= sign_bit[0] | sign_bit[1] | sign_bit[2];
1951 /* fall through */
1952 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1953 result = FMT_BC6;
1954 goto out_word4;
1955 default:
1956 goto out_unknown;
1957 }
1958 }
1959
1960 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1961 switch (format) {
1962 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1963 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1964 result = FMT_GB_GR;
1965 goto out_word4;
1966 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1967 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1968 result = FMT_BG_RG;
1969 goto out_word4;
1970 default:
1971 goto out_unknown;
1972 }
1973 }
1974
1975 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1976 result = FMT_5_9_9_9_SHAREDEXP;
1977 goto out_word4;
1978 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1979 result = FMT_10_11_11_FLOAT;
1980 goto out_word4;
1981 }
1982
1983
1984 for (i = 0; i < desc->nr_channels; i++) {
1985 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1986 word4 |= sign_bit[i];
1987 }
1988 }
1989
1990 /* R8G8Bx_SNORM - XXX CxV8U8 */
1991
1992 /* See whether the components are of the same size. */
1993 for (i = 1; i < desc->nr_channels; i++) {
1994 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1995 }
1996
1997 /* Non-uniform formats. */
1998 if (!uniform) {
1999 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
2000 desc->channel[0].pure_integer)
2001 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2002 switch(desc->nr_channels) {
2003 case 3:
2004 if (desc->channel[0].size == 5 &&
2005 desc->channel[1].size == 6 &&
2006 desc->channel[2].size == 5) {
2007 result = FMT_5_6_5;
2008 goto out_word4;
2009 }
2010 goto out_unknown;
2011 case 4:
2012 if (desc->channel[0].size == 5 &&
2013 desc->channel[1].size == 5 &&
2014 desc->channel[2].size == 5 &&
2015 desc->channel[3].size == 1) {
2016 result = FMT_1_5_5_5;
2017 goto out_word4;
2018 }
2019 if (desc->channel[0].size == 10 &&
2020 desc->channel[1].size == 10 &&
2021 desc->channel[2].size == 10 &&
2022 desc->channel[3].size == 2) {
2023 result = FMT_2_10_10_10;
2024 goto out_word4;
2025 }
2026 goto out_unknown;
2027 }
2028 goto out_unknown;
2029 }
2030
2031 /* Find the first non-VOID channel. */
2032 for (i = 0; i < 4; i++) {
2033 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2034 break;
2035 }
2036 }
2037
2038 if (i == 4)
2039 goto out_unknown;
2040
2041 /* uniform formats */
2042 switch (desc->channel[i].type) {
2043 case UTIL_FORMAT_TYPE_UNSIGNED:
2044 case UTIL_FORMAT_TYPE_SIGNED:
2045 #if 0
2046 if (!desc->channel[i].normalized &&
2047 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
2048 goto out_unknown;
2049 }
2050 #endif
2051 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
2052 desc->channel[i].pure_integer)
2053 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2054
2055 switch (desc->channel[i].size) {
2056 case 4:
2057 switch (desc->nr_channels) {
2058 case 2:
2059 result = FMT_4_4;
2060 goto out_word4;
2061 case 4:
2062 result = FMT_4_4_4_4;
2063 goto out_word4;
2064 }
2065 goto out_unknown;
2066 case 8:
2067 switch (desc->nr_channels) {
2068 case 1:
2069 result = FMT_8;
2070 goto out_word4;
2071 case 2:
2072 result = FMT_8_8;
2073 goto out_word4;
2074 case 4:
2075 result = FMT_8_8_8_8;
2076 is_srgb_valid = TRUE;
2077 goto out_word4;
2078 }
2079 goto out_unknown;
2080 case 16:
2081 switch (desc->nr_channels) {
2082 case 1:
2083 result = FMT_16;
2084 goto out_word4;
2085 case 2:
2086 result = FMT_16_16;
2087 goto out_word4;
2088 case 4:
2089 result = FMT_16_16_16_16;
2090 goto out_word4;
2091 }
2092 goto out_unknown;
2093 case 32:
2094 switch (desc->nr_channels) {
2095 case 1:
2096 result = FMT_32;
2097 goto out_word4;
2098 case 2:
2099 result = FMT_32_32;
2100 goto out_word4;
2101 case 4:
2102 result = FMT_32_32_32_32;
2103 goto out_word4;
2104 }
2105 }
2106 goto out_unknown;
2107
2108 case UTIL_FORMAT_TYPE_FLOAT:
2109 switch (desc->channel[i].size) {
2110 case 16:
2111 switch (desc->nr_channels) {
2112 case 1:
2113 result = FMT_16_FLOAT;
2114 goto out_word4;
2115 case 2:
2116 result = FMT_16_16_FLOAT;
2117 goto out_word4;
2118 case 4:
2119 result = FMT_16_16_16_16_FLOAT;
2120 goto out_word4;
2121 }
2122 goto out_unknown;
2123 case 32:
2124 switch (desc->nr_channels) {
2125 case 1:
2126 result = FMT_32_FLOAT;
2127 goto out_word4;
2128 case 2:
2129 result = FMT_32_32_FLOAT;
2130 goto out_word4;
2131 case 4:
2132 result = FMT_32_32_32_32_FLOAT;
2133 goto out_word4;
2134 }
2135 }
2136 goto out_unknown;
2137 }
2138
2139 out_word4:
2140
2141 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid)
2142 return ~0;
2143 if (word4_p)
2144 *word4_p = word4;
2145 if (yuv_format_p)
2146 *yuv_format_p = yuv_format;
2147 return result;
2148 out_unknown:
2149 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
2150 return ~0;
2151 }
2152
2153 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format)
2154 {
2155 const struct util_format_description *desc = util_format_description(format);
2156 int channel = util_format_get_first_non_void_channel(format);
2157 bool is_float;
2158
2159 #define HAS_SIZE(x,y,z,w) \
2160 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
2161 desc->channel[2].size == (z) && desc->channel[3].size == (w))
2162
2163 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
2164 return V_0280A0_COLOR_10_11_11_FLOAT;
2165
2166 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN ||
2167 channel == -1)
2168 return ~0U;
2169
2170 is_float = desc->channel[channel].type == UTIL_FORMAT_TYPE_FLOAT;
2171
2172 switch (desc->nr_channels) {
2173 case 1:
2174 switch (desc->channel[0].size) {
2175 case 8:
2176 return V_0280A0_COLOR_8;
2177 case 16:
2178 if (is_float)
2179 return V_0280A0_COLOR_16_FLOAT;
2180 else
2181 return V_0280A0_COLOR_16;
2182 case 32:
2183 if (is_float)
2184 return V_0280A0_COLOR_32_FLOAT;
2185 else
2186 return V_0280A0_COLOR_32;
2187 }
2188 break;
2189 case 2:
2190 if (desc->channel[0].size == desc->channel[1].size) {
2191 switch (desc->channel[0].size) {
2192 case 4:
2193 if (chip <= R700)
2194 return V_0280A0_COLOR_4_4;
2195 else
2196 return ~0U; /* removed on Evergreen */
2197 case 8:
2198 return V_0280A0_COLOR_8_8;
2199 case 16:
2200 if (is_float)
2201 return V_0280A0_COLOR_16_16_FLOAT;
2202 else
2203 return V_0280A0_COLOR_16_16;
2204 case 32:
2205 if (is_float)
2206 return V_0280A0_COLOR_32_32_FLOAT;
2207 else
2208 return V_0280A0_COLOR_32_32;
2209 }
2210 } else if (HAS_SIZE(8,24,0,0)) {
2211 return V_0280A0_COLOR_24_8;
2212 } else if (HAS_SIZE(24,8,0,0)) {
2213 return V_0280A0_COLOR_8_24;
2214 }
2215 break;
2216 case 3:
2217 if (HAS_SIZE(5,6,5,0)) {
2218 return V_0280A0_COLOR_5_6_5;
2219 } else if (HAS_SIZE(32,8,24,0)) {
2220 return V_0280A0_COLOR_X24_8_32_FLOAT;
2221 }
2222 break;
2223 case 4:
2224 if (desc->channel[0].size == desc->channel[1].size &&
2225 desc->channel[0].size == desc->channel[2].size &&
2226 desc->channel[0].size == desc->channel[3].size) {
2227 switch (desc->channel[0].size) {
2228 case 4:
2229 return V_0280A0_COLOR_4_4_4_4;
2230 case 8:
2231 return V_0280A0_COLOR_8_8_8_8;
2232 case 16:
2233 if (is_float)
2234 return V_0280A0_COLOR_16_16_16_16_FLOAT;
2235 else
2236 return V_0280A0_COLOR_16_16_16_16;
2237 case 32:
2238 if (is_float)
2239 return V_0280A0_COLOR_32_32_32_32_FLOAT;
2240 else
2241 return V_0280A0_COLOR_32_32_32_32;
2242 }
2243 } else if (HAS_SIZE(5,5,5,1)) {
2244 return V_0280A0_COLOR_1_5_5_5;
2245 } else if (HAS_SIZE(10,10,10,2)) {
2246 return V_0280A0_COLOR_2_10_10_10;
2247 }
2248 break;
2249 }
2250 return ~0U;
2251 }
2252
2253 uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
2254 {
2255 if (R600_BIG_ENDIAN) {
2256 switch(colorformat) {
2257 /* 8-bit buffers. */
2258 case V_0280A0_COLOR_4_4:
2259 case V_0280A0_COLOR_8:
2260 return ENDIAN_NONE;
2261
2262 /* 16-bit buffers. */
2263 case V_0280A0_COLOR_5_6_5:
2264 case V_0280A0_COLOR_1_5_5_5:
2265 case V_0280A0_COLOR_4_4_4_4:
2266 case V_0280A0_COLOR_16:
2267 case V_0280A0_COLOR_8_8:
2268 return ENDIAN_8IN16;
2269
2270 /* 32-bit buffers. */
2271 case V_0280A0_COLOR_8_8_8_8:
2272 case V_0280A0_COLOR_2_10_10_10:
2273 case V_0280A0_COLOR_8_24:
2274 case V_0280A0_COLOR_24_8:
2275 case V_0280A0_COLOR_32_FLOAT:
2276 case V_0280A0_COLOR_16_16_FLOAT:
2277 case V_0280A0_COLOR_16_16:
2278 return ENDIAN_8IN32;
2279
2280 /* 64-bit buffers. */
2281 case V_0280A0_COLOR_16_16_16_16:
2282 case V_0280A0_COLOR_16_16_16_16_FLOAT:
2283 return ENDIAN_8IN16;
2284
2285 case V_0280A0_COLOR_32_32_FLOAT:
2286 case V_0280A0_COLOR_32_32:
2287 case V_0280A0_COLOR_X24_8_32_FLOAT:
2288 return ENDIAN_8IN32;
2289
2290 /* 128-bit buffers. */
2291 case V_0280A0_COLOR_32_32_32_32_FLOAT:
2292 case V_0280A0_COLOR_32_32_32_32:
2293 return ENDIAN_8IN32;
2294 default:
2295 return ENDIAN_NONE; /* Unsupported. */
2296 }
2297 } else {
2298 return ENDIAN_NONE;
2299 }
2300 }
2301
2302 static void r600_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource *buf)
2303 {
2304 struct r600_context *rctx = (struct r600_context*)ctx;
2305 struct r600_resource *rbuffer = r600_resource(buf);
2306 unsigned i, shader, mask, alignment = rbuffer->buf->alignment;
2307 struct r600_pipe_sampler_view *view;
2308
2309 /* Reallocate the buffer in the same pipe_resource. */
2310 r600_init_resource(&rctx->screen->b, rbuffer, rbuffer->b.b.width0,
2311 alignment, TRUE);
2312
2313 /* We changed the buffer, now we need to bind it where the old one was bound. */
2314 /* Vertex buffers. */
2315 mask = rctx->vertex_buffer_state.enabled_mask;
2316 while (mask) {
2317 i = u_bit_scan(&mask);
2318 if (rctx->vertex_buffer_state.vb[i].buffer == &rbuffer->b.b) {
2319 rctx->vertex_buffer_state.dirty_mask |= 1 << i;
2320 r600_vertex_buffers_dirty(rctx);
2321 }
2322 }
2323 /* Streamout buffers. */
2324 for (i = 0; i < rctx->b.streamout.num_targets; i++) {
2325 if (rctx->b.streamout.targets[i]->b.buffer == &rbuffer->b.b) {
2326 if (rctx->b.streamout.begin_emitted) {
2327 r600_emit_streamout_end(&rctx->b);
2328 }
2329 rctx->b.streamout.append_bitmask = rctx->b.streamout.enabled_mask;
2330 r600_streamout_buffers_dirty(&rctx->b);
2331 }
2332 }
2333
2334 /* Constant buffers. */
2335 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
2336 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
2337 bool found = false;
2338 uint32_t mask = state->enabled_mask;
2339
2340 while (mask) {
2341 unsigned i = u_bit_scan(&mask);
2342 if (state->cb[i].buffer == &rbuffer->b.b) {
2343 found = true;
2344 state->dirty_mask |= 1 << i;
2345 }
2346 }
2347 if (found) {
2348 r600_constant_buffers_dirty(rctx, state);
2349 }
2350 }
2351
2352 /* Texture buffer objects - update the virtual addresses in descriptors. */
2353 LIST_FOR_EACH_ENTRY(view, &rctx->b.texture_buffers, list) {
2354 if (view->base.texture == &rbuffer->b.b) {
2355 unsigned stride = util_format_get_blocksize(view->base.format);
2356 uint64_t offset = (uint64_t)view->base.u.buf.first_element * stride;
2357 uint64_t va = rbuffer->gpu_address + offset;
2358
2359 view->tex_resource_words[0] = va;
2360 view->tex_resource_words[2] &= C_038008_BASE_ADDRESS_HI;
2361 view->tex_resource_words[2] |= S_038008_BASE_ADDRESS_HI(va >> 32);
2362 }
2363 }
2364 /* Texture buffer objects - make bindings dirty if needed. */
2365 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
2366 struct r600_samplerview_state *state = &rctx->samplers[shader].views;
2367 bool found = false;
2368 uint32_t mask = state->enabled_mask;
2369
2370 while (mask) {
2371 unsigned i = u_bit_scan(&mask);
2372 if (state->views[i]->base.texture == &rbuffer->b.b) {
2373 found = true;
2374 state->dirty_mask |= 1 << i;
2375 }
2376 }
2377 if (found) {
2378 r600_sampler_views_dirty(rctx, state);
2379 }
2380 }
2381 }
2382
2383 static void r600_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
2384 {
2385 struct r600_context *rctx = (struct r600_context*)ctx;
2386
2387 if (rctx->db_misc_state.occlusion_query_enabled != enable) {
2388 rctx->db_misc_state.occlusion_query_enabled = enable;
2389 rctx->db_misc_state.atom.dirty = true;
2390 }
2391 }
2392
2393 static void r600_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
2394 bool include_draw_vbo)
2395 {
2396 r600_need_cs_space((struct r600_context*)ctx, num_dw, include_draw_vbo);
2397 }
2398
2399 /* keep this at the end of this file, please */
2400 void r600_init_common_state_functions(struct r600_context *rctx)
2401 {
2402 rctx->b.b.create_fs_state = r600_create_ps_state;
2403 rctx->b.b.create_vs_state = r600_create_vs_state;
2404 rctx->b.b.create_gs_state = r600_create_gs_state;
2405 rctx->b.b.create_vertex_elements_state = r600_create_vertex_fetch_shader;
2406 rctx->b.b.bind_blend_state = r600_bind_blend_state;
2407 rctx->b.b.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
2408 rctx->b.b.bind_sampler_states = r600_bind_sampler_states;
2409 rctx->b.b.bind_fs_state = r600_bind_ps_state;
2410 rctx->b.b.bind_rasterizer_state = r600_bind_rs_state;
2411 rctx->b.b.bind_vertex_elements_state = r600_bind_vertex_elements;
2412 rctx->b.b.bind_vs_state = r600_bind_vs_state;
2413 rctx->b.b.bind_gs_state = r600_bind_gs_state;
2414 rctx->b.b.delete_blend_state = r600_delete_blend_state;
2415 rctx->b.b.delete_depth_stencil_alpha_state = r600_delete_dsa_state;
2416 rctx->b.b.delete_fs_state = r600_delete_ps_state;
2417 rctx->b.b.delete_rasterizer_state = r600_delete_rs_state;
2418 rctx->b.b.delete_sampler_state = r600_delete_sampler_state;
2419 rctx->b.b.delete_vertex_elements_state = r600_delete_vertex_elements;
2420 rctx->b.b.delete_vs_state = r600_delete_vs_state;
2421 rctx->b.b.delete_gs_state = r600_delete_gs_state;
2422 rctx->b.b.set_blend_color = r600_set_blend_color;
2423 rctx->b.b.set_clip_state = r600_set_clip_state;
2424 rctx->b.b.set_constant_buffer = r600_set_constant_buffer;
2425 rctx->b.b.set_sample_mask = r600_set_sample_mask;
2426 rctx->b.b.set_stencil_ref = r600_set_pipe_stencil_ref;
2427 rctx->b.b.set_viewport_states = r600_set_viewport_states;
2428 rctx->b.b.set_vertex_buffers = r600_set_vertex_buffers;
2429 rctx->b.b.set_index_buffer = r600_set_index_buffer;
2430 rctx->b.b.set_sampler_views = r600_set_sampler_views;
2431 rctx->b.b.sampler_view_destroy = r600_sampler_view_destroy;
2432 rctx->b.b.texture_barrier = r600_texture_barrier;
2433 rctx->b.b.set_stream_output_targets = r600_set_streamout_targets;
2434 rctx->b.b.draw_vbo = r600_draw_vbo;
2435 rctx->b.invalidate_buffer = r600_invalidate_buffer;
2436 rctx->b.set_occlusion_query_state = r600_set_occlusion_query_state;
2437 rctx->b.need_gfx_cs_space = r600_need_gfx_cs_space;
2438 }
2439
2440 void r600_trace_emit(struct r600_context *rctx)
2441 {
2442 struct r600_screen *rscreen = rctx->screen;
2443 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2444 uint64_t va;
2445 uint32_t reloc;
2446
2447 va = rscreen->b.trace_bo->gpu_address;
2448 reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rscreen->b.trace_bo,
2449 RADEON_USAGE_READWRITE, RADEON_PRIO_MIN);
2450 radeon_emit(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
2451 radeon_emit(cs, va & 0xFFFFFFFFUL);
2452 radeon_emit(cs, (va >> 32UL) & 0xFFUL);
2453 radeon_emit(cs, cs->cdw);
2454 radeon_emit(cs, rscreen->b.cs_count);
2455 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2456 radeon_emit(cs, reloc);
2457 }