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r600g: suballocate memory for the STRMOUT_BUFFER_FILLED_SIZE register
[mesa.git] / src / gallium / drivers / r600 / r600_state_common.c
1 /*
2 * Copyright 2010 Red Hat Inc.
3 * 2010 Jerome Glisse
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
26 */
27 #include "r600_formats.h"
28 #include "r600_shader.h"
29 #include "r600d.h"
30
31 #include "util/u_draw_quad.h"
32 #include "util/u_index_modify.h"
33 #include "util/u_memory.h"
34 #include "util/u_upload_mgr.h"
35 #include "tgsi/tgsi_parse.h"
36 #include <byteswap.h>
37
38 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
39
40 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw)
41 {
42 cb->buf = CALLOC(1, 4 * num_dw);
43 cb->max_num_dw = num_dw;
44 }
45
46 void r600_release_command_buffer(struct r600_command_buffer *cb)
47 {
48 FREE(cb->buf);
49 }
50
51 void r600_init_atom(struct r600_context *rctx,
52 struct r600_atom *atom,
53 unsigned id,
54 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
55 unsigned num_dw)
56 {
57 assert(id < R600_NUM_ATOMS);
58 assert(rctx->atoms[id] == NULL);
59 rctx->atoms[id] = atom;
60 atom->id = id;
61 atom->emit = emit;
62 atom->num_dw = num_dw;
63 atom->dirty = false;
64 }
65
66 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom)
67 {
68 r600_emit_command_buffer(rctx->cs, ((struct r600_cso_state*)atom)->cb);
69 }
70
71 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom)
72 {
73 struct radeon_winsys_cs *cs = rctx->cs;
74 struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom;
75 unsigned alpha_ref = a->sx_alpha_ref;
76
77 if (rctx->chip_class >= EVERGREEN && a->cb0_export_16bpc) {
78 alpha_ref &= ~0x1FFF;
79 }
80
81 r600_write_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL,
82 a->sx_alpha_test_control |
83 S_028410_ALPHA_TEST_BYPASS(a->bypass));
84 r600_write_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref);
85 }
86
87 static void r600_texture_barrier(struct pipe_context *ctx)
88 {
89 struct r600_context *rctx = (struct r600_context *)ctx;
90
91 rctx->flags |= R600_CONTEXT_CB_FLUSH | R600_CONTEXT_TEX_FLUSH;
92
93 /* R6xx errata */
94 if (rctx->chip_class == R600) {
95 rctx->flags |= R600_CONTEXT_FLUSH_AND_INV;
96 }
97 }
98
99 static unsigned r600_conv_pipe_prim(unsigned prim)
100 {
101 static const unsigned prim_conv[] = {
102 V_008958_DI_PT_POINTLIST,
103 V_008958_DI_PT_LINELIST,
104 V_008958_DI_PT_LINELOOP,
105 V_008958_DI_PT_LINESTRIP,
106 V_008958_DI_PT_TRILIST,
107 V_008958_DI_PT_TRISTRIP,
108 V_008958_DI_PT_TRIFAN,
109 V_008958_DI_PT_QUADLIST,
110 V_008958_DI_PT_QUADSTRIP,
111 V_008958_DI_PT_POLYGON,
112 V_008958_DI_PT_LINELIST_ADJ,
113 V_008958_DI_PT_LINESTRIP_ADJ,
114 V_008958_DI_PT_TRILIST_ADJ,
115 V_008958_DI_PT_TRISTRIP_ADJ,
116 V_008958_DI_PT_RECTLIST
117 };
118 return prim_conv[prim];
119 }
120
121 /* common state between evergreen and r600 */
122
123 static void r600_bind_blend_state_internal(struct r600_context *rctx,
124 struct r600_blend_state *blend, bool blend_disable)
125 {
126 unsigned color_control;
127 bool update_cb = false;
128
129 rctx->alpha_to_one = blend->alpha_to_one;
130 rctx->dual_src_blend = blend->dual_src_blend;
131
132 if (!blend_disable) {
133 r600_set_cso_state_with_cb(&rctx->blend_state, blend, &blend->buffer);
134 color_control = blend->cb_color_control;
135 } else {
136 /* Blending is disabled. */
137 r600_set_cso_state_with_cb(&rctx->blend_state, blend, &blend->buffer_no_blend);
138 color_control = blend->cb_color_control_no_blend;
139 }
140
141 /* Update derived states. */
142 if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) {
143 rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
144 update_cb = true;
145 }
146 if (rctx->chip_class <= R700 &&
147 rctx->cb_misc_state.cb_color_control != color_control) {
148 rctx->cb_misc_state.cb_color_control = color_control;
149 update_cb = true;
150 }
151 if (rctx->cb_misc_state.dual_src_blend != blend->dual_src_blend) {
152 rctx->cb_misc_state.dual_src_blend = blend->dual_src_blend;
153 update_cb = true;
154 }
155 if (update_cb) {
156 rctx->cb_misc_state.atom.dirty = true;
157 }
158 }
159
160 static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
161 {
162 struct r600_context *rctx = (struct r600_context *)ctx;
163 struct r600_blend_state *blend = (struct r600_blend_state *)state;
164
165 if (blend == NULL)
166 return;
167
168 r600_bind_blend_state_internal(rctx, blend, rctx->force_blend_disable);
169 }
170
171 static void r600_set_blend_color(struct pipe_context *ctx,
172 const struct pipe_blend_color *state)
173 {
174 struct r600_context *rctx = (struct r600_context *)ctx;
175
176 rctx->blend_color.state = *state;
177 rctx->blend_color.atom.dirty = true;
178 }
179
180 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom)
181 {
182 struct radeon_winsys_cs *cs = rctx->cs;
183 struct pipe_blend_color *state = &rctx->blend_color.state;
184
185 r600_write_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
186 r600_write_value(cs, fui(state->color[0])); /* R_028414_CB_BLEND_RED */
187 r600_write_value(cs, fui(state->color[1])); /* R_028418_CB_BLEND_GREEN */
188 r600_write_value(cs, fui(state->color[2])); /* R_02841C_CB_BLEND_BLUE */
189 r600_write_value(cs, fui(state->color[3])); /* R_028420_CB_BLEND_ALPHA */
190 }
191
192 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom)
193 {
194 struct radeon_winsys_cs *cs = rctx->cs;
195 struct r600_vgt_state *a = (struct r600_vgt_state *)atom;
196
197 r600_write_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, a->vgt_multi_prim_ib_reset_en);
198 r600_write_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, a->vgt_multi_prim_ib_reset_indx);
199 }
200
201 void r600_emit_vgt2_state(struct r600_context *rctx, struct r600_atom *atom)
202 {
203 struct radeon_winsys_cs *cs = rctx->cs;
204 struct r600_vgt2_state *a = (struct r600_vgt2_state *)atom;
205
206 r600_write_context_reg(cs, R_028408_VGT_INDX_OFFSET, a->vgt_indx_offset);
207 }
208
209 static void r600_set_clip_state(struct pipe_context *ctx,
210 const struct pipe_clip_state *state)
211 {
212 struct r600_context *rctx = (struct r600_context *)ctx;
213 struct pipe_constant_buffer cb;
214
215 rctx->clip_state.state = *state;
216 rctx->clip_state.atom.dirty = true;
217
218 cb.buffer = NULL;
219 cb.user_buffer = state->ucp;
220 cb.buffer_offset = 0;
221 cb.buffer_size = 4*4*8;
222 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, R600_UCP_CONST_BUFFER, &cb);
223 pipe_resource_reference(&cb.buffer, NULL);
224 }
225
226 static void r600_set_stencil_ref(struct pipe_context *ctx,
227 const struct r600_stencil_ref *state)
228 {
229 struct r600_context *rctx = (struct r600_context *)ctx;
230
231 rctx->stencil_ref.state = *state;
232 rctx->stencil_ref.atom.dirty = true;
233 }
234
235 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom)
236 {
237 struct radeon_winsys_cs *cs = rctx->cs;
238 struct r600_stencil_ref_state *a = (struct r600_stencil_ref_state*)atom;
239
240 r600_write_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
241 r600_write_value(cs, /* R_028430_DB_STENCILREFMASK */
242 S_028430_STENCILREF(a->state.ref_value[0]) |
243 S_028430_STENCILMASK(a->state.valuemask[0]) |
244 S_028430_STENCILWRITEMASK(a->state.writemask[0]));
245 r600_write_value(cs, /* R_028434_DB_STENCILREFMASK_BF */
246 S_028434_STENCILREF_BF(a->state.ref_value[1]) |
247 S_028434_STENCILMASK_BF(a->state.valuemask[1]) |
248 S_028434_STENCILWRITEMASK_BF(a->state.writemask[1]));
249 }
250
251 static void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
252 const struct pipe_stencil_ref *state)
253 {
254 struct r600_context *rctx = (struct r600_context *)ctx;
255 struct r600_dsa_state *dsa = (struct r600_dsa_state*)rctx->dsa_state.cso;
256 struct r600_stencil_ref ref;
257
258 rctx->stencil_ref.pipe_state = *state;
259
260 if (!dsa)
261 return;
262
263 ref.ref_value[0] = state->ref_value[0];
264 ref.ref_value[1] = state->ref_value[1];
265 ref.valuemask[0] = dsa->valuemask[0];
266 ref.valuemask[1] = dsa->valuemask[1];
267 ref.writemask[0] = dsa->writemask[0];
268 ref.writemask[1] = dsa->writemask[1];
269
270 r600_set_stencil_ref(ctx, &ref);
271 }
272
273 static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
274 {
275 struct r600_context *rctx = (struct r600_context *)ctx;
276 struct r600_dsa_state *dsa = state;
277 struct r600_stencil_ref ref;
278
279 if (state == NULL)
280 return;
281
282 r600_set_cso_state_with_cb(&rctx->dsa_state, dsa, &dsa->buffer);
283
284 ref.ref_value[0] = rctx->stencil_ref.pipe_state.ref_value[0];
285 ref.ref_value[1] = rctx->stencil_ref.pipe_state.ref_value[1];
286 ref.valuemask[0] = dsa->valuemask[0];
287 ref.valuemask[1] = dsa->valuemask[1];
288 ref.writemask[0] = dsa->writemask[0];
289 ref.writemask[1] = dsa->writemask[1];
290
291 r600_set_stencil_ref(ctx, &ref);
292
293 /* Update alphatest state. */
294 if (rctx->alphatest_state.sx_alpha_test_control != dsa->sx_alpha_test_control ||
295 rctx->alphatest_state.sx_alpha_ref != dsa->alpha_ref) {
296 rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control;
297 rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref;
298 rctx->alphatest_state.atom.dirty = true;
299 }
300 }
301
302 static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
303 {
304 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
305 struct r600_context *rctx = (struct r600_context *)ctx;
306
307 if (state == NULL)
308 return;
309
310 rctx->rasterizer = rs;
311
312 r600_set_cso_state_with_cb(&rctx->rasterizer_state, rs, &rs->buffer);
313
314 if (rs->offset_enable &&
315 (rs->offset_units != rctx->poly_offset_state.offset_units ||
316 rs->offset_scale != rctx->poly_offset_state.offset_scale)) {
317 rctx->poly_offset_state.offset_units = rs->offset_units;
318 rctx->poly_offset_state.offset_scale = rs->offset_scale;
319 rctx->poly_offset_state.atom.dirty = true;
320 }
321
322 /* Update clip_misc_state. */
323 if (rctx->clip_misc_state.pa_cl_clip_cntl != rs->pa_cl_clip_cntl ||
324 rctx->clip_misc_state.clip_plane_enable != rs->clip_plane_enable) {
325 rctx->clip_misc_state.pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
326 rctx->clip_misc_state.clip_plane_enable = rs->clip_plane_enable;
327 rctx->clip_misc_state.atom.dirty = true;
328 }
329
330 /* Workaround for a missing scissor enable on r600. */
331 if (rctx->chip_class == R600 &&
332 rs->scissor_enable != rctx->scissor.enable) {
333 rctx->scissor.enable = rs->scissor_enable;
334 rctx->scissor.atom.dirty = true;
335 }
336
337 /* Re-emit PA_SC_LINE_STIPPLE. */
338 rctx->last_primitive_type = -1;
339 }
340
341 static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
342 {
343 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
344
345 r600_release_command_buffer(&rs->buffer);
346 FREE(rs);
347 }
348
349 static void r600_sampler_view_destroy(struct pipe_context *ctx,
350 struct pipe_sampler_view *state)
351 {
352 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
353
354 pipe_resource_reference(&state->texture, NULL);
355 FREE(resource);
356 }
357
358 void r600_sampler_states_dirty(struct r600_context *rctx,
359 struct r600_sampler_states *state)
360 {
361 if (state->dirty_mask) {
362 if (state->dirty_mask & state->has_bordercolor_mask) {
363 rctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
364 }
365 state->atom.num_dw =
366 util_bitcount(state->dirty_mask & state->has_bordercolor_mask) * 11 +
367 util_bitcount(state->dirty_mask & ~state->has_bordercolor_mask) * 5;
368 state->atom.dirty = true;
369 }
370 }
371
372 static void r600_bind_sampler_states(struct pipe_context *pipe,
373 unsigned shader,
374 unsigned start,
375 unsigned count, void **states)
376 {
377 struct r600_context *rctx = (struct r600_context *)pipe;
378 struct r600_textures_info *dst = &rctx->samplers[shader];
379 struct r600_pipe_sampler_state **rstates = (struct r600_pipe_sampler_state**)states;
380 int seamless_cube_map = -1;
381 unsigned i;
382 /* This sets 1-bit for states with index >= count. */
383 uint32_t disable_mask = ~((1ull << count) - 1);
384 /* These are the new states set by this function. */
385 uint32_t new_mask = 0;
386
387 assert(start == 0); /* XXX fix below */
388
389 for (i = 0; i < count; i++) {
390 struct r600_pipe_sampler_state *rstate = rstates[i];
391
392 if (rstate == dst->states.states[i]) {
393 continue;
394 }
395
396 if (rstate) {
397 if (rstate->border_color_use) {
398 dst->states.has_bordercolor_mask |= 1 << i;
399 } else {
400 dst->states.has_bordercolor_mask &= ~(1 << i);
401 }
402 seamless_cube_map = rstate->seamless_cube_map;
403
404 new_mask |= 1 << i;
405 } else {
406 disable_mask |= 1 << i;
407 }
408 }
409
410 memcpy(dst->states.states, rstates, sizeof(void*) * count);
411 memset(dst->states.states + count, 0, sizeof(void*) * (NUM_TEX_UNITS - count));
412
413 dst->states.enabled_mask &= ~disable_mask;
414 dst->states.dirty_mask &= dst->states.enabled_mask;
415 dst->states.enabled_mask |= new_mask;
416 dst->states.dirty_mask |= new_mask;
417 dst->states.has_bordercolor_mask &= dst->states.enabled_mask;
418
419 r600_sampler_states_dirty(rctx, &dst->states);
420
421 /* Seamless cubemap state. */
422 if (rctx->chip_class <= R700 &&
423 seamless_cube_map != -1 &&
424 seamless_cube_map != rctx->seamless_cube_map.enabled) {
425 /* change in TA_CNTL_AUX need a pipeline flush */
426 rctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
427 rctx->seamless_cube_map.enabled = seamless_cube_map;
428 rctx->seamless_cube_map.atom.dirty = true;
429 }
430 }
431
432 static void r600_bind_vs_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
433 {
434 r600_bind_sampler_states(ctx, PIPE_SHADER_VERTEX, 0, count, states);
435 }
436
437 static void r600_bind_ps_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
438 {
439 r600_bind_sampler_states(ctx, PIPE_SHADER_FRAGMENT, 0, count, states);
440 }
441
442 static void r600_delete_sampler_state(struct pipe_context *ctx, void *state)
443 {
444 free(state);
445 }
446
447 static void r600_delete_blend_state(struct pipe_context *ctx, void *state)
448 {
449 struct r600_blend_state *blend = (struct r600_blend_state*)state;
450
451 r600_release_command_buffer(&blend->buffer);
452 r600_release_command_buffer(&blend->buffer_no_blend);
453 FREE(blend);
454 }
455
456 static void r600_delete_dsa_state(struct pipe_context *ctx, void *state)
457 {
458 struct r600_dsa_state *dsa = (struct r600_dsa_state *)state;
459
460 r600_release_command_buffer(&dsa->buffer);
461 free(dsa);
462 }
463
464 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
465 {
466 struct r600_context *rctx = (struct r600_context *)ctx;
467
468 r600_set_cso_state(&rctx->vertex_fetch_shader, state);
469 }
470
471 static void r600_delete_vertex_elements(struct pipe_context *ctx, void *state)
472 {
473 pipe_resource_reference((struct pipe_resource**)&state, NULL);
474 }
475
476 static void r600_set_index_buffer(struct pipe_context *ctx,
477 const struct pipe_index_buffer *ib)
478 {
479 struct r600_context *rctx = (struct r600_context *)ctx;
480
481 if (ib) {
482 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
483 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
484 } else {
485 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
486 }
487 }
488
489 void r600_vertex_buffers_dirty(struct r600_context *rctx)
490 {
491 if (rctx->vertex_buffer_state.dirty_mask) {
492 rctx->flags |= rctx->has_vertex_cache ? R600_CONTEXT_VTX_FLUSH : R600_CONTEXT_TEX_FLUSH;
493 rctx->vertex_buffer_state.atom.num_dw = (rctx->chip_class >= EVERGREEN ? 12 : 11) *
494 util_bitcount(rctx->vertex_buffer_state.dirty_mask);
495 rctx->vertex_buffer_state.atom.dirty = true;
496 }
497 }
498
499 static void r600_set_vertex_buffers(struct pipe_context *ctx,
500 unsigned start_slot, unsigned count,
501 const struct pipe_vertex_buffer *input)
502 {
503 struct r600_context *rctx = (struct r600_context *)ctx;
504 struct r600_vertexbuf_state *state = &rctx->vertex_buffer_state;
505 struct pipe_vertex_buffer *vb = state->vb + start_slot;
506 unsigned i;
507 uint32_t disable_mask = 0;
508 /* These are the new buffers set by this function. */
509 uint32_t new_buffer_mask = 0;
510
511 /* Set vertex buffers. */
512 if (input) {
513 for (i = 0; i < count; i++) {
514 if (memcmp(&input[i], &vb[i], sizeof(struct pipe_vertex_buffer))) {
515 if (input[i].buffer) {
516 vb[i].stride = input[i].stride;
517 vb[i].buffer_offset = input[i].buffer_offset;
518 pipe_resource_reference(&vb[i].buffer, input[i].buffer);
519 new_buffer_mask |= 1 << i;
520 } else {
521 pipe_resource_reference(&vb[i].buffer, NULL);
522 disable_mask |= 1 << i;
523 }
524 }
525 }
526 } else {
527 for (i = 0; i < count; i++) {
528 pipe_resource_reference(&vb[i].buffer, NULL);
529 }
530 disable_mask = ((1ull << count) - 1);
531 }
532
533 disable_mask <<= start_slot;
534 new_buffer_mask <<= start_slot;
535
536 rctx->vertex_buffer_state.enabled_mask &= ~disable_mask;
537 rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask;
538 rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask;
539 rctx->vertex_buffer_state.dirty_mask |= new_buffer_mask;
540
541 r600_vertex_buffers_dirty(rctx);
542 }
543
544 void r600_sampler_views_dirty(struct r600_context *rctx,
545 struct r600_samplerview_state *state)
546 {
547 if (state->dirty_mask) {
548 rctx->flags |= R600_CONTEXT_TEX_FLUSH;
549 state->atom.num_dw = (rctx->chip_class >= EVERGREEN ? 14 : 13) *
550 util_bitcount(state->dirty_mask);
551 state->atom.dirty = true;
552 }
553 }
554
555 static void r600_set_sampler_views(struct pipe_context *pipe, unsigned shader,
556 unsigned start, unsigned count,
557 struct pipe_sampler_view **views)
558 {
559 struct r600_context *rctx = (struct r600_context *) pipe;
560 struct r600_textures_info *dst = &rctx->samplers[shader];
561 struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
562 uint32_t dirty_sampler_states_mask = 0;
563 unsigned i;
564 /* This sets 1-bit for textures with index >= count. */
565 uint32_t disable_mask = ~((1ull << count) - 1);
566 /* These are the new textures set by this function. */
567 uint32_t new_mask = 0;
568
569 /* Set textures with index >= count to NULL. */
570 uint32_t remaining_mask;
571
572 assert(start == 0); /* XXX fix below */
573
574 remaining_mask = dst->views.enabled_mask & disable_mask;
575
576 while (remaining_mask) {
577 i = u_bit_scan(&remaining_mask);
578 assert(dst->views.views[i]);
579
580 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
581 }
582
583 for (i = 0; i < count; i++) {
584 if (rviews[i] == dst->views.views[i]) {
585 continue;
586 }
587
588 if (rviews[i]) {
589 struct r600_texture *rtex =
590 (struct r600_texture*)rviews[i]->base.texture;
591
592 if (rtex->is_depth && !rtex->is_flushing_texture) {
593 dst->views.compressed_depthtex_mask |= 1 << i;
594 } else {
595 dst->views.compressed_depthtex_mask &= ~(1 << i);
596 }
597
598 /* Track compressed colorbuffers. */
599 if (rtex->cmask_size && rtex->fmask_size) {
600 dst->views.compressed_colortex_mask |= 1 << i;
601 } else {
602 dst->views.compressed_colortex_mask &= ~(1 << i);
603 }
604
605 /* Changing from array to non-arrays textures and vice versa requires
606 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
607 if (rctx->chip_class <= R700 &&
608 (dst->states.enabled_mask & (1 << i)) &&
609 (rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
610 rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) {
611 dirty_sampler_states_mask |= 1 << i;
612 }
613
614 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]);
615 new_mask |= 1 << i;
616 } else {
617 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
618 disable_mask |= 1 << i;
619 }
620 }
621
622 dst->views.enabled_mask &= ~disable_mask;
623 dst->views.dirty_mask &= dst->views.enabled_mask;
624 dst->views.enabled_mask |= new_mask;
625 dst->views.dirty_mask |= new_mask;
626 dst->views.compressed_depthtex_mask &= dst->views.enabled_mask;
627 dst->views.compressed_colortex_mask &= dst->views.enabled_mask;
628 dst->views.dirty_txq_constants = TRUE;
629 r600_sampler_views_dirty(rctx, &dst->views);
630
631 if (dirty_sampler_states_mask) {
632 dst->states.dirty_mask |= dirty_sampler_states_mask;
633 r600_sampler_states_dirty(rctx, &dst->states);
634 }
635 }
636
637 static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
638 struct pipe_sampler_view **views)
639 {
640 r600_set_sampler_views(ctx, PIPE_SHADER_VERTEX, 0, count, views);
641 }
642
643 static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
644 struct pipe_sampler_view **views)
645 {
646 r600_set_sampler_views(ctx, PIPE_SHADER_FRAGMENT, 0, count, views);
647 }
648
649 static void r600_set_viewport_state(struct pipe_context *ctx,
650 const struct pipe_viewport_state *state)
651 {
652 struct r600_context *rctx = (struct r600_context *)ctx;
653
654 rctx->viewport.state = *state;
655 rctx->viewport.atom.dirty = true;
656 }
657
658 void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom)
659 {
660 struct radeon_winsys_cs *cs = rctx->cs;
661 struct pipe_viewport_state *state = &rctx->viewport.state;
662
663 r600_write_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE_0, 6);
664 r600_write_value(cs, fui(state->scale[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
665 r600_write_value(cs, fui(state->translate[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
666 r600_write_value(cs, fui(state->scale[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
667 r600_write_value(cs, fui(state->translate[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
668 r600_write_value(cs, fui(state->scale[2])); /* R_02844C_PA_CL_VPORT_ZSCALE_0 */
669 r600_write_value(cs, fui(state->translate[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
670 }
671
672 /* Compute the key for the hw shader variant */
673 static INLINE struct r600_shader_key r600_shader_selector_key(struct pipe_context * ctx,
674 struct r600_pipe_shader_selector * sel)
675 {
676 struct r600_context *rctx = (struct r600_context *)ctx;
677 struct r600_shader_key key;
678 memset(&key, 0, sizeof(key));
679
680 if (sel->type == PIPE_SHADER_FRAGMENT) {
681 key.color_two_side = rctx->rasterizer && rctx->rasterizer->two_side;
682 key.alpha_to_one = rctx->alpha_to_one &&
683 rctx->rasterizer && rctx->rasterizer->multisample_enable &&
684 !rctx->framebuffer.cb0_is_integer;
685 key.nr_cbufs = rctx->framebuffer.state.nr_cbufs;
686 /* Dual-source blending only makes sense with nr_cbufs == 1. */
687 if (key.nr_cbufs == 1 && rctx->dual_src_blend)
688 key.nr_cbufs = 2;
689 }
690 return key;
691 }
692
693 /* Select the hw shader variant depending on the current state.
694 * (*dirty) is set to 1 if current variant was changed */
695 static int r600_shader_select(struct pipe_context *ctx,
696 struct r600_pipe_shader_selector* sel,
697 unsigned *dirty)
698 {
699 struct r600_shader_key key;
700 struct r600_context *rctx = (struct r600_context *)ctx;
701 struct r600_pipe_shader * shader = NULL;
702 int r;
703
704 key = r600_shader_selector_key(ctx, sel);
705
706 /* Check if we don't need to change anything.
707 * This path is also used for most shaders that don't need multiple
708 * variants, it will cost just a computation of the key and this
709 * test. */
710 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
711 return 0;
712 }
713
714 /* lookup if we have other variants in the list */
715 if (sel->num_shaders > 1) {
716 struct r600_pipe_shader *p = sel->current, *c = p->next_variant;
717
718 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
719 p = c;
720 c = c->next_variant;
721 }
722
723 if (c) {
724 p->next_variant = c->next_variant;
725 shader = c;
726 }
727 }
728
729 if (unlikely(!shader)) {
730 shader = CALLOC(1, sizeof(struct r600_pipe_shader));
731 shader->selector = sel;
732
733 r = r600_pipe_shader_create(ctx, shader, key);
734 if (unlikely(r)) {
735 R600_ERR("Failed to build shader variant (type=%u) %d\n",
736 sel->type, r);
737 sel->current = NULL;
738 return r;
739 }
740
741 /* We don't know the value of nr_ps_max_color_exports until we built
742 * at least one variant, so we may need to recompute the key after
743 * building first variant. */
744 if (sel->type == PIPE_SHADER_FRAGMENT &&
745 sel->num_shaders == 0) {
746 sel->nr_ps_max_color_exports = shader->shader.nr_ps_max_color_exports;
747 key = r600_shader_selector_key(ctx, sel);
748 }
749
750 shader->key = key;
751 sel->num_shaders++;
752 }
753
754 if (dirty)
755 *dirty = 1;
756
757 shader->next_variant = sel->current;
758 sel->current = shader;
759
760 if (rctx->ps_shader &&
761 rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
762 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
763 rctx->cb_misc_state.atom.dirty = true;
764 }
765 return 0;
766 }
767
768 static void *r600_create_shader_state(struct pipe_context *ctx,
769 const struct pipe_shader_state *state,
770 unsigned pipe_shader_type)
771 {
772 struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector);
773 int r;
774
775 sel->type = pipe_shader_type;
776 sel->tokens = tgsi_dup_tokens(state->tokens);
777 sel->so = state->stream_output;
778
779 r = r600_shader_select(ctx, sel, NULL);
780 if (r)
781 return NULL;
782
783 return sel;
784 }
785
786 static void *r600_create_ps_state(struct pipe_context *ctx,
787 const struct pipe_shader_state *state)
788 {
789 return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
790 }
791
792 static void *r600_create_vs_state(struct pipe_context *ctx,
793 const struct pipe_shader_state *state)
794 {
795 return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
796 }
797
798 static void r600_bind_ps_state(struct pipe_context *ctx, void *state)
799 {
800 struct r600_context *rctx = (struct r600_context *)ctx;
801
802 if (!state)
803 state = rctx->dummy_pixel_shader;
804
805 rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
806 r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
807
808 if (rctx->chip_class <= R700) {
809 bool multiwrite = rctx->ps_shader->current->shader.fs_write_all;
810
811 if (rctx->cb_misc_state.multiwrite != multiwrite) {
812 rctx->cb_misc_state.multiwrite = multiwrite;
813 rctx->cb_misc_state.atom.dirty = true;
814 }
815 }
816
817 if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
818 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
819 rctx->cb_misc_state.atom.dirty = true;
820 }
821
822 if (rctx->chip_class >= EVERGREEN) {
823 evergreen_update_db_shader_control(rctx);
824 } else {
825 r600_update_db_shader_control(rctx);
826 }
827 }
828
829 static void r600_bind_vs_state(struct pipe_context *ctx, void *state)
830 {
831 struct r600_context *rctx = (struct r600_context *)ctx;
832
833 rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
834 if (state) {
835 r600_context_pipe_state_set(rctx, &rctx->vs_shader->current->rstate);
836
837 /* Update clip misc state. */
838 if (rctx->vs_shader->current->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
839 rctx->vs_shader->current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write) {
840 rctx->clip_misc_state.pa_cl_vs_out_cntl = rctx->vs_shader->current->pa_cl_vs_out_cntl;
841 rctx->clip_misc_state.clip_dist_write = rctx->vs_shader->current->shader.clip_dist_write;
842 rctx->clip_misc_state.atom.dirty = true;
843 }
844 }
845 }
846
847 static void r600_delete_shader_selector(struct pipe_context *ctx,
848 struct r600_pipe_shader_selector *sel)
849 {
850 struct r600_pipe_shader *p = sel->current, *c;
851 while (p) {
852 c = p->next_variant;
853 r600_pipe_shader_destroy(ctx, p);
854 free(p);
855 p = c;
856 }
857
858 free(sel->tokens);
859 free(sel);
860 }
861
862
863 static void r600_delete_ps_state(struct pipe_context *ctx, void *state)
864 {
865 struct r600_context *rctx = (struct r600_context *)ctx;
866 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
867
868 if (rctx->ps_shader == sel) {
869 rctx->ps_shader = NULL;
870 }
871
872 r600_delete_shader_selector(ctx, sel);
873 }
874
875 static void r600_delete_vs_state(struct pipe_context *ctx, void *state)
876 {
877 struct r600_context *rctx = (struct r600_context *)ctx;
878 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
879
880 if (rctx->vs_shader == sel) {
881 rctx->vs_shader = NULL;
882 }
883
884 r600_delete_shader_selector(ctx, sel);
885 }
886
887 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
888 {
889 if (state->dirty_mask) {
890 rctx->flags |= R600_CONTEXT_SHADERCONST_FLUSH;
891 state->atom.num_dw = rctx->chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
892 : util_bitcount(state->dirty_mask)*19;
893 state->atom.dirty = true;
894 }
895 }
896
897 static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
898 struct pipe_constant_buffer *input)
899 {
900 struct r600_context *rctx = (struct r600_context *)ctx;
901 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
902 struct pipe_constant_buffer *cb;
903 const uint8_t *ptr;
904
905 /* Note that the state tracker can unbind constant buffers by
906 * passing NULL here.
907 */
908 if (unlikely(!input)) {
909 state->enabled_mask &= ~(1 << index);
910 state->dirty_mask &= ~(1 << index);
911 pipe_resource_reference(&state->cb[index].buffer, NULL);
912 return;
913 }
914
915 cb = &state->cb[index];
916 cb->buffer_size = input->buffer_size;
917
918 ptr = input->user_buffer;
919
920 if (ptr) {
921 /* Upload the user buffer. */
922 if (R600_BIG_ENDIAN) {
923 uint32_t *tmpPtr;
924 unsigned i, size = input->buffer_size;
925
926 if (!(tmpPtr = malloc(size))) {
927 R600_ERR("Failed to allocate BE swap buffer.\n");
928 return;
929 }
930
931 for (i = 0; i < size / 4; ++i) {
932 tmpPtr[i] = bswap_32(((uint32_t *)ptr)[i]);
933 }
934
935 u_upload_data(rctx->uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer);
936 free(tmpPtr);
937 } else {
938 u_upload_data(rctx->uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer);
939 }
940 } else {
941 /* Setup the hw buffer. */
942 cb->buffer_offset = input->buffer_offset;
943 pipe_resource_reference(&cb->buffer, input->buffer);
944 }
945
946 state->enabled_mask |= 1 << index;
947 state->dirty_mask |= 1 << index;
948 r600_constant_buffers_dirty(rctx, state);
949 }
950
951 static struct pipe_stream_output_target *
952 r600_create_so_target(struct pipe_context *ctx,
953 struct pipe_resource *buffer,
954 unsigned buffer_offset,
955 unsigned buffer_size)
956 {
957 struct r600_context *rctx = (struct r600_context *)ctx;
958 struct r600_so_target *t;
959
960 t = CALLOC_STRUCT(r600_so_target);
961 if (!t) {
962 return NULL;
963 }
964
965 u_suballocator_alloc(rctx->allocator_so_filled_size, 4,
966 &t->buf_filled_size_offset,
967 (struct pipe_resource**)&t->buf_filled_size);
968 if (!t->buf_filled_size) {
969 FREE(t);
970 return NULL;
971 }
972
973 t->b.reference.count = 1;
974 t->b.context = ctx;
975 pipe_resource_reference(&t->b.buffer, buffer);
976 t->b.buffer_offset = buffer_offset;
977 t->b.buffer_size = buffer_size;
978 return &t->b;
979 }
980
981 static void r600_so_target_destroy(struct pipe_context *ctx,
982 struct pipe_stream_output_target *target)
983 {
984 struct r600_so_target *t = (struct r600_so_target*)target;
985 pipe_resource_reference(&t->b.buffer, NULL);
986 pipe_resource_reference((struct pipe_resource**)&t->buf_filled_size, NULL);
987 FREE(t);
988 }
989
990 static void r600_set_so_targets(struct pipe_context *ctx,
991 unsigned num_targets,
992 struct pipe_stream_output_target **targets,
993 unsigned append_bitmask)
994 {
995 struct r600_context *rctx = (struct r600_context *)ctx;
996 unsigned i;
997
998 /* Stop streamout. */
999 if (rctx->num_so_targets && !rctx->streamout_start) {
1000 r600_context_streamout_end(rctx);
1001 }
1002
1003 /* Set the new targets. */
1004 for (i = 0; i < num_targets; i++) {
1005 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]);
1006 }
1007 for (; i < rctx->num_so_targets; i++) {
1008 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL);
1009 }
1010
1011 rctx->num_so_targets = num_targets;
1012 rctx->streamout_start = num_targets != 0;
1013 rctx->streamout_append_bitmask = append_bitmask;
1014 }
1015
1016 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1017 {
1018 struct r600_context *rctx = (struct r600_context*)pipe;
1019
1020 if (rctx->sample_mask.sample_mask == (uint16_t)sample_mask)
1021 return;
1022
1023 rctx->sample_mask.sample_mask = sample_mask;
1024 rctx->sample_mask.atom.dirty = true;
1025 }
1026
1027 static void r600_setup_txq_cube_array_constants(struct r600_context *rctx, int shader_type)
1028 {
1029 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1030 int bits;
1031 uint32_t array_size;
1032 struct pipe_constant_buffer cb;
1033 int i;
1034
1035 if (!samplers->views.dirty_txq_constants)
1036 return;
1037
1038 samplers->views.dirty_txq_constants = FALSE;
1039
1040 bits = util_last_bit(samplers->views.enabled_mask);
1041 array_size = bits * sizeof(uint32_t) * 4;
1042 samplers->txq_constants = realloc(samplers->txq_constants, array_size);
1043 memset(samplers->txq_constants, 0, array_size);
1044 for (i = 0; i < bits; i++)
1045 if (samplers->views.enabled_mask & (1 << i))
1046 samplers->txq_constants[i] = samplers->views.views[i]->base.texture->array_size / 6;
1047
1048 cb.buffer = NULL;
1049 cb.user_buffer = samplers->txq_constants;
1050 cb.buffer_offset = 0;
1051 cb.buffer_size = array_size;
1052 rctx->context.set_constant_buffer(&rctx->context, shader_type, R600_TXQ_CONST_BUFFER, &cb);
1053 pipe_resource_reference(&cb.buffer, NULL);
1054 }
1055
1056 static bool r600_update_derived_state(struct r600_context *rctx)
1057 {
1058 struct pipe_context * ctx = (struct pipe_context*)rctx;
1059 unsigned ps_dirty = 0;
1060 bool blend_disable;
1061
1062 if (!rctx->blitter->running) {
1063 unsigned i;
1064
1065 /* Decompress textures if needed. */
1066 for (i = 0; i < PIPE_SHADER_TYPES; i++) {
1067 struct r600_samplerview_state *views = &rctx->samplers[i].views;
1068 if (views->compressed_depthtex_mask) {
1069 r600_decompress_depth_textures(rctx, views);
1070 }
1071 if (views->compressed_colortex_mask) {
1072 r600_decompress_color_textures(rctx, views);
1073 }
1074 }
1075 }
1076
1077 r600_shader_select(ctx, rctx->ps_shader, &ps_dirty);
1078
1079 if (rctx->ps_shader && rctx->rasterizer &&
1080 ((rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable) ||
1081 (rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade))) {
1082
1083 if (rctx->chip_class >= EVERGREEN)
1084 evergreen_pipe_shader_ps(ctx, rctx->ps_shader->current);
1085 else
1086 r600_pipe_shader_ps(ctx, rctx->ps_shader->current);
1087
1088 ps_dirty = 1;
1089 }
1090
1091 if (ps_dirty)
1092 r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
1093
1094 if (rctx->ps_shader && rctx->ps_shader->current->shader.has_txq_cube_array_z_comp)
1095 r600_setup_txq_cube_array_constants(rctx, PIPE_SHADER_FRAGMENT);
1096 if (rctx->vs_shader && rctx->vs_shader->current->shader.has_txq_cube_array_z_comp)
1097 r600_setup_txq_cube_array_constants(rctx, PIPE_SHADER_VERTEX);
1098
1099 if (rctx->chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
1100 if (!r600_adjust_gprs(rctx)) {
1101 /* discard rendering */
1102 return false;
1103 }
1104 }
1105
1106 blend_disable = (rctx->dual_src_blend &&
1107 rctx->ps_shader->current->nr_ps_color_outputs < 2);
1108
1109 if (blend_disable != rctx->force_blend_disable) {
1110 rctx->force_blend_disable = blend_disable;
1111 r600_bind_blend_state_internal(rctx,
1112 rctx->blend_state.cso,
1113 blend_disable);
1114 }
1115 return true;
1116 }
1117
1118 static unsigned r600_conv_prim_to_gs_out(unsigned mode)
1119 {
1120 static const int prim_conv[] = {
1121 V_028A6C_OUTPRIM_TYPE_POINTLIST,
1122 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1123 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1124 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1125 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1126 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1127 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1128 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1129 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1130 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1131 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1132 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1133 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1134 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1135 V_028A6C_OUTPRIM_TYPE_TRISTRIP
1136 };
1137 assert(mode < Elements(prim_conv));
1138
1139 return prim_conv[mode];
1140 }
1141
1142 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1143 {
1144 struct radeon_winsys_cs *cs = rctx->cs;
1145 struct r600_clip_misc_state *state = &rctx->clip_misc_state;
1146
1147 r600_write_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
1148 state->pa_cl_clip_cntl |
1149 (state->clip_dist_write ? 0 : state->clip_plane_enable & 0x3F));
1150 r600_write_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
1151 state->pa_cl_vs_out_cntl |
1152 (state->clip_plane_enable & state->clip_dist_write));
1153 }
1154
1155 static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
1156 {
1157 struct r600_context *rctx = (struct r600_context *)ctx;
1158 struct pipe_draw_info info = *dinfo;
1159 struct pipe_index_buffer ib = {};
1160 unsigned i;
1161 struct r600_block *dirty_block = NULL, *next_block = NULL;
1162 struct radeon_winsys_cs *cs = rctx->cs;
1163
1164 if (!info.count && (info.indexed || !info.count_from_stream_output)) {
1165 assert(0);
1166 return;
1167 }
1168
1169 if (!rctx->vs_shader) {
1170 assert(0);
1171 return;
1172 }
1173
1174 if (!r600_update_derived_state(rctx)) {
1175 /* useless to render because current rendering command
1176 * can't be achieved
1177 */
1178 return;
1179 }
1180
1181 if (info.indexed) {
1182 /* Initialize the index buffer struct. */
1183 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
1184 ib.user_buffer = rctx->index_buffer.user_buffer;
1185 ib.index_size = rctx->index_buffer.index_size;
1186 ib.offset = rctx->index_buffer.offset + info.start * ib.index_size;
1187
1188 /* Translate 8-bit indices to 16-bit. */
1189 if (ib.index_size == 1) {
1190 struct pipe_resource *out_buffer = NULL;
1191 unsigned out_offset;
1192 void *ptr;
1193
1194 u_upload_alloc(rctx->uploader, 0, info.count * 2,
1195 &out_offset, &out_buffer, &ptr);
1196
1197 util_shorten_ubyte_elts_to_userptr(
1198 &rctx->context, &ib, 0, ib.offset, info.count, ptr);
1199
1200 pipe_resource_reference(&ib.buffer, NULL);
1201 ib.user_buffer = NULL;
1202 ib.buffer = out_buffer;
1203 ib.offset = out_offset;
1204 ib.index_size = 2;
1205 }
1206
1207 /* Upload the index buffer.
1208 * The upload is skipped for small index counts on little-endian machines
1209 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
1210 * Note: Instanced rendering in combination with immediate indices hangs. */
1211 if (ib.user_buffer && (R600_BIG_ENDIAN || info.instance_count > 1 ||
1212 info.count*ib.index_size > 20)) {
1213 u_upload_data(rctx->uploader, 0, info.count * ib.index_size,
1214 ib.user_buffer, &ib.offset, &ib.buffer);
1215 ib.user_buffer = NULL;
1216 }
1217 } else {
1218 info.index_bias = info.start;
1219 }
1220
1221 /* Enable stream out if needed. */
1222 if (rctx->streamout_start) {
1223 r600_context_streamout_begin(rctx);
1224 rctx->streamout_start = FALSE;
1225 }
1226
1227 /* Set the index offset and multi primitive */
1228 if (rctx->vgt2_state.vgt_indx_offset != info.index_bias) {
1229 rctx->vgt2_state.vgt_indx_offset = info.index_bias;
1230 rctx->vgt2_state.atom.dirty = true;
1231 }
1232 if (rctx->vgt_state.vgt_multi_prim_ib_reset_en != info.primitive_restart ||
1233 rctx->vgt_state.vgt_multi_prim_ib_reset_indx != info.restart_index) {
1234 rctx->vgt_state.vgt_multi_prim_ib_reset_en = info.primitive_restart;
1235 rctx->vgt_state.vgt_multi_prim_ib_reset_indx = info.restart_index;
1236 rctx->vgt_state.atom.dirty = true;
1237 }
1238
1239 /* Emit states. */
1240 r600_need_cs_space(rctx, ib.user_buffer ? 5 : 0, TRUE);
1241 r600_flush_emit(rctx);
1242
1243 for (i = 0; i < R600_NUM_ATOMS; i++) {
1244 if (rctx->atoms[i] == NULL || !rctx->atoms[i]->dirty) {
1245 continue;
1246 }
1247 r600_emit_atom(rctx, rctx->atoms[i]);
1248 }
1249 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) {
1250 r600_context_block_emit_dirty(rctx, dirty_block, 0 /* pkt_flags */);
1251 }
1252 rctx->pm4_dirty_cdwords = 0;
1253
1254 /* Update start instance. */
1255 if (rctx->last_start_instance != info.start_instance) {
1256 r600_write_ctl_const(cs, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
1257 rctx->last_start_instance = info.start_instance;
1258 }
1259
1260 /* Update the primitive type. */
1261 if (rctx->last_primitive_type != info.mode) {
1262 unsigned ls_mask = 0;
1263
1264 if (info.mode == PIPE_PRIM_LINES)
1265 ls_mask = 1;
1266 else if (info.mode == PIPE_PRIM_LINE_STRIP ||
1267 info.mode == PIPE_PRIM_LINE_LOOP)
1268 ls_mask = 2;
1269
1270 r600_write_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
1271 S_028A0C_AUTO_RESET_CNTL(ls_mask) |
1272 (rctx->rasterizer ? rctx->rasterizer->pa_sc_line_stipple : 0));
1273 r600_write_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
1274 r600_conv_prim_to_gs_out(info.mode));
1275 r600_write_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE,
1276 r600_conv_pipe_prim(info.mode));
1277
1278 rctx->last_primitive_type = info.mode;
1279 }
1280
1281 /* Draw packets. */
1282 cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->predicate_drawing);
1283 cs->buf[cs->cdw++] = info.instance_count;
1284 if (info.indexed) {
1285 cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->predicate_drawing);
1286 cs->buf[cs->cdw++] = ib.index_size == 4 ?
1287 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
1288 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
1289
1290 if (ib.user_buffer) {
1291 unsigned size_bytes = info.count*ib.index_size;
1292 unsigned size_dw = align(size_bytes, 4) / 4;
1293 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_IMMD, 1 + size_dw, rctx->predicate_drawing);
1294 cs->buf[cs->cdw++] = info.count;
1295 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_IMMEDIATE;
1296 memcpy(cs->buf+cs->cdw, ib.user_buffer, size_bytes);
1297 cs->cdw += size_dw;
1298 } else {
1299 uint64_t va = r600_resource_va(ctx->screen, ib.buffer) + ib.offset;
1300 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->predicate_drawing);
1301 cs->buf[cs->cdw++] = va;
1302 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
1303 cs->buf[cs->cdw++] = info.count;
1304 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
1305 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->predicate_drawing);
1306 cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
1307 }
1308 } else {
1309 if (info.count_from_stream_output) {
1310 struct r600_so_target *t = (struct r600_so_target*)info.count_from_stream_output;
1311 uint64_t va = r600_resource_va(&rctx->screen->screen, (void*)t->buf_filled_size) + t->buf_filled_size_offset;
1312
1313 r600_write_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
1314
1315 cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0);
1316 cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG;
1317 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */
1318 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
1319 cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */
1320 cs->buf[cs->cdw++] = 0; /* unused */
1321
1322 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1323 cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, t->buf_filled_size, RADEON_USAGE_READ);
1324 }
1325
1326 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->predicate_drawing);
1327 cs->buf[cs->cdw++] = info.count;
1328 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
1329 (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
1330 }
1331
1332 /* Set the depth buffer as dirty. */
1333 if (rctx->framebuffer.state.zsbuf) {
1334 struct pipe_surface *surf = rctx->framebuffer.state.zsbuf;
1335 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
1336
1337 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1338 }
1339 if (rctx->framebuffer.compressed_cb_mask) {
1340 struct pipe_surface *surf;
1341 struct r600_texture *rtex;
1342 unsigned mask = rctx->framebuffer.compressed_cb_mask;
1343
1344 do {
1345 unsigned i = u_bit_scan(&mask);
1346 surf = rctx->framebuffer.state.cbufs[i];
1347 rtex = (struct r600_texture*)surf->texture;
1348
1349 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1350
1351 } while (mask);
1352 }
1353
1354 pipe_resource_reference(&ib.buffer, NULL);
1355 }
1356
1357 void r600_draw_rectangle(struct blitter_context *blitter,
1358 int x1, int y1, int x2, int y2, float depth,
1359 enum blitter_attrib_type type, const union pipe_color_union *attrib)
1360 {
1361 struct r600_context *rctx = (struct r600_context*)util_blitter_get_pipe(blitter);
1362 struct pipe_viewport_state viewport;
1363 struct pipe_resource *buf = NULL;
1364 unsigned offset = 0;
1365 float *vb;
1366
1367 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
1368 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
1369 return;
1370 }
1371
1372 /* Some operations (like color resolve on r6xx) don't work
1373 * with the conventional primitive types.
1374 * One that works is PT_RECTLIST, which we use here. */
1375
1376 /* setup viewport */
1377 viewport.scale[0] = 1.0f;
1378 viewport.scale[1] = 1.0f;
1379 viewport.scale[2] = 1.0f;
1380 viewport.scale[3] = 1.0f;
1381 viewport.translate[0] = 0.0f;
1382 viewport.translate[1] = 0.0f;
1383 viewport.translate[2] = 0.0f;
1384 viewport.translate[3] = 0.0f;
1385 rctx->context.set_viewport_state(&rctx->context, &viewport);
1386
1387 /* Upload vertices. The hw rectangle has only 3 vertices,
1388 * I guess the 4th one is derived from the first 3.
1389 * The vertex specification should match u_blitter's vertex element state. */
1390 u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, &offset, &buf, (void**)&vb);
1391 vb[0] = x1;
1392 vb[1] = y1;
1393 vb[2] = depth;
1394 vb[3] = 1;
1395
1396 vb[8] = x1;
1397 vb[9] = y2;
1398 vb[10] = depth;
1399 vb[11] = 1;
1400
1401 vb[16] = x2;
1402 vb[17] = y1;
1403 vb[18] = depth;
1404 vb[19] = 1;
1405
1406 if (attrib) {
1407 memcpy(vb+4, attrib->f, sizeof(float)*4);
1408 memcpy(vb+12, attrib->f, sizeof(float)*4);
1409 memcpy(vb+20, attrib->f, sizeof(float)*4);
1410 }
1411
1412 /* draw */
1413 util_draw_vertex_buffer(&rctx->context, NULL, buf, rctx->blitter->vb_slot, offset,
1414 R600_PRIM_RECTANGLE_LIST, 3, 2);
1415 pipe_resource_reference(&buf, NULL);
1416 }
1417
1418 void _r600_pipe_state_add_reg_bo(struct r600_context *ctx,
1419 struct r600_pipe_state *state,
1420 uint32_t offset, uint32_t value,
1421 uint32_t range_id, uint32_t block_id,
1422 struct r600_resource *bo,
1423 enum radeon_bo_usage usage)
1424
1425 {
1426 struct r600_range *range;
1427 struct r600_block *block;
1428
1429 if (bo) assert(usage);
1430
1431 range = &ctx->range[range_id];
1432 block = range->blocks[block_id];
1433 state->regs[state->nregs].block = block;
1434 state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
1435
1436 state->regs[state->nregs].value = value;
1437 state->regs[state->nregs].bo = bo;
1438 state->regs[state->nregs].bo_usage = usage;
1439
1440 state->nregs++;
1441 assert(state->nregs < R600_BLOCK_MAX_REG);
1442 }
1443
1444 void _r600_pipe_state_add_reg(struct r600_context *ctx,
1445 struct r600_pipe_state *state,
1446 uint32_t offset, uint32_t value,
1447 uint32_t range_id, uint32_t block_id)
1448 {
1449 _r600_pipe_state_add_reg_bo(ctx, state, offset, value,
1450 range_id, block_id, NULL, 0);
1451 }
1452
1453 uint32_t r600_translate_stencil_op(int s_op)
1454 {
1455 switch (s_op) {
1456 case PIPE_STENCIL_OP_KEEP:
1457 return V_028800_STENCIL_KEEP;
1458 case PIPE_STENCIL_OP_ZERO:
1459 return V_028800_STENCIL_ZERO;
1460 case PIPE_STENCIL_OP_REPLACE:
1461 return V_028800_STENCIL_REPLACE;
1462 case PIPE_STENCIL_OP_INCR:
1463 return V_028800_STENCIL_INCR;
1464 case PIPE_STENCIL_OP_DECR:
1465 return V_028800_STENCIL_DECR;
1466 case PIPE_STENCIL_OP_INCR_WRAP:
1467 return V_028800_STENCIL_INCR_WRAP;
1468 case PIPE_STENCIL_OP_DECR_WRAP:
1469 return V_028800_STENCIL_DECR_WRAP;
1470 case PIPE_STENCIL_OP_INVERT:
1471 return V_028800_STENCIL_INVERT;
1472 default:
1473 R600_ERR("Unknown stencil op %d", s_op);
1474 assert(0);
1475 break;
1476 }
1477 return 0;
1478 }
1479
1480 uint32_t r600_translate_fill(uint32_t func)
1481 {
1482 switch(func) {
1483 case PIPE_POLYGON_MODE_FILL:
1484 return 2;
1485 case PIPE_POLYGON_MODE_LINE:
1486 return 1;
1487 case PIPE_POLYGON_MODE_POINT:
1488 return 0;
1489 default:
1490 assert(0);
1491 return 0;
1492 }
1493 }
1494
1495 unsigned r600_tex_wrap(unsigned wrap)
1496 {
1497 switch (wrap) {
1498 default:
1499 case PIPE_TEX_WRAP_REPEAT:
1500 return V_03C000_SQ_TEX_WRAP;
1501 case PIPE_TEX_WRAP_CLAMP:
1502 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1503 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1504 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1505 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1506 return V_03C000_SQ_TEX_CLAMP_BORDER;
1507 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1508 return V_03C000_SQ_TEX_MIRROR;
1509 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1510 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1511 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1512 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1513 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1514 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1515 }
1516 }
1517
1518 unsigned r600_tex_filter(unsigned filter)
1519 {
1520 switch (filter) {
1521 default:
1522 case PIPE_TEX_FILTER_NEAREST:
1523 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1524 case PIPE_TEX_FILTER_LINEAR:
1525 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1526 }
1527 }
1528
1529 unsigned r600_tex_mipfilter(unsigned filter)
1530 {
1531 switch (filter) {
1532 case PIPE_TEX_MIPFILTER_NEAREST:
1533 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1534 case PIPE_TEX_MIPFILTER_LINEAR:
1535 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1536 default:
1537 case PIPE_TEX_MIPFILTER_NONE:
1538 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1539 }
1540 }
1541
1542 unsigned r600_tex_compare(unsigned compare)
1543 {
1544 switch (compare) {
1545 default:
1546 case PIPE_FUNC_NEVER:
1547 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1548 case PIPE_FUNC_LESS:
1549 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1550 case PIPE_FUNC_EQUAL:
1551 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1552 case PIPE_FUNC_LEQUAL:
1553 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1554 case PIPE_FUNC_GREATER:
1555 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1556 case PIPE_FUNC_NOTEQUAL:
1557 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1558 case PIPE_FUNC_GEQUAL:
1559 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1560 case PIPE_FUNC_ALWAYS:
1561 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1562 }
1563 }
1564
1565 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
1566 {
1567 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
1568 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
1569 (linear_filter &&
1570 (wrap == PIPE_TEX_WRAP_CLAMP ||
1571 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
1572 }
1573
1574 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
1575 {
1576 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
1577 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
1578
1579 return (state->border_color.ui[0] || state->border_color.ui[1] ||
1580 state->border_color.ui[2] || state->border_color.ui[3]) &&
1581 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
1582 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
1583 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
1584 }
1585
1586 /* keep this at the end of this file, please */
1587 void r600_init_common_state_functions(struct r600_context *rctx)
1588 {
1589 rctx->context.create_fs_state = r600_create_ps_state;
1590 rctx->context.create_vs_state = r600_create_vs_state;
1591 rctx->context.create_vertex_elements_state = r600_create_vertex_fetch_shader;
1592 rctx->context.bind_blend_state = r600_bind_blend_state;
1593 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1594 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler_states;
1595 rctx->context.bind_fs_state = r600_bind_ps_state;
1596 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1597 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1598 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler_states;
1599 rctx->context.bind_vs_state = r600_bind_vs_state;
1600 rctx->context.delete_blend_state = r600_delete_blend_state;
1601 rctx->context.delete_depth_stencil_alpha_state = r600_delete_dsa_state;
1602 rctx->context.delete_fs_state = r600_delete_ps_state;
1603 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1604 rctx->context.delete_sampler_state = r600_delete_sampler_state;
1605 rctx->context.delete_vertex_elements_state = r600_delete_vertex_elements;
1606 rctx->context.delete_vs_state = r600_delete_vs_state;
1607 rctx->context.set_blend_color = r600_set_blend_color;
1608 rctx->context.set_clip_state = r600_set_clip_state;
1609 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1610 rctx->context.set_sample_mask = r600_set_sample_mask;
1611 rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1612 rctx->context.set_viewport_state = r600_set_viewport_state;
1613 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1614 rctx->context.set_index_buffer = r600_set_index_buffer;
1615 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views;
1616 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views;
1617 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1618 rctx->context.texture_barrier = r600_texture_barrier;
1619 rctx->context.create_stream_output_target = r600_create_so_target;
1620 rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1621 rctx->context.set_stream_output_targets = r600_set_so_targets;
1622 rctx->context.draw_vbo = r600_draw_vbo;
1623 }