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r600g: consolidate the main draw code
[mesa.git] / src / gallium / drivers / r600 / r600_state_common.c
1 /*
2 * Copyright 2010 Red Hat Inc.
3 * 2010 Jerome Glisse
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
26 */
27 #include "util/u_blitter.h"
28 #include "util/u_memory.h"
29 #include "util/u_format.h"
30 #include "pipebuffer/pb_buffer.h"
31 #include "pipe/p_shader_tokens.h"
32 #include "tgsi/tgsi_parse.h"
33 #include "r600_formats.h"
34 #include "r600_pipe.h"
35 #include "r600d.h"
36 #include "r600_hw_context_priv.h"
37
38 static void r600_emit_command_buffer(struct r600_context *rctx, struct r600_atom *atom)
39 {
40 struct radeon_winsys_cs *cs = rctx->cs;
41 struct r600_command_buffer *cb = (struct r600_command_buffer*)atom;
42
43 assert(cs->cdw + cb->atom.num_dw <= RADEON_MAX_CMDBUF_DWORDS);
44 memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->atom.num_dw);
45 cs->cdw += cb->atom.num_dw;
46 }
47
48 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags)
49 {
50 cb->atom.emit = r600_emit_command_buffer;
51 cb->atom.num_dw = 0;
52 cb->atom.flags = flags;
53 cb->buf = CALLOC(1, 4 * num_dw);
54 cb->max_num_dw = num_dw;
55 }
56
57 void r600_release_command_buffer(struct r600_command_buffer *cb)
58 {
59 FREE(cb->buf);
60 }
61
62 static void r600_emit_surface_sync(struct r600_context *rctx, struct r600_atom *atom)
63 {
64 struct radeon_winsys_cs *cs = rctx->cs;
65 struct r600_atom_surface_sync *a = (struct r600_atom_surface_sync*)atom;
66
67 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
68 cs->buf[cs->cdw++] = a->flush_flags; /* CP_COHER_CNTL */
69 cs->buf[cs->cdw++] = 0xffffffff; /* CP_COHER_SIZE */
70 cs->buf[cs->cdw++] = 0; /* CP_COHER_BASE */
71 cs->buf[cs->cdw++] = 0x0000000A; /* POLL_INTERVAL */
72
73 a->flush_flags = 0;
74 }
75
76 static void r600_emit_r6xx_flush_and_inv(struct r600_context *rctx, struct r600_atom *atom)
77 {
78 struct radeon_winsys_cs *cs = rctx->cs;
79 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
80 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
81 }
82
83 static void r600_init_atom(struct r600_atom *atom,
84 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
85 unsigned num_dw,
86 enum r600_atom_flags flags)
87 {
88 atom->emit = emit;
89 atom->num_dw = num_dw;
90 atom->flags = flags;
91 }
92
93 void r600_init_common_atoms(struct r600_context *rctx)
94 {
95 r600_init_atom(&rctx->atom_surface_sync.atom, r600_emit_surface_sync, 5, EMIT_EARLY);
96 r600_init_atom(&rctx->atom_r6xx_flush_and_inv, r600_emit_r6xx_flush_and_inv, 2, EMIT_EARLY);
97 }
98
99 unsigned r600_get_cb_flush_flags(struct r600_context *rctx)
100 {
101 unsigned flags = 0;
102
103 if (rctx->framebuffer.nr_cbufs) {
104 flags |= S_0085F0_CB_ACTION_ENA(1) |
105 (((1 << rctx->framebuffer.nr_cbufs) - 1) << S_0085F0_CB0_DEST_BASE_ENA_SHIFT);
106 }
107
108 /* Workaround for broken flushing on some R6xx chipsets. */
109 if (rctx->family == CHIP_RV670 ||
110 rctx->family == CHIP_RS780 ||
111 rctx->family == CHIP_RS880) {
112 flags |= S_0085F0_CB1_DEST_BASE_ENA(1) |
113 S_0085F0_DEST_BASE_0_ENA(1);
114 }
115 return flags;
116 }
117
118 void r600_texture_barrier(struct pipe_context *ctx)
119 {
120 struct r600_context *rctx = (struct r600_context *)ctx;
121
122 rctx->atom_surface_sync.flush_flags |= S_0085F0_TC_ACTION_ENA(1) | r600_get_cb_flush_flags(rctx);
123 r600_atom_dirty(rctx, &rctx->atom_surface_sync.atom);
124 }
125
126 static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
127 {
128 static const int prim_conv[] = {
129 V_008958_DI_PT_POINTLIST,
130 V_008958_DI_PT_LINELIST,
131 V_008958_DI_PT_LINELOOP,
132 V_008958_DI_PT_LINESTRIP,
133 V_008958_DI_PT_TRILIST,
134 V_008958_DI_PT_TRISTRIP,
135 V_008958_DI_PT_TRIFAN,
136 V_008958_DI_PT_QUADLIST,
137 V_008958_DI_PT_QUADSTRIP,
138 V_008958_DI_PT_POLYGON,
139 -1,
140 -1,
141 -1,
142 -1
143 };
144
145 *prim = prim_conv[pprim];
146 if (*prim == -1) {
147 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim);
148 return false;
149 }
150 return true;
151 }
152
153 /* common state between evergreen and r600 */
154 void r600_bind_blend_state(struct pipe_context *ctx, void *state)
155 {
156 struct r600_context *rctx = (struct r600_context *)ctx;
157 struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
158 struct r600_pipe_state *rstate;
159
160 if (state == NULL)
161 return;
162 rstate = &blend->rstate;
163 rctx->states[rstate->id] = rstate;
164 rctx->cb_target_mask = blend->cb_target_mask;
165
166 /* Replace every bit except MULTIWRITE_ENABLE. */
167 rctx->cb_color_control &= ~C_028808_MULTIWRITE_ENABLE;
168 rctx->cb_color_control |= blend->cb_color_control & C_028808_MULTIWRITE_ENABLE;
169
170 r600_context_pipe_state_set(rctx, rstate);
171 }
172
173 void r600_set_blend_color(struct pipe_context *ctx,
174 const struct pipe_blend_color *state)
175 {
176 struct r600_context *rctx = (struct r600_context *)ctx;
177 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
178
179 if (rstate == NULL)
180 return;
181
182 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
183 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), NULL, 0);
184 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), NULL, 0);
185 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), NULL, 0);
186 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), NULL, 0);
187
188 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
189 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
190 r600_context_pipe_state_set(rctx, rstate);
191 }
192
193 static void r600_set_stencil_ref(struct pipe_context *ctx,
194 const struct r600_stencil_ref *state)
195 {
196 struct r600_context *rctx = (struct r600_context *)ctx;
197 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
198
199 if (rstate == NULL)
200 return;
201
202 rstate->id = R600_PIPE_STATE_STENCIL_REF;
203 r600_pipe_state_add_reg(rstate,
204 R_028430_DB_STENCILREFMASK,
205 S_028430_STENCILREF(state->ref_value[0]) |
206 S_028430_STENCILMASK(state->valuemask[0]) |
207 S_028430_STENCILWRITEMASK(state->writemask[0]),
208 NULL, 0);
209 r600_pipe_state_add_reg(rstate,
210 R_028434_DB_STENCILREFMASK_BF,
211 S_028434_STENCILREF_BF(state->ref_value[1]) |
212 S_028434_STENCILMASK_BF(state->valuemask[1]) |
213 S_028434_STENCILWRITEMASK_BF(state->writemask[1]),
214 NULL, 0);
215
216 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
217 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
218 r600_context_pipe_state_set(rctx, rstate);
219 }
220
221 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
222 const struct pipe_stencil_ref *state)
223 {
224 struct r600_context *rctx = (struct r600_context *)ctx;
225 struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA];
226 struct r600_stencil_ref ref;
227
228 rctx->stencil_ref = *state;
229
230 if (!dsa)
231 return;
232
233 ref.ref_value[0] = state->ref_value[0];
234 ref.ref_value[1] = state->ref_value[1];
235 ref.valuemask[0] = dsa->valuemask[0];
236 ref.valuemask[1] = dsa->valuemask[1];
237 ref.writemask[0] = dsa->writemask[0];
238 ref.writemask[1] = dsa->writemask[1];
239
240 r600_set_stencil_ref(ctx, &ref);
241 }
242
243 void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
244 {
245 struct r600_context *rctx = (struct r600_context *)ctx;
246 struct r600_pipe_dsa *dsa = state;
247 struct r600_pipe_state *rstate;
248 struct r600_stencil_ref ref;
249
250 if (state == NULL)
251 return;
252 rstate = &dsa->rstate;
253 rctx->states[rstate->id] = rstate;
254 rctx->alpha_ref = dsa->alpha_ref;
255 rctx->alpha_ref_dirty = true;
256 r600_context_pipe_state_set(rctx, rstate);
257
258 ref.ref_value[0] = rctx->stencil_ref.ref_value[0];
259 ref.ref_value[1] = rctx->stencil_ref.ref_value[1];
260 ref.valuemask[0] = dsa->valuemask[0];
261 ref.valuemask[1] = dsa->valuemask[1];
262 ref.writemask[0] = dsa->writemask[0];
263 ref.writemask[1] = dsa->writemask[1];
264
265 r600_set_stencil_ref(ctx, &ref);
266 }
267
268 void r600_bind_rs_state(struct pipe_context *ctx, void *state)
269 {
270 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
271 struct r600_context *rctx = (struct r600_context *)ctx;
272
273 if (state == NULL)
274 return;
275
276 rctx->sprite_coord_enable = rs->sprite_coord_enable;
277 rctx->two_side = rs->two_side;
278 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
279 rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
280
281 rctx->rasterizer = rs;
282
283 rctx->states[rs->rstate.id] = &rs->rstate;
284 r600_context_pipe_state_set(rctx, &rs->rstate);
285
286 if (rctx->chip_class >= EVERGREEN) {
287 evergreen_polygon_offset_update(rctx);
288 } else {
289 r600_polygon_offset_update(rctx);
290 }
291 }
292
293 void r600_delete_rs_state(struct pipe_context *ctx, void *state)
294 {
295 struct r600_context *rctx = (struct r600_context *)ctx;
296 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
297
298 if (rctx->rasterizer == rs) {
299 rctx->rasterizer = NULL;
300 }
301 if (rctx->states[rs->rstate.id] == &rs->rstate) {
302 rctx->states[rs->rstate.id] = NULL;
303 }
304 free(rs);
305 }
306
307 void r600_sampler_view_destroy(struct pipe_context *ctx,
308 struct pipe_sampler_view *state)
309 {
310 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
311
312 pipe_resource_reference(&state->texture, NULL);
313 FREE(resource);
314 }
315
316 void r600_delete_state(struct pipe_context *ctx, void *state)
317 {
318 struct r600_context *rctx = (struct r600_context *)ctx;
319 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
320
321 if (rctx->states[rstate->id] == rstate) {
322 rctx->states[rstate->id] = NULL;
323 }
324 for (int i = 0; i < rstate->nregs; i++) {
325 pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL);
326 }
327 free(rstate);
328 }
329
330 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
331 {
332 struct r600_context *rctx = (struct r600_context *)ctx;
333 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
334
335 rctx->vertex_elements = v;
336 if (v) {
337 r600_inval_shader_cache(rctx);
338 u_vbuf_bind_vertex_elements(rctx->vbuf_mgr, state,
339 v->vmgr_elements);
340
341 rctx->states[v->rstate.id] = &v->rstate;
342 r600_context_pipe_state_set(rctx, &v->rstate);
343 }
344 }
345
346 void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
347 {
348 struct r600_context *rctx = (struct r600_context *)ctx;
349 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
350
351 if (rctx->states[v->rstate.id] == &v->rstate) {
352 rctx->states[v->rstate.id] = NULL;
353 }
354 if (rctx->vertex_elements == state)
355 rctx->vertex_elements = NULL;
356
357 pipe_resource_reference((struct pipe_resource**)&v->fetch_shader, NULL);
358 u_vbuf_destroy_vertex_elements(rctx->vbuf_mgr, v->vmgr_elements);
359 FREE(state);
360 }
361
362
363 void r600_set_index_buffer(struct pipe_context *ctx,
364 const struct pipe_index_buffer *ib)
365 {
366 struct r600_context *rctx = (struct r600_context *)ctx;
367
368 u_vbuf_set_index_buffer(rctx->vbuf_mgr, ib);
369 }
370
371 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
372 const struct pipe_vertex_buffer *buffers)
373 {
374 struct r600_context *rctx = (struct r600_context *)ctx;
375 int i;
376
377 /* Zero states. */
378 for (i = 0; i < count; i++) {
379 if (!buffers[i].buffer) {
380 if (rctx->chip_class >= EVERGREEN) {
381 evergreen_context_pipe_state_set_fs_resource(rctx, NULL, i);
382 } else {
383 r600_context_pipe_state_set_fs_resource(rctx, NULL, i);
384 }
385 }
386 }
387 for (; i < rctx->vbuf_mgr->nr_real_vertex_buffers; i++) {
388 if (rctx->chip_class >= EVERGREEN) {
389 evergreen_context_pipe_state_set_fs_resource(rctx, NULL, i);
390 } else {
391 r600_context_pipe_state_set_fs_resource(rctx, NULL, i);
392 }
393 }
394
395 u_vbuf_set_vertex_buffers(rctx->vbuf_mgr, count, buffers);
396 }
397
398 void *r600_create_vertex_elements(struct pipe_context *ctx,
399 unsigned count,
400 const struct pipe_vertex_element *elements)
401 {
402 struct r600_context *rctx = (struct r600_context *)ctx;
403 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
404
405 assert(count < 32);
406 if (!v)
407 return NULL;
408
409 v->count = count;
410 v->vmgr_elements =
411 u_vbuf_create_vertex_elements(rctx->vbuf_mgr, count,
412 elements, v->elements);
413
414 if (r600_vertex_elements_build_fetch_shader(rctx, v)) {
415 FREE(v);
416 return NULL;
417 }
418
419 return v;
420 }
421
422 void *r600_create_shader_state(struct pipe_context *ctx,
423 const struct pipe_shader_state *state)
424 {
425 struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader);
426 int r;
427
428 shader->tokens = tgsi_dup_tokens(state->tokens);
429 shader->so = state->stream_output;
430
431 r = r600_pipe_shader_create(ctx, shader);
432 if (r) {
433 return NULL;
434 }
435 return shader;
436 }
437
438 void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
439 {
440 struct r600_context *rctx = (struct r600_context *)ctx;
441
442 /* TODO delete old shader */
443 rctx->ps_shader = (struct r600_pipe_shader *)state;
444 if (state) {
445 r600_inval_shader_cache(rctx);
446 r600_context_pipe_state_set(rctx, &rctx->ps_shader->rstate);
447
448 rctx->cb_color_control &= C_028808_MULTIWRITE_ENABLE;
449 rctx->cb_color_control |= S_028808_MULTIWRITE_ENABLE(!!rctx->ps_shader->shader.fs_write_all);
450 }
451 if (rctx->ps_shader && rctx->vs_shader) {
452 r600_adjust_gprs(rctx);
453 }
454 }
455
456 void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
457 {
458 struct r600_context *rctx = (struct r600_context *)ctx;
459
460 /* TODO delete old shader */
461 rctx->vs_shader = (struct r600_pipe_shader *)state;
462 if (state) {
463 r600_inval_shader_cache(rctx);
464 r600_context_pipe_state_set(rctx, &rctx->vs_shader->rstate);
465 }
466 if (rctx->ps_shader && rctx->vs_shader) {
467 r600_adjust_gprs(rctx);
468 }
469 }
470
471 void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
472 {
473 struct r600_context *rctx = (struct r600_context *)ctx;
474 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
475
476 if (rctx->ps_shader == shader) {
477 rctx->ps_shader = NULL;
478 }
479
480 free(shader->tokens);
481 r600_pipe_shader_destroy(ctx, shader);
482 free(shader);
483 }
484
485 void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
486 {
487 struct r600_context *rctx = (struct r600_context *)ctx;
488 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
489
490 if (rctx->vs_shader == shader) {
491 rctx->vs_shader = NULL;
492 }
493
494 free(shader->tokens);
495 r600_pipe_shader_destroy(ctx, shader);
496 free(shader);
497 }
498
499 static void r600_update_alpha_ref(struct r600_context *rctx)
500 {
501 unsigned alpha_ref;
502 struct r600_pipe_state rstate;
503
504 alpha_ref = rctx->alpha_ref;
505 rstate.nregs = 0;
506 if (rctx->export_16bpc)
507 alpha_ref &= ~0x1FFF;
508 r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref, NULL, 0);
509
510 r600_context_pipe_state_set(rctx, &rstate);
511 rctx->alpha_ref_dirty = false;
512 }
513
514 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
515 struct pipe_resource *buffer)
516 {
517 struct r600_context *rctx = (struct r600_context *)ctx;
518 struct r600_resource *rbuffer = r600_resource(buffer);
519 struct r600_pipe_resource_state *rstate;
520 uint64_t va_offset;
521 uint32_t offset;
522
523 /* Note that the state tracker can unbind constant buffers by
524 * passing NULL here.
525 */
526 if (buffer == NULL) {
527 return;
528 }
529
530 r600_inval_shader_cache(rctx);
531
532 r600_upload_const_buffer(rctx, &rbuffer, &offset);
533 va_offset = r600_resource_va(ctx->screen, (void*)rbuffer);
534 va_offset += offset;
535 va_offset >>= 8;
536
537 switch (shader) {
538 case PIPE_SHADER_VERTEX:
539 rctx->vs_const_buffer.nregs = 0;
540 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
541 R_028180_ALU_CONST_BUFFER_SIZE_VS_0 + index * 4,
542 ALIGN_DIVUP(buffer->width0 >> 4, 16),
543 NULL, 0);
544 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
545 R_028980_ALU_CONST_CACHE_VS_0 + index * 4,
546 va_offset, rbuffer, RADEON_USAGE_READ);
547 r600_context_pipe_state_set(rctx, &rctx->vs_const_buffer);
548
549 rstate = &rctx->vs_const_buffer_resource[index];
550 if (!rstate->id) {
551 if (rctx->chip_class >= EVERGREEN) {
552 evergreen_pipe_init_buffer_resource(rctx, rstate);
553 } else {
554 r600_pipe_init_buffer_resource(rctx, rstate);
555 }
556 }
557
558 if (rctx->chip_class >= EVERGREEN) {
559 evergreen_pipe_mod_buffer_resource(ctx, rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
560 evergreen_context_pipe_state_set_vs_resource(rctx, rstate, index);
561 } else {
562 r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
563 r600_context_pipe_state_set_vs_resource(rctx, rstate, index);
564 }
565 break;
566 case PIPE_SHADER_FRAGMENT:
567 rctx->ps_const_buffer.nregs = 0;
568 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
569 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
570 ALIGN_DIVUP(buffer->width0 >> 4, 16),
571 NULL, 0);
572 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
573 R_028940_ALU_CONST_CACHE_PS_0,
574 va_offset, rbuffer, RADEON_USAGE_READ);
575 r600_context_pipe_state_set(rctx, &rctx->ps_const_buffer);
576
577 rstate = &rctx->ps_const_buffer_resource[index];
578 if (!rstate->id) {
579 if (rctx->chip_class >= EVERGREEN) {
580 evergreen_pipe_init_buffer_resource(rctx, rstate);
581 } else {
582 r600_pipe_init_buffer_resource(rctx, rstate);
583 }
584 }
585 if (rctx->chip_class >= EVERGREEN) {
586 evergreen_pipe_mod_buffer_resource(ctx, rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
587 evergreen_context_pipe_state_set_ps_resource(rctx, rstate, index);
588 } else {
589 r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
590 r600_context_pipe_state_set_ps_resource(rctx, rstate, index);
591 }
592 break;
593 default:
594 R600_ERR("unsupported %d\n", shader);
595 return;
596 }
597
598 if (buffer != &rbuffer->b.b.b)
599 pipe_resource_reference((struct pipe_resource**)&rbuffer, NULL);
600 }
601
602 struct pipe_stream_output_target *
603 r600_create_so_target(struct pipe_context *ctx,
604 struct pipe_resource *buffer,
605 unsigned buffer_offset,
606 unsigned buffer_size)
607 {
608 struct r600_context *rctx = (struct r600_context *)ctx;
609 struct r600_so_target *t;
610 void *ptr;
611
612 t = CALLOC_STRUCT(r600_so_target);
613 if (!t) {
614 return NULL;
615 }
616
617 t->b.reference.count = 1;
618 t->b.context = ctx;
619 pipe_resource_reference(&t->b.buffer, buffer);
620 t->b.buffer_offset = buffer_offset;
621 t->b.buffer_size = buffer_size;
622
623 t->filled_size = (struct r600_resource*)
624 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4);
625 ptr = rctx->ws->buffer_map(t->filled_size->buf, rctx->cs, PIPE_TRANSFER_WRITE);
626 memset(ptr, 0, t->filled_size->buf->size);
627 rctx->ws->buffer_unmap(t->filled_size->buf);
628
629 return &t->b;
630 }
631
632 void r600_so_target_destroy(struct pipe_context *ctx,
633 struct pipe_stream_output_target *target)
634 {
635 struct r600_so_target *t = (struct r600_so_target*)target;
636 pipe_resource_reference(&t->b.buffer, NULL);
637 pipe_resource_reference((struct pipe_resource**)&t->filled_size, NULL);
638 FREE(t);
639 }
640
641 void r600_set_so_targets(struct pipe_context *ctx,
642 unsigned num_targets,
643 struct pipe_stream_output_target **targets,
644 unsigned append_bitmask)
645 {
646 struct r600_context *rctx = (struct r600_context *)ctx;
647 unsigned i;
648
649 /* Stop streamout. */
650 if (rctx->num_so_targets) {
651 r600_context_streamout_end(rctx);
652 }
653
654 /* Set the new targets. */
655 for (i = 0; i < num_targets; i++) {
656 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]);
657 }
658 for (; i < rctx->num_so_targets; i++) {
659 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL);
660 }
661
662 rctx->num_so_targets = num_targets;
663 rctx->streamout_start = num_targets != 0;
664 rctx->streamout_append_bitmask = append_bitmask;
665 }
666
667 static void r600_vertex_buffer_update(struct r600_context *rctx)
668 {
669 struct r600_pipe_resource_state *rstate;
670 struct r600_resource *rbuffer;
671 struct pipe_vertex_buffer *vertex_buffer;
672 unsigned i, count, offset;
673
674 r600_inval_vertex_cache(rctx);
675
676 if (rctx->vertex_elements->vbuffer_need_offset) {
677 /* one resource per vertex elements */
678 count = rctx->vertex_elements->count;
679 } else {
680 /* bind vertex buffer once */
681 count = rctx->vbuf_mgr->nr_real_vertex_buffers;
682 }
683
684 for (i = 0 ; i < count; i++) {
685 rstate = &rctx->fs_resource[i];
686
687 if (rctx->vertex_elements->vbuffer_need_offset) {
688 /* one resource per vertex elements */
689 unsigned vbuffer_index;
690 vbuffer_index = rctx->vertex_elements->elements[i].vertex_buffer_index;
691 vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[vbuffer_index];
692 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
693 offset = rctx->vertex_elements->vbuffer_offset[i];
694 } else {
695 /* bind vertex buffer once */
696 vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[i];
697 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
698 offset = 0;
699 }
700 if (vertex_buffer == NULL || rbuffer == NULL)
701 continue;
702 offset += vertex_buffer->buffer_offset;
703
704 if (!rstate->id) {
705 if (rctx->chip_class >= EVERGREEN) {
706 evergreen_pipe_init_buffer_resource(rctx, rstate);
707 } else {
708 r600_pipe_init_buffer_resource(rctx, rstate);
709 }
710 }
711
712 if (rctx->chip_class >= EVERGREEN) {
713 evergreen_pipe_mod_buffer_resource(&rctx->context, rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ);
714 evergreen_context_pipe_state_set_fs_resource(rctx, rstate, i);
715 } else {
716 r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ);
717 r600_context_pipe_state_set_fs_resource(rctx, rstate, i);
718 }
719 }
720 }
721
722 static int r600_shader_rebuild(struct pipe_context * ctx, struct r600_pipe_shader * shader)
723 {
724 struct r600_context *rctx = (struct r600_context *)ctx;
725 int r;
726
727 r600_pipe_shader_destroy(ctx, shader);
728 r = r600_pipe_shader_create(ctx, shader);
729 if (r) {
730 return r;
731 }
732 r600_context_pipe_state_set(rctx, &shader->rstate);
733
734 return 0;
735 }
736
737 static void r600_update_derived_state(struct r600_context *rctx)
738 {
739 struct pipe_context * ctx = (struct pipe_context*)rctx;
740 struct r600_pipe_state rstate;
741
742 rstate.nregs = 0;
743
744 if (rstate.nregs)
745 r600_context_pipe_state_set(rctx, &rstate);
746
747 if (!rctx->blitter->running) {
748 if (rctx->have_depth_fb || rctx->have_depth_texture)
749 r600_flush_depth_textures(rctx);
750 }
751
752 if (rctx->chip_class < EVERGREEN) {
753 r600_update_sampler_states(rctx);
754 }
755
756 if ((rctx->ps_shader->shader.two_side != rctx->two_side) ||
757 ((rctx->chip_class >= EVERGREEN) && rctx->ps_shader->shader.fs_write_all &&
758 (rctx->ps_shader->shader.nr_cbufs != rctx->nr_cbufs))) {
759 r600_shader_rebuild(&rctx->context, rctx->ps_shader);
760 }
761
762 if (rctx->alpha_ref_dirty) {
763 r600_update_alpha_ref(rctx);
764 }
765
766 if (rctx->ps_shader && ((rctx->sprite_coord_enable &&
767 (rctx->ps_shader->sprite_coord_enable != rctx->sprite_coord_enable)) ||
768 (rctx->rasterizer && rctx->rasterizer->flatshade != rctx->ps_shader->flatshade))) {
769
770 if (rctx->chip_class >= EVERGREEN)
771 evergreen_pipe_shader_ps(ctx, rctx->ps_shader);
772 else
773 r600_pipe_shader_ps(ctx, rctx->ps_shader);
774
775 r600_context_pipe_state_set(rctx, &rctx->ps_shader->rstate);
776 }
777
778 }
779
780 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
781 {
782 struct r600_context *rctx = (struct r600_context *)ctx;
783 struct pipe_draw_info info = *dinfo;
784 struct pipe_index_buffer ib = {};
785 unsigned prim, mask, ls_mask = 0;
786 struct r600_block *dirty_block = NULL, *next_block = NULL;
787 struct r600_atom *state = NULL, *next_state = NULL;
788 struct radeon_winsys_cs *cs = rctx->cs;
789 uint64_t va;
790
791 if ((!info.count && (info.indexed || !info.count_from_stream_output)) ||
792 (info.indexed && !rctx->vbuf_mgr->index_buffer.buffer) ||
793 !r600_conv_pipe_prim(info.mode, &prim)) {
794 return;
795 }
796
797 if (!rctx->ps_shader || !rctx->vs_shader)
798 return;
799
800 r600_update_derived_state(rctx);
801
802 u_vbuf_draw_begin(rctx->vbuf_mgr, &info);
803 r600_vertex_buffer_update(rctx);
804
805 if (info.indexed) {
806 /* Initialize the index buffer struct. */
807 pipe_resource_reference(&ib.buffer, rctx->vbuf_mgr->index_buffer.buffer);
808 ib.index_size = rctx->vbuf_mgr->index_buffer.index_size;
809 ib.offset = rctx->vbuf_mgr->index_buffer.offset + info.start * ib.index_size;
810
811 /* Translate or upload, if needed. */
812 r600_translate_index_buffer(rctx, &ib, info.count);
813
814 if (u_vbuf_resource(ib.buffer)->user_ptr) {
815 r600_upload_index_buffer(rctx, &ib, info.count);
816 }
817 } else {
818 info.index_bias = info.start;
819 if (info.count_from_stream_output) {
820 r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info.count_from_stream_output);
821 }
822 }
823
824 mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
825
826 if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
827 rctx->vgt.id = R600_PIPE_STATE_VGT;
828 rctx->vgt.nregs = 0;
829 r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, NULL, 0);
830 r600_pipe_state_add_reg(&rctx->vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, NULL, 0);
831 r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias, NULL, 0);
832 r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index, NULL, 0);
833 r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart, NULL, 0);
834 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance, NULL, 0);
835 r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0, NULL, 0);
836 if (rctx->chip_class <= R700)
837 r600_pipe_state_add_reg(&rctx->vgt, R_028808_CB_COLOR_CONTROL, rctx->cb_color_control, NULL, 0);
838 r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0, NULL, 0);
839 r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0, NULL, 0);
840 }
841
842 rctx->vgt.nregs = 0;
843 r600_pipe_state_mod_reg(&rctx->vgt, prim);
844 r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_target_mask & mask);
845 r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
846 r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
847 r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart);
848 r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance);
849
850 if (prim == V_008958_DI_PT_LINELIST)
851 ls_mask = 1;
852 else if (prim == V_008958_DI_PT_LINESTRIP)
853 ls_mask = 2;
854 r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask) | rctx->pa_sc_line_stipple);
855 if (rctx->chip_class <= R700)
856 r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_color_control);
857 r600_pipe_state_mod_reg(&rctx->vgt,
858 rctx->vs_shader->pa_cl_vs_out_cntl |
859 (rctx->rasterizer->clip_plane_enable & rctx->vs_shader->shader.clip_dist_write));
860 r600_pipe_state_mod_reg(&rctx->vgt,
861 rctx->pa_cl_clip_cntl |
862 (rctx->vs_shader->shader.clip_dist_write ||
863 rctx->vs_shader->shader.vs_prohibit_ucps ?
864 0 : rctx->rasterizer->clip_plane_enable & 0x3F));
865
866 r600_context_pipe_state_set(rctx, &rctx->vgt);
867
868 /* Emit states (the function expects that we emit at most 17 dwords here). */
869 r600_need_cs_space(rctx, 0, TRUE);
870
871 LIST_FOR_EACH_ENTRY_SAFE(state, next_state, &rctx->dirty_states, head) {
872 r600_emit_atom(rctx, state);
873 }
874 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) {
875 r600_context_block_emit_dirty(rctx, dirty_block);
876 }
877 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->resource_dirty,list) {
878 r600_context_block_resource_emit_dirty(rctx, dirty_block);
879 }
880 rctx->pm4_dirty_cdwords = 0;
881
882 /* Enable stream out if needed. */
883 if (rctx->streamout_start) {
884 r600_context_streamout_begin(rctx);
885 rctx->streamout_start = FALSE;
886 }
887
888 if (rctx->chip_class >= EVERGREEN) {
889 evergreen_context_draw_prepare(rctx);
890 } else {
891 r600_context_draw_prepare(rctx);
892 }
893
894 /* draw packet */
895 cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->predicate_drawing);
896 cs->buf[cs->cdw++] = ib.index_size == 4 ?
897 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
898 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
899 cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->predicate_drawing);
900 cs->buf[cs->cdw++] = info.instance_count;
901 if (info.indexed) {
902 va = r600_resource_va(ctx->screen, ib.buffer);
903 va += ib.offset;
904 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->predicate_drawing);
905 cs->buf[cs->cdw++] = va;
906 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
907 cs->buf[cs->cdw++] = info.count;
908 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
909 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->predicate_drawing);
910 cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
911 } else {
912 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->predicate_drawing);
913 cs->buf[cs->cdw++] = info.count;
914 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
915 (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
916 }
917
918 rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING;
919
920 if (rctx->framebuffer.zsbuf)
921 {
922 struct pipe_resource *tex = rctx->framebuffer.zsbuf->texture;
923 ((struct r600_resource_texture *)tex)->dirty_db = TRUE;
924 }
925
926 pipe_resource_reference(&ib.buffer, NULL);
927 u_vbuf_draw_end(rctx->vbuf_mgr);
928 }
929
930 void _r600_pipe_state_add_reg(struct r600_context *ctx,
931 struct r600_pipe_state *state,
932 uint32_t offset, uint32_t value,
933 uint32_t range_id, uint32_t block_id,
934 struct r600_resource *bo,
935 enum radeon_bo_usage usage)
936 {
937 struct r600_range *range;
938 struct r600_block *block;
939
940 if (bo) assert(usage);
941
942 range = &ctx->range[range_id];
943 block = range->blocks[block_id];
944 state->regs[state->nregs].block = block;
945 state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
946
947 state->regs[state->nregs].value = value;
948 state->regs[state->nregs].bo = bo;
949 state->regs[state->nregs].bo_usage = usage;
950
951 state->nregs++;
952 assert(state->nregs < R600_BLOCK_MAX_REG);
953 }
954
955 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
956 uint32_t offset, uint32_t value,
957 struct r600_resource *bo,
958 enum radeon_bo_usage usage)
959 {
960 if (bo) assert(usage);
961
962 state->regs[state->nregs].id = offset;
963 state->regs[state->nregs].block = NULL;
964 state->regs[state->nregs].value = value;
965 state->regs[state->nregs].bo = bo;
966 state->regs[state->nregs].bo_usage = usage;
967
968 state->nregs++;
969 assert(state->nregs < R600_BLOCK_MAX_REG);
970 }
971
972 uint32_t r600_translate_stencil_op(int s_op)
973 {
974 switch (s_op) {
975 case PIPE_STENCIL_OP_KEEP:
976 return V_028800_STENCIL_KEEP;
977 case PIPE_STENCIL_OP_ZERO:
978 return V_028800_STENCIL_ZERO;
979 case PIPE_STENCIL_OP_REPLACE:
980 return V_028800_STENCIL_REPLACE;
981 case PIPE_STENCIL_OP_INCR:
982 return V_028800_STENCIL_INCR;
983 case PIPE_STENCIL_OP_DECR:
984 return V_028800_STENCIL_DECR;
985 case PIPE_STENCIL_OP_INCR_WRAP:
986 return V_028800_STENCIL_INCR_WRAP;
987 case PIPE_STENCIL_OP_DECR_WRAP:
988 return V_028800_STENCIL_DECR_WRAP;
989 case PIPE_STENCIL_OP_INVERT:
990 return V_028800_STENCIL_INVERT;
991 default:
992 R600_ERR("Unknown stencil op %d", s_op);
993 assert(0);
994 break;
995 }
996 return 0;
997 }
998
999 uint32_t r600_translate_fill(uint32_t func)
1000 {
1001 switch(func) {
1002 case PIPE_POLYGON_MODE_FILL:
1003 return 2;
1004 case PIPE_POLYGON_MODE_LINE:
1005 return 1;
1006 case PIPE_POLYGON_MODE_POINT:
1007 return 0;
1008 default:
1009 assert(0);
1010 return 0;
1011 }
1012 }
1013
1014 unsigned r600_tex_wrap(unsigned wrap)
1015 {
1016 switch (wrap) {
1017 default:
1018 case PIPE_TEX_WRAP_REPEAT:
1019 return V_03C000_SQ_TEX_WRAP;
1020 case PIPE_TEX_WRAP_CLAMP:
1021 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1022 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1023 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1024 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1025 return V_03C000_SQ_TEX_CLAMP_BORDER;
1026 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1027 return V_03C000_SQ_TEX_MIRROR;
1028 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1029 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1030 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1031 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1032 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1033 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1034 }
1035 }
1036
1037 unsigned r600_tex_filter(unsigned filter)
1038 {
1039 switch (filter) {
1040 default:
1041 case PIPE_TEX_FILTER_NEAREST:
1042 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1043 case PIPE_TEX_FILTER_LINEAR:
1044 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1045 }
1046 }
1047
1048 unsigned r600_tex_mipfilter(unsigned filter)
1049 {
1050 switch (filter) {
1051 case PIPE_TEX_MIPFILTER_NEAREST:
1052 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1053 case PIPE_TEX_MIPFILTER_LINEAR:
1054 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1055 default:
1056 case PIPE_TEX_MIPFILTER_NONE:
1057 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1058 }
1059 }
1060
1061 unsigned r600_tex_compare(unsigned compare)
1062 {
1063 switch (compare) {
1064 default:
1065 case PIPE_FUNC_NEVER:
1066 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1067 case PIPE_FUNC_LESS:
1068 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1069 case PIPE_FUNC_EQUAL:
1070 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1071 case PIPE_FUNC_LEQUAL:
1072 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1073 case PIPE_FUNC_GREATER:
1074 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1075 case PIPE_FUNC_NOTEQUAL:
1076 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1077 case PIPE_FUNC_GEQUAL:
1078 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1079 case PIPE_FUNC_ALWAYS:
1080 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1081 }
1082 }