src/gallium/drivers/r600/r600_state_common.c

   1 /*
   2  * Copyright 2010 Red Hat Inc.
   3  *           2010 Jerome Glisse
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie <airlied@redhat.com>
  25  *          Jerome Glisse <jglisse@redhat.com>
  26  */
  27 #include "util/u_blitter.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_format.h"
  30 #include "pipebuffer/pb_buffer.h"
  31 #include "pipe/p_shader_tokens.h"
  32 #include "tgsi/tgsi_parse.h"
  33 #include "r600_formats.h"
  34 #include "r600_pipe.h"
  35 #include "r600d.h"
  36
  37 static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
  38 {
  39         static const int prim_conv[] = {
  40                 V_008958_DI_PT_POINTLIST,
  41                 V_008958_DI_PT_LINELIST,
  42                 V_008958_DI_PT_LINELOOP,
  43                 V_008958_DI_PT_LINESTRIP,
  44                 V_008958_DI_PT_TRILIST,
  45                 V_008958_DI_PT_TRISTRIP,
  46                 V_008958_DI_PT_TRIFAN,
  47                 V_008958_DI_PT_QUADLIST,
  48                 V_008958_DI_PT_QUADSTRIP,
  49                 V_008958_DI_PT_POLYGON,
  50                 -1,
  51                 -1,
  52                 -1,
  53                 -1
  54         };
  55
  56         *prim = prim_conv[pprim];
  57         if (*prim == -1) {
  58                 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim);
  59                 return false;
  60         }
  61         return true;
  62 }
  63
  64 /* common state between evergreen and r600 */
  65 void r600_bind_blend_state(struct pipe_context *ctx, void *state)
  66 {
  67         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
  68         struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
  69         struct r600_pipe_state *rstate;
  70
  71         if (state == NULL)
  72                 return;
  73         rstate = &blend->rstate;
  74         rctx->states[rstate->id] = rstate;
  75         rctx->cb_target_mask = blend->cb_target_mask;
  76         r600_context_pipe_state_set(&rctx->ctx, rstate);
  77 }
  78
  79 void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
  80 {
  81         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
  82         struct r600_pipe_dsa *dsa = state;
  83         struct r600_pipe_state *rstate;
  84
  85         if (state == NULL)
  86                 return;
  87         rstate = &dsa->rstate;
  88         rctx->states[rstate->id] = rstate;
  89         rctx->alpha_ref = dsa->alpha_ref;
  90         rctx->alpha_ref_dirty = true;
  91         r600_context_pipe_state_set(&rctx->ctx, rstate);
  92 }
  93
  94 void r600_bind_rs_state(struct pipe_context *ctx, void *state)
  95 {
  96         struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
  97         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
  98
  99         if (state == NULL)
 100                 return;
 101
 102         rctx->clamp_vertex_color = rs->clamp_vertex_color;
 103         rctx->clamp_fragment_color = rs->clamp_fragment_color;
 104
 105         rctx->sprite_coord_enable = rs->sprite_coord_enable;
 106         rctx->two_side = rs->two_side;
 107
 108         rctx->rasterizer = rs;
 109
 110         rctx->states[rs->rstate.id] = &rs->rstate;
 111         r600_context_pipe_state_set(&rctx->ctx, &rs->rstate);
 112
 113         if (rctx->chip_class >= EVERGREEN) {
 114                 evergreen_polygon_offset_update(rctx);
 115         } else {
 116                 r600_polygon_offset_update(rctx);
 117         }
 118 }
 119
 120 void r600_delete_rs_state(struct pipe_context *ctx, void *state)
 121 {
 122         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 123         struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
 124
 125         if (rctx->rasterizer == rs) {
 126                 rctx->rasterizer = NULL;
 127         }
 128         if (rctx->states[rs->rstate.id] == &rs->rstate) {
 129                 rctx->states[rs->rstate.id] = NULL;
 130         }
 131         free(rs);
 132 }
 133
 134 void r600_sampler_view_destroy(struct pipe_context *ctx,
 135                                struct pipe_sampler_view *state)
 136 {
 137         struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
 138
 139         pipe_resource_reference(&state->texture, NULL);
 140         FREE(resource);
 141 }
 142
 143 void r600_delete_state(struct pipe_context *ctx, void *state)
 144 {
 145         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 146         struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
 147
 148         if (rctx->states[rstate->id] == rstate) {
 149                 rctx->states[rstate->id] = NULL;
 150         }
 151         for (int i = 0; i < rstate->nregs; i++) {
 152                 pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL);
 153         }
 154         free(rstate);
 155 }
 156
 157 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
 158 {
 159         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 160         struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 161
 162         rctx->vertex_elements = v;
 163         if (v) {
 164                 u_vbuf_bind_vertex_elements(rctx->vbuf_mgr, state,
 165                                                 v->vmgr_elements);
 166
 167                 rctx->states[v->rstate.id] = &v->rstate;
 168                 r600_context_pipe_state_set(&rctx->ctx, &v->rstate);
 169         }
 170 }
 171
 172 void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
 173 {
 174         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 175         struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 176
 177         if (rctx->states[v->rstate.id] == &v->rstate) {
 178                 rctx->states[v->rstate.id] = NULL;
 179         }
 180         if (rctx->vertex_elements == state)
 181                 rctx->vertex_elements = NULL;
 182
 183         pipe_resource_reference((struct pipe_resource**)&v->fetch_shader, NULL);
 184         u_vbuf_destroy_vertex_elements(rctx->vbuf_mgr, v->vmgr_elements);
 185         FREE(state);
 186 }
 187
 188
 189 void r600_set_index_buffer(struct pipe_context *ctx,
 190                            const struct pipe_index_buffer *ib)
 191 {
 192         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 193
 194         u_vbuf_set_index_buffer(rctx->vbuf_mgr, ib);
 195 }
 196
 197 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
 198                              const struct pipe_vertex_buffer *buffers)
 199 {
 200         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 201         int i;
 202
 203         /* Zero states. */
 204         for (i = 0; i < count; i++) {
 205                 if (!buffers[i].buffer) {
 206                         if (rctx->chip_class >= EVERGREEN) {
 207                                 evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
 208                         } else {
 209                                 r600_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
 210                         }
 211                 }
 212         }
 213         for (; i < rctx->vbuf_mgr->nr_real_vertex_buffers; i++) {
 214                 if (rctx->chip_class >= EVERGREEN) {
 215                         evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
 216                 } else {
 217                         r600_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
 218                 }
 219         }
 220
 221         u_vbuf_set_vertex_buffers(rctx->vbuf_mgr, count, buffers);
 222 }
 223
 224 void *r600_create_vertex_elements(struct pipe_context *ctx,
 225                                   unsigned count,
 226                                   const struct pipe_vertex_element *elements)
 227 {
 228         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 229         struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
 230
 231         assert(count < 32);
 232         if (!v)
 233                 return NULL;
 234
 235         v->count = count;
 236         v->vmgr_elements =
 237                 u_vbuf_create_vertex_elements(rctx->vbuf_mgr, count,
 238                                                   elements, v->elements);
 239
 240         if (r600_vertex_elements_build_fetch_shader(rctx, v)) {
 241                 FREE(v);
 242                 return NULL;
 243         }
 244
 245         return v;
 246 }
 247
 248 void *r600_create_shader_state(struct pipe_context *ctx,
 249                                const struct pipe_shader_state *state)
 250 {
 251         struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader);
 252         int r;
 253
 254         shader->tokens = tgsi_dup_tokens(state->tokens);
 255         shader->so = state->stream_output;
 256
 257         r =  r600_pipe_shader_create(ctx, shader);
 258         if (r) {
 259                 return NULL;
 260         }
 261         return shader;
 262 }
 263
 264 void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
 265 {
 266         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 267
 268         /* TODO delete old shader */
 269         rctx->ps_shader = (struct r600_pipe_shader *)state;
 270         if (state) {
 271                 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_shader->rstate);
 272         }
 273         if (rctx->ps_shader && rctx->vs_shader) {
 274                 r600_adjust_gprs(rctx);
 275         }
 276 }
 277
 278 void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
 279 {
 280         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 281
 282         /* TODO delete old shader */
 283         rctx->vs_shader = (struct r600_pipe_shader *)state;
 284         if (state) {
 285                 r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_shader->rstate);
 286         }
 287         if (rctx->ps_shader && rctx->vs_shader) {
 288                 r600_adjust_gprs(rctx);
 289         }
 290 }
 291
 292 void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
 293 {
 294         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 295         struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
 296
 297         if (rctx->ps_shader == shader) {
 298                 rctx->ps_shader = NULL;
 299         }
 300
 301         free(shader->tokens);
 302         r600_pipe_shader_destroy(ctx, shader);
 303         free(shader);
 304 }
 305
 306 void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
 307 {
 308         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 309         struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
 310
 311         if (rctx->vs_shader == shader) {
 312                 rctx->vs_shader = NULL;
 313         }
 314
 315         free(shader->tokens);
 316         r600_pipe_shader_destroy(ctx, shader);
 317         free(shader);
 318 }
 319
 320 static void r600_update_alpha_ref(struct r600_pipe_context *rctx)
 321 {
 322         unsigned alpha_ref;
 323         struct r600_pipe_state rstate;
 324
 325         alpha_ref = rctx->alpha_ref;
 326         rstate.nregs = 0;
 327         if (rctx->export_16bpc)
 328                 alpha_ref &= ~0x1FFF;
 329         r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL, 0);
 330
 331         r600_context_pipe_state_set(&rctx->ctx, &rstate);
 332         rctx->alpha_ref_dirty = false;
 333 }
 334
 335 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 336                               struct pipe_resource *buffer)
 337 {
 338         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 339         struct r600_resource *rbuffer = r600_resource(buffer);
 340         struct r600_pipe_resource_state *rstate;
 341         uint64_t va_offset;
 342         uint32_t offset;
 343
 344         /* Note that the state tracker can unbind constant buffers by
 345          * passing NULL here.
 346          */
 347         if (buffer == NULL) {
 348                 return;
 349         }
 350
 351         r600_upload_const_buffer(rctx, &rbuffer, &offset);
 352         va_offset = r600_resource_va(ctx->screen, (void*)rbuffer);
 353         va_offset += offset;
 354         va_offset >>= 8;
 355
 356         switch (shader) {
 357         case PIPE_SHADER_VERTEX:
 358                 rctx->vs_const_buffer.nregs = 0;
 359                 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
 360                                         R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
 361                                         ALIGN_DIVUP(buffer->width0 >> 4, 16),
 362                                         0xFFFFFFFF, NULL, 0);
 363                 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
 364                                         R_028980_ALU_CONST_CACHE_VS_0,
 365                                         va_offset, 0xFFFFFFFF, rbuffer, RADEON_USAGE_READ);
 366                 r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_const_buffer);
 367
 368                 rstate = &rctx->vs_const_buffer_resource[index];
 369                 if (!rstate->id) {
 370                         if (rctx->chip_class >= EVERGREEN) {
 371                                 evergreen_pipe_init_buffer_resource(rctx, rstate);
 372                         } else {
 373                                 r600_pipe_init_buffer_resource(rctx, rstate);
 374                         }
 375                 }
 376
 377                 if (rctx->chip_class >= EVERGREEN) {
 378                         evergreen_pipe_mod_buffer_resource(ctx, rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 379                         evergreen_context_pipe_state_set_vs_resource(&rctx->ctx, rstate, index);
 380                 } else {
 381                         r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 382                         r600_context_pipe_state_set_vs_resource(&rctx->ctx, rstate, index);
 383                 }
 384                 break;
 385         case PIPE_SHADER_FRAGMENT:
 386                 rctx->ps_const_buffer.nregs = 0;
 387                 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
 388                                         R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
 389                                         ALIGN_DIVUP(buffer->width0 >> 4, 16),
 390                                         0xFFFFFFFF, NULL, 0);
 391                 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
 392                                         R_028940_ALU_CONST_CACHE_PS_0,
 393                                         va_offset, 0xFFFFFFFF, rbuffer, RADEON_USAGE_READ);
 394                 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_const_buffer);
 395
 396                 rstate = &rctx->ps_const_buffer_resource[index];
 397                 if (!rstate->id) {
 398                         if (rctx->chip_class >= EVERGREEN) {
 399                                 evergreen_pipe_init_buffer_resource(rctx, rstate);
 400                         } else {
 401                                 r600_pipe_init_buffer_resource(rctx, rstate);
 402                         }
 403                 }
 404                 if (rctx->chip_class >= EVERGREEN) {
 405                         evergreen_pipe_mod_buffer_resource(ctx, rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 406                         evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, rstate, index);
 407                 } else {
 408                         r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 409                         r600_context_pipe_state_set_ps_resource(&rctx->ctx, rstate, index);
 410                 }
 411                 break;
 412         default:
 413                 R600_ERR("unsupported %d\n", shader);
 414                 return;
 415         }
 416
 417         if (buffer != &rbuffer->b.b.b)
 418                 pipe_resource_reference((struct pipe_resource**)&rbuffer, NULL);
 419 }
 420
 421 struct pipe_stream_output_target *
 422 r600_create_so_target(struct pipe_context *ctx,
 423                       struct pipe_resource *buffer,
 424                       unsigned buffer_offset,
 425                       unsigned buffer_size)
 426 {
 427         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 428         struct r600_so_target *t;
 429         void *ptr;
 430
 431         t = CALLOC_STRUCT(r600_so_target);
 432         if (!t) {
 433                 return NULL;
 434         }
 435
 436         t->b.reference.count = 1;
 437         t->b.context = ctx;
 438         pipe_resource_reference(&t->b.buffer, buffer);
 439         t->b.buffer_offset = buffer_offset;
 440         t->b.buffer_size = buffer_size;
 441
 442         t->filled_size = (struct r600_resource*)
 443                 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4);
 444         ptr = rctx->ws->buffer_map(t->filled_size->buf, rctx->ctx.cs, PIPE_TRANSFER_WRITE);
 445         memset(ptr, 0, t->filled_size->buf->size);
 446         rctx->ws->buffer_unmap(t->filled_size->buf);
 447
 448         return &t->b;
 449 }
 450
 451 void r600_so_target_destroy(struct pipe_context *ctx,
 452                             struct pipe_stream_output_target *target)
 453 {
 454         struct r600_so_target *t = (struct r600_so_target*)target;
 455         pipe_resource_reference(&t->b.buffer, NULL);
 456         pipe_resource_reference((struct pipe_resource**)&t->filled_size, NULL);
 457         FREE(t);
 458 }
 459
 460 void r600_set_so_targets(struct pipe_context *ctx,
 461                          unsigned num_targets,
 462                          struct pipe_stream_output_target **targets,
 463                          unsigned append_bitmask)
 464 {
 465         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 466         unsigned i;
 467
 468         /* Stop streamout. */
 469         if (rctx->ctx.num_so_targets) {
 470                 r600_context_streamout_end(&rctx->ctx);
 471         }
 472
 473         /* Set the new targets. */
 474         for (i = 0; i < num_targets; i++) {
 475                 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->ctx.so_targets[i], targets[i]);
 476         }
 477         for (; i < rctx->ctx.num_so_targets; i++) {
 478                 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->ctx.so_targets[i], NULL);
 479         }
 480
 481         rctx->ctx.num_so_targets = num_targets;
 482         rctx->ctx.streamout_start = num_targets != 0;
 483         rctx->ctx.streamout_append_bitmask = append_bitmask;
 484 }
 485
 486 static void r600_vertex_buffer_update(struct r600_pipe_context *rctx)
 487 {
 488         struct r600_pipe_resource_state *rstate;
 489         struct r600_resource *rbuffer;
 490         struct pipe_vertex_buffer *vertex_buffer;
 491         unsigned i, count, offset;
 492
 493         if (rctx->vertex_elements->vbuffer_need_offset) {
 494                 /* one resource per vertex elements */
 495                 count = rctx->vertex_elements->count;
 496         } else {
 497                 /* bind vertex buffer once */
 498                 count = rctx->vbuf_mgr->nr_real_vertex_buffers;
 499         }
 500
 501         for (i = 0 ; i < count; i++) {
 502                 rstate = &rctx->fs_resource[i];
 503
 504                 if (rctx->vertex_elements->vbuffer_need_offset) {
 505                         /* one resource per vertex elements */
 506                         unsigned vbuffer_index;
 507                         vbuffer_index = rctx->vertex_elements->elements[i].vertex_buffer_index;
 508                         vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[vbuffer_index];
 509                         rbuffer = (struct r600_resource*)vertex_buffer->buffer;
 510                         offset = rctx->vertex_elements->vbuffer_offset[i];
 511                 } else {
 512                         /* bind vertex buffer once */
 513                         vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[i];
 514                         rbuffer = (struct r600_resource*)vertex_buffer->buffer;
 515                         offset = 0;
 516                 }
 517                 if (vertex_buffer == NULL || rbuffer == NULL)
 518                         continue;
 519                 offset += vertex_buffer->buffer_offset;
 520
 521                 if (!rstate->id) {
 522                         if (rctx->chip_class >= EVERGREEN) {
 523                                 evergreen_pipe_init_buffer_resource(rctx, rstate);
 524                         } else {
 525                                 r600_pipe_init_buffer_resource(rctx, rstate);
 526                         }
 527                 }
 528
 529                 if (rctx->chip_class >= EVERGREEN) {
 530                         evergreen_pipe_mod_buffer_resource(&rctx->context, rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ);
 531                         evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, rstate, i);
 532                 } else {
 533                         r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ);
 534                         r600_context_pipe_state_set_fs_resource(&rctx->ctx, rstate, i);
 535                 }
 536         }
 537 }
 538
 539 static int r600_shader_rebuild(struct pipe_context * ctx, struct r600_pipe_shader * shader)
 540 {
 541         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 542         int r;
 543
 544         r600_pipe_shader_destroy(ctx, shader);
 545         r = r600_pipe_shader_create(ctx, shader);
 546         if (r) {
 547                 return r;
 548         }
 549         r600_context_pipe_state_set(&rctx->ctx, &shader->rstate);
 550
 551         return 0;
 552 }
 553
 554 static void r600_update_derived_state(struct r600_pipe_context *rctx)
 555 {
 556         struct pipe_context * ctx = (struct pipe_context*)rctx;
 557         struct r600_pipe_state rstate;
 558         unsigned user_clip_plane_enable;
 559         unsigned clip_dist_enable;
 560
 561         if (rctx->vs_shader->shader.clip_dist_write || rctx->vs_shader->shader.vs_prohibit_ucps)
 562                 user_clip_plane_enable = 0;
 563         else
 564                 user_clip_plane_enable = rctx->rasterizer->clip_plane_enable & 0x3F;
 565
 566         clip_dist_enable = rctx->rasterizer->clip_plane_enable & rctx->vs_shader->shader.clip_dist_write & 0xFF;
 567         rstate.nregs = 0;
 568
 569         if (user_clip_plane_enable != rctx->user_clip_plane_enable) {
 570                 r600_pipe_state_add_reg(&rstate, R_028810_PA_CL_CLIP_CNTL, user_clip_plane_enable , 0x3F, NULL, 0);
 571                 rctx->user_clip_plane_enable = user_clip_plane_enable;
 572         }
 573
 574         if (clip_dist_enable != rctx->clip_dist_enable) {
 575                 r600_pipe_state_add_reg(&rstate, R_02881C_PA_CL_VS_OUT_CNTL, clip_dist_enable, 0xFF, NULL, 0);
 576                 rctx->clip_dist_enable = clip_dist_enable;
 577         }
 578
 579         if (rstate.nregs)
 580                 r600_context_pipe_state_set(&rctx->ctx, &rstate);
 581
 582         if (!rctx->blitter->running) {
 583                 if (rctx->have_depth_fb || rctx->have_depth_texture)
 584                         r600_flush_depth_textures(rctx);
 585         }
 586
 587         if (rctx->chip_class < EVERGREEN) {
 588                 r600_update_sampler_states(rctx);
 589         }
 590
 591         if (rctx->vs_shader->shader.clamp_color != rctx->clamp_vertex_color) {
 592                 r600_shader_rebuild(&rctx->context, rctx->vs_shader);
 593         }
 594
 595         if ((rctx->ps_shader->shader.clamp_color != rctx->clamp_fragment_color) ||
 596             (rctx->ps_shader->shader.two_side != rctx->two_side) ||
 597             ((rctx->chip_class >= EVERGREEN) && rctx->ps_shader->shader.fs_write_all &&
 598              (rctx->ps_shader->shader.nr_cbufs != rctx->nr_cbufs))) {
 599                 r600_shader_rebuild(&rctx->context, rctx->ps_shader);
 600         }
 601
 602         if (rctx->alpha_ref_dirty) {
 603                 r600_update_alpha_ref(rctx);
 604         }
 605
 606         if (rctx->ps_shader && rctx->sprite_coord_enable &&
 607                 (rctx->ps_shader->sprite_coord_enable != rctx->sprite_coord_enable)) {
 608
 609                 if (rctx->chip_class >= EVERGREEN)
 610                         evergreen_pipe_shader_ps(ctx, rctx->ps_shader);
 611                 else
 612                         r600_pipe_shader_ps(ctx, rctx->ps_shader);
 613
 614                 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_shader->rstate);
 615         }
 616
 617 }
 618
 619 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
 620 {
 621         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 622         struct pipe_draw_info info = *dinfo;
 623         struct r600_draw rdraw = {};
 624         struct pipe_index_buffer ib = {};
 625         unsigned prim, mask, ls_mask = 0;
 626
 627         if ((!info.count && (info.indexed || !info.count_from_stream_output)) ||
 628             (info.indexed && !rctx->vbuf_mgr->index_buffer.buffer) ||
 629             !r600_conv_pipe_prim(info.mode, &prim)) {
 630                 return;
 631         }
 632
 633         if (!rctx->ps_shader || !rctx->vs_shader)
 634                 return;
 635
 636         r600_update_derived_state(rctx);
 637
 638         u_vbuf_draw_begin(rctx->vbuf_mgr, &info);
 639         r600_vertex_buffer_update(rctx);
 640
 641         rdraw.vgt_num_indices = info.count;
 642         rdraw.vgt_num_instances = info.instance_count;
 643
 644         if (info.indexed) {
 645                 /* Initialize the index buffer struct. */
 646                 pipe_resource_reference(&ib.buffer, rctx->vbuf_mgr->index_buffer.buffer);
 647                 ib.index_size = rctx->vbuf_mgr->index_buffer.index_size;
 648                 ib.offset = rctx->vbuf_mgr->index_buffer.offset + info.start * ib.index_size;
 649
 650                 /* Translate or upload, if needed. */
 651                 r600_translate_index_buffer(rctx, &ib, info.count);
 652
 653                 if (u_vbuf_resource(ib.buffer)->user_ptr) {
 654                         r600_upload_index_buffer(rctx, &ib, info.count);
 655                 }
 656
 657                 /* Initialize the r600_draw struct with index buffer info. */
 658                 if (ib.index_size == 4) {
 659                         rdraw.vgt_index_type = VGT_INDEX_32 |
 660                                 (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0);
 661                 } else {
 662                         rdraw.vgt_index_type = VGT_INDEX_16 |
 663                                 (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0);
 664                 }
 665                 rdraw.indices = (struct r600_resource*)ib.buffer;
 666                 rdraw.indices_bo_offset = ib.offset;
 667                 rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_DMA;
 668         } else {
 669                 info.index_bias = info.start;
 670                 rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_AUTO_INDEX;
 671                 if (info.count_from_stream_output) {
 672                         rdraw.vgt_draw_initiator |= S_0287F0_USE_OPAQUE(1);
 673
 674                         r600_context_draw_opaque_count(&rctx->ctx, (struct r600_so_target*)info.count_from_stream_output);
 675                 }
 676         }
 677
 678         rctx->ctx.vs_so_stride_in_dw = rctx->vs_shader->so.stride;
 679
 680         mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
 681
 682         if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
 683                 rctx->vgt.id = R600_PIPE_STATE_VGT;
 684                 rctx->vgt.nregs = 0;
 685                 r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL, 0);
 686                 r600_pipe_state_add_reg(&rctx->vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL, 0);
 687                 r600_pipe_state_add_reg(&rctx->vgt, R_028400_VGT_MAX_VTX_INDX, ~0, 0xFFFFFFFF, NULL, 0);
 688                 r600_pipe_state_add_reg(&rctx->vgt, R_028404_VGT_MIN_VTX_INDX, 0, 0xFFFFFFFF, NULL, 0);
 689                 r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias, 0xFFFFFFFF, NULL, 0);
 690                 r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index, 0xFFFFFFFF, NULL, 0);
 691                 r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart, 0xFFFFFFFF, NULL, 0);
 692                 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0xFFFFFFFF, NULL, 0);
 693                 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance, 0xFFFFFFFF, NULL, 0);
 694                 r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE,
 695                                         0,
 696                                         S_028A0C_AUTO_RESET_CNTL(3), NULL, 0);
 697                 r600_pipe_state_add_reg(&rctx->vgt, R_028814_PA_SU_SC_MODE_CNTL,
 698                                         0,
 699                                         S_028814_PROVOKING_VTX_LAST(1), NULL, 0);
 700         }
 701
 702         rctx->vgt.nregs = 0;
 703         r600_pipe_state_mod_reg(&rctx->vgt, prim);
 704         r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_target_mask & mask);
 705         r600_pipe_state_mod_reg(&rctx->vgt, ~0);
 706         r600_pipe_state_mod_reg(&rctx->vgt, 0);
 707         r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
 708         r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
 709         r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart);
 710         r600_pipe_state_mod_reg(&rctx->vgt, 0);
 711         r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance);
 712
 713         if (prim == V_008958_DI_PT_LINELIST)
 714                 ls_mask = 1;
 715         else if (prim == V_008958_DI_PT_LINESTRIP)
 716                 ls_mask = 2;
 717         r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask));
 718
 719         if (info.mode == PIPE_PRIM_QUADS || info.mode == PIPE_PRIM_QUAD_STRIP || info.mode == PIPE_PRIM_POLYGON) {
 720                 r600_pipe_state_mod_reg(&rctx->vgt, S_028814_PROVOKING_VTX_LAST(1));
 721         }
 722
 723         r600_context_pipe_state_set(&rctx->ctx, &rctx->vgt);
 724
 725         if (rctx->chip_class >= EVERGREEN) {
 726                 evergreen_context_draw(&rctx->ctx, &rdraw);
 727         } else {
 728                 r600_context_draw(&rctx->ctx, &rdraw);
 729         }
 730
 731         if (rctx->framebuffer.zsbuf)
 732         {
 733                 struct pipe_resource *tex = rctx->framebuffer.zsbuf->texture;
 734                 ((struct r600_resource_texture *)tex)->dirty_db = TRUE;
 735         }
 736
 737         pipe_resource_reference(&ib.buffer, NULL);
 738         u_vbuf_draw_end(rctx->vbuf_mgr);
 739 }
 740
 741 void _r600_pipe_state_add_reg(struct r600_context *ctx,
 742                               struct r600_pipe_state *state,
 743                               u32 offset, u32 value, u32 mask,
 744                               u32 range_id, u32 block_id,
 745                               struct r600_resource *bo,
 746                               enum radeon_bo_usage usage)
 747 {
 748         struct r600_range *range;
 749         struct r600_block *block;
 750
 751         if (bo) assert(usage);
 752
 753         range = &ctx->range[range_id];
 754         block = range->blocks[block_id];
 755         state->regs[state->nregs].block = block;
 756         state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
 757
 758         state->regs[state->nregs].value = value;
 759         state->regs[state->nregs].mask = mask;
 760         state->regs[state->nregs].bo = bo;
 761         state->regs[state->nregs].bo_usage = usage;
 762
 763         state->nregs++;
 764         assert(state->nregs < R600_BLOCK_MAX_REG);
 765 }
 766
 767 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
 768                                      u32 offset, u32 value, u32 mask,
 769                                      struct r600_resource *bo,
 770                                      enum radeon_bo_usage usage)
 771 {
 772         if (bo) assert(usage);
 773
 774         state->regs[state->nregs].id = offset;
 775         state->regs[state->nregs].block = NULL;
 776         state->regs[state->nregs].value = value;
 777         state->regs[state->nregs].mask = mask;
 778         state->regs[state->nregs].bo = bo;
 779         state->regs[state->nregs].bo_usage = usage;
 780
 781         state->nregs++;
 782         assert(state->nregs < R600_BLOCK_MAX_REG);
 783 }