src/gallium/drivers/r600/r600_state_common.c

   1 /*
   2  * Copyright 2010 Red Hat Inc.
   3  *           2010 Jerome Glisse
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie <airlied@redhat.com>
  25  *          Jerome Glisse <jglisse@redhat.com>
  26  */
  27 #include "util/u_blitter.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_format.h"
  30 #include "pipebuffer/pb_buffer.h"
  31 #include "pipe/p_shader_tokens.h"
  32 #include "tgsi/tgsi_parse.h"
  33 #include "r600_formats.h"
  34 #include "r600_pipe.h"
  35 #include "r600d.h"
  36
  37 static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
  38 {
  39         static const int prim_conv[] = {
  40                 V_008958_DI_PT_POINTLIST,
  41                 V_008958_DI_PT_LINELIST,
  42                 V_008958_DI_PT_LINELOOP,
  43                 V_008958_DI_PT_LINESTRIP,
  44                 V_008958_DI_PT_TRILIST,
  45                 V_008958_DI_PT_TRISTRIP,
  46                 V_008958_DI_PT_TRIFAN,
  47                 V_008958_DI_PT_QUADLIST,
  48                 V_008958_DI_PT_QUADSTRIP,
  49                 V_008958_DI_PT_POLYGON,
  50                 -1,
  51                 -1,
  52                 -1,
  53                 -1
  54         };
  55
  56         *prim = prim_conv[pprim];
  57         if (*prim == -1) {
  58                 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim);
  59                 return false;
  60         }
  61         return true;
  62 }
  63
  64 /* common state between evergreen and r600 */
  65 void r600_bind_blend_state(struct pipe_context *ctx, void *state)
  66 {
  67         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
  68         struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
  69         struct r600_pipe_state *rstate;
  70
  71         if (state == NULL)
  72                 return;
  73         rstate = &blend->rstate;
  74         rctx->states[rstate->id] = rstate;
  75         rctx->cb_target_mask = blend->cb_target_mask;
  76
  77         /* Replace every bit except MULTIWRITE_ENABLE. */
  78         rctx->cb_color_control &= ~C_028808_MULTIWRITE_ENABLE;
  79         rctx->cb_color_control |= blend->cb_color_control & C_028808_MULTIWRITE_ENABLE;
  80
  81         r600_context_pipe_state_set(&rctx->ctx, rstate);
  82 }
  83
  84 static void r600_set_stencil_ref(struct pipe_context *ctx,
  85                                  const struct r600_stencil_ref *state)
  86 {
  87         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
  88         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
  89
  90         if (rstate == NULL)
  91                 return;
  92
  93         rstate->id = R600_PIPE_STATE_STENCIL_REF;
  94         r600_pipe_state_add_reg(rstate,
  95                                 R_028430_DB_STENCILREFMASK,
  96                                 S_028430_STENCILREF(state->ref_value[0]) |
  97                                 S_028430_STENCILMASK(state->valuemask[0]) |
  98                                 S_028430_STENCILWRITEMASK(state->writemask[0]),
  99                                 0xFFFFFFFF, NULL, 0);
 100         r600_pipe_state_add_reg(rstate,
 101                                 R_028434_DB_STENCILREFMASK_BF,
 102                                 S_028434_STENCILREF_BF(state->ref_value[1]) |
 103                                 S_028434_STENCILMASK_BF(state->valuemask[1]) |
 104                                 S_028434_STENCILWRITEMASK_BF(state->writemask[1]),
 105                                 0xFFFFFFFF, NULL, 0);
 106
 107         free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
 108         rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
 109         r600_context_pipe_state_set(&rctx->ctx, rstate);
 110 }
 111
 112 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
 113                                const struct pipe_stencil_ref *state)
 114 {
 115         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 116         struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA];
 117         struct r600_stencil_ref ref;
 118
 119         rctx->stencil_ref = *state;
 120
 121         if (!dsa)
 122                 return;
 123
 124         ref.ref_value[0] = state->ref_value[0];
 125         ref.ref_value[1] = state->ref_value[1];
 126         ref.valuemask[0] = dsa->valuemask[0];
 127         ref.valuemask[1] = dsa->valuemask[1];
 128         ref.writemask[0] = dsa->writemask[0];
 129         ref.writemask[1] = dsa->writemask[1];
 130
 131         r600_set_stencil_ref(ctx, &ref);
 132 }
 133
 134 void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
 135 {
 136         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 137         struct r600_pipe_dsa *dsa = state;
 138         struct r600_pipe_state *rstate;
 139         struct r600_stencil_ref ref;
 140
 141         if (state == NULL)
 142                 return;
 143         rstate = &dsa->rstate;
 144         rctx->states[rstate->id] = rstate;
 145         rctx->alpha_ref = dsa->alpha_ref;
 146         rctx->alpha_ref_dirty = true;
 147         r600_context_pipe_state_set(&rctx->ctx, rstate);
 148
 149         ref.ref_value[0] = rctx->stencil_ref.ref_value[0];
 150         ref.ref_value[1] = rctx->stencil_ref.ref_value[1];
 151         ref.valuemask[0] = dsa->valuemask[0];
 152         ref.valuemask[1] = dsa->valuemask[1];
 153         ref.writemask[0] = dsa->writemask[0];
 154         ref.writemask[1] = dsa->writemask[1];
 155
 156         r600_set_stencil_ref(ctx, &ref);
 157 }
 158
 159 void r600_bind_rs_state(struct pipe_context *ctx, void *state)
 160 {
 161         struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
 162         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 163
 164         if (state == NULL)
 165                 return;
 166
 167         rctx->sprite_coord_enable = rs->sprite_coord_enable;
 168         rctx->two_side = rs->two_side;
 169         rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
 170         rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
 171
 172         rctx->rasterizer = rs;
 173
 174         rctx->states[rs->rstate.id] = &rs->rstate;
 175         r600_context_pipe_state_set(&rctx->ctx, &rs->rstate);
 176
 177         if (rctx->chip_class >= EVERGREEN) {
 178                 evergreen_polygon_offset_update(rctx);
 179         } else {
 180                 r600_polygon_offset_update(rctx);
 181         }
 182 }
 183
 184 void r600_delete_rs_state(struct pipe_context *ctx, void *state)
 185 {
 186         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 187         struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
 188
 189         if (rctx->rasterizer == rs) {
 190                 rctx->rasterizer = NULL;
 191         }
 192         if (rctx->states[rs->rstate.id] == &rs->rstate) {
 193                 rctx->states[rs->rstate.id] = NULL;
 194         }
 195         free(rs);
 196 }
 197
 198 void r600_sampler_view_destroy(struct pipe_context *ctx,
 199                                struct pipe_sampler_view *state)
 200 {
 201         struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
 202
 203         pipe_resource_reference(&state->texture, NULL);
 204         FREE(resource);
 205 }
 206
 207 void r600_delete_state(struct pipe_context *ctx, void *state)
 208 {
 209         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 210         struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
 211
 212         if (rctx->states[rstate->id] == rstate) {
 213                 rctx->states[rstate->id] = NULL;
 214         }
 215         for (int i = 0; i < rstate->nregs; i++) {
 216                 pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL);
 217         }
 218         free(rstate);
 219 }
 220
 221 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
 222 {
 223         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 224         struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 225
 226         rctx->vertex_elements = v;
 227         if (v) {
 228                 u_vbuf_bind_vertex_elements(rctx->vbuf_mgr, state,
 229                                                 v->vmgr_elements);
 230
 231                 rctx->states[v->rstate.id] = &v->rstate;
 232                 r600_context_pipe_state_set(&rctx->ctx, &v->rstate);
 233         }
 234 }
 235
 236 void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
 237 {
 238         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 239         struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 240
 241         if (rctx->states[v->rstate.id] == &v->rstate) {
 242                 rctx->states[v->rstate.id] = NULL;
 243         }
 244         if (rctx->vertex_elements == state)
 245                 rctx->vertex_elements = NULL;
 246
 247         pipe_resource_reference((struct pipe_resource**)&v->fetch_shader, NULL);
 248         u_vbuf_destroy_vertex_elements(rctx->vbuf_mgr, v->vmgr_elements);
 249         FREE(state);
 250 }
 251
 252
 253 void r600_set_index_buffer(struct pipe_context *ctx,
 254                            const struct pipe_index_buffer *ib)
 255 {
 256         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 257
 258         u_vbuf_set_index_buffer(rctx->vbuf_mgr, ib);
 259 }
 260
 261 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
 262                              const struct pipe_vertex_buffer *buffers)
 263 {
 264         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 265         int i;
 266
 267         /* Zero states. */
 268         for (i = 0; i < count; i++) {
 269                 if (!buffers[i].buffer) {
 270                         if (rctx->chip_class >= EVERGREEN) {
 271                                 evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
 272                         } else {
 273                                 r600_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
 274                         }
 275                 }
 276         }
 277         for (; i < rctx->vbuf_mgr->nr_real_vertex_buffers; i++) {
 278                 if (rctx->chip_class >= EVERGREEN) {
 279                         evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
 280                 } else {
 281                         r600_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
 282                 }
 283         }
 284
 285         u_vbuf_set_vertex_buffers(rctx->vbuf_mgr, count, buffers);
 286 }
 287
 288 void *r600_create_vertex_elements(struct pipe_context *ctx,
 289                                   unsigned count,
 290                                   const struct pipe_vertex_element *elements)
 291 {
 292         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 293         struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
 294
 295         assert(count < 32);
 296         if (!v)
 297                 return NULL;
 298
 299         v->count = count;
 300         v->vmgr_elements =
 301                 u_vbuf_create_vertex_elements(rctx->vbuf_mgr, count,
 302                                                   elements, v->elements);
 303
 304         if (r600_vertex_elements_build_fetch_shader(rctx, v)) {
 305                 FREE(v);
 306                 return NULL;
 307         }
 308
 309         return v;
 310 }
 311
 312 void *r600_create_shader_state(struct pipe_context *ctx,
 313                                const struct pipe_shader_state *state)
 314 {
 315         struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader);
 316         int r;
 317
 318         shader->tokens = tgsi_dup_tokens(state->tokens);
 319         shader->so = state->stream_output;
 320
 321         r =  r600_pipe_shader_create(ctx, shader);
 322         if (r) {
 323                 return NULL;
 324         }
 325         return shader;
 326 }
 327
 328 void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
 329 {
 330         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 331
 332         /* TODO delete old shader */
 333         rctx->ps_shader = (struct r600_pipe_shader *)state;
 334         if (state) {
 335                 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_shader->rstate);
 336
 337                 rctx->cb_color_control &= C_028808_MULTIWRITE_ENABLE;
 338                 rctx->cb_color_control |= S_028808_MULTIWRITE_ENABLE(!!rctx->ps_shader->shader.fs_write_all);
 339         }
 340         if (rctx->ps_shader && rctx->vs_shader) {
 341                 r600_adjust_gprs(rctx);
 342         }
 343 }
 344
 345 void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
 346 {
 347         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 348
 349         /* TODO delete old shader */
 350         rctx->vs_shader = (struct r600_pipe_shader *)state;
 351         if (state) {
 352                 r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_shader->rstate);
 353         }
 354         if (rctx->ps_shader && rctx->vs_shader) {
 355                 r600_adjust_gprs(rctx);
 356         }
 357 }
 358
 359 void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
 360 {
 361         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 362         struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
 363
 364         if (rctx->ps_shader == shader) {
 365                 rctx->ps_shader = NULL;
 366         }
 367
 368         free(shader->tokens);
 369         r600_pipe_shader_destroy(ctx, shader);
 370         free(shader);
 371 }
 372
 373 void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
 374 {
 375         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 376         struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
 377
 378         if (rctx->vs_shader == shader) {
 379                 rctx->vs_shader = NULL;
 380         }
 381
 382         free(shader->tokens);
 383         r600_pipe_shader_destroy(ctx, shader);
 384         free(shader);
 385 }
 386
 387 static void r600_update_alpha_ref(struct r600_pipe_context *rctx)
 388 {
 389         unsigned alpha_ref;
 390         struct r600_pipe_state rstate;
 391
 392         alpha_ref = rctx->alpha_ref;
 393         rstate.nregs = 0;
 394         if (rctx->export_16bpc)
 395                 alpha_ref &= ~0x1FFF;
 396         r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL, 0);
 397
 398         r600_context_pipe_state_set(&rctx->ctx, &rstate);
 399         rctx->alpha_ref_dirty = false;
 400 }
 401
 402 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 403                               struct pipe_resource *buffer)
 404 {
 405         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 406         struct r600_resource *rbuffer = r600_resource(buffer);
 407         struct r600_pipe_resource_state *rstate;
 408         uint64_t va_offset;
 409         uint32_t offset;
 410
 411         /* Note that the state tracker can unbind constant buffers by
 412          * passing NULL here.
 413          */
 414         if (buffer == NULL) {
 415                 return;
 416         }
 417
 418         r600_upload_const_buffer(rctx, &rbuffer, &offset);
 419         va_offset = r600_resource_va(ctx->screen, (void*)rbuffer);
 420         va_offset += offset;
 421         va_offset >>= 8;
 422
 423         switch (shader) {
 424         case PIPE_SHADER_VERTEX:
 425                 rctx->vs_const_buffer.nregs = 0;
 426                 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
 427                                         R_028180_ALU_CONST_BUFFER_SIZE_VS_0 + index * 4,
 428                                         ALIGN_DIVUP(buffer->width0 >> 4, 16),
 429                                         0xFFFFFFFF, NULL, 0);
 430                 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
 431                                         R_028980_ALU_CONST_CACHE_VS_0 + index * 4,
 432                                         va_offset, 0xFFFFFFFF, rbuffer, RADEON_USAGE_READ);
 433                 r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_const_buffer);
 434
 435                 rstate = &rctx->vs_const_buffer_resource[index];
 436                 if (!rstate->id) {
 437                         if (rctx->chip_class >= EVERGREEN) {
 438                                 evergreen_pipe_init_buffer_resource(rctx, rstate);
 439                         } else {
 440                                 r600_pipe_init_buffer_resource(rctx, rstate);
 441                         }
 442                 }
 443
 444                 if (rctx->chip_class >= EVERGREEN) {
 445                         evergreen_pipe_mod_buffer_resource(ctx, rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 446                         evergreen_context_pipe_state_set_vs_resource(&rctx->ctx, rstate, index);
 447                 } else {
 448                         r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 449                         r600_context_pipe_state_set_vs_resource(&rctx->ctx, rstate, index);
 450                 }
 451                 break;
 452         case PIPE_SHADER_FRAGMENT:
 453                 rctx->ps_const_buffer.nregs = 0;
 454                 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
 455                                         R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
 456                                         ALIGN_DIVUP(buffer->width0 >> 4, 16),
 457                                         0xFFFFFFFF, NULL, 0);
 458                 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
 459                                         R_028940_ALU_CONST_CACHE_PS_0,
 460                                         va_offset, 0xFFFFFFFF, rbuffer, RADEON_USAGE_READ);
 461                 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_const_buffer);
 462
 463                 rstate = &rctx->ps_const_buffer_resource[index];
 464                 if (!rstate->id) {
 465                         if (rctx->chip_class >= EVERGREEN) {
 466                                 evergreen_pipe_init_buffer_resource(rctx, rstate);
 467                         } else {
 468                                 r600_pipe_init_buffer_resource(rctx, rstate);
 469                         }
 470                 }
 471                 if (rctx->chip_class >= EVERGREEN) {
 472                         evergreen_pipe_mod_buffer_resource(ctx, rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 473                         evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, rstate, index);
 474                 } else {
 475                         r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 476                         r600_context_pipe_state_set_ps_resource(&rctx->ctx, rstate, index);
 477                 }
 478                 break;
 479         default:
 480                 R600_ERR("unsupported %d\n", shader);
 481                 return;
 482         }
 483
 484         if (buffer != &rbuffer->b.b.b)
 485                 pipe_resource_reference((struct pipe_resource**)&rbuffer, NULL);
 486 }
 487
 488 struct pipe_stream_output_target *
 489 r600_create_so_target(struct pipe_context *ctx,
 490                       struct pipe_resource *buffer,
 491                       unsigned buffer_offset,
 492                       unsigned buffer_size)
 493 {
 494         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 495         struct r600_so_target *t;
 496         void *ptr;
 497
 498         t = CALLOC_STRUCT(r600_so_target);
 499         if (!t) {
 500                 return NULL;
 501         }
 502
 503         t->b.reference.count = 1;
 504         t->b.context = ctx;
 505         pipe_resource_reference(&t->b.buffer, buffer);
 506         t->b.buffer_offset = buffer_offset;
 507         t->b.buffer_size = buffer_size;
 508
 509         t->filled_size = (struct r600_resource*)
 510                 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4);
 511         ptr = rctx->ws->buffer_map(t->filled_size->buf, rctx->ctx.cs, PIPE_TRANSFER_WRITE);
 512         memset(ptr, 0, t->filled_size->buf->size);
 513         rctx->ws->buffer_unmap(t->filled_size->buf);
 514
 515         return &t->b;
 516 }
 517
 518 void r600_so_target_destroy(struct pipe_context *ctx,
 519                             struct pipe_stream_output_target *target)
 520 {
 521         struct r600_so_target *t = (struct r600_so_target*)target;
 522         pipe_resource_reference(&t->b.buffer, NULL);
 523         pipe_resource_reference((struct pipe_resource**)&t->filled_size, NULL);
 524         FREE(t);
 525 }
 526
 527 void r600_set_so_targets(struct pipe_context *ctx,
 528                          unsigned num_targets,
 529                          struct pipe_stream_output_target **targets,
 530                          unsigned append_bitmask)
 531 {
 532         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 533         unsigned i;
 534
 535         /* Stop streamout. */
 536         if (rctx->ctx.num_so_targets) {
 537                 r600_context_streamout_end(&rctx->ctx);
 538         }
 539
 540         /* Set the new targets. */
 541         for (i = 0; i < num_targets; i++) {
 542                 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->ctx.so_targets[i], targets[i]);
 543         }
 544         for (; i < rctx->ctx.num_so_targets; i++) {
 545                 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->ctx.so_targets[i], NULL);
 546         }
 547
 548         rctx->ctx.num_so_targets = num_targets;
 549         rctx->ctx.streamout_start = num_targets != 0;
 550         rctx->ctx.streamout_append_bitmask = append_bitmask;
 551 }
 552
 553 static void r600_vertex_buffer_update(struct r600_pipe_context *rctx)
 554 {
 555         struct r600_pipe_resource_state *rstate;
 556         struct r600_resource *rbuffer;
 557         struct pipe_vertex_buffer *vertex_buffer;
 558         unsigned i, count, offset;
 559
 560         if (rctx->vertex_elements->vbuffer_need_offset) {
 561                 /* one resource per vertex elements */
 562                 count = rctx->vertex_elements->count;
 563         } else {
 564                 /* bind vertex buffer once */
 565                 count = rctx->vbuf_mgr->nr_real_vertex_buffers;
 566         }
 567
 568         for (i = 0 ; i < count; i++) {
 569                 rstate = &rctx->fs_resource[i];
 570
 571                 if (rctx->vertex_elements->vbuffer_need_offset) {
 572                         /* one resource per vertex elements */
 573                         unsigned vbuffer_index;
 574                         vbuffer_index = rctx->vertex_elements->elements[i].vertex_buffer_index;
 575                         vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[vbuffer_index];
 576                         rbuffer = (struct r600_resource*)vertex_buffer->buffer;
 577                         offset = rctx->vertex_elements->vbuffer_offset[i];
 578                 } else {
 579                         /* bind vertex buffer once */
 580                         vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[i];
 581                         rbuffer = (struct r600_resource*)vertex_buffer->buffer;
 582                         offset = 0;
 583                 }
 584                 if (vertex_buffer == NULL || rbuffer == NULL)
 585                         continue;
 586                 offset += vertex_buffer->buffer_offset;
 587
 588                 if (!rstate->id) {
 589                         if (rctx->chip_class >= EVERGREEN) {
 590                                 evergreen_pipe_init_buffer_resource(rctx, rstate);
 591                         } else {
 592                                 r600_pipe_init_buffer_resource(rctx, rstate);
 593                         }
 594                 }
 595
 596                 if (rctx->chip_class >= EVERGREEN) {
 597                         evergreen_pipe_mod_buffer_resource(&rctx->context, rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ);
 598                         evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, rstate, i);
 599                 } else {
 600                         r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ);
 601                         r600_context_pipe_state_set_fs_resource(&rctx->ctx, rstate, i);
 602                 }
 603         }
 604 }
 605
 606 static int r600_shader_rebuild(struct pipe_context * ctx, struct r600_pipe_shader * shader)
 607 {
 608         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 609         int r;
 610
 611         r600_pipe_shader_destroy(ctx, shader);
 612         r = r600_pipe_shader_create(ctx, shader);
 613         if (r) {
 614                 return r;
 615         }
 616         r600_context_pipe_state_set(&rctx->ctx, &shader->rstate);
 617
 618         return 0;
 619 }
 620
 621 static void r600_update_derived_state(struct r600_pipe_context *rctx)
 622 {
 623         struct pipe_context * ctx = (struct pipe_context*)rctx;
 624         struct r600_pipe_state rstate;
 625         unsigned user_clip_plane_enable;
 626
 627         if (rctx->vs_shader->shader.clip_dist_write || rctx->vs_shader->shader.vs_prohibit_ucps)
 628                 user_clip_plane_enable = 0;
 629         else
 630                 user_clip_plane_enable = rctx->rasterizer->clip_plane_enable & 0x3F;
 631
 632         rstate.nregs = 0;
 633
 634         if (user_clip_plane_enable != rctx->user_clip_plane_enable) {
 635                 r600_pipe_state_add_reg(&rstate, R_028810_PA_CL_CLIP_CNTL, user_clip_plane_enable , 0x3F, NULL, 0);
 636                 rctx->user_clip_plane_enable = user_clip_plane_enable;
 637         }
 638
 639         if (rstate.nregs)
 640                 r600_context_pipe_state_set(&rctx->ctx, &rstate);
 641
 642         if (!rctx->blitter->running) {
 643                 if (rctx->have_depth_fb || rctx->have_depth_texture)
 644                         r600_flush_depth_textures(rctx);
 645         }
 646
 647         if (rctx->chip_class < EVERGREEN) {
 648                 r600_update_sampler_states(rctx);
 649         }
 650
 651         if ((rctx->ps_shader->shader.two_side != rctx->two_side) ||
 652             ((rctx->chip_class >= EVERGREEN) && rctx->ps_shader->shader.fs_write_all &&
 653              (rctx->ps_shader->shader.nr_cbufs != rctx->nr_cbufs))) {
 654                 r600_shader_rebuild(&rctx->context, rctx->ps_shader);
 655         }
 656
 657         if (rctx->alpha_ref_dirty) {
 658                 r600_update_alpha_ref(rctx);
 659         }
 660
 661         if (rctx->ps_shader && ((rctx->sprite_coord_enable &&
 662                 (rctx->ps_shader->sprite_coord_enable != rctx->sprite_coord_enable)) ||
 663                 (rctx->rasterizer && rctx->rasterizer->flatshade != rctx->ps_shader->flatshade))) {
 664
 665                 if (rctx->chip_class >= EVERGREEN)
 666                         evergreen_pipe_shader_ps(ctx, rctx->ps_shader);
 667                 else
 668                         r600_pipe_shader_ps(ctx, rctx->ps_shader);
 669
 670                 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_shader->rstate);
 671         }
 672
 673 }
 674
 675 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
 676 {
 677         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 678         struct pipe_draw_info info = *dinfo;
 679         struct r600_draw rdraw = {};
 680         struct pipe_index_buffer ib = {};
 681         unsigned prim, mask, ls_mask = 0;
 682
 683         if ((!info.count && (info.indexed || !info.count_from_stream_output)) ||
 684             (info.indexed && !rctx->vbuf_mgr->index_buffer.buffer) ||
 685             !r600_conv_pipe_prim(info.mode, &prim)) {
 686                 return;
 687         }
 688
 689         if (!rctx->ps_shader || !rctx->vs_shader)
 690                 return;
 691
 692         r600_update_derived_state(rctx);
 693
 694         u_vbuf_draw_begin(rctx->vbuf_mgr, &info);
 695         r600_vertex_buffer_update(rctx);
 696
 697         rdraw.vgt_num_indices = info.count;
 698         rdraw.vgt_num_instances = info.instance_count;
 699
 700         if (info.indexed) {
 701                 /* Initialize the index buffer struct. */
 702                 pipe_resource_reference(&ib.buffer, rctx->vbuf_mgr->index_buffer.buffer);
 703                 ib.index_size = rctx->vbuf_mgr->index_buffer.index_size;
 704                 ib.offset = rctx->vbuf_mgr->index_buffer.offset + info.start * ib.index_size;
 705
 706                 /* Translate or upload, if needed. */
 707                 r600_translate_index_buffer(rctx, &ib, info.count);
 708
 709                 if (u_vbuf_resource(ib.buffer)->user_ptr) {
 710                         r600_upload_index_buffer(rctx, &ib, info.count);
 711                 }
 712
 713                 /* Initialize the r600_draw struct with index buffer info. */
 714                 if (ib.index_size == 4) {
 715                         rdraw.vgt_index_type = VGT_INDEX_32 |
 716                                 (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0);
 717                 } else {
 718                         rdraw.vgt_index_type = VGT_INDEX_16 |
 719                                 (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0);
 720                 }
 721                 rdraw.indices = (struct r600_resource*)ib.buffer;
 722                 rdraw.indices_bo_offset = ib.offset;
 723                 rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_DMA;
 724         } else {
 725                 info.index_bias = info.start;
 726                 rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_AUTO_INDEX;
 727                 if (info.count_from_stream_output) {
 728                         rdraw.vgt_draw_initiator |= S_0287F0_USE_OPAQUE(1);
 729
 730                         r600_context_draw_opaque_count(&rctx->ctx, (struct r600_so_target*)info.count_from_stream_output);
 731                 }
 732         }
 733
 734         rctx->ctx.vs_so_stride_in_dw = rctx->vs_shader->so.stride;
 735
 736         mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
 737
 738         if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
 739                 rctx->vgt.id = R600_PIPE_STATE_VGT;
 740                 rctx->vgt.nregs = 0;
 741                 r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL, 0);
 742                 r600_pipe_state_add_reg(&rctx->vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL, 0);
 743                 r600_pipe_state_add_reg(&rctx->vgt, R_028400_VGT_MAX_VTX_INDX, ~0, 0xFFFFFFFF, NULL, 0);
 744                 r600_pipe_state_add_reg(&rctx->vgt, R_028404_VGT_MIN_VTX_INDX, 0, 0xFFFFFFFF, NULL, 0);
 745                 r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias, 0xFFFFFFFF, NULL, 0);
 746                 r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index, 0xFFFFFFFF, NULL, 0);
 747                 r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart, 0xFFFFFFFF, NULL, 0);
 748                 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0xFFFFFFFF, NULL, 0);
 749                 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance, 0xFFFFFFFF, NULL, 0);
 750                 r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0, 0xFFFFFFFF, NULL, 0);
 751                 r600_pipe_state_add_reg(&rctx->vgt, R_028814_PA_SU_SC_MODE_CNTL, 0, 0xFFFFFFFF, NULL, 0);
 752                 if (rctx->chip_class <= R700)
 753                         r600_pipe_state_add_reg(&rctx->vgt, R_028808_CB_COLOR_CONTROL, rctx->cb_color_control, 0xFFFFFFFF, NULL, 0);
 754                 r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0, 0xFFFFFFFF, NULL, 0);
 755         }
 756
 757         rctx->vgt.nregs = 0;
 758         r600_pipe_state_mod_reg(&rctx->vgt, prim);
 759         r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_target_mask & mask);
 760         r600_pipe_state_mod_reg(&rctx->vgt, ~0);
 761         r600_pipe_state_mod_reg(&rctx->vgt, 0);
 762         r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
 763         r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
 764         r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart);
 765         r600_pipe_state_mod_reg(&rctx->vgt, 0);
 766         r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance);
 767
 768         if (prim == V_008958_DI_PT_LINELIST)
 769                 ls_mask = 1;
 770         else if (prim == V_008958_DI_PT_LINESTRIP)
 771                 ls_mask = 2;
 772         r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask) | rctx->pa_sc_line_stipple);
 773
 774         if (info.mode == PIPE_PRIM_QUADS || info.mode == PIPE_PRIM_QUAD_STRIP || info.mode == PIPE_PRIM_POLYGON) {
 775                 r600_pipe_state_mod_reg(&rctx->vgt, S_028814_PROVOKING_VTX_LAST(1) | rctx->pa_su_sc_mode_cntl);
 776         } else {
 777                 r600_pipe_state_mod_reg(&rctx->vgt, rctx->pa_su_sc_mode_cntl);
 778         }
 779         if (rctx->chip_class <= R700)
 780                 r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_color_control);
 781         r600_pipe_state_mod_reg(&rctx->vgt,
 782                                 rctx->vs_shader->pa_cl_vs_out_cntl |
 783                                 (rctx->rasterizer->clip_plane_enable & rctx->vs_shader->shader.clip_dist_write));
 784
 785         r600_context_pipe_state_set(&rctx->ctx, &rctx->vgt);
 786
 787         if (rctx->chip_class >= EVERGREEN) {
 788                 evergreen_context_draw(&rctx->ctx, &rdraw);
 789         } else {
 790                 r600_context_draw(&rctx->ctx, &rdraw);
 791         }
 792
 793         if (rctx->framebuffer.zsbuf)
 794         {
 795                 struct pipe_resource *tex = rctx->framebuffer.zsbuf->texture;
 796                 ((struct r600_resource_texture *)tex)->dirty_db = TRUE;
 797         }
 798
 799         pipe_resource_reference(&ib.buffer, NULL);
 800         u_vbuf_draw_end(rctx->vbuf_mgr);
 801 }
 802
 803 void _r600_pipe_state_add_reg(struct r600_context *ctx,
 804                               struct r600_pipe_state *state,
 805                               u32 offset, u32 value, u32 mask,
 806                               u32 range_id, u32 block_id,
 807                               struct r600_resource *bo,
 808                               enum radeon_bo_usage usage)
 809 {
 810         struct r600_range *range;
 811         struct r600_block *block;
 812
 813         if (bo) assert(usage);
 814
 815         range = &ctx->range[range_id];
 816         block = range->blocks[block_id];
 817         state->regs[state->nregs].block = block;
 818         state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
 819
 820         state->regs[state->nregs].value = value;
 821         state->regs[state->nregs].mask = mask;
 822         state->regs[state->nregs].bo = bo;
 823         state->regs[state->nregs].bo_usage = usage;
 824
 825         state->nregs++;
 826         assert(state->nregs < R600_BLOCK_MAX_REG);
 827 }
 828
 829 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
 830                                      u32 offset, u32 value, u32 mask,
 831                                      struct r600_resource *bo,
 832                                      enum radeon_bo_usage usage)
 833 {
 834         if (bo) assert(usage);
 835
 836         state->regs[state->nregs].id = offset;
 837         state->regs[state->nregs].block = NULL;
 838         state->regs[state->nregs].value = value;
 839         state->regs[state->nregs].mask = mask;
 840         state->regs[state->nregs].bo = bo;
 841         state->regs[state->nregs].bo_usage = usage;
 842
 843         state->nregs++;
 844         assert(state->nregs < R600_BLOCK_MAX_REG);
 845 }