src/gallium/drivers/r600/r600_state_common.c

   1 /*
   2  * Copyright 2010 Red Hat Inc.
   3  *           2010 Jerome Glisse
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie <airlied@redhat.com>
  25  *          Jerome Glisse <jglisse@redhat.com>
  26  */
  27 #include "util/u_blitter.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_format.h"
  30 #include "pipebuffer/pb_buffer.h"
  31 #include "pipe/p_shader_tokens.h"
  32 #include "tgsi/tgsi_parse.h"
  33 #include "r600_formats.h"
  34 #include "r600_pipe.h"
  35 #include "r600d.h"
  36
  37 static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
  38 {
  39         static const int prim_conv[] = {
  40                 V_008958_DI_PT_POINTLIST,
  41                 V_008958_DI_PT_LINELIST,
  42                 V_008958_DI_PT_LINELOOP,
  43                 V_008958_DI_PT_LINESTRIP,
  44                 V_008958_DI_PT_TRILIST,
  45                 V_008958_DI_PT_TRISTRIP,
  46                 V_008958_DI_PT_TRIFAN,
  47                 V_008958_DI_PT_QUADLIST,
  48                 V_008958_DI_PT_QUADSTRIP,
  49                 V_008958_DI_PT_POLYGON,
  50                 -1,
  51                 -1,
  52                 -1,
  53                 -1
  54         };
  55
  56         *prim = prim_conv[pprim];
  57         if (*prim == -1) {
  58                 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim);
  59                 return false;
  60         }
  61         return true;
  62 }
  63
  64 /* common state between evergreen and r600 */
  65 void r600_bind_blend_state(struct pipe_context *ctx, void *state)
  66 {
  67         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
  68         struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
  69         struct r600_pipe_state *rstate;
  70
  71         if (state == NULL)
  72                 return;
  73         rstate = &blend->rstate;
  74         rctx->states[rstate->id] = rstate;
  75         rctx->cb_target_mask = blend->cb_target_mask;
  76         r600_context_pipe_state_set(&rctx->ctx, rstate);
  77 }
  78
  79 void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
  80 {
  81         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
  82         struct r600_pipe_dsa *dsa = state;
  83         struct r600_pipe_state *rstate;
  84
  85         if (state == NULL)
  86                 return;
  87         rstate = &dsa->rstate;
  88         rctx->states[rstate->id] = rstate;
  89         rctx->alpha_ref = dsa->alpha_ref;
  90         rctx->alpha_ref_dirty = true;
  91         r600_context_pipe_state_set(&rctx->ctx, rstate);
  92 }
  93
  94 void r600_bind_rs_state(struct pipe_context *ctx, void *state)
  95 {
  96         struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
  97         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
  98
  99         if (state == NULL)
 100                 return;
 101
 102         rctx->clamp_vertex_color = rs->clamp_vertex_color;
 103         rctx->clamp_fragment_color = rs->clamp_fragment_color;
 104
 105         rctx->sprite_coord_enable = rs->sprite_coord_enable;
 106
 107         rctx->rasterizer = rs;
 108
 109         rctx->states[rs->rstate.id] = &rs->rstate;
 110         r600_context_pipe_state_set(&rctx->ctx, &rs->rstate);
 111
 112         if (rctx->chip_class >= EVERGREEN) {
 113                 evergreen_polygon_offset_update(rctx);
 114         } else {
 115                 r600_polygon_offset_update(rctx);
 116         }
 117 }
 118
 119 void r600_delete_rs_state(struct pipe_context *ctx, void *state)
 120 {
 121         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 122         struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
 123
 124         if (rctx->rasterizer == rs) {
 125                 rctx->rasterizer = NULL;
 126         }
 127         if (rctx->states[rs->rstate.id] == &rs->rstate) {
 128                 rctx->states[rs->rstate.id] = NULL;
 129         }
 130         free(rs);
 131 }
 132
 133 void r600_sampler_view_destroy(struct pipe_context *ctx,
 134                                struct pipe_sampler_view *state)
 135 {
 136         struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
 137
 138         pipe_resource_reference(&state->texture, NULL);
 139         FREE(resource);
 140 }
 141
 142 void r600_delete_state(struct pipe_context *ctx, void *state)
 143 {
 144         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 145         struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
 146
 147         if (rctx->states[rstate->id] == rstate) {
 148                 rctx->states[rstate->id] = NULL;
 149         }
 150         for (int i = 0; i < rstate->nregs; i++) {
 151                 pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL);
 152         }
 153         free(rstate);
 154 }
 155
 156 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
 157 {
 158         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 159         struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 160
 161         rctx->vertex_elements = v;
 162         if (v) {
 163                 u_vbuf_bind_vertex_elements(rctx->vbuf_mgr, state,
 164                                                 v->vmgr_elements);
 165
 166                 rctx->states[v->rstate.id] = &v->rstate;
 167                 r600_context_pipe_state_set(&rctx->ctx, &v->rstate);
 168         }
 169 }
 170
 171 void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
 172 {
 173         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 174         struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 175
 176         if (rctx->states[v->rstate.id] == &v->rstate) {
 177                 rctx->states[v->rstate.id] = NULL;
 178         }
 179         if (rctx->vertex_elements == state)
 180                 rctx->vertex_elements = NULL;
 181
 182         pipe_resource_reference((struct pipe_resource**)&v->fetch_shader, NULL);
 183         u_vbuf_destroy_vertex_elements(rctx->vbuf_mgr, v->vmgr_elements);
 184         FREE(state);
 185 }
 186
 187
 188 void r600_set_index_buffer(struct pipe_context *ctx,
 189                            const struct pipe_index_buffer *ib)
 190 {
 191         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 192
 193         if (ib) {
 194                 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
 195                 memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer));
 196         } else {
 197                 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
 198                 memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer));
 199         }
 200
 201         /* TODO make this more like a state */
 202 }
 203
 204 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
 205                              const struct pipe_vertex_buffer *buffers)
 206 {
 207         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 208         int i;
 209
 210         /* Zero states. */
 211         for (i = 0; i < count; i++) {
 212                 if (!buffers[i].buffer) {
 213                         if (rctx->chip_class >= EVERGREEN) {
 214                                 evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
 215                         } else {
 216                                 r600_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
 217                         }
 218                 }
 219         }
 220         for (; i < rctx->vbuf_mgr->nr_real_vertex_buffers; i++) {
 221                 if (rctx->chip_class >= EVERGREEN) {
 222                         evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
 223                 } else {
 224                         r600_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
 225                 }
 226         }
 227
 228         u_vbuf_set_vertex_buffers(rctx->vbuf_mgr, count, buffers);
 229 }
 230
 231 void *r600_create_vertex_elements(struct pipe_context *ctx,
 232                                   unsigned count,
 233                                   const struct pipe_vertex_element *elements)
 234 {
 235         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 236         struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
 237
 238         assert(count < 32);
 239         if (!v)
 240                 return NULL;
 241
 242         v->count = count;
 243         v->vmgr_elements =
 244                 u_vbuf_create_vertex_elements(rctx->vbuf_mgr, count,
 245                                                   elements, v->elements);
 246
 247         if (r600_vertex_elements_build_fetch_shader(rctx, v)) {
 248                 FREE(v);
 249                 return NULL;
 250         }
 251
 252         return v;
 253 }
 254
 255 void *r600_create_shader_state(struct pipe_context *ctx,
 256                                const struct pipe_shader_state *state)
 257 {
 258         struct r600_pipe_shader *shader =  CALLOC_STRUCT(r600_pipe_shader);
 259         int r;
 260
 261         shader->tokens = tgsi_dup_tokens(state->tokens);
 262
 263         r =  r600_pipe_shader_create(ctx, shader);
 264         if (r) {
 265                 return NULL;
 266         }
 267         return shader;
 268 }
 269
 270 void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
 271 {
 272         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 273
 274         /* TODO delete old shader */
 275         rctx->ps_shader = (struct r600_pipe_shader *)state;
 276         if (state) {
 277                 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_shader->rstate);
 278         }
 279         if (rctx->ps_shader && rctx->vs_shader) {
 280                 r600_adjust_gprs(rctx);
 281         }
 282 }
 283
 284 void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
 285 {
 286         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 287
 288         /* TODO delete old shader */
 289         rctx->vs_shader = (struct r600_pipe_shader *)state;
 290         if (state) {
 291                 r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_shader->rstate);
 292         }
 293         if (rctx->ps_shader && rctx->vs_shader) {
 294                 r600_adjust_gprs(rctx);
 295         }
 296 }
 297
 298 void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
 299 {
 300         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 301         struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
 302
 303         if (rctx->ps_shader == shader) {
 304                 rctx->ps_shader = NULL;
 305         }
 306
 307         free(shader->tokens);
 308         r600_pipe_shader_destroy(ctx, shader);
 309         free(shader);
 310 }
 311
 312 void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
 313 {
 314         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 315         struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
 316
 317         if (rctx->vs_shader == shader) {
 318                 rctx->vs_shader = NULL;
 319         }
 320
 321         free(shader->tokens);
 322         r600_pipe_shader_destroy(ctx, shader);
 323         free(shader);
 324 }
 325
 326 static void r600_update_alpha_ref(struct r600_pipe_context *rctx)
 327 {
 328         unsigned alpha_ref;
 329         struct r600_pipe_state rstate;
 330
 331         alpha_ref = rctx->alpha_ref;
 332         rstate.nregs = 0;
 333         if (rctx->export_16bpc)
 334                 alpha_ref &= ~0x1FFF;
 335         r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL, 0);
 336
 337         r600_context_pipe_state_set(&rctx->ctx, &rstate);
 338         rctx->alpha_ref_dirty = false;
 339 }
 340
 341 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 342                               struct pipe_resource *buffer)
 343 {
 344         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 345         struct r600_resource *rbuffer = r600_resource(buffer);
 346         struct r600_pipe_resource_state *rstate;
 347         uint32_t offset;
 348
 349         /* Note that the state tracker can unbind constant buffers by
 350          * passing NULL here.
 351          */
 352         if (buffer == NULL) {
 353                 return;
 354         }
 355
 356         r600_upload_const_buffer(rctx, &rbuffer, &offset);
 357
 358         switch (shader) {
 359         case PIPE_SHADER_VERTEX:
 360                 rctx->vs_const_buffer.nregs = 0;
 361                 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
 362                                         R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
 363                                         ALIGN_DIVUP(buffer->width0 >> 4, 16),
 364                                         0xFFFFFFFF, NULL, 0);
 365                 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
 366                                         R_028980_ALU_CONST_CACHE_VS_0,
 367                                         offset >> 8, 0xFFFFFFFF, rbuffer, RADEON_USAGE_READ);
 368                 r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_const_buffer);
 369
 370                 rstate = &rctx->vs_const_buffer_resource[index];
 371                 if (!rstate->id) {
 372                         if (rctx->chip_class >= EVERGREEN) {
 373                                 evergreen_pipe_init_buffer_resource(rctx, rstate);
 374                         } else {
 375                                 r600_pipe_init_buffer_resource(rctx, rstate);
 376                         }
 377                 }
 378
 379                 if (rctx->chip_class >= EVERGREEN) {
 380                         evergreen_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 381                         evergreen_context_pipe_state_set_vs_resource(&rctx->ctx, rstate, index);
 382                 } else {
 383                         r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 384                         r600_context_pipe_state_set_vs_resource(&rctx->ctx, rstate, index);
 385                 }
 386                 break;
 387         case PIPE_SHADER_FRAGMENT:
 388                 rctx->ps_const_buffer.nregs = 0;
 389                 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
 390                                         R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
 391                                         ALIGN_DIVUP(buffer->width0 >> 4, 16),
 392                                         0xFFFFFFFF, NULL, 0);
 393                 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
 394                                         R_028940_ALU_CONST_CACHE_PS_0,
 395                                         offset >> 8, 0xFFFFFFFF, rbuffer, RADEON_USAGE_READ);
 396                 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_const_buffer);
 397
 398                 rstate = &rctx->ps_const_buffer_resource[index];
 399                 if (!rstate->id) {
 400                         if (rctx->chip_class >= EVERGREEN) {
 401                                 evergreen_pipe_init_buffer_resource(rctx, rstate);
 402                         } else {
 403                                 r600_pipe_init_buffer_resource(rctx, rstate);
 404                         }
 405                 }
 406                 if (rctx->chip_class >= EVERGREEN) {
 407                         evergreen_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 408                         evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, rstate, index);
 409                 } else {
 410                         r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 411                         r600_context_pipe_state_set_ps_resource(&rctx->ctx, rstate, index);
 412                 }
 413                 break;
 414         default:
 415                 R600_ERR("unsupported %d\n", shader);
 416                 return;
 417         }
 418
 419         if (buffer != &rbuffer->b.b.b)
 420                 pipe_resource_reference((struct pipe_resource**)&rbuffer, NULL);
 421 }
 422
 423 static void r600_vertex_buffer_update(struct r600_pipe_context *rctx)
 424 {
 425         struct r600_pipe_resource_state *rstate;
 426         struct r600_resource *rbuffer;
 427         struct pipe_vertex_buffer *vertex_buffer;
 428         unsigned i, count, offset;
 429
 430         if (rctx->vertex_elements->vbuffer_need_offset) {
 431                 /* one resource per vertex elements */
 432                 count = rctx->vertex_elements->count;
 433         } else {
 434                 /* bind vertex buffer once */
 435                 count = rctx->vbuf_mgr->nr_real_vertex_buffers;
 436         }
 437
 438         for (i = 0 ; i < count; i++) {
 439                 rstate = &rctx->fs_resource[i];
 440
 441                 if (rctx->vertex_elements->vbuffer_need_offset) {
 442                         /* one resource per vertex elements */
 443                         unsigned vbuffer_index;
 444                         vbuffer_index = rctx->vertex_elements->elements[i].vertex_buffer_index;
 445                         vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[vbuffer_index];
 446                         rbuffer = (struct r600_resource*)vertex_buffer->buffer;
 447                         offset = rctx->vertex_elements->vbuffer_offset[i];
 448                 } else {
 449                         /* bind vertex buffer once */
 450                         vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[i];
 451                         rbuffer = (struct r600_resource*)vertex_buffer->buffer;
 452                         offset = 0;
 453                 }
 454                 if (vertex_buffer == NULL || rbuffer == NULL)
 455                         continue;
 456                 offset += vertex_buffer->buffer_offset;
 457
 458                 if (!rstate->id) {
 459                         if (rctx->chip_class >= EVERGREEN) {
 460                                 evergreen_pipe_init_buffer_resource(rctx, rstate);
 461                         } else {
 462                                 r600_pipe_init_buffer_resource(rctx, rstate);
 463                         }
 464                 }
 465
 466                 if (rctx->chip_class >= EVERGREEN) {
 467                         evergreen_pipe_mod_buffer_resource(rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ);
 468                         evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, rstate, i);
 469                 } else {
 470                         r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ);
 471                         r600_context_pipe_state_set_fs_resource(&rctx->ctx, rstate, i);
 472                 }
 473         }
 474 }
 475
 476 static int r600_shader_rebuild(struct pipe_context * ctx, struct r600_pipe_shader * shader)
 477 {
 478         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 479         int r;
 480
 481         r600_pipe_shader_destroy(ctx, shader);
 482         r = r600_pipe_shader_create(ctx, shader);
 483         if (r) {
 484                 return r;
 485         }
 486         r600_context_pipe_state_set(&rctx->ctx, &shader->rstate);
 487
 488         return 0;
 489 }
 490
 491 static void r600_update_derived_state(struct r600_pipe_context *rctx)
 492 {
 493         struct pipe_context * ctx = (struct pipe_context*)rctx;
 494
 495         if (!rctx->blitter->running) {
 496                 if (rctx->have_depth_fb || rctx->have_depth_texture)
 497                         r600_flush_depth_textures(rctx);
 498         }
 499
 500         if (rctx->chip_class < EVERGREEN) {
 501                 r600_update_sampler_states(rctx);
 502         }
 503
 504         if (rctx->vs_shader->shader.clamp_color != rctx->clamp_vertex_color) {
 505                 r600_shader_rebuild(&rctx->context, rctx->vs_shader);
 506         }
 507
 508         if ((rctx->ps_shader->shader.clamp_color != rctx->clamp_fragment_color) ||
 509             ((rctx->chip_class >= EVERGREEN) && rctx->ps_shader->shader.fs_write_all &&
 510              (rctx->ps_shader->shader.nr_cbufs != rctx->nr_cbufs))) {
 511                 r600_shader_rebuild(&rctx->context, rctx->ps_shader);
 512         }
 513
 514         if (rctx->alpha_ref_dirty) {
 515                 r600_update_alpha_ref(rctx);
 516         }
 517
 518         if (rctx->ps_shader && rctx->sprite_coord_enable &&
 519                 (rctx->ps_shader->sprite_coord_enable != rctx->sprite_coord_enable)) {
 520
 521                 if (rctx->chip_class >= EVERGREEN)
 522                         evergreen_pipe_shader_ps(ctx, rctx->ps_shader);
 523                 else
 524                         r600_pipe_shader_ps(ctx, rctx->ps_shader);
 525
 526                 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_shader->rstate);
 527         }
 528
 529 }
 530
 531 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
 532 {
 533         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 534         struct pipe_draw_info info = *dinfo;
 535         struct r600_draw rdraw = {};
 536         struct pipe_index_buffer ib = {};
 537         unsigned prim, mask;
 538
 539         if (!info.count ||
 540             (info.indexed && !rctx->index_buffer.buffer) ||
 541             !r600_conv_pipe_prim(info.mode, &prim)) {
 542                 return;
 543         }
 544
 545         r600_update_derived_state(rctx);
 546
 547         u_vbuf_draw_begin(rctx->vbuf_mgr, dinfo);
 548         r600_vertex_buffer_update(rctx);
 549
 550         rdraw.vgt_num_indices = info.count;
 551         rdraw.vgt_num_instances = info.instance_count;
 552
 553         if (info.indexed) {
 554                 /* Adjust min/max_index by the index bias. */
 555                 if (info.max_index != ~0) {
 556                         info.min_index += info.index_bias;
 557                         info.max_index += info.index_bias;
 558                 }
 559
 560                 /* Initialize the index buffer struct. */
 561                 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
 562                 ib.index_size = rctx->index_buffer.index_size;
 563                 ib.offset = rctx->index_buffer.offset + info.start * ib.index_size;
 564
 565                 /* Translate or upload, if needed. */
 566                 r600_translate_index_buffer(rctx, &ib, info.count);
 567
 568                 if (u_vbuf_resource(ib.buffer)->user_ptr) {
 569                         r600_upload_index_buffer(rctx, &ib, info.count);
 570                 }
 571
 572                 /* Initialize the r600_draw struct with index buffer info. */
 573                 if (ib.index_size == 4) {
 574                         rdraw.vgt_index_type = VGT_INDEX_32 |
 575                                 (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0);
 576                 } else {
 577                         rdraw.vgt_index_type = VGT_INDEX_16 |
 578                                 (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0);
 579                 }
 580                 rdraw.indices = (struct r600_resource*)ib.buffer;
 581                 rdraw.indices_bo_offset = ib.offset;
 582                 rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_DMA;
 583         } else {
 584                 info.index_bias = info.start;
 585                 rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_AUTO_INDEX;
 586         }
 587
 588         mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
 589
 590         if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
 591                 rctx->vgt.id = R600_PIPE_STATE_VGT;
 592                 rctx->vgt.nregs = 0;
 593                 r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL, 0);
 594                 r600_pipe_state_add_reg(&rctx->vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL, 0);
 595                 r600_pipe_state_add_reg(&rctx->vgt, R_028400_VGT_MAX_VTX_INDX, info.max_index, 0xFFFFFFFF, NULL, 0);
 596                 r600_pipe_state_add_reg(&rctx->vgt, R_028404_VGT_MIN_VTX_INDX, info.min_index, 0xFFFFFFFF, NULL, 0);
 597                 r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias, 0xFFFFFFFF, NULL, 0);
 598                 r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index, 0xFFFFFFFF, NULL, 0);
 599                 r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart, 0xFFFFFFFF, NULL, 0);
 600                 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0xFFFFFFFF, NULL, 0);
 601                 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance, 0xFFFFFFFF, NULL, 0);
 602                 r600_pipe_state_add_reg(&rctx->vgt, R_028814_PA_SU_SC_MODE_CNTL,
 603                                         0,
 604                                         S_028814_PROVOKING_VTX_LAST(1), NULL, 0);
 605         }
 606
 607         rctx->vgt.nregs = 0;
 608         r600_pipe_state_mod_reg(&rctx->vgt, prim);
 609         r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_target_mask & mask);
 610         r600_pipe_state_mod_reg(&rctx->vgt, info.max_index);
 611         r600_pipe_state_mod_reg(&rctx->vgt, info.min_index);
 612         r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
 613         r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
 614         r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart);
 615         r600_pipe_state_mod_reg(&rctx->vgt, 0);
 616         r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance);
 617         if (info.mode == PIPE_PRIM_QUADS || info.mode == PIPE_PRIM_QUAD_STRIP || info.mode == PIPE_PRIM_POLYGON) {
 618                 r600_pipe_state_mod_reg(&rctx->vgt, S_028814_PROVOKING_VTX_LAST(1));
 619         }
 620
 621         r600_context_pipe_state_set(&rctx->ctx, &rctx->vgt);
 622
 623         if (rctx->chip_class >= EVERGREEN) {
 624                 evergreen_context_draw(&rctx->ctx, &rdraw);
 625         } else {
 626                 r600_context_draw(&rctx->ctx, &rdraw);
 627         }
 628
 629         if (rctx->framebuffer.zsbuf)
 630         {
 631                 struct pipe_resource *tex = rctx->framebuffer.zsbuf->texture;
 632                 ((struct r600_resource_texture *)tex)->dirty_db = TRUE;
 633         }
 634
 635         pipe_resource_reference(&ib.buffer, NULL);
 636         u_vbuf_draw_end(rctx->vbuf_mgr);
 637 }
 638
 639 void _r600_pipe_state_add_reg(struct r600_context *ctx,
 640                               struct r600_pipe_state *state,
 641                               u32 offset, u32 value, u32 mask,
 642                               u32 range_id, u32 block_id,
 643                               struct r600_resource *bo,
 644                               enum radeon_bo_usage usage)
 645 {
 646         struct r600_range *range;
 647         struct r600_block *block;
 648
 649         if (bo) assert(usage);
 650
 651         range = &ctx->range[range_id];
 652         block = range->blocks[block_id];
 653         state->regs[state->nregs].block = block;
 654         state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
 655
 656         state->regs[state->nregs].value = value;
 657         state->regs[state->nregs].mask = mask;
 658         state->regs[state->nregs].bo = bo;
 659         state->regs[state->nregs].bo_usage = usage;
 660
 661         state->nregs++;
 662         assert(state->nregs < R600_BLOCK_MAX_REG);
 663 }
 664
 665 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
 666                                      u32 offset, u32 value, u32 mask,
 667                                      struct r600_resource *bo,
 668                                      enum radeon_bo_usage usage)
 669 {
 670         if (bo) assert(usage);
 671
 672         state->regs[state->nregs].id = offset;
 673         state->regs[state->nregs].block = NULL;
 674         state->regs[state->nregs].value = value;
 675         state->regs[state->nregs].mask = mask;
 676         state->regs[state->nregs].bo = bo;
 677         state->regs[state->nregs].bo_usage = usage;
 678
 679         state->nregs++;
 680         assert(state->nregs < R600_BLOCK_MAX_REG);
 681 }