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r600g: defer shader variant selection and depending state updates
[mesa.git] / src / gallium / drivers / r600 / r600_state_common.c
1 /*
2 * Copyright 2010 Red Hat Inc.
3 * 2010 Jerome Glisse
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
26 */
27 #include "r600_formats.h"
28 #include "r600_shader.h"
29 #include "r600d.h"
30
31 #include "util/u_draw_quad.h"
32 #include "util/u_format_s3tc.h"
33 #include "util/u_index_modify.h"
34 #include "util/u_memory.h"
35 #include "util/u_upload_mgr.h"
36 #include "util/u_math.h"
37 #include "tgsi/tgsi_parse.h"
38
39 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
40
41 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw)
42 {
43 assert(!cb->buf);
44 cb->buf = CALLOC(1, 4 * num_dw);
45 cb->max_num_dw = num_dw;
46 }
47
48 void r600_release_command_buffer(struct r600_command_buffer *cb)
49 {
50 FREE(cb->buf);
51 }
52
53 void r600_init_atom(struct r600_context *rctx,
54 struct r600_atom *atom,
55 unsigned id,
56 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
57 unsigned num_dw)
58 {
59 assert(id < R600_NUM_ATOMS);
60 assert(rctx->atoms[id] == NULL);
61 rctx->atoms[id] = atom;
62 atom->emit = (void*)emit;
63 atom->num_dw = num_dw;
64 atom->dirty = false;
65 }
66
67 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom)
68 {
69 r600_emit_command_buffer(rctx->b.rings.gfx.cs, ((struct r600_cso_state*)atom)->cb);
70 }
71
72 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom)
73 {
74 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
75 struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom;
76 unsigned alpha_ref = a->sx_alpha_ref;
77
78 if (rctx->b.chip_class >= EVERGREEN && a->cb0_export_16bpc) {
79 alpha_ref &= ~0x1FFF;
80 }
81
82 r600_write_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL,
83 a->sx_alpha_test_control |
84 S_028410_ALPHA_TEST_BYPASS(a->bypass));
85 r600_write_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref);
86 }
87
88 static void r600_texture_barrier(struct pipe_context *ctx)
89 {
90 struct r600_context *rctx = (struct r600_context *)ctx;
91
92 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
93 R600_CONTEXT_FLUSH_AND_INV_CB |
94 R600_CONTEXT_FLUSH_AND_INV |
95 R600_CONTEXT_WAIT_3D_IDLE;
96 }
97
98 static unsigned r600_conv_pipe_prim(unsigned prim)
99 {
100 static const unsigned prim_conv[] = {
101 V_008958_DI_PT_POINTLIST,
102 V_008958_DI_PT_LINELIST,
103 V_008958_DI_PT_LINELOOP,
104 V_008958_DI_PT_LINESTRIP,
105 V_008958_DI_PT_TRILIST,
106 V_008958_DI_PT_TRISTRIP,
107 V_008958_DI_PT_TRIFAN,
108 V_008958_DI_PT_QUADLIST,
109 V_008958_DI_PT_QUADSTRIP,
110 V_008958_DI_PT_POLYGON,
111 V_008958_DI_PT_LINELIST_ADJ,
112 V_008958_DI_PT_LINESTRIP_ADJ,
113 V_008958_DI_PT_TRILIST_ADJ,
114 V_008958_DI_PT_TRISTRIP_ADJ,
115 V_008958_DI_PT_RECTLIST
116 };
117 return prim_conv[prim];
118 }
119
120 /* common state between evergreen and r600 */
121
122 static void r600_bind_blend_state_internal(struct r600_context *rctx,
123 struct r600_blend_state *blend, bool blend_disable)
124 {
125 unsigned color_control;
126 bool update_cb = false;
127
128 rctx->alpha_to_one = blend->alpha_to_one;
129 rctx->dual_src_blend = blend->dual_src_blend;
130
131 if (!blend_disable) {
132 r600_set_cso_state_with_cb(&rctx->blend_state, blend, &blend->buffer);
133 color_control = blend->cb_color_control;
134 } else {
135 /* Blending is disabled. */
136 r600_set_cso_state_with_cb(&rctx->blend_state, blend, &blend->buffer_no_blend);
137 color_control = blend->cb_color_control_no_blend;
138 }
139
140 /* Update derived states. */
141 if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) {
142 rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
143 update_cb = true;
144 }
145 if (rctx->b.chip_class <= R700 &&
146 rctx->cb_misc_state.cb_color_control != color_control) {
147 rctx->cb_misc_state.cb_color_control = color_control;
148 update_cb = true;
149 }
150 if (rctx->cb_misc_state.dual_src_blend != blend->dual_src_blend) {
151 rctx->cb_misc_state.dual_src_blend = blend->dual_src_blend;
152 update_cb = true;
153 }
154 if (update_cb) {
155 rctx->cb_misc_state.atom.dirty = true;
156 }
157 }
158
159 static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
160 {
161 struct r600_context *rctx = (struct r600_context *)ctx;
162 struct r600_blend_state *blend = (struct r600_blend_state *)state;
163
164 if (blend == NULL)
165 return;
166
167 r600_bind_blend_state_internal(rctx, blend, rctx->force_blend_disable);
168 }
169
170 static void r600_set_blend_color(struct pipe_context *ctx,
171 const struct pipe_blend_color *state)
172 {
173 struct r600_context *rctx = (struct r600_context *)ctx;
174
175 rctx->blend_color.state = *state;
176 rctx->blend_color.atom.dirty = true;
177 }
178
179 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom)
180 {
181 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
182 struct pipe_blend_color *state = &rctx->blend_color.state;
183
184 r600_write_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
185 radeon_emit(cs, fui(state->color[0])); /* R_028414_CB_BLEND_RED */
186 radeon_emit(cs, fui(state->color[1])); /* R_028418_CB_BLEND_GREEN */
187 radeon_emit(cs, fui(state->color[2])); /* R_02841C_CB_BLEND_BLUE */
188 radeon_emit(cs, fui(state->color[3])); /* R_028420_CB_BLEND_ALPHA */
189 }
190
191 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom)
192 {
193 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
194 struct r600_vgt_state *a = (struct r600_vgt_state *)atom;
195
196 r600_write_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, a->vgt_multi_prim_ib_reset_en);
197 r600_write_context_reg_seq(cs, R_028408_VGT_INDX_OFFSET, 2);
198 radeon_emit(cs, a->vgt_indx_offset); /* R_028408_VGT_INDX_OFFSET */
199 radeon_emit(cs, a->vgt_multi_prim_ib_reset_indx); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
200 }
201
202 static void r600_set_clip_state(struct pipe_context *ctx,
203 const struct pipe_clip_state *state)
204 {
205 struct r600_context *rctx = (struct r600_context *)ctx;
206 struct pipe_constant_buffer cb;
207
208 rctx->clip_state.state = *state;
209 rctx->clip_state.atom.dirty = true;
210
211 cb.buffer = NULL;
212 cb.user_buffer = state->ucp;
213 cb.buffer_offset = 0;
214 cb.buffer_size = 4*4*8;
215 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, R600_UCP_CONST_BUFFER, &cb);
216 pipe_resource_reference(&cb.buffer, NULL);
217 }
218
219 static void r600_set_stencil_ref(struct pipe_context *ctx,
220 const struct r600_stencil_ref *state)
221 {
222 struct r600_context *rctx = (struct r600_context *)ctx;
223
224 rctx->stencil_ref.state = *state;
225 rctx->stencil_ref.atom.dirty = true;
226 }
227
228 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom)
229 {
230 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
231 struct r600_stencil_ref_state *a = (struct r600_stencil_ref_state*)atom;
232
233 r600_write_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
234 radeon_emit(cs, /* R_028430_DB_STENCILREFMASK */
235 S_028430_STENCILREF(a->state.ref_value[0]) |
236 S_028430_STENCILMASK(a->state.valuemask[0]) |
237 S_028430_STENCILWRITEMASK(a->state.writemask[0]));
238 radeon_emit(cs, /* R_028434_DB_STENCILREFMASK_BF */
239 S_028434_STENCILREF_BF(a->state.ref_value[1]) |
240 S_028434_STENCILMASK_BF(a->state.valuemask[1]) |
241 S_028434_STENCILWRITEMASK_BF(a->state.writemask[1]));
242 }
243
244 static void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
245 const struct pipe_stencil_ref *state)
246 {
247 struct r600_context *rctx = (struct r600_context *)ctx;
248 struct r600_dsa_state *dsa = (struct r600_dsa_state*)rctx->dsa_state.cso;
249 struct r600_stencil_ref ref;
250
251 rctx->stencil_ref.pipe_state = *state;
252
253 if (!dsa)
254 return;
255
256 ref.ref_value[0] = state->ref_value[0];
257 ref.ref_value[1] = state->ref_value[1];
258 ref.valuemask[0] = dsa->valuemask[0];
259 ref.valuemask[1] = dsa->valuemask[1];
260 ref.writemask[0] = dsa->writemask[0];
261 ref.writemask[1] = dsa->writemask[1];
262
263 r600_set_stencil_ref(ctx, &ref);
264 }
265
266 static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
267 {
268 struct r600_context *rctx = (struct r600_context *)ctx;
269 struct r600_dsa_state *dsa = state;
270 struct r600_stencil_ref ref;
271
272 if (state == NULL) {
273 r600_set_cso_state_with_cb(&rctx->dsa_state, NULL, NULL);
274 return;
275 }
276
277 r600_set_cso_state_with_cb(&rctx->dsa_state, dsa, &dsa->buffer);
278
279 ref.ref_value[0] = rctx->stencil_ref.pipe_state.ref_value[0];
280 ref.ref_value[1] = rctx->stencil_ref.pipe_state.ref_value[1];
281 ref.valuemask[0] = dsa->valuemask[0];
282 ref.valuemask[1] = dsa->valuemask[1];
283 ref.writemask[0] = dsa->writemask[0];
284 ref.writemask[1] = dsa->writemask[1];
285 if (rctx->zwritemask != dsa->zwritemask) {
286 rctx->zwritemask = dsa->zwritemask;
287 if (rctx->b.chip_class >= EVERGREEN) {
288 /* work around some issue when not writting to zbuffer
289 * we are having lockup on evergreen so do not enable
290 * hyperz when not writting zbuffer
291 */
292 rctx->db_misc_state.atom.dirty = true;
293 }
294 }
295
296 r600_set_stencil_ref(ctx, &ref);
297
298 /* Update alphatest state. */
299 if (rctx->alphatest_state.sx_alpha_test_control != dsa->sx_alpha_test_control ||
300 rctx->alphatest_state.sx_alpha_ref != dsa->alpha_ref) {
301 rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control;
302 rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref;
303 rctx->alphatest_state.atom.dirty = true;
304 }
305 }
306
307 static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
308 {
309 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
310 struct r600_context *rctx = (struct r600_context *)ctx;
311
312 if (state == NULL)
313 return;
314
315 rctx->rasterizer = rs;
316
317 r600_set_cso_state_with_cb(&rctx->rasterizer_state, rs, &rs->buffer);
318
319 if (rs->offset_enable &&
320 (rs->offset_units != rctx->poly_offset_state.offset_units ||
321 rs->offset_scale != rctx->poly_offset_state.offset_scale)) {
322 rctx->poly_offset_state.offset_units = rs->offset_units;
323 rctx->poly_offset_state.offset_scale = rs->offset_scale;
324 rctx->poly_offset_state.atom.dirty = true;
325 }
326
327 /* Update clip_misc_state. */
328 if (rctx->clip_misc_state.pa_cl_clip_cntl != rs->pa_cl_clip_cntl ||
329 rctx->clip_misc_state.clip_plane_enable != rs->clip_plane_enable) {
330 rctx->clip_misc_state.pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
331 rctx->clip_misc_state.clip_plane_enable = rs->clip_plane_enable;
332 rctx->clip_misc_state.atom.dirty = true;
333 }
334
335 /* Workaround for a missing scissor enable on r600. */
336 if (rctx->b.chip_class == R600 &&
337 rs->scissor_enable != rctx->scissor.enable) {
338 rctx->scissor.enable = rs->scissor_enable;
339 rctx->scissor.atom.dirty = true;
340 }
341
342 /* Re-emit PA_SC_LINE_STIPPLE. */
343 rctx->last_primitive_type = -1;
344 }
345
346 static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
347 {
348 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
349
350 r600_release_command_buffer(&rs->buffer);
351 FREE(rs);
352 }
353
354 static void r600_sampler_view_destroy(struct pipe_context *ctx,
355 struct pipe_sampler_view *state)
356 {
357 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
358
359 pipe_resource_reference(&state->texture, NULL);
360 FREE(resource);
361 }
362
363 void r600_sampler_states_dirty(struct r600_context *rctx,
364 struct r600_sampler_states *state)
365 {
366 if (state->dirty_mask) {
367 if (state->dirty_mask & state->has_bordercolor_mask) {
368 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
369 }
370 state->atom.num_dw =
371 util_bitcount(state->dirty_mask & state->has_bordercolor_mask) * 11 +
372 util_bitcount(state->dirty_mask & ~state->has_bordercolor_mask) * 5;
373 state->atom.dirty = true;
374 }
375 }
376
377 static void r600_bind_sampler_states(struct pipe_context *pipe,
378 unsigned shader,
379 unsigned start,
380 unsigned count, void **states)
381 {
382 struct r600_context *rctx = (struct r600_context *)pipe;
383 struct r600_textures_info *dst = &rctx->samplers[shader];
384 struct r600_pipe_sampler_state **rstates = (struct r600_pipe_sampler_state**)states;
385 int seamless_cube_map = -1;
386 unsigned i;
387 /* This sets 1-bit for states with index >= count. */
388 uint32_t disable_mask = ~((1ull << count) - 1);
389 /* These are the new states set by this function. */
390 uint32_t new_mask = 0;
391
392 assert(start == 0); /* XXX fix below */
393
394 if (shader != PIPE_SHADER_VERTEX &&
395 shader != PIPE_SHADER_FRAGMENT) {
396 return;
397 }
398
399 for (i = 0; i < count; i++) {
400 struct r600_pipe_sampler_state *rstate = rstates[i];
401
402 if (rstate == dst->states.states[i]) {
403 continue;
404 }
405
406 if (rstate) {
407 if (rstate->border_color_use) {
408 dst->states.has_bordercolor_mask |= 1 << i;
409 } else {
410 dst->states.has_bordercolor_mask &= ~(1 << i);
411 }
412 seamless_cube_map = rstate->seamless_cube_map;
413
414 new_mask |= 1 << i;
415 } else {
416 disable_mask |= 1 << i;
417 }
418 }
419
420 memcpy(dst->states.states, rstates, sizeof(void*) * count);
421 memset(dst->states.states + count, 0, sizeof(void*) * (NUM_TEX_UNITS - count));
422
423 dst->states.enabled_mask &= ~disable_mask;
424 dst->states.dirty_mask &= dst->states.enabled_mask;
425 dst->states.enabled_mask |= new_mask;
426 dst->states.dirty_mask |= new_mask;
427 dst->states.has_bordercolor_mask &= dst->states.enabled_mask;
428
429 r600_sampler_states_dirty(rctx, &dst->states);
430
431 /* Seamless cubemap state. */
432 if (rctx->b.chip_class <= R700 &&
433 seamless_cube_map != -1 &&
434 seamless_cube_map != rctx->seamless_cube_map.enabled) {
435 /* change in TA_CNTL_AUX need a pipeline flush */
436 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
437 rctx->seamless_cube_map.enabled = seamless_cube_map;
438 rctx->seamless_cube_map.atom.dirty = true;
439 }
440 }
441
442 static void r600_delete_sampler_state(struct pipe_context *ctx, void *state)
443 {
444 free(state);
445 }
446
447 static void r600_delete_blend_state(struct pipe_context *ctx, void *state)
448 {
449 struct r600_blend_state *blend = (struct r600_blend_state*)state;
450
451 r600_release_command_buffer(&blend->buffer);
452 r600_release_command_buffer(&blend->buffer_no_blend);
453 FREE(blend);
454 }
455
456 static void r600_delete_dsa_state(struct pipe_context *ctx, void *state)
457 {
458 struct r600_context *rctx = (struct r600_context *)ctx;
459 struct r600_dsa_state *dsa = (struct r600_dsa_state *)state;
460
461 if (rctx->dsa_state.cso == state) {
462 ctx->bind_depth_stencil_alpha_state(ctx, NULL);
463 }
464
465 r600_release_command_buffer(&dsa->buffer);
466 free(dsa);
467 }
468
469 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
470 {
471 struct r600_context *rctx = (struct r600_context *)ctx;
472
473 r600_set_cso_state(&rctx->vertex_fetch_shader, state);
474 }
475
476 static void r600_delete_vertex_elements(struct pipe_context *ctx, void *state)
477 {
478 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state;
479 pipe_resource_reference((struct pipe_resource**)&shader->buffer, NULL);
480 FREE(shader);
481 }
482
483 static void r600_set_index_buffer(struct pipe_context *ctx,
484 const struct pipe_index_buffer *ib)
485 {
486 struct r600_context *rctx = (struct r600_context *)ctx;
487
488 if (ib) {
489 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
490 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
491 r600_context_add_resource_size(ctx, ib->buffer);
492 } else {
493 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
494 }
495 }
496
497 void r600_vertex_buffers_dirty(struct r600_context *rctx)
498 {
499 if (rctx->vertex_buffer_state.dirty_mask) {
500 rctx->b.flags |= R600_CONTEXT_INV_VERTEX_CACHE;
501 rctx->vertex_buffer_state.atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 12 : 11) *
502 util_bitcount(rctx->vertex_buffer_state.dirty_mask);
503 rctx->vertex_buffer_state.atom.dirty = true;
504 }
505 }
506
507 static void r600_set_vertex_buffers(struct pipe_context *ctx,
508 unsigned start_slot, unsigned count,
509 const struct pipe_vertex_buffer *input)
510 {
511 struct r600_context *rctx = (struct r600_context *)ctx;
512 struct r600_vertexbuf_state *state = &rctx->vertex_buffer_state;
513 struct pipe_vertex_buffer *vb = state->vb + start_slot;
514 unsigned i;
515 uint32_t disable_mask = 0;
516 /* These are the new buffers set by this function. */
517 uint32_t new_buffer_mask = 0;
518
519 /* Set vertex buffers. */
520 if (input) {
521 for (i = 0; i < count; i++) {
522 if (memcmp(&input[i], &vb[i], sizeof(struct pipe_vertex_buffer))) {
523 if (input[i].buffer) {
524 vb[i].stride = input[i].stride;
525 vb[i].buffer_offset = input[i].buffer_offset;
526 pipe_resource_reference(&vb[i].buffer, input[i].buffer);
527 new_buffer_mask |= 1 << i;
528 r600_context_add_resource_size(ctx, input[i].buffer);
529 } else {
530 pipe_resource_reference(&vb[i].buffer, NULL);
531 disable_mask |= 1 << i;
532 }
533 }
534 }
535 } else {
536 for (i = 0; i < count; i++) {
537 pipe_resource_reference(&vb[i].buffer, NULL);
538 }
539 disable_mask = ((1ull << count) - 1);
540 }
541
542 disable_mask <<= start_slot;
543 new_buffer_mask <<= start_slot;
544
545 rctx->vertex_buffer_state.enabled_mask &= ~disable_mask;
546 rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask;
547 rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask;
548 rctx->vertex_buffer_state.dirty_mask |= new_buffer_mask;
549
550 r600_vertex_buffers_dirty(rctx);
551 }
552
553 void r600_sampler_views_dirty(struct r600_context *rctx,
554 struct r600_samplerview_state *state)
555 {
556 if (state->dirty_mask) {
557 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
558 state->atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 14 : 13) *
559 util_bitcount(state->dirty_mask);
560 state->atom.dirty = true;
561 }
562 }
563
564 static void r600_set_sampler_views(struct pipe_context *pipe, unsigned shader,
565 unsigned start, unsigned count,
566 struct pipe_sampler_view **views)
567 {
568 struct r600_context *rctx = (struct r600_context *) pipe;
569 struct r600_textures_info *dst = &rctx->samplers[shader];
570 struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
571 uint32_t dirty_sampler_states_mask = 0;
572 unsigned i;
573 /* This sets 1-bit for textures with index >= count. */
574 uint32_t disable_mask = ~((1ull << count) - 1);
575 /* These are the new textures set by this function. */
576 uint32_t new_mask = 0;
577
578 /* Set textures with index >= count to NULL. */
579 uint32_t remaining_mask;
580
581 assert(start == 0); /* XXX fix below */
582
583 if (shader == PIPE_SHADER_COMPUTE) {
584 evergreen_set_cs_sampler_view(pipe, start, count, views);
585 return;
586 }
587
588 remaining_mask = dst->views.enabled_mask & disable_mask;
589
590 while (remaining_mask) {
591 i = u_bit_scan(&remaining_mask);
592 assert(dst->views.views[i]);
593
594 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
595 }
596
597 for (i = 0; i < count; i++) {
598 if (rviews[i] == dst->views.views[i]) {
599 continue;
600 }
601
602 if (rviews[i]) {
603 struct r600_texture *rtex =
604 (struct r600_texture*)rviews[i]->base.texture;
605
606 if (rviews[i]->base.texture->target != PIPE_BUFFER) {
607 if (rtex->is_depth && !rtex->is_flushing_texture) {
608 dst->views.compressed_depthtex_mask |= 1 << i;
609 } else {
610 dst->views.compressed_depthtex_mask &= ~(1 << i);
611 }
612
613 /* Track compressed colorbuffers. */
614 if (rtex->cmask.size) {
615 dst->views.compressed_colortex_mask |= 1 << i;
616 } else {
617 dst->views.compressed_colortex_mask &= ~(1 << i);
618 }
619 }
620 /* Changing from array to non-arrays textures and vice versa requires
621 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
622 if (rctx->b.chip_class <= R700 &&
623 (dst->states.enabled_mask & (1 << i)) &&
624 (rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
625 rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) {
626 dirty_sampler_states_mask |= 1 << i;
627 }
628
629 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]);
630 new_mask |= 1 << i;
631 r600_context_add_resource_size(pipe, views[i]->texture);
632 } else {
633 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
634 disable_mask |= 1 << i;
635 }
636 }
637
638 dst->views.enabled_mask &= ~disable_mask;
639 dst->views.dirty_mask &= dst->views.enabled_mask;
640 dst->views.enabled_mask |= new_mask;
641 dst->views.dirty_mask |= new_mask;
642 dst->views.compressed_depthtex_mask &= dst->views.enabled_mask;
643 dst->views.compressed_colortex_mask &= dst->views.enabled_mask;
644 dst->views.dirty_txq_constants = TRUE;
645 dst->views.dirty_buffer_constants = TRUE;
646 r600_sampler_views_dirty(rctx, &dst->views);
647
648 if (dirty_sampler_states_mask) {
649 dst->states.dirty_mask |= dirty_sampler_states_mask;
650 r600_sampler_states_dirty(rctx, &dst->states);
651 }
652 }
653
654 static void r600_set_viewport_states(struct pipe_context *ctx,
655 unsigned start_slot,
656 unsigned num_viewports,
657 const struct pipe_viewport_state *state)
658 {
659 struct r600_context *rctx = (struct r600_context *)ctx;
660
661 rctx->viewport.state = *state;
662 rctx->viewport.atom.dirty = true;
663 }
664
665 void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom)
666 {
667 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
668 struct pipe_viewport_state *state = &rctx->viewport.state;
669
670 r600_write_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE_0, 6);
671 radeon_emit(cs, fui(state->scale[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
672 radeon_emit(cs, fui(state->translate[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
673 radeon_emit(cs, fui(state->scale[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
674 radeon_emit(cs, fui(state->translate[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
675 radeon_emit(cs, fui(state->scale[2])); /* R_02844C_PA_CL_VPORT_ZSCALE_0 */
676 radeon_emit(cs, fui(state->translate[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
677 }
678
679 /* Compute the key for the hw shader variant */
680 static INLINE struct r600_shader_key r600_shader_selector_key(struct pipe_context * ctx,
681 struct r600_pipe_shader_selector * sel)
682 {
683 struct r600_context *rctx = (struct r600_context *)ctx;
684 struct r600_shader_key key;
685 memset(&key, 0, sizeof(key));
686
687 if (sel->type == PIPE_SHADER_FRAGMENT) {
688 key.color_two_side = rctx->rasterizer && rctx->rasterizer->two_side;
689 key.alpha_to_one = rctx->alpha_to_one &&
690 rctx->rasterizer && rctx->rasterizer->multisample_enable &&
691 !rctx->framebuffer.cb0_is_integer;
692 key.nr_cbufs = rctx->framebuffer.state.nr_cbufs;
693 /* Dual-source blending only makes sense with nr_cbufs == 1. */
694 if (key.nr_cbufs == 1 && rctx->dual_src_blend)
695 key.nr_cbufs = 2;
696 }
697 return key;
698 }
699
700 /* Select the hw shader variant depending on the current state.
701 * (*dirty) is set to 1 if current variant was changed */
702 static int r600_shader_select(struct pipe_context *ctx,
703 struct r600_pipe_shader_selector* sel,
704 bool *dirty)
705 {
706 struct r600_shader_key key;
707 struct r600_pipe_shader * shader = NULL;
708 int r;
709
710 memset(&key, 0, sizeof(key));
711 key = r600_shader_selector_key(ctx, sel);
712
713 /* Check if we don't need to change anything.
714 * This path is also used for most shaders that don't need multiple
715 * variants, it will cost just a computation of the key and this
716 * test. */
717 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
718 return 0;
719 }
720
721 /* lookup if we have other variants in the list */
722 if (sel->num_shaders > 1) {
723 struct r600_pipe_shader *p = sel->current, *c = p->next_variant;
724
725 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
726 p = c;
727 c = c->next_variant;
728 }
729
730 if (c) {
731 p->next_variant = c->next_variant;
732 shader = c;
733 }
734 }
735
736 if (unlikely(!shader)) {
737 shader = CALLOC(1, sizeof(struct r600_pipe_shader));
738 shader->selector = sel;
739
740 r = r600_pipe_shader_create(ctx, shader, key);
741 if (unlikely(r)) {
742 R600_ERR("Failed to build shader variant (type=%u) %d\n",
743 sel->type, r);
744 sel->current = NULL;
745 FREE(shader);
746 return r;
747 }
748
749 /* We don't know the value of nr_ps_max_color_exports until we built
750 * at least one variant, so we may need to recompute the key after
751 * building first variant. */
752 if (sel->type == PIPE_SHADER_FRAGMENT &&
753 sel->num_shaders == 0) {
754 sel->nr_ps_max_color_exports = shader->shader.nr_ps_max_color_exports;
755 key = r600_shader_selector_key(ctx, sel);
756 }
757
758 memcpy(&shader->key, &key, sizeof(key));
759 sel->num_shaders++;
760 }
761
762 if (dirty)
763 *dirty = true;
764
765 shader->next_variant = sel->current;
766 sel->current = shader;
767
768 return 0;
769 }
770
771 static void *r600_create_shader_state(struct pipe_context *ctx,
772 const struct pipe_shader_state *state,
773 unsigned pipe_shader_type)
774 {
775 struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector);
776
777 sel->type = pipe_shader_type;
778 sel->tokens = tgsi_dup_tokens(state->tokens);
779 sel->so = state->stream_output;
780 return sel;
781 }
782
783 static void *r600_create_ps_state(struct pipe_context *ctx,
784 const struct pipe_shader_state *state)
785 {
786 return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
787 }
788
789 static void *r600_create_vs_state(struct pipe_context *ctx,
790 const struct pipe_shader_state *state)
791 {
792 return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
793 }
794
795 static void r600_bind_ps_state(struct pipe_context *ctx, void *state)
796 {
797 struct r600_context *rctx = (struct r600_context *)ctx;
798
799 if (!state)
800 state = rctx->dummy_pixel_shader;
801
802 rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
803 }
804
805 static void r600_bind_vs_state(struct pipe_context *ctx, void *state)
806 {
807 struct r600_context *rctx = (struct r600_context *)ctx;
808
809 if (!state)
810 return;
811
812 rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
813 rctx->b.streamout.stride_in_dw = rctx->vs_shader->so.stride;
814 }
815
816 static void r600_delete_shader_selector(struct pipe_context *ctx,
817 struct r600_pipe_shader_selector *sel)
818 {
819 struct r600_pipe_shader *p = sel->current, *c;
820 while (p) {
821 c = p->next_variant;
822 r600_pipe_shader_destroy(ctx, p);
823 free(p);
824 p = c;
825 }
826
827 free(sel->tokens);
828 free(sel);
829 }
830
831
832 static void r600_delete_ps_state(struct pipe_context *ctx, void *state)
833 {
834 struct r600_context *rctx = (struct r600_context *)ctx;
835 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
836
837 if (rctx->ps_shader == sel) {
838 rctx->ps_shader = NULL;
839 }
840
841 r600_delete_shader_selector(ctx, sel);
842 }
843
844 static void r600_delete_vs_state(struct pipe_context *ctx, void *state)
845 {
846 struct r600_context *rctx = (struct r600_context *)ctx;
847 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
848
849 if (rctx->vs_shader == sel) {
850 rctx->vs_shader = NULL;
851 }
852
853 r600_delete_shader_selector(ctx, sel);
854 }
855
856 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
857 {
858 if (state->dirty_mask) {
859 rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE;
860 state->atom.num_dw = rctx->b.chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
861 : util_bitcount(state->dirty_mask)*19;
862 state->atom.dirty = true;
863 }
864 }
865
866 static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
867 struct pipe_constant_buffer *input)
868 {
869 struct r600_context *rctx = (struct r600_context *)ctx;
870 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
871 struct pipe_constant_buffer *cb;
872 const uint8_t *ptr;
873
874 /* Note that the state tracker can unbind constant buffers by
875 * passing NULL here.
876 */
877 if (unlikely(!input || (!input->buffer && !input->user_buffer))) {
878 state->enabled_mask &= ~(1 << index);
879 state->dirty_mask &= ~(1 << index);
880 pipe_resource_reference(&state->cb[index].buffer, NULL);
881 return;
882 }
883
884 cb = &state->cb[index];
885 cb->buffer_size = input->buffer_size;
886
887 ptr = input->user_buffer;
888
889 if (ptr) {
890 /* Upload the user buffer. */
891 if (R600_BIG_ENDIAN) {
892 uint32_t *tmpPtr;
893 unsigned i, size = input->buffer_size;
894
895 if (!(tmpPtr = malloc(size))) {
896 R600_ERR("Failed to allocate BE swap buffer.\n");
897 return;
898 }
899
900 for (i = 0; i < size / 4; ++i) {
901 tmpPtr[i] = util_bswap32(((uint32_t *)ptr)[i]);
902 }
903
904 u_upload_data(rctx->b.uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer);
905 free(tmpPtr);
906 } else {
907 u_upload_data(rctx->b.uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer);
908 }
909 /* account it in gtt */
910 rctx->b.gtt += input->buffer_size;
911 } else {
912 /* Setup the hw buffer. */
913 cb->buffer_offset = input->buffer_offset;
914 pipe_resource_reference(&cb->buffer, input->buffer);
915 r600_context_add_resource_size(ctx, input->buffer);
916 }
917
918 state->enabled_mask |= 1 << index;
919 state->dirty_mask |= 1 << index;
920 r600_constant_buffers_dirty(rctx, state);
921 }
922
923 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
924 {
925 struct r600_context *rctx = (struct r600_context*)pipe;
926
927 if (rctx->sample_mask.sample_mask == (uint16_t)sample_mask)
928 return;
929
930 rctx->sample_mask.sample_mask = sample_mask;
931 rctx->sample_mask.atom.dirty = true;
932 }
933
934 /*
935 * On r600/700 hw we don't have vertex fetch swizzle, though TBO
936 * doesn't require full swizzles it does need masking and setting alpha
937 * to one, so we setup a set of 5 constants with the masks + alpha value
938 * then in the shader, we AND the 4 components with 0xffffffff or 0,
939 * then OR the alpha with the value given here.
940 * We use a 6th constant to store the txq buffer size in
941 */
942 static void r600_setup_buffer_constants(struct r600_context *rctx, int shader_type)
943 {
944 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
945 int bits;
946 uint32_t array_size;
947 struct pipe_constant_buffer cb;
948 int i, j;
949
950 if (!samplers->views.dirty_buffer_constants)
951 return;
952
953 samplers->views.dirty_buffer_constants = FALSE;
954
955 bits = util_last_bit(samplers->views.enabled_mask);
956 array_size = bits * 8 * sizeof(uint32_t) * 4;
957 samplers->buffer_constants = realloc(samplers->buffer_constants, array_size);
958 memset(samplers->buffer_constants, 0, array_size);
959 for (i = 0; i < bits; i++) {
960 if (samplers->views.enabled_mask & (1 << i)) {
961 int offset = i * 8;
962 const struct util_format_description *desc;
963 desc = util_format_description(samplers->views.views[i]->base.format);
964
965 for (j = 0; j < 4; j++)
966 if (j < desc->nr_channels)
967 samplers->buffer_constants[offset+j] = 0xffffffff;
968 else
969 samplers->buffer_constants[offset+j] = 0x0;
970 if (desc->nr_channels < 4) {
971 if (desc->channel[0].pure_integer)
972 samplers->buffer_constants[offset+4] = 1;
973 else
974 samplers->buffer_constants[offset+4] = 0x3f800000;
975 } else
976 samplers->buffer_constants[offset + 4] = 0;
977
978 samplers->buffer_constants[offset + 5] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
979 }
980 }
981
982 cb.buffer = NULL;
983 cb.user_buffer = samplers->buffer_constants;
984 cb.buffer_offset = 0;
985 cb.buffer_size = array_size;
986 rctx->b.b.set_constant_buffer(&rctx->b.b, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
987 pipe_resource_reference(&cb.buffer, NULL);
988 }
989
990 /* On evergreen we only need to store the buffer size for TXQ */
991 static void eg_setup_buffer_constants(struct r600_context *rctx, int shader_type)
992 {
993 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
994 int bits;
995 uint32_t array_size;
996 struct pipe_constant_buffer cb;
997 int i;
998
999 if (!samplers->views.dirty_buffer_constants)
1000 return;
1001
1002 samplers->views.dirty_buffer_constants = FALSE;
1003
1004 bits = util_last_bit(samplers->views.enabled_mask);
1005 array_size = bits * sizeof(uint32_t) * 4;
1006 samplers->buffer_constants = realloc(samplers->buffer_constants, array_size);
1007 memset(samplers->buffer_constants, 0, array_size);
1008 for (i = 0; i < bits; i++)
1009 if (samplers->views.enabled_mask & (1 << i))
1010 samplers->buffer_constants[i] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
1011
1012 cb.buffer = NULL;
1013 cb.user_buffer = samplers->buffer_constants;
1014 cb.buffer_offset = 0;
1015 cb.buffer_size = array_size;
1016 rctx->b.b.set_constant_buffer(&rctx->b.b, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
1017 pipe_resource_reference(&cb.buffer, NULL);
1018 }
1019
1020 static void r600_setup_txq_cube_array_constants(struct r600_context *rctx, int shader_type)
1021 {
1022 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1023 int bits;
1024 uint32_t array_size;
1025 struct pipe_constant_buffer cb;
1026 int i;
1027
1028 if (!samplers->views.dirty_txq_constants)
1029 return;
1030
1031 samplers->views.dirty_txq_constants = FALSE;
1032
1033 bits = util_last_bit(samplers->views.enabled_mask);
1034 array_size = bits * sizeof(uint32_t) * 4;
1035 samplers->txq_constants = realloc(samplers->txq_constants, array_size);
1036 memset(samplers->txq_constants, 0, array_size);
1037 for (i = 0; i < bits; i++)
1038 if (samplers->views.enabled_mask & (1 << i))
1039 samplers->txq_constants[i] = samplers->views.views[i]->base.texture->array_size / 6;
1040
1041 cb.buffer = NULL;
1042 cb.user_buffer = samplers->txq_constants;
1043 cb.buffer_offset = 0;
1044 cb.buffer_size = array_size;
1045 rctx->b.b.set_constant_buffer(&rctx->b.b, shader_type, R600_TXQ_CONST_BUFFER, &cb);
1046 pipe_resource_reference(&cb.buffer, NULL);
1047 }
1048
1049 static bool r600_update_derived_state(struct r600_context *rctx)
1050 {
1051 struct pipe_context * ctx = (struct pipe_context*)rctx;
1052 bool ps_dirty = false, vs_dirty = false;
1053 bool blend_disable;
1054
1055 if (!rctx->blitter->running) {
1056 unsigned i;
1057
1058 /* Decompress textures if needed. */
1059 for (i = 0; i < PIPE_SHADER_TYPES; i++) {
1060 struct r600_samplerview_state *views = &rctx->samplers[i].views;
1061 if (views->compressed_depthtex_mask) {
1062 r600_decompress_depth_textures(rctx, views);
1063 }
1064 if (views->compressed_colortex_mask) {
1065 r600_decompress_color_textures(rctx, views);
1066 }
1067 }
1068 }
1069
1070 if (unlikely(rctx->vertex_shader.shader != rctx->vs_shader)) {
1071 r600_shader_select(ctx, rctx->vs_shader, &vs_dirty);
1072
1073 if (unlikely(!rctx->vs_shader->current))
1074 return false;
1075
1076 rctx->vertex_shader.shader = rctx->vs_shader;
1077 rctx->vertex_shader.atom.dirty = true;
1078 r600_context_add_resource_size(ctx, (struct pipe_resource *)rctx->vs_shader->current->bo);
1079
1080 /* Update clip misc state. */
1081 if (rctx->vs_shader->current->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
1082 rctx->vs_shader->current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write) {
1083 rctx->clip_misc_state.pa_cl_vs_out_cntl = rctx->vs_shader->current->pa_cl_vs_out_cntl;
1084 rctx->clip_misc_state.clip_dist_write = rctx->vs_shader->current->shader.clip_dist_write;
1085 rctx->clip_misc_state.atom.dirty = true;
1086 }
1087 }
1088
1089 r600_shader_select(ctx, rctx->ps_shader, &ps_dirty);
1090 if (unlikely(!rctx->ps_shader->current))
1091 return false;
1092
1093 if (unlikely(ps_dirty || rctx->pixel_shader.shader != rctx->ps_shader)) {
1094
1095 if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
1096 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
1097 rctx->cb_misc_state.atom.dirty = true;
1098 }
1099
1100 if (rctx->b.chip_class <= R700) {
1101 bool multiwrite = rctx->ps_shader->current->shader.fs_write_all;
1102
1103 if (rctx->cb_misc_state.multiwrite != multiwrite) {
1104 rctx->cb_misc_state.multiwrite = multiwrite;
1105 rctx->cb_misc_state.atom.dirty = true;
1106 }
1107 }
1108
1109 if (rctx->b.chip_class >= EVERGREEN) {
1110 evergreen_update_db_shader_control(rctx);
1111 } else {
1112 r600_update_db_shader_control(rctx);
1113 }
1114
1115 if (!ps_dirty && rctx->ps_shader && rctx->rasterizer &&
1116 ((rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable) ||
1117 (rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade))) {
1118
1119 if (rctx->b.chip_class >= EVERGREEN)
1120 evergreen_update_ps_state(ctx, rctx->ps_shader->current);
1121 else
1122 r600_update_ps_state(ctx, rctx->ps_shader->current);
1123 }
1124
1125 rctx->pixel_shader.shader = rctx->ps_shader;
1126 rctx->pixel_shader.atom.num_dw = rctx->ps_shader->current->command_buffer.num_dw;
1127 rctx->pixel_shader.atom.dirty = true;
1128 r600_context_add_resource_size(ctx,
1129 (struct pipe_resource *)rctx->ps_shader->current->bo);
1130 }
1131
1132 /* on R600 we stuff masks + txq info into one constant buffer */
1133 /* on evergreen we only need a txq info one */
1134 if (rctx->b.chip_class < EVERGREEN) {
1135 if (rctx->ps_shader && rctx->ps_shader->current->shader.uses_tex_buffers)
1136 r600_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
1137 if (rctx->vs_shader && rctx->vs_shader->current->shader.uses_tex_buffers)
1138 r600_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
1139 } else {
1140 if (rctx->ps_shader && rctx->ps_shader->current->shader.uses_tex_buffers)
1141 eg_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
1142 if (rctx->vs_shader && rctx->vs_shader->current->shader.uses_tex_buffers)
1143 eg_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
1144 }
1145
1146
1147 if (rctx->ps_shader && rctx->ps_shader->current->shader.has_txq_cube_array_z_comp)
1148 r600_setup_txq_cube_array_constants(rctx, PIPE_SHADER_FRAGMENT);
1149 if (rctx->vs_shader && rctx->vs_shader->current->shader.has_txq_cube_array_z_comp)
1150 r600_setup_txq_cube_array_constants(rctx, PIPE_SHADER_VERTEX);
1151
1152 if (rctx->b.chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
1153 if (!r600_adjust_gprs(rctx)) {
1154 /* discard rendering */
1155 return false;
1156 }
1157 }
1158
1159 blend_disable = (rctx->dual_src_blend &&
1160 rctx->ps_shader->current->nr_ps_color_outputs < 2);
1161
1162 if (blend_disable != rctx->force_blend_disable) {
1163 rctx->force_blend_disable = blend_disable;
1164 r600_bind_blend_state_internal(rctx,
1165 rctx->blend_state.cso,
1166 blend_disable);
1167 }
1168 return true;
1169 }
1170
1171 static unsigned r600_conv_prim_to_gs_out(unsigned mode)
1172 {
1173 static const int prim_conv[] = {
1174 V_028A6C_OUTPRIM_TYPE_POINTLIST,
1175 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1176 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1177 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1178 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1179 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1180 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1181 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1182 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1183 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1184 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1185 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1186 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1187 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1188 V_028A6C_OUTPRIM_TYPE_TRISTRIP
1189 };
1190 assert(mode < Elements(prim_conv));
1191
1192 return prim_conv[mode];
1193 }
1194
1195 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1196 {
1197 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1198 struct r600_clip_misc_state *state = &rctx->clip_misc_state;
1199
1200 r600_write_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
1201 state->pa_cl_clip_cntl |
1202 (state->clip_dist_write ? 0 : state->clip_plane_enable & 0x3F));
1203 r600_write_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
1204 state->pa_cl_vs_out_cntl |
1205 (state->clip_plane_enable & state->clip_dist_write));
1206 }
1207
1208 static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
1209 {
1210 struct r600_context *rctx = (struct r600_context *)ctx;
1211 struct pipe_draw_info info = *dinfo;
1212 struct pipe_index_buffer ib = {};
1213 unsigned i;
1214 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1215
1216 if (!info.count && (info.indexed || !info.count_from_stream_output)) {
1217 assert(0);
1218 return;
1219 }
1220
1221 if (!rctx->vs_shader || !rctx->ps_shader) {
1222 assert(0);
1223 return;
1224 }
1225
1226 /* make sure that the gfx ring is only one active */
1227 if (rctx->b.rings.dma.cs) {
1228 rctx->b.rings.dma.flush(rctx, RADEON_FLUSH_ASYNC);
1229 }
1230
1231 if (!r600_update_derived_state(rctx)) {
1232 /* useless to render because current rendering command
1233 * can't be achieved
1234 */
1235 return;
1236 }
1237
1238 if (info.indexed) {
1239 /* Initialize the index buffer struct. */
1240 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
1241 ib.user_buffer = rctx->index_buffer.user_buffer;
1242 ib.index_size = rctx->index_buffer.index_size;
1243 ib.offset = rctx->index_buffer.offset + info.start * ib.index_size;
1244
1245 /* Translate 8-bit indices to 16-bit. */
1246 if (ib.index_size == 1) {
1247 struct pipe_resource *out_buffer = NULL;
1248 unsigned out_offset;
1249 void *ptr;
1250
1251 u_upload_alloc(rctx->b.uploader, 0, info.count * 2,
1252 &out_offset, &out_buffer, &ptr);
1253
1254 util_shorten_ubyte_elts_to_userptr(
1255 &rctx->b.b, &ib, 0, ib.offset, info.count, ptr);
1256
1257 pipe_resource_reference(&ib.buffer, NULL);
1258 ib.user_buffer = NULL;
1259 ib.buffer = out_buffer;
1260 ib.offset = out_offset;
1261 ib.index_size = 2;
1262 }
1263
1264 /* Upload the index buffer.
1265 * The upload is skipped for small index counts on little-endian machines
1266 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
1267 * Note: Instanced rendering in combination with immediate indices hangs. */
1268 if (ib.user_buffer && (R600_BIG_ENDIAN || info.instance_count > 1 ||
1269 info.count*ib.index_size > 20)) {
1270 u_upload_data(rctx->b.uploader, 0, info.count * ib.index_size,
1271 ib.user_buffer, &ib.offset, &ib.buffer);
1272 ib.user_buffer = NULL;
1273 }
1274 } else {
1275 info.index_bias = info.start;
1276 }
1277
1278 /* Set the index offset and primitive restart. */
1279 if (rctx->vgt_state.vgt_multi_prim_ib_reset_en != info.primitive_restart ||
1280 rctx->vgt_state.vgt_multi_prim_ib_reset_indx != info.restart_index ||
1281 rctx->vgt_state.vgt_indx_offset != info.index_bias) {
1282 rctx->vgt_state.vgt_multi_prim_ib_reset_en = info.primitive_restart;
1283 rctx->vgt_state.vgt_multi_prim_ib_reset_indx = info.restart_index;
1284 rctx->vgt_state.vgt_indx_offset = info.index_bias;
1285 rctx->vgt_state.atom.dirty = true;
1286 }
1287
1288 /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
1289 if (rctx->b.chip_class == R600) {
1290 rctx->b.flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
1291 rctx->cb_misc_state.atom.dirty = true;
1292 }
1293
1294 /* Emit states. */
1295 r600_need_cs_space(rctx, ib.user_buffer ? 5 : 0, TRUE);
1296 r600_flush_emit(rctx);
1297
1298 for (i = 0; i < R600_NUM_ATOMS; i++) {
1299 if (rctx->atoms[i] == NULL || !rctx->atoms[i]->dirty) {
1300 continue;
1301 }
1302 r600_emit_atom(rctx, rctx->atoms[i]);
1303 }
1304
1305 /* Update start instance. */
1306 if (rctx->last_start_instance != info.start_instance) {
1307 r600_write_ctl_const(cs, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
1308 rctx->last_start_instance = info.start_instance;
1309 }
1310
1311 /* Update the primitive type. */
1312 if (rctx->last_primitive_type != info.mode) {
1313 unsigned ls_mask = 0;
1314
1315 if (info.mode == PIPE_PRIM_LINES)
1316 ls_mask = 1;
1317 else if (info.mode == PIPE_PRIM_LINE_STRIP ||
1318 info.mode == PIPE_PRIM_LINE_LOOP)
1319 ls_mask = 2;
1320
1321 r600_write_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
1322 S_028A0C_AUTO_RESET_CNTL(ls_mask) |
1323 (rctx->rasterizer ? rctx->rasterizer->pa_sc_line_stipple : 0));
1324 r600_write_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
1325 r600_conv_prim_to_gs_out(info.mode));
1326 r600_write_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE,
1327 r600_conv_pipe_prim(info.mode));
1328
1329 rctx->last_primitive_type = info.mode;
1330 }
1331
1332 /* Draw packets. */
1333 cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->b.predicate_drawing);
1334 cs->buf[cs->cdw++] = info.instance_count;
1335 if (info.indexed) {
1336 cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->b.predicate_drawing);
1337 cs->buf[cs->cdw++] = ib.index_size == 4 ?
1338 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
1339 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
1340
1341 if (ib.user_buffer) {
1342 unsigned size_bytes = info.count*ib.index_size;
1343 unsigned size_dw = align(size_bytes, 4) / 4;
1344 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_IMMD, 1 + size_dw, rctx->b.predicate_drawing);
1345 cs->buf[cs->cdw++] = info.count;
1346 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_IMMEDIATE;
1347 memcpy(cs->buf+cs->cdw, ib.user_buffer, size_bytes);
1348 cs->cdw += size_dw;
1349 } else {
1350 uint64_t va = r600_resource_va(ctx->screen, ib.buffer) + ib.offset;
1351 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->b.predicate_drawing);
1352 cs->buf[cs->cdw++] = va;
1353 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
1354 cs->buf[cs->cdw++] = info.count;
1355 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
1356 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->b.predicate_drawing);
1357 cs->buf[cs->cdw++] = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
1358 }
1359 } else {
1360 if (info.count_from_stream_output) {
1361 struct r600_so_target *t = (struct r600_so_target*)info.count_from_stream_output;
1362 uint64_t va = r600_resource_va(&rctx->screen->b.b, (void*)t->buf_filled_size) + t->buf_filled_size_offset;
1363
1364 r600_write_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
1365
1366 cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0);
1367 cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG;
1368 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */
1369 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
1370 cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */
1371 cs->buf[cs->cdw++] = 0; /* unused */
1372
1373 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1374 cs->buf[cs->cdw++] = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, t->buf_filled_size, RADEON_USAGE_READ);
1375 }
1376
1377 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->b.predicate_drawing);
1378 cs->buf[cs->cdw++] = info.count;
1379 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
1380 (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
1381 }
1382
1383 if (rctx->screen->b.trace_bo) {
1384 r600_trace_emit(rctx);
1385 }
1386
1387 /* Set the depth buffer as dirty. */
1388 if (rctx->framebuffer.state.zsbuf) {
1389 struct pipe_surface *surf = rctx->framebuffer.state.zsbuf;
1390 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
1391
1392 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1393 }
1394 if (rctx->framebuffer.compressed_cb_mask) {
1395 struct pipe_surface *surf;
1396 struct r600_texture *rtex;
1397 unsigned mask = rctx->framebuffer.compressed_cb_mask;
1398
1399 do {
1400 unsigned i = u_bit_scan(&mask);
1401 surf = rctx->framebuffer.state.cbufs[i];
1402 rtex = (struct r600_texture*)surf->texture;
1403
1404 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1405
1406 } while (mask);
1407 }
1408
1409 pipe_resource_reference(&ib.buffer, NULL);
1410 rctx->b.num_draw_calls++;
1411 }
1412
1413 void r600_draw_rectangle(struct blitter_context *blitter,
1414 int x1, int y1, int x2, int y2, float depth,
1415 enum blitter_attrib_type type, const union pipe_color_union *attrib)
1416 {
1417 struct r600_context *rctx = (struct r600_context*)util_blitter_get_pipe(blitter);
1418 struct pipe_viewport_state viewport;
1419 struct pipe_resource *buf = NULL;
1420 unsigned offset = 0;
1421 float *vb;
1422
1423 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
1424 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
1425 return;
1426 }
1427
1428 /* Some operations (like color resolve on r6xx) don't work
1429 * with the conventional primitive types.
1430 * One that works is PT_RECTLIST, which we use here. */
1431
1432 /* setup viewport */
1433 viewport.scale[0] = 1.0f;
1434 viewport.scale[1] = 1.0f;
1435 viewport.scale[2] = 1.0f;
1436 viewport.scale[3] = 1.0f;
1437 viewport.translate[0] = 0.0f;
1438 viewport.translate[1] = 0.0f;
1439 viewport.translate[2] = 0.0f;
1440 viewport.translate[3] = 0.0f;
1441 rctx->b.b.set_viewport_states(&rctx->b.b, 0, 1, &viewport);
1442
1443 /* Upload vertices. The hw rectangle has only 3 vertices,
1444 * I guess the 4th one is derived from the first 3.
1445 * The vertex specification should match u_blitter's vertex element state. */
1446 u_upload_alloc(rctx->b.uploader, 0, sizeof(float) * 24, &offset, &buf, (void**)&vb);
1447 vb[0] = x1;
1448 vb[1] = y1;
1449 vb[2] = depth;
1450 vb[3] = 1;
1451
1452 vb[8] = x1;
1453 vb[9] = y2;
1454 vb[10] = depth;
1455 vb[11] = 1;
1456
1457 vb[16] = x2;
1458 vb[17] = y1;
1459 vb[18] = depth;
1460 vb[19] = 1;
1461
1462 if (attrib) {
1463 memcpy(vb+4, attrib->f, sizeof(float)*4);
1464 memcpy(vb+12, attrib->f, sizeof(float)*4);
1465 memcpy(vb+20, attrib->f, sizeof(float)*4);
1466 }
1467
1468 /* draw */
1469 util_draw_vertex_buffer(&rctx->b.b, NULL, buf, rctx->blitter->vb_slot, offset,
1470 R600_PRIM_RECTANGLE_LIST, 3, 2);
1471 pipe_resource_reference(&buf, NULL);
1472 }
1473
1474 uint32_t r600_translate_stencil_op(int s_op)
1475 {
1476 switch (s_op) {
1477 case PIPE_STENCIL_OP_KEEP:
1478 return V_028800_STENCIL_KEEP;
1479 case PIPE_STENCIL_OP_ZERO:
1480 return V_028800_STENCIL_ZERO;
1481 case PIPE_STENCIL_OP_REPLACE:
1482 return V_028800_STENCIL_REPLACE;
1483 case PIPE_STENCIL_OP_INCR:
1484 return V_028800_STENCIL_INCR;
1485 case PIPE_STENCIL_OP_DECR:
1486 return V_028800_STENCIL_DECR;
1487 case PIPE_STENCIL_OP_INCR_WRAP:
1488 return V_028800_STENCIL_INCR_WRAP;
1489 case PIPE_STENCIL_OP_DECR_WRAP:
1490 return V_028800_STENCIL_DECR_WRAP;
1491 case PIPE_STENCIL_OP_INVERT:
1492 return V_028800_STENCIL_INVERT;
1493 default:
1494 R600_ERR("Unknown stencil op %d", s_op);
1495 assert(0);
1496 break;
1497 }
1498 return 0;
1499 }
1500
1501 uint32_t r600_translate_fill(uint32_t func)
1502 {
1503 switch(func) {
1504 case PIPE_POLYGON_MODE_FILL:
1505 return 2;
1506 case PIPE_POLYGON_MODE_LINE:
1507 return 1;
1508 case PIPE_POLYGON_MODE_POINT:
1509 return 0;
1510 default:
1511 assert(0);
1512 return 0;
1513 }
1514 }
1515
1516 unsigned r600_tex_wrap(unsigned wrap)
1517 {
1518 switch (wrap) {
1519 default:
1520 case PIPE_TEX_WRAP_REPEAT:
1521 return V_03C000_SQ_TEX_WRAP;
1522 case PIPE_TEX_WRAP_CLAMP:
1523 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1524 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1525 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1526 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1527 return V_03C000_SQ_TEX_CLAMP_BORDER;
1528 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1529 return V_03C000_SQ_TEX_MIRROR;
1530 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1531 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1532 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1533 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1534 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1535 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1536 }
1537 }
1538
1539 unsigned r600_tex_filter(unsigned filter)
1540 {
1541 switch (filter) {
1542 default:
1543 case PIPE_TEX_FILTER_NEAREST:
1544 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1545 case PIPE_TEX_FILTER_LINEAR:
1546 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1547 }
1548 }
1549
1550 unsigned r600_tex_mipfilter(unsigned filter)
1551 {
1552 switch (filter) {
1553 case PIPE_TEX_MIPFILTER_NEAREST:
1554 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1555 case PIPE_TEX_MIPFILTER_LINEAR:
1556 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1557 default:
1558 case PIPE_TEX_MIPFILTER_NONE:
1559 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1560 }
1561 }
1562
1563 unsigned r600_tex_compare(unsigned compare)
1564 {
1565 switch (compare) {
1566 default:
1567 case PIPE_FUNC_NEVER:
1568 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1569 case PIPE_FUNC_LESS:
1570 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1571 case PIPE_FUNC_EQUAL:
1572 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1573 case PIPE_FUNC_LEQUAL:
1574 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1575 case PIPE_FUNC_GREATER:
1576 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1577 case PIPE_FUNC_NOTEQUAL:
1578 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1579 case PIPE_FUNC_GEQUAL:
1580 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1581 case PIPE_FUNC_ALWAYS:
1582 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1583 }
1584 }
1585
1586 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
1587 {
1588 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
1589 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
1590 (linear_filter &&
1591 (wrap == PIPE_TEX_WRAP_CLAMP ||
1592 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
1593 }
1594
1595 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
1596 {
1597 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
1598 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
1599
1600 return (state->border_color.ui[0] || state->border_color.ui[1] ||
1601 state->border_color.ui[2] || state->border_color.ui[3]) &&
1602 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
1603 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
1604 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
1605 }
1606
1607 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a)
1608 {
1609 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1610 struct r600_pipe_shader *shader = ((struct r600_shader_state*)a)->shader->current;
1611
1612 r600_emit_command_buffer(cs, &shader->command_buffer);
1613
1614 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1615 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, shader->bo, RADEON_USAGE_READ));
1616 }
1617
1618 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
1619 struct pipe_resource *texture,
1620 const struct pipe_surface *templ,
1621 unsigned width, unsigned height)
1622 {
1623 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
1624
1625 assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level));
1626 assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level));
1627 assert(templ->u.tex.first_layer == templ->u.tex.last_layer);
1628 if (surface == NULL)
1629 return NULL;
1630 pipe_reference_init(&surface->base.reference, 1);
1631 pipe_resource_reference(&surface->base.texture, texture);
1632 surface->base.context = pipe;
1633 surface->base.format = templ->format;
1634 surface->base.width = width;
1635 surface->base.height = height;
1636 surface->base.u = templ->u;
1637 return &surface->base;
1638 }
1639
1640 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
1641 struct pipe_resource *tex,
1642 const struct pipe_surface *templ)
1643 {
1644 unsigned level = templ->u.tex.level;
1645
1646 return r600_create_surface_custom(pipe, tex, templ,
1647 u_minify(tex->width0, level),
1648 u_minify(tex->height0, level));
1649 }
1650
1651 static void r600_surface_destroy(struct pipe_context *pipe,
1652 struct pipe_surface *surface)
1653 {
1654 struct r600_surface *surf = (struct r600_surface*)surface;
1655 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, NULL);
1656 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, NULL);
1657 pipe_resource_reference(&surface->texture, NULL);
1658 FREE(surface);
1659 }
1660
1661 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
1662 const unsigned char *swizzle_view,
1663 boolean vtx)
1664 {
1665 unsigned i;
1666 unsigned char swizzle[4];
1667 unsigned result = 0;
1668 const uint32_t tex_swizzle_shift[4] = {
1669 16, 19, 22, 25,
1670 };
1671 const uint32_t vtx_swizzle_shift[4] = {
1672 3, 6, 9, 12,
1673 };
1674 const uint32_t swizzle_bit[4] = {
1675 0, 1, 2, 3,
1676 };
1677 const uint32_t *swizzle_shift = tex_swizzle_shift;
1678
1679 if (vtx)
1680 swizzle_shift = vtx_swizzle_shift;
1681
1682 if (swizzle_view) {
1683 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
1684 } else {
1685 memcpy(swizzle, swizzle_format, 4);
1686 }
1687
1688 /* Get swizzle. */
1689 for (i = 0; i < 4; i++) {
1690 switch (swizzle[i]) {
1691 case UTIL_FORMAT_SWIZZLE_Y:
1692 result |= swizzle_bit[1] << swizzle_shift[i];
1693 break;
1694 case UTIL_FORMAT_SWIZZLE_Z:
1695 result |= swizzle_bit[2] << swizzle_shift[i];
1696 break;
1697 case UTIL_FORMAT_SWIZZLE_W:
1698 result |= swizzle_bit[3] << swizzle_shift[i];
1699 break;
1700 case UTIL_FORMAT_SWIZZLE_0:
1701 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
1702 break;
1703 case UTIL_FORMAT_SWIZZLE_1:
1704 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
1705 break;
1706 default: /* UTIL_FORMAT_SWIZZLE_X */
1707 result |= swizzle_bit[0] << swizzle_shift[i];
1708 }
1709 }
1710 return result;
1711 }
1712
1713 /* texture format translate */
1714 uint32_t r600_translate_texformat(struct pipe_screen *screen,
1715 enum pipe_format format,
1716 const unsigned char *swizzle_view,
1717 uint32_t *word4_p, uint32_t *yuv_format_p)
1718 {
1719 struct r600_screen *rscreen = (struct r600_screen *)screen;
1720 uint32_t result = 0, word4 = 0, yuv_format = 0;
1721 const struct util_format_description *desc;
1722 boolean uniform = TRUE;
1723 bool enable_s3tc = rscreen->b.info.drm_minor >= 9;
1724 bool is_srgb_valid = FALSE;
1725 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
1726 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
1727
1728 int i;
1729 const uint32_t sign_bit[4] = {
1730 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
1731 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
1732 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
1733 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
1734 };
1735 desc = util_format_description(format);
1736
1737 /* Depth and stencil swizzling is handled separately. */
1738 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS) {
1739 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view, FALSE);
1740 }
1741
1742 /* Colorspace (return non-RGB formats directly). */
1743 switch (desc->colorspace) {
1744 /* Depth stencil formats */
1745 case UTIL_FORMAT_COLORSPACE_ZS:
1746 switch (format) {
1747 /* Depth sampler formats. */
1748 case PIPE_FORMAT_Z16_UNORM:
1749 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1750 result = FMT_16;
1751 goto out_word4;
1752 case PIPE_FORMAT_Z24X8_UNORM:
1753 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1754 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1755 result = FMT_8_24;
1756 goto out_word4;
1757 case PIPE_FORMAT_X8Z24_UNORM:
1758 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1759 if (rscreen->b.chip_class < EVERGREEN)
1760 goto out_unknown;
1761 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
1762 result = FMT_24_8;
1763 goto out_word4;
1764 case PIPE_FORMAT_Z32_FLOAT:
1765 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1766 result = FMT_32_FLOAT;
1767 goto out_word4;
1768 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1769 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1770 result = FMT_X24_8_32_FLOAT;
1771 goto out_word4;
1772 /* Stencil sampler formats. */
1773 case PIPE_FORMAT_S8_UINT:
1774 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1775 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1776 result = FMT_8;
1777 goto out_word4;
1778 case PIPE_FORMAT_X24S8_UINT:
1779 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1780 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
1781 result = FMT_8_24;
1782 goto out_word4;
1783 case PIPE_FORMAT_S8X24_UINT:
1784 if (rscreen->b.chip_class < EVERGREEN)
1785 goto out_unknown;
1786 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1787 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1788 result = FMT_24_8;
1789 goto out_word4;
1790 case PIPE_FORMAT_X32_S8X24_UINT:
1791 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1792 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
1793 result = FMT_X24_8_32_FLOAT;
1794 goto out_word4;
1795 default:
1796 goto out_unknown;
1797 }
1798
1799 case UTIL_FORMAT_COLORSPACE_YUV:
1800 yuv_format |= (1 << 30);
1801 switch (format) {
1802 case PIPE_FORMAT_UYVY:
1803 case PIPE_FORMAT_YUYV:
1804 default:
1805 break;
1806 }
1807 goto out_unknown; /* XXX */
1808
1809 case UTIL_FORMAT_COLORSPACE_SRGB:
1810 word4 |= S_038010_FORCE_DEGAMMA(1);
1811 break;
1812
1813 default:
1814 break;
1815 }
1816
1817 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1818 if (!enable_s3tc)
1819 goto out_unknown;
1820
1821 switch (format) {
1822 case PIPE_FORMAT_RGTC1_SNORM:
1823 case PIPE_FORMAT_LATC1_SNORM:
1824 word4 |= sign_bit[0];
1825 case PIPE_FORMAT_RGTC1_UNORM:
1826 case PIPE_FORMAT_LATC1_UNORM:
1827 result = FMT_BC4;
1828 goto out_word4;
1829 case PIPE_FORMAT_RGTC2_SNORM:
1830 case PIPE_FORMAT_LATC2_SNORM:
1831 word4 |= sign_bit[0] | sign_bit[1];
1832 case PIPE_FORMAT_RGTC2_UNORM:
1833 case PIPE_FORMAT_LATC2_UNORM:
1834 result = FMT_BC5;
1835 goto out_word4;
1836 default:
1837 goto out_unknown;
1838 }
1839 }
1840
1841 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1842
1843 if (!enable_s3tc)
1844 goto out_unknown;
1845
1846 if (!util_format_s3tc_enabled) {
1847 goto out_unknown;
1848 }
1849
1850 switch (format) {
1851 case PIPE_FORMAT_DXT1_RGB:
1852 case PIPE_FORMAT_DXT1_RGBA:
1853 case PIPE_FORMAT_DXT1_SRGB:
1854 case PIPE_FORMAT_DXT1_SRGBA:
1855 result = FMT_BC1;
1856 is_srgb_valid = TRUE;
1857 goto out_word4;
1858 case PIPE_FORMAT_DXT3_RGBA:
1859 case PIPE_FORMAT_DXT3_SRGBA:
1860 result = FMT_BC2;
1861 is_srgb_valid = TRUE;
1862 goto out_word4;
1863 case PIPE_FORMAT_DXT5_RGBA:
1864 case PIPE_FORMAT_DXT5_SRGBA:
1865 result = FMT_BC3;
1866 is_srgb_valid = TRUE;
1867 goto out_word4;
1868 default:
1869 goto out_unknown;
1870 }
1871 }
1872
1873 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1874 switch (format) {
1875 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1876 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1877 result = FMT_GB_GR;
1878 goto out_word4;
1879 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1880 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1881 result = FMT_BG_RG;
1882 goto out_word4;
1883 default:
1884 goto out_unknown;
1885 }
1886 }
1887
1888 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1889 result = FMT_5_9_9_9_SHAREDEXP;
1890 goto out_word4;
1891 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1892 result = FMT_10_11_11_FLOAT;
1893 goto out_word4;
1894 }
1895
1896
1897 for (i = 0; i < desc->nr_channels; i++) {
1898 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1899 word4 |= sign_bit[i];
1900 }
1901 }
1902
1903 /* R8G8Bx_SNORM - XXX CxV8U8 */
1904
1905 /* See whether the components are of the same size. */
1906 for (i = 1; i < desc->nr_channels; i++) {
1907 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1908 }
1909
1910 /* Non-uniform formats. */
1911 if (!uniform) {
1912 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1913 desc->channel[0].pure_integer)
1914 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1915 switch(desc->nr_channels) {
1916 case 3:
1917 if (desc->channel[0].size == 5 &&
1918 desc->channel[1].size == 6 &&
1919 desc->channel[2].size == 5) {
1920 result = FMT_5_6_5;
1921 goto out_word4;
1922 }
1923 goto out_unknown;
1924 case 4:
1925 if (desc->channel[0].size == 5 &&
1926 desc->channel[1].size == 5 &&
1927 desc->channel[2].size == 5 &&
1928 desc->channel[3].size == 1) {
1929 result = FMT_1_5_5_5;
1930 goto out_word4;
1931 }
1932 if (desc->channel[0].size == 10 &&
1933 desc->channel[1].size == 10 &&
1934 desc->channel[2].size == 10 &&
1935 desc->channel[3].size == 2) {
1936 result = FMT_2_10_10_10;
1937 goto out_word4;
1938 }
1939 goto out_unknown;
1940 }
1941 goto out_unknown;
1942 }
1943
1944 /* Find the first non-VOID channel. */
1945 for (i = 0; i < 4; i++) {
1946 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1947 break;
1948 }
1949 }
1950
1951 if (i == 4)
1952 goto out_unknown;
1953
1954 /* uniform formats */
1955 switch (desc->channel[i].type) {
1956 case UTIL_FORMAT_TYPE_UNSIGNED:
1957 case UTIL_FORMAT_TYPE_SIGNED:
1958 #if 0
1959 if (!desc->channel[i].normalized &&
1960 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
1961 goto out_unknown;
1962 }
1963 #endif
1964 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1965 desc->channel[i].pure_integer)
1966 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1967
1968 switch (desc->channel[i].size) {
1969 case 4:
1970 switch (desc->nr_channels) {
1971 case 2:
1972 result = FMT_4_4;
1973 goto out_word4;
1974 case 4:
1975 result = FMT_4_4_4_4;
1976 goto out_word4;
1977 }
1978 goto out_unknown;
1979 case 8:
1980 switch (desc->nr_channels) {
1981 case 1:
1982 result = FMT_8;
1983 goto out_word4;
1984 case 2:
1985 result = FMT_8_8;
1986 goto out_word4;
1987 case 4:
1988 result = FMT_8_8_8_8;
1989 is_srgb_valid = TRUE;
1990 goto out_word4;
1991 }
1992 goto out_unknown;
1993 case 16:
1994 switch (desc->nr_channels) {
1995 case 1:
1996 result = FMT_16;
1997 goto out_word4;
1998 case 2:
1999 result = FMT_16_16;
2000 goto out_word4;
2001 case 4:
2002 result = FMT_16_16_16_16;
2003 goto out_word4;
2004 }
2005 goto out_unknown;
2006 case 32:
2007 switch (desc->nr_channels) {
2008 case 1:
2009 result = FMT_32;
2010 goto out_word4;
2011 case 2:
2012 result = FMT_32_32;
2013 goto out_word4;
2014 case 4:
2015 result = FMT_32_32_32_32;
2016 goto out_word4;
2017 }
2018 }
2019 goto out_unknown;
2020
2021 case UTIL_FORMAT_TYPE_FLOAT:
2022 switch (desc->channel[i].size) {
2023 case 16:
2024 switch (desc->nr_channels) {
2025 case 1:
2026 result = FMT_16_FLOAT;
2027 goto out_word4;
2028 case 2:
2029 result = FMT_16_16_FLOAT;
2030 goto out_word4;
2031 case 4:
2032 result = FMT_16_16_16_16_FLOAT;
2033 goto out_word4;
2034 }
2035 goto out_unknown;
2036 case 32:
2037 switch (desc->nr_channels) {
2038 case 1:
2039 result = FMT_32_FLOAT;
2040 goto out_word4;
2041 case 2:
2042 result = FMT_32_32_FLOAT;
2043 goto out_word4;
2044 case 4:
2045 result = FMT_32_32_32_32_FLOAT;
2046 goto out_word4;
2047 }
2048 }
2049 goto out_unknown;
2050 }
2051
2052 out_word4:
2053
2054 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid)
2055 return ~0;
2056 if (word4_p)
2057 *word4_p = word4;
2058 if (yuv_format_p)
2059 *yuv_format_p = yuv_format;
2060 return result;
2061 out_unknown:
2062 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
2063 return ~0;
2064 }
2065
2066 static void r600_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource *buf)
2067 {
2068 struct r600_context *rctx = (struct r600_context*)ctx;
2069 struct r600_resource *rbuffer = r600_resource(buf);
2070 unsigned i, shader, mask, alignment = rbuffer->buf->alignment;
2071
2072 /* Discard the buffer. */
2073 pb_reference(&rbuffer->buf, NULL);
2074
2075 /* Create a new one in the same pipe_resource. */
2076 r600_init_resource(&rctx->screen->b, rbuffer, rbuffer->b.b.width0, alignment,
2077 TRUE, rbuffer->b.b.usage);
2078
2079 /* We changed the buffer, now we need to bind it where the old one was bound. */
2080 /* Vertex buffers. */
2081 mask = rctx->vertex_buffer_state.enabled_mask;
2082 while (mask) {
2083 i = u_bit_scan(&mask);
2084 if (rctx->vertex_buffer_state.vb[i].buffer == &rbuffer->b.b) {
2085 rctx->vertex_buffer_state.dirty_mask |= 1 << i;
2086 r600_vertex_buffers_dirty(rctx);
2087 }
2088 }
2089 /* Streamout buffers. */
2090 for (i = 0; i < rctx->b.streamout.num_targets; i++) {
2091 if (rctx->b.streamout.targets[i]->b.buffer == &rbuffer->b.b) {
2092 if (rctx->b.streamout.begin_emitted) {
2093 r600_emit_streamout_end(&rctx->b);
2094 }
2095 rctx->b.streamout.append_bitmask = rctx->b.streamout.enabled_mask;
2096 r600_streamout_buffers_dirty(&rctx->b);
2097 }
2098 }
2099
2100 /* Constant buffers. */
2101 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
2102 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
2103 bool found = false;
2104 uint32_t mask = state->enabled_mask;
2105
2106 while (mask) {
2107 unsigned i = u_bit_scan(&mask);
2108 if (state->cb[i].buffer == &rbuffer->b.b) {
2109 found = true;
2110 state->dirty_mask |= 1 << i;
2111 }
2112 }
2113 if (found) {
2114 r600_constant_buffers_dirty(rctx, state);
2115 }
2116 }
2117
2118 /* XXX TODO: texture buffer objects */
2119 }
2120
2121 static void r600_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
2122 {
2123 struct r600_context *rctx = (struct r600_context*)ctx;
2124
2125 if (rctx->db_misc_state.occlusion_query_enabled != enable) {
2126 rctx->db_misc_state.occlusion_query_enabled = enable;
2127 rctx->db_misc_state.atom.dirty = true;
2128 }
2129 }
2130
2131 static void r600_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
2132 bool include_draw_vbo)
2133 {
2134 r600_need_cs_space((struct r600_context*)ctx, num_dw, include_draw_vbo);
2135 }
2136
2137 /* keep this at the end of this file, please */
2138 void r600_init_common_state_functions(struct r600_context *rctx)
2139 {
2140 rctx->b.b.create_fs_state = r600_create_ps_state;
2141 rctx->b.b.create_vs_state = r600_create_vs_state;
2142 rctx->b.b.create_vertex_elements_state = r600_create_vertex_fetch_shader;
2143 rctx->b.b.bind_blend_state = r600_bind_blend_state;
2144 rctx->b.b.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
2145 rctx->b.b.bind_sampler_states = r600_bind_sampler_states;
2146 rctx->b.b.bind_fs_state = r600_bind_ps_state;
2147 rctx->b.b.bind_rasterizer_state = r600_bind_rs_state;
2148 rctx->b.b.bind_vertex_elements_state = r600_bind_vertex_elements;
2149 rctx->b.b.bind_vs_state = r600_bind_vs_state;
2150 rctx->b.b.delete_blend_state = r600_delete_blend_state;
2151 rctx->b.b.delete_depth_stencil_alpha_state = r600_delete_dsa_state;
2152 rctx->b.b.delete_fs_state = r600_delete_ps_state;
2153 rctx->b.b.delete_rasterizer_state = r600_delete_rs_state;
2154 rctx->b.b.delete_sampler_state = r600_delete_sampler_state;
2155 rctx->b.b.delete_vertex_elements_state = r600_delete_vertex_elements;
2156 rctx->b.b.delete_vs_state = r600_delete_vs_state;
2157 rctx->b.b.set_blend_color = r600_set_blend_color;
2158 rctx->b.b.set_clip_state = r600_set_clip_state;
2159 rctx->b.b.set_constant_buffer = r600_set_constant_buffer;
2160 rctx->b.b.set_sample_mask = r600_set_sample_mask;
2161 rctx->b.b.set_stencil_ref = r600_set_pipe_stencil_ref;
2162 rctx->b.b.set_viewport_states = r600_set_viewport_states;
2163 rctx->b.b.set_vertex_buffers = r600_set_vertex_buffers;
2164 rctx->b.b.set_index_buffer = r600_set_index_buffer;
2165 rctx->b.b.set_sampler_views = r600_set_sampler_views;
2166 rctx->b.b.sampler_view_destroy = r600_sampler_view_destroy;
2167 rctx->b.b.texture_barrier = r600_texture_barrier;
2168 rctx->b.b.set_stream_output_targets = r600_set_streamout_targets;
2169 rctx->b.b.create_surface = r600_create_surface;
2170 rctx->b.b.surface_destroy = r600_surface_destroy;
2171 rctx->b.b.draw_vbo = r600_draw_vbo;
2172 rctx->b.invalidate_buffer = r600_invalidate_buffer;
2173 rctx->b.set_occlusion_query_state = r600_set_occlusion_query_state;
2174 rctx->b.need_gfx_cs_space = r600_need_gfx_cs_space;
2175 }
2176
2177 void r600_trace_emit(struct r600_context *rctx)
2178 {
2179 struct r600_screen *rscreen = rctx->screen;
2180 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2181 uint64_t va;
2182 uint32_t reloc;
2183
2184 va = r600_resource_va(&rscreen->b.b, (void*)rscreen->b.trace_bo);
2185 reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rscreen->b.trace_bo, RADEON_USAGE_READWRITE);
2186 radeon_emit(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
2187 radeon_emit(cs, va & 0xFFFFFFFFUL);
2188 radeon_emit(cs, (va >> 32UL) & 0xFFUL);
2189 radeon_emit(cs, cs->cdw);
2190 radeon_emit(cs, rscreen->b.cs_count);
2191 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2192 radeon_emit(cs, reloc);
2193 }