src/gallium/drivers/r600/r600_state_common.c

   1 /*
   2  * Copyright 2010 Red Hat Inc.
   3  *           2010 Jerome Glisse
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie <airlied@redhat.com>
  25  *          Jerome Glisse <jglisse@redhat.com>
  26  */
  27 #include "util/u_blitter.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_format.h"
  30 #include "pipebuffer/pb_buffer.h"
  31 #include "pipe/p_shader_tokens.h"
  32 #include "tgsi/tgsi_parse.h"
  33 #include "r600_formats.h"
  34 #include "r600_pipe.h"
  35 #include "r600d.h"
  36
  37 static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
  38 {
  39         static const int prim_conv[] = {
  40                 V_008958_DI_PT_POINTLIST,
  41                 V_008958_DI_PT_LINELIST,
  42                 V_008958_DI_PT_LINELOOP,
  43                 V_008958_DI_PT_LINESTRIP,
  44                 V_008958_DI_PT_TRILIST,
  45                 V_008958_DI_PT_TRISTRIP,
  46                 V_008958_DI_PT_TRIFAN,
  47                 V_008958_DI_PT_QUADLIST,
  48                 V_008958_DI_PT_QUADSTRIP,
  49                 V_008958_DI_PT_POLYGON,
  50                 -1,
  51                 -1,
  52                 -1,
  53                 -1
  54         };
  55
  56         *prim = prim_conv[pprim];
  57         if (*prim == -1) {
  58                 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim);
  59                 return false;
  60         }
  61         return true;
  62 }
  63
  64 /* common state between evergreen and r600 */
  65 void r600_bind_blend_state(struct pipe_context *ctx, void *state)
  66 {
  67         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
  68         struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
  69         struct r600_pipe_state *rstate;
  70
  71         if (state == NULL)
  72                 return;
  73         rstate = &blend->rstate;
  74         rctx->states[rstate->id] = rstate;
  75         rctx->cb_target_mask = blend->cb_target_mask;
  76         r600_context_pipe_state_set(&rctx->ctx, rstate);
  77 }
  78
  79 static void r600_set_stencil_ref(struct pipe_context *ctx,
  80                                  const struct r600_stencil_ref *state)
  81 {
  82         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
  83         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
  84
  85         if (rstate == NULL)
  86                 return;
  87
  88         rstate->id = R600_PIPE_STATE_STENCIL_REF;
  89         r600_pipe_state_add_reg(rstate,
  90                                 R_028430_DB_STENCILREFMASK,
  91                                 S_028430_STENCILREF(state->ref_value[0]) |
  92                                 S_028430_STENCILMASK(state->valuemask[0]) |
  93                                 S_028430_STENCILWRITEMASK(state->writemask[0]),
  94                                 0xFFFFFFFF, NULL, 0);
  95         r600_pipe_state_add_reg(rstate,
  96                                 R_028434_DB_STENCILREFMASK_BF,
  97                                 S_028434_STENCILREF_BF(state->ref_value[1]) |
  98                                 S_028434_STENCILMASK_BF(state->valuemask[1]) |
  99                                 S_028434_STENCILWRITEMASK_BF(state->writemask[1]),
 100                                 0xFFFFFFFF, NULL, 0);
 101
 102         free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
 103         rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
 104         r600_context_pipe_state_set(&rctx->ctx, rstate);
 105 }
 106
 107 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
 108                                const struct pipe_stencil_ref *state)
 109 {
 110         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 111         struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA];
 112         struct r600_stencil_ref ref;
 113
 114         rctx->stencil_ref = *state;
 115
 116         if (!dsa)
 117                 return;
 118
 119         ref.ref_value[0] = state->ref_value[0];
 120         ref.ref_value[1] = state->ref_value[1];
 121         ref.valuemask[0] = dsa->valuemask[0];
 122         ref.valuemask[1] = dsa->valuemask[1];
 123         ref.writemask[0] = dsa->writemask[0];
 124         ref.writemask[1] = dsa->writemask[1];
 125
 126         r600_set_stencil_ref(ctx, &ref);
 127 }
 128
 129 void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
 130 {
 131         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 132         struct r600_pipe_dsa *dsa = state;
 133         struct r600_pipe_state *rstate;
 134         struct r600_stencil_ref ref;
 135
 136         if (state == NULL)
 137                 return;
 138         rstate = &dsa->rstate;
 139         rctx->states[rstate->id] = rstate;
 140         rctx->alpha_ref = dsa->alpha_ref;
 141         rctx->alpha_ref_dirty = true;
 142         r600_context_pipe_state_set(&rctx->ctx, rstate);
 143
 144         ref.ref_value[0] = rctx->stencil_ref.ref_value[0];
 145         ref.ref_value[1] = rctx->stencil_ref.ref_value[1];
 146         ref.valuemask[0] = dsa->valuemask[0];
 147         ref.valuemask[1] = dsa->valuemask[1];
 148         ref.writemask[0] = dsa->writemask[0];
 149         ref.writemask[1] = dsa->writemask[1];
 150
 151         r600_set_stencil_ref(ctx, &ref);
 152 }
 153
 154 void r600_bind_rs_state(struct pipe_context *ctx, void *state)
 155 {
 156         struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
 157         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 158
 159         if (state == NULL)
 160                 return;
 161
 162         rctx->sprite_coord_enable = rs->sprite_coord_enable;
 163         rctx->two_side = rs->two_side;
 164
 165         rctx->rasterizer = rs;
 166
 167         rctx->states[rs->rstate.id] = &rs->rstate;
 168         r600_context_pipe_state_set(&rctx->ctx, &rs->rstate);
 169
 170         if (rctx->chip_class >= EVERGREEN) {
 171                 evergreen_polygon_offset_update(rctx);
 172         } else {
 173                 r600_polygon_offset_update(rctx);
 174         }
 175 }
 176
 177 void r600_delete_rs_state(struct pipe_context *ctx, void *state)
 178 {
 179         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 180         struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
 181
 182         if (rctx->rasterizer == rs) {
 183                 rctx->rasterizer = NULL;
 184         }
 185         if (rctx->states[rs->rstate.id] == &rs->rstate) {
 186                 rctx->states[rs->rstate.id] = NULL;
 187         }
 188         free(rs);
 189 }
 190
 191 void r600_sampler_view_destroy(struct pipe_context *ctx,
 192                                struct pipe_sampler_view *state)
 193 {
 194         struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
 195
 196         pipe_resource_reference(&state->texture, NULL);
 197         FREE(resource);
 198 }
 199
 200 void r600_delete_state(struct pipe_context *ctx, void *state)
 201 {
 202         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 203         struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
 204
 205         if (rctx->states[rstate->id] == rstate) {
 206                 rctx->states[rstate->id] = NULL;
 207         }
 208         for (int i = 0; i < rstate->nregs; i++) {
 209                 pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL);
 210         }
 211         free(rstate);
 212 }
 213
 214 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
 215 {
 216         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 217         struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 218
 219         rctx->vertex_elements = v;
 220         if (v) {
 221                 u_vbuf_bind_vertex_elements(rctx->vbuf_mgr, state,
 222                                                 v->vmgr_elements);
 223
 224                 rctx->states[v->rstate.id] = &v->rstate;
 225                 r600_context_pipe_state_set(&rctx->ctx, &v->rstate);
 226         }
 227 }
 228
 229 void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
 230 {
 231         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 232         struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 233
 234         if (rctx->states[v->rstate.id] == &v->rstate) {
 235                 rctx->states[v->rstate.id] = NULL;
 236         }
 237         if (rctx->vertex_elements == state)
 238                 rctx->vertex_elements = NULL;
 239
 240         pipe_resource_reference((struct pipe_resource**)&v->fetch_shader, NULL);
 241         u_vbuf_destroy_vertex_elements(rctx->vbuf_mgr, v->vmgr_elements);
 242         FREE(state);
 243 }
 244
 245
 246 void r600_set_index_buffer(struct pipe_context *ctx,
 247                            const struct pipe_index_buffer *ib)
 248 {
 249         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 250
 251         u_vbuf_set_index_buffer(rctx->vbuf_mgr, ib);
 252 }
 253
 254 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
 255                              const struct pipe_vertex_buffer *buffers)
 256 {
 257         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 258         int i;
 259
 260         /* Zero states. */
 261         for (i = 0; i < count; i++) {
 262                 if (!buffers[i].buffer) {
 263                         if (rctx->chip_class >= EVERGREEN) {
 264                                 evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
 265                         } else {
 266                                 r600_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
 267                         }
 268                 }
 269         }
 270         for (; i < rctx->vbuf_mgr->nr_real_vertex_buffers; i++) {
 271                 if (rctx->chip_class >= EVERGREEN) {
 272                         evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
 273                 } else {
 274                         r600_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
 275                 }
 276         }
 277
 278         u_vbuf_set_vertex_buffers(rctx->vbuf_mgr, count, buffers);
 279 }
 280
 281 void *r600_create_vertex_elements(struct pipe_context *ctx,
 282                                   unsigned count,
 283                                   const struct pipe_vertex_element *elements)
 284 {
 285         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 286         struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
 287
 288         assert(count < 32);
 289         if (!v)
 290                 return NULL;
 291
 292         v->count = count;
 293         v->vmgr_elements =
 294                 u_vbuf_create_vertex_elements(rctx->vbuf_mgr, count,
 295                                                   elements, v->elements);
 296
 297         if (r600_vertex_elements_build_fetch_shader(rctx, v)) {
 298                 FREE(v);
 299                 return NULL;
 300         }
 301
 302         return v;
 303 }
 304
 305 void *r600_create_shader_state(struct pipe_context *ctx,
 306                                const struct pipe_shader_state *state)
 307 {
 308         struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader);
 309         int r;
 310
 311         shader->tokens = tgsi_dup_tokens(state->tokens);
 312         shader->so = state->stream_output;
 313
 314         r =  r600_pipe_shader_create(ctx, shader);
 315         if (r) {
 316                 return NULL;
 317         }
 318         return shader;
 319 }
 320
 321 void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
 322 {
 323         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 324
 325         /* TODO delete old shader */
 326         rctx->ps_shader = (struct r600_pipe_shader *)state;
 327         if (state) {
 328                 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_shader->rstate);
 329         }
 330         if (rctx->ps_shader && rctx->vs_shader) {
 331                 r600_adjust_gprs(rctx);
 332         }
 333 }
 334
 335 void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
 336 {
 337         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 338
 339         /* TODO delete old shader */
 340         rctx->vs_shader = (struct r600_pipe_shader *)state;
 341         if (state) {
 342                 r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_shader->rstate);
 343         }
 344         if (rctx->ps_shader && rctx->vs_shader) {
 345                 r600_adjust_gprs(rctx);
 346         }
 347 }
 348
 349 void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
 350 {
 351         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 352         struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
 353
 354         if (rctx->ps_shader == shader) {
 355                 rctx->ps_shader = NULL;
 356         }
 357
 358         free(shader->tokens);
 359         r600_pipe_shader_destroy(ctx, shader);
 360         free(shader);
 361 }
 362
 363 void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
 364 {
 365         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 366         struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
 367
 368         if (rctx->vs_shader == shader) {
 369                 rctx->vs_shader = NULL;
 370         }
 371
 372         free(shader->tokens);
 373         r600_pipe_shader_destroy(ctx, shader);
 374         free(shader);
 375 }
 376
 377 static void r600_update_alpha_ref(struct r600_pipe_context *rctx)
 378 {
 379         unsigned alpha_ref;
 380         struct r600_pipe_state rstate;
 381
 382         alpha_ref = rctx->alpha_ref;
 383         rstate.nregs = 0;
 384         if (rctx->export_16bpc)
 385                 alpha_ref &= ~0x1FFF;
 386         r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL, 0);
 387
 388         r600_context_pipe_state_set(&rctx->ctx, &rstate);
 389         rctx->alpha_ref_dirty = false;
 390 }
 391
 392 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 393                               struct pipe_resource *buffer)
 394 {
 395         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 396         struct r600_resource *rbuffer = r600_resource(buffer);
 397         struct r600_pipe_resource_state *rstate;
 398         uint64_t va_offset;
 399         uint32_t offset;
 400
 401         /* Note that the state tracker can unbind constant buffers by
 402          * passing NULL here.
 403          */
 404         if (buffer == NULL) {
 405                 return;
 406         }
 407
 408         r600_upload_const_buffer(rctx, &rbuffer, &offset);
 409         va_offset = r600_resource_va(ctx->screen, (void*)rbuffer);
 410         va_offset += offset;
 411         va_offset >>= 8;
 412
 413         switch (shader) {
 414         case PIPE_SHADER_VERTEX:
 415                 rctx->vs_const_buffer.nregs = 0;
 416                 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
 417                                         R_028180_ALU_CONST_BUFFER_SIZE_VS_0 + index * 4,
 418                                         ALIGN_DIVUP(buffer->width0 >> 4, 16),
 419                                         0xFFFFFFFF, NULL, 0);
 420                 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
 421                                         R_028980_ALU_CONST_CACHE_VS_0 + index * 4,
 422                                         va_offset, 0xFFFFFFFF, rbuffer, RADEON_USAGE_READ);
 423                 r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_const_buffer);
 424
 425                 rstate = &rctx->vs_const_buffer_resource[index];
 426                 if (!rstate->id) {
 427                         if (rctx->chip_class >= EVERGREEN) {
 428                                 evergreen_pipe_init_buffer_resource(rctx, rstate);
 429                         } else {
 430                                 r600_pipe_init_buffer_resource(rctx, rstate);
 431                         }
 432                 }
 433
 434                 if (rctx->chip_class >= EVERGREEN) {
 435                         evergreen_pipe_mod_buffer_resource(ctx, rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 436                         evergreen_context_pipe_state_set_vs_resource(&rctx->ctx, rstate, index);
 437                 } else {
 438                         r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 439                         r600_context_pipe_state_set_vs_resource(&rctx->ctx, rstate, index);
 440                 }
 441                 break;
 442         case PIPE_SHADER_FRAGMENT:
 443                 rctx->ps_const_buffer.nregs = 0;
 444                 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
 445                                         R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
 446                                         ALIGN_DIVUP(buffer->width0 >> 4, 16),
 447                                         0xFFFFFFFF, NULL, 0);
 448                 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
 449                                         R_028940_ALU_CONST_CACHE_PS_0,
 450                                         va_offset, 0xFFFFFFFF, rbuffer, RADEON_USAGE_READ);
 451                 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_const_buffer);
 452
 453                 rstate = &rctx->ps_const_buffer_resource[index];
 454                 if (!rstate->id) {
 455                         if (rctx->chip_class >= EVERGREEN) {
 456                                 evergreen_pipe_init_buffer_resource(rctx, rstate);
 457                         } else {
 458                                 r600_pipe_init_buffer_resource(rctx, rstate);
 459                         }
 460                 }
 461                 if (rctx->chip_class >= EVERGREEN) {
 462                         evergreen_pipe_mod_buffer_resource(ctx, rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 463                         evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, rstate, index);
 464                 } else {
 465                         r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 466                         r600_context_pipe_state_set_ps_resource(&rctx->ctx, rstate, index);
 467                 }
 468                 break;
 469         default:
 470                 R600_ERR("unsupported %d\n", shader);
 471                 return;
 472         }
 473
 474         if (buffer != &rbuffer->b.b.b)
 475                 pipe_resource_reference((struct pipe_resource**)&rbuffer, NULL);
 476 }
 477
 478 struct pipe_stream_output_target *
 479 r600_create_so_target(struct pipe_context *ctx,
 480                       struct pipe_resource *buffer,
 481                       unsigned buffer_offset,
 482                       unsigned buffer_size)
 483 {
 484         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 485         struct r600_so_target *t;
 486         void *ptr;
 487
 488         t = CALLOC_STRUCT(r600_so_target);
 489         if (!t) {
 490                 return NULL;
 491         }
 492
 493         t->b.reference.count = 1;
 494         t->b.context = ctx;
 495         pipe_resource_reference(&t->b.buffer, buffer);
 496         t->b.buffer_offset = buffer_offset;
 497         t->b.buffer_size = buffer_size;
 498
 499         t->filled_size = (struct r600_resource*)
 500                 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4);
 501         ptr = rctx->ws->buffer_map(t->filled_size->buf, rctx->ctx.cs, PIPE_TRANSFER_WRITE);
 502         memset(ptr, 0, t->filled_size->buf->size);
 503         rctx->ws->buffer_unmap(t->filled_size->buf);
 504
 505         return &t->b;
 506 }
 507
 508 void r600_so_target_destroy(struct pipe_context *ctx,
 509                             struct pipe_stream_output_target *target)
 510 {
 511         struct r600_so_target *t = (struct r600_so_target*)target;
 512         pipe_resource_reference(&t->b.buffer, NULL);
 513         pipe_resource_reference((struct pipe_resource**)&t->filled_size, NULL);
 514         FREE(t);
 515 }
 516
 517 void r600_set_so_targets(struct pipe_context *ctx,
 518                          unsigned num_targets,
 519                          struct pipe_stream_output_target **targets,
 520                          unsigned append_bitmask)
 521 {
 522         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 523         unsigned i;
 524
 525         /* Stop streamout. */
 526         if (rctx->ctx.num_so_targets) {
 527                 r600_context_streamout_end(&rctx->ctx);
 528         }
 529
 530         /* Set the new targets. */
 531         for (i = 0; i < num_targets; i++) {
 532                 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->ctx.so_targets[i], targets[i]);
 533         }
 534         for (; i < rctx->ctx.num_so_targets; i++) {
 535                 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->ctx.so_targets[i], NULL);
 536         }
 537
 538         rctx->ctx.num_so_targets = num_targets;
 539         rctx->ctx.streamout_start = num_targets != 0;
 540         rctx->ctx.streamout_append_bitmask = append_bitmask;
 541 }
 542
 543 static void r600_vertex_buffer_update(struct r600_pipe_context *rctx)
 544 {
 545         struct r600_pipe_resource_state *rstate;
 546         struct r600_resource *rbuffer;
 547         struct pipe_vertex_buffer *vertex_buffer;
 548         unsigned i, count, offset;
 549
 550         if (rctx->vertex_elements->vbuffer_need_offset) {
 551                 /* one resource per vertex elements */
 552                 count = rctx->vertex_elements->count;
 553         } else {
 554                 /* bind vertex buffer once */
 555                 count = rctx->vbuf_mgr->nr_real_vertex_buffers;
 556         }
 557
 558         for (i = 0 ; i < count; i++) {
 559                 rstate = &rctx->fs_resource[i];
 560
 561                 if (rctx->vertex_elements->vbuffer_need_offset) {
 562                         /* one resource per vertex elements */
 563                         unsigned vbuffer_index;
 564                         vbuffer_index = rctx->vertex_elements->elements[i].vertex_buffer_index;
 565                         vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[vbuffer_index];
 566                         rbuffer = (struct r600_resource*)vertex_buffer->buffer;
 567                         offset = rctx->vertex_elements->vbuffer_offset[i];
 568                 } else {
 569                         /* bind vertex buffer once */
 570                         vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[i];
 571                         rbuffer = (struct r600_resource*)vertex_buffer->buffer;
 572                         offset = 0;
 573                 }
 574                 if (vertex_buffer == NULL || rbuffer == NULL)
 575                         continue;
 576                 offset += vertex_buffer->buffer_offset;
 577
 578                 if (!rstate->id) {
 579                         if (rctx->chip_class >= EVERGREEN) {
 580                                 evergreen_pipe_init_buffer_resource(rctx, rstate);
 581                         } else {
 582                                 r600_pipe_init_buffer_resource(rctx, rstate);
 583                         }
 584                 }
 585
 586                 if (rctx->chip_class >= EVERGREEN) {
 587                         evergreen_pipe_mod_buffer_resource(&rctx->context, rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ);
 588                         evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, rstate, i);
 589                 } else {
 590                         r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ);
 591                         r600_context_pipe_state_set_fs_resource(&rctx->ctx, rstate, i);
 592                 }
 593         }
 594 }
 595
 596 static int r600_shader_rebuild(struct pipe_context * ctx, struct r600_pipe_shader * shader)
 597 {
 598         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 599         int r;
 600
 601         r600_pipe_shader_destroy(ctx, shader);
 602         r = r600_pipe_shader_create(ctx, shader);
 603         if (r) {
 604                 return r;
 605         }
 606         r600_context_pipe_state_set(&rctx->ctx, &shader->rstate);
 607
 608         return 0;
 609 }
 610
 611 static void r600_update_derived_state(struct r600_pipe_context *rctx)
 612 {
 613         struct pipe_context * ctx = (struct pipe_context*)rctx;
 614         struct r600_pipe_state rstate;
 615         unsigned user_clip_plane_enable;
 616         unsigned clip_dist_enable;
 617
 618         if (rctx->vs_shader->shader.clip_dist_write || rctx->vs_shader->shader.vs_prohibit_ucps)
 619                 user_clip_plane_enable = 0;
 620         else
 621                 user_clip_plane_enable = rctx->rasterizer->clip_plane_enable & 0x3F;
 622
 623         clip_dist_enable = rctx->rasterizer->clip_plane_enable & rctx->vs_shader->shader.clip_dist_write;
 624         rstate.nregs = 0;
 625
 626         if (user_clip_plane_enable != rctx->user_clip_plane_enable) {
 627                 r600_pipe_state_add_reg(&rstate, R_028810_PA_CL_CLIP_CNTL, user_clip_plane_enable , 0x3F, NULL, 0);
 628                 rctx->user_clip_plane_enable = user_clip_plane_enable;
 629         }
 630
 631         if (clip_dist_enable != rctx->clip_dist_enable) {
 632                 r600_pipe_state_add_reg(&rstate, R_02881C_PA_CL_VS_OUT_CNTL, clip_dist_enable, 0xFF, NULL, 0);
 633                 rctx->clip_dist_enable = clip_dist_enable;
 634         }
 635
 636         if (rstate.nregs)
 637                 r600_context_pipe_state_set(&rctx->ctx, &rstate);
 638
 639         if (!rctx->blitter->running) {
 640                 if (rctx->have_depth_fb || rctx->have_depth_texture)
 641                         r600_flush_depth_textures(rctx);
 642         }
 643
 644         if (rctx->chip_class < EVERGREEN) {
 645                 r600_update_sampler_states(rctx);
 646         }
 647
 648         if ((rctx->ps_shader->shader.two_side != rctx->two_side) ||
 649             ((rctx->chip_class >= EVERGREEN) && rctx->ps_shader->shader.fs_write_all &&
 650              (rctx->ps_shader->shader.nr_cbufs != rctx->nr_cbufs))) {
 651                 r600_shader_rebuild(&rctx->context, rctx->ps_shader);
 652         }
 653
 654         if (rctx->alpha_ref_dirty) {
 655                 r600_update_alpha_ref(rctx);
 656         }
 657
 658         if (rctx->ps_shader && ((rctx->sprite_coord_enable &&
 659                 (rctx->ps_shader->sprite_coord_enable != rctx->sprite_coord_enable)) ||
 660                 (rctx->rasterizer && rctx->rasterizer->flatshade != rctx->ps_shader->flatshade))) {
 661
 662                 if (rctx->chip_class >= EVERGREEN)
 663                         evergreen_pipe_shader_ps(ctx, rctx->ps_shader);
 664                 else
 665                         r600_pipe_shader_ps(ctx, rctx->ps_shader);
 666
 667                 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_shader->rstate);
 668         }
 669
 670 }
 671
 672 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
 673 {
 674         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 675         struct pipe_draw_info info = *dinfo;
 676         struct r600_draw rdraw = {};
 677         struct pipe_index_buffer ib = {};
 678         unsigned prim, mask, ls_mask = 0;
 679
 680         if ((!info.count && (info.indexed || !info.count_from_stream_output)) ||
 681             (info.indexed && !rctx->vbuf_mgr->index_buffer.buffer) ||
 682             !r600_conv_pipe_prim(info.mode, &prim)) {
 683                 return;
 684         }
 685
 686         if (!rctx->ps_shader || !rctx->vs_shader)
 687                 return;
 688
 689         r600_update_derived_state(rctx);
 690
 691         u_vbuf_draw_begin(rctx->vbuf_mgr, &info);
 692         r600_vertex_buffer_update(rctx);
 693
 694         rdraw.vgt_num_indices = info.count;
 695         rdraw.vgt_num_instances = info.instance_count;
 696
 697         if (info.indexed) {
 698                 /* Initialize the index buffer struct. */
 699                 pipe_resource_reference(&ib.buffer, rctx->vbuf_mgr->index_buffer.buffer);
 700                 ib.index_size = rctx->vbuf_mgr->index_buffer.index_size;
 701                 ib.offset = rctx->vbuf_mgr->index_buffer.offset + info.start * ib.index_size;
 702
 703                 /* Translate or upload, if needed. */
 704                 r600_translate_index_buffer(rctx, &ib, info.count);
 705
 706                 if (u_vbuf_resource(ib.buffer)->user_ptr) {
 707                         r600_upload_index_buffer(rctx, &ib, info.count);
 708                 }
 709
 710                 /* Initialize the r600_draw struct with index buffer info. */
 711                 if (ib.index_size == 4) {
 712                         rdraw.vgt_index_type = VGT_INDEX_32 |
 713                                 (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0);
 714                 } else {
 715                         rdraw.vgt_index_type = VGT_INDEX_16 |
 716                                 (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0);
 717                 }
 718                 rdraw.indices = (struct r600_resource*)ib.buffer;
 719                 rdraw.indices_bo_offset = ib.offset;
 720                 rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_DMA;
 721         } else {
 722                 info.index_bias = info.start;
 723                 rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_AUTO_INDEX;
 724                 if (info.count_from_stream_output) {
 725                         rdraw.vgt_draw_initiator |= S_0287F0_USE_OPAQUE(1);
 726
 727                         r600_context_draw_opaque_count(&rctx->ctx, (struct r600_so_target*)info.count_from_stream_output);
 728                 }
 729         }
 730
 731         rctx->ctx.vs_so_stride_in_dw = rctx->vs_shader->so.stride;
 732
 733         mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
 734
 735         if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
 736                 rctx->vgt.id = R600_PIPE_STATE_VGT;
 737                 rctx->vgt.nregs = 0;
 738                 r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL, 0);
 739                 r600_pipe_state_add_reg(&rctx->vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL, 0);
 740                 r600_pipe_state_add_reg(&rctx->vgt, R_028400_VGT_MAX_VTX_INDX, ~0, 0xFFFFFFFF, NULL, 0);
 741                 r600_pipe_state_add_reg(&rctx->vgt, R_028404_VGT_MIN_VTX_INDX, 0, 0xFFFFFFFF, NULL, 0);
 742                 r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias, 0xFFFFFFFF, NULL, 0);
 743                 r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index, 0xFFFFFFFF, NULL, 0);
 744                 r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart, 0xFFFFFFFF, NULL, 0);
 745                 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0xFFFFFFFF, NULL, 0);
 746                 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance, 0xFFFFFFFF, NULL, 0);
 747                 r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE,
 748                                         0,
 749                                         S_028A0C_AUTO_RESET_CNTL(3), NULL, 0);
 750                 r600_pipe_state_add_reg(&rctx->vgt, R_028814_PA_SU_SC_MODE_CNTL,
 751                                         0,
 752                                         S_028814_PROVOKING_VTX_LAST(1), NULL, 0);
 753         }
 754
 755         rctx->vgt.nregs = 0;
 756         r600_pipe_state_mod_reg(&rctx->vgt, prim);
 757         r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_target_mask & mask);
 758         r600_pipe_state_mod_reg(&rctx->vgt, ~0);
 759         r600_pipe_state_mod_reg(&rctx->vgt, 0);
 760         r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
 761         r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
 762         r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart);
 763         r600_pipe_state_mod_reg(&rctx->vgt, 0);
 764         r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance);
 765
 766         if (prim == V_008958_DI_PT_LINELIST)
 767                 ls_mask = 1;
 768         else if (prim == V_008958_DI_PT_LINESTRIP)
 769                 ls_mask = 2;
 770         r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask));
 771
 772         if (info.mode == PIPE_PRIM_QUADS || info.mode == PIPE_PRIM_QUAD_STRIP || info.mode == PIPE_PRIM_POLYGON) {
 773                 r600_pipe_state_mod_reg(&rctx->vgt, S_028814_PROVOKING_VTX_LAST(1));
 774         }
 775
 776         r600_context_pipe_state_set(&rctx->ctx, &rctx->vgt);
 777
 778         if (rctx->chip_class >= EVERGREEN) {
 779                 evergreen_context_draw(&rctx->ctx, &rdraw);
 780         } else {
 781                 r600_context_draw(&rctx->ctx, &rdraw);
 782         }
 783
 784         if (rctx->framebuffer.zsbuf)
 785         {
 786                 struct pipe_resource *tex = rctx->framebuffer.zsbuf->texture;
 787                 ((struct r600_resource_texture *)tex)->dirty_db = TRUE;
 788         }
 789
 790         pipe_resource_reference(&ib.buffer, NULL);
 791         u_vbuf_draw_end(rctx->vbuf_mgr);
 792 }
 793
 794 void _r600_pipe_state_add_reg(struct r600_context *ctx,
 795                               struct r600_pipe_state *state,
 796                               u32 offset, u32 value, u32 mask,
 797                               u32 range_id, u32 block_id,
 798                               struct r600_resource *bo,
 799                               enum radeon_bo_usage usage)
 800 {
 801         struct r600_range *range;
 802         struct r600_block *block;
 803
 804         if (bo) assert(usage);
 805
 806         range = &ctx->range[range_id];
 807         block = range->blocks[block_id];
 808         state->regs[state->nregs].block = block;
 809         state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
 810
 811         state->regs[state->nregs].value = value;
 812         state->regs[state->nregs].mask = mask;
 813         state->regs[state->nregs].bo = bo;
 814         state->regs[state->nregs].bo_usage = usage;
 815
 816         state->nregs++;
 817         assert(state->nregs < R600_BLOCK_MAX_REG);
 818 }
 819
 820 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
 821                                      u32 offset, u32 value, u32 mask,
 822                                      struct r600_resource *bo,
 823                                      enum radeon_bo_usage usage)
 824 {
 825         if (bo) assert(usage);
 826
 827         state->regs[state->nregs].id = offset;
 828         state->regs[state->nregs].block = NULL;
 829         state->regs[state->nregs].value = value;
 830         state->regs[state->nregs].mask = mask;
 831         state->regs[state->nregs].bo = bo;
 832         state->regs[state->nregs].bo_usage = usage;
 833
 834         state->nregs++;
 835         assert(state->nregs < R600_BLOCK_MAX_REG);
 836 }