2 * Copyright 2010 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
27 #include "util/u_blitter.h"
28 #include "util/u_memory.h"
29 #include "util/u_format.h"
30 #include "pipebuffer/pb_buffer.h"
31 #include "pipe/p_shader_tokens.h"
32 #include "tgsi/tgsi_parse.h"
33 #include "r600_formats.h"
34 #include "r600_pipe.h"
37 static void r600_emit_surface_sync(struct r600_context
*rctx
, struct r600_atom
*atom
)
39 struct radeon_winsys_cs
*cs
= rctx
->cs
;
40 struct r600_atom_surface_sync
*a
= (struct r600_atom_surface_sync
*)atom
;
42 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SURFACE_SYNC
, 3, 0);
43 cs
->buf
[cs
->cdw
++] = a
->flush_flags
; /* CP_COHER_CNTL */
44 cs
->buf
[cs
->cdw
++] = 0xffffffff; /* CP_COHER_SIZE */
45 cs
->buf
[cs
->cdw
++] = 0; /* CP_COHER_BASE */
46 cs
->buf
[cs
->cdw
++] = 0x0000000A; /* POLL_INTERVAL */
51 static void r600_emit_r6xx_flush_and_inv(struct r600_context
*rctx
, struct r600_atom
*atom
)
53 struct radeon_winsys_cs
*cs
= rctx
->cs
;
54 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_EVENT_WRITE
, 0, 0);
55 cs
->buf
[cs
->cdw
++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT
) | EVENT_INDEX(0);
58 static void r600_init_atom(struct r600_atom
*atom
,
59 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
61 enum r600_atom_flags flags
)
64 atom
->num_dw
= num_dw
;
68 void r600_init_common_atoms(struct r600_context
*rctx
)
70 r600_init_atom(&rctx
->atom_surface_sync
.atom
, r600_emit_surface_sync
, 5, EMIT_EARLY
);
71 r600_init_atom(&rctx
->atom_r6xx_flush_and_inv
, r600_emit_r6xx_flush_and_inv
, 2, EMIT_EARLY
);
74 unsigned r600_get_cb_flush_flags(struct r600_context
*rctx
)
78 if (rctx
->framebuffer
.nr_cbufs
) {
79 flags
|= S_0085F0_CB_ACTION_ENA(1) |
80 (((1 << rctx
->framebuffer
.nr_cbufs
) - 1) << S_0085F0_CB0_DEST_BASE_ENA_SHIFT
);
83 /* Workaround for broken flushing on some R6xx chipsets. */
84 if (rctx
->family
== CHIP_RV670
||
85 rctx
->family
== CHIP_RS780
||
86 rctx
->family
== CHIP_RS880
) {
87 flags
|= S_0085F0_CB1_DEST_BASE_ENA(1) |
88 S_0085F0_DEST_BASE_0_ENA(1);
93 void r600_texture_barrier(struct pipe_context
*ctx
)
95 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
97 rctx
->atom_surface_sync
.flush_flags
|= S_0085F0_TC_ACTION_ENA(1) | r600_get_cb_flush_flags(rctx
);
98 r600_atom_dirty(rctx
, &rctx
->atom_surface_sync
.atom
);
101 static bool r600_conv_pipe_prim(unsigned pprim
, unsigned *prim
)
103 static const int prim_conv
[] = {
104 V_008958_DI_PT_POINTLIST
,
105 V_008958_DI_PT_LINELIST
,
106 V_008958_DI_PT_LINELOOP
,
107 V_008958_DI_PT_LINESTRIP
,
108 V_008958_DI_PT_TRILIST
,
109 V_008958_DI_PT_TRISTRIP
,
110 V_008958_DI_PT_TRIFAN
,
111 V_008958_DI_PT_QUADLIST
,
112 V_008958_DI_PT_QUADSTRIP
,
113 V_008958_DI_PT_POLYGON
,
120 *prim
= prim_conv
[pprim
];
122 fprintf(stderr
, "%s:%d unsupported %d\n", __func__
, __LINE__
, pprim
);
128 /* common state between evergreen and r600 */
129 void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
)
131 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
132 struct r600_pipe_blend
*blend
= (struct r600_pipe_blend
*)state
;
133 struct r600_pipe_state
*rstate
;
137 rstate
= &blend
->rstate
;
138 rctx
->states
[rstate
->id
] = rstate
;
139 rctx
->cb_target_mask
= blend
->cb_target_mask
;
141 /* Replace every bit except MULTIWRITE_ENABLE. */
142 rctx
->cb_color_control
&= ~C_028808_MULTIWRITE_ENABLE
;
143 rctx
->cb_color_control
|= blend
->cb_color_control
& C_028808_MULTIWRITE_ENABLE
;
145 r600_context_pipe_state_set(rctx
, rstate
);
148 void r600_set_blend_color(struct pipe_context
*ctx
,
149 const struct pipe_blend_color
*state
)
151 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
152 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
157 rstate
->id
= R600_PIPE_STATE_BLEND_COLOR
;
158 r600_pipe_state_add_reg(rstate
, R_028414_CB_BLEND_RED
, fui(state
->color
[0]), NULL
, 0);
159 r600_pipe_state_add_reg(rstate
, R_028418_CB_BLEND_GREEN
, fui(state
->color
[1]), NULL
, 0);
160 r600_pipe_state_add_reg(rstate
, R_02841C_CB_BLEND_BLUE
, fui(state
->color
[2]), NULL
, 0);
161 r600_pipe_state_add_reg(rstate
, R_028420_CB_BLEND_ALPHA
, fui(state
->color
[3]), NULL
, 0);
163 free(rctx
->states
[R600_PIPE_STATE_BLEND_COLOR
]);
164 rctx
->states
[R600_PIPE_STATE_BLEND_COLOR
] = rstate
;
165 r600_context_pipe_state_set(rctx
, rstate
);
168 static void r600_set_stencil_ref(struct pipe_context
*ctx
,
169 const struct r600_stencil_ref
*state
)
171 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
172 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
177 rstate
->id
= R600_PIPE_STATE_STENCIL_REF
;
178 r600_pipe_state_add_reg(rstate
,
179 R_028430_DB_STENCILREFMASK
,
180 S_028430_STENCILREF(state
->ref_value
[0]) |
181 S_028430_STENCILMASK(state
->valuemask
[0]) |
182 S_028430_STENCILWRITEMASK(state
->writemask
[0]),
184 r600_pipe_state_add_reg(rstate
,
185 R_028434_DB_STENCILREFMASK_BF
,
186 S_028434_STENCILREF_BF(state
->ref_value
[1]) |
187 S_028434_STENCILMASK_BF(state
->valuemask
[1]) |
188 S_028434_STENCILWRITEMASK_BF(state
->writemask
[1]),
191 free(rctx
->states
[R600_PIPE_STATE_STENCIL_REF
]);
192 rctx
->states
[R600_PIPE_STATE_STENCIL_REF
] = rstate
;
193 r600_context_pipe_state_set(rctx
, rstate
);
196 void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
197 const struct pipe_stencil_ref
*state
)
199 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
200 struct r600_pipe_dsa
*dsa
= (struct r600_pipe_dsa
*)rctx
->states
[R600_PIPE_STATE_DSA
];
201 struct r600_stencil_ref ref
;
203 rctx
->stencil_ref
= *state
;
208 ref
.ref_value
[0] = state
->ref_value
[0];
209 ref
.ref_value
[1] = state
->ref_value
[1];
210 ref
.valuemask
[0] = dsa
->valuemask
[0];
211 ref
.valuemask
[1] = dsa
->valuemask
[1];
212 ref
.writemask
[0] = dsa
->writemask
[0];
213 ref
.writemask
[1] = dsa
->writemask
[1];
215 r600_set_stencil_ref(ctx
, &ref
);
218 void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
220 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
221 struct r600_pipe_dsa
*dsa
= state
;
222 struct r600_pipe_state
*rstate
;
223 struct r600_stencil_ref ref
;
227 rstate
= &dsa
->rstate
;
228 rctx
->states
[rstate
->id
] = rstate
;
229 rctx
->alpha_ref
= dsa
->alpha_ref
;
230 rctx
->alpha_ref_dirty
= true;
231 r600_context_pipe_state_set(rctx
, rstate
);
233 ref
.ref_value
[0] = rctx
->stencil_ref
.ref_value
[0];
234 ref
.ref_value
[1] = rctx
->stencil_ref
.ref_value
[1];
235 ref
.valuemask
[0] = dsa
->valuemask
[0];
236 ref
.valuemask
[1] = dsa
->valuemask
[1];
237 ref
.writemask
[0] = dsa
->writemask
[0];
238 ref
.writemask
[1] = dsa
->writemask
[1];
240 r600_set_stencil_ref(ctx
, &ref
);
243 void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
)
245 struct r600_pipe_rasterizer
*rs
= (struct r600_pipe_rasterizer
*)state
;
246 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
251 rctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
252 rctx
->two_side
= rs
->two_side
;
253 rctx
->pa_sc_line_stipple
= rs
->pa_sc_line_stipple
;
254 rctx
->pa_cl_clip_cntl
= rs
->pa_cl_clip_cntl
;
256 rctx
->rasterizer
= rs
;
258 rctx
->states
[rs
->rstate
.id
] = &rs
->rstate
;
259 r600_context_pipe_state_set(rctx
, &rs
->rstate
);
261 if (rctx
->chip_class
>= EVERGREEN
) {
262 evergreen_polygon_offset_update(rctx
);
264 r600_polygon_offset_update(rctx
);
268 void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
)
270 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
271 struct r600_pipe_rasterizer
*rs
= (struct r600_pipe_rasterizer
*)state
;
273 if (rctx
->rasterizer
== rs
) {
274 rctx
->rasterizer
= NULL
;
276 if (rctx
->states
[rs
->rstate
.id
] == &rs
->rstate
) {
277 rctx
->states
[rs
->rstate
.id
] = NULL
;
282 void r600_sampler_view_destroy(struct pipe_context
*ctx
,
283 struct pipe_sampler_view
*state
)
285 struct r600_pipe_sampler_view
*resource
= (struct r600_pipe_sampler_view
*)state
;
287 pipe_resource_reference(&state
->texture
, NULL
);
291 void r600_delete_state(struct pipe_context
*ctx
, void *state
)
293 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
294 struct r600_pipe_state
*rstate
= (struct r600_pipe_state
*)state
;
296 if (rctx
->states
[rstate
->id
] == rstate
) {
297 rctx
->states
[rstate
->id
] = NULL
;
299 for (int i
= 0; i
< rstate
->nregs
; i
++) {
300 pipe_resource_reference((struct pipe_resource
**)&rstate
->regs
[i
].bo
, NULL
);
305 void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
307 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
308 struct r600_vertex_element
*v
= (struct r600_vertex_element
*)state
;
310 rctx
->vertex_elements
= v
;
312 r600_inval_shader_cache(rctx
);
313 u_vbuf_bind_vertex_elements(rctx
->vbuf_mgr
, state
,
316 rctx
->states
[v
->rstate
.id
] = &v
->rstate
;
317 r600_context_pipe_state_set(rctx
, &v
->rstate
);
321 void r600_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
323 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
324 struct r600_vertex_element
*v
= (struct r600_vertex_element
*)state
;
326 if (rctx
->states
[v
->rstate
.id
] == &v
->rstate
) {
327 rctx
->states
[v
->rstate
.id
] = NULL
;
329 if (rctx
->vertex_elements
== state
)
330 rctx
->vertex_elements
= NULL
;
332 pipe_resource_reference((struct pipe_resource
**)&v
->fetch_shader
, NULL
);
333 u_vbuf_destroy_vertex_elements(rctx
->vbuf_mgr
, v
->vmgr_elements
);
338 void r600_set_index_buffer(struct pipe_context
*ctx
,
339 const struct pipe_index_buffer
*ib
)
341 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
343 u_vbuf_set_index_buffer(rctx
->vbuf_mgr
, ib
);
346 void r600_set_vertex_buffers(struct pipe_context
*ctx
, unsigned count
,
347 const struct pipe_vertex_buffer
*buffers
)
349 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
353 for (i
= 0; i
< count
; i
++) {
354 if (!buffers
[i
].buffer
) {
355 if (rctx
->chip_class
>= EVERGREEN
) {
356 evergreen_context_pipe_state_set_fs_resource(rctx
, NULL
, i
);
358 r600_context_pipe_state_set_fs_resource(rctx
, NULL
, i
);
362 for (; i
< rctx
->vbuf_mgr
->nr_real_vertex_buffers
; i
++) {
363 if (rctx
->chip_class
>= EVERGREEN
) {
364 evergreen_context_pipe_state_set_fs_resource(rctx
, NULL
, i
);
366 r600_context_pipe_state_set_fs_resource(rctx
, NULL
, i
);
370 u_vbuf_set_vertex_buffers(rctx
->vbuf_mgr
, count
, buffers
);
373 void *r600_create_vertex_elements(struct pipe_context
*ctx
,
375 const struct pipe_vertex_element
*elements
)
377 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
378 struct r600_vertex_element
*v
= CALLOC_STRUCT(r600_vertex_element
);
386 u_vbuf_create_vertex_elements(rctx
->vbuf_mgr
, count
,
387 elements
, v
->elements
);
389 if (r600_vertex_elements_build_fetch_shader(rctx
, v
)) {
397 void *r600_create_shader_state(struct pipe_context
*ctx
,
398 const struct pipe_shader_state
*state
)
400 struct r600_pipe_shader
*shader
= CALLOC_STRUCT(r600_pipe_shader
);
403 shader
->tokens
= tgsi_dup_tokens(state
->tokens
);
404 shader
->so
= state
->stream_output
;
406 r
= r600_pipe_shader_create(ctx
, shader
);
413 void r600_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
415 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
417 /* TODO delete old shader */
418 rctx
->ps_shader
= (struct r600_pipe_shader
*)state
;
420 r600_inval_shader_cache(rctx
);
421 r600_context_pipe_state_set(rctx
, &rctx
->ps_shader
->rstate
);
423 rctx
->cb_color_control
&= C_028808_MULTIWRITE_ENABLE
;
424 rctx
->cb_color_control
|= S_028808_MULTIWRITE_ENABLE(!!rctx
->ps_shader
->shader
.fs_write_all
);
426 if (rctx
->ps_shader
&& rctx
->vs_shader
) {
427 r600_adjust_gprs(rctx
);
431 void r600_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
433 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
435 /* TODO delete old shader */
436 rctx
->vs_shader
= (struct r600_pipe_shader
*)state
;
438 r600_inval_shader_cache(rctx
);
439 r600_context_pipe_state_set(rctx
, &rctx
->vs_shader
->rstate
);
441 if (rctx
->ps_shader
&& rctx
->vs_shader
) {
442 r600_adjust_gprs(rctx
);
446 void r600_delete_ps_shader(struct pipe_context
*ctx
, void *state
)
448 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
449 struct r600_pipe_shader
*shader
= (struct r600_pipe_shader
*)state
;
451 if (rctx
->ps_shader
== shader
) {
452 rctx
->ps_shader
= NULL
;
455 free(shader
->tokens
);
456 r600_pipe_shader_destroy(ctx
, shader
);
460 void r600_delete_vs_shader(struct pipe_context
*ctx
, void *state
)
462 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
463 struct r600_pipe_shader
*shader
= (struct r600_pipe_shader
*)state
;
465 if (rctx
->vs_shader
== shader
) {
466 rctx
->vs_shader
= NULL
;
469 free(shader
->tokens
);
470 r600_pipe_shader_destroy(ctx
, shader
);
474 static void r600_update_alpha_ref(struct r600_context
*rctx
)
477 struct r600_pipe_state rstate
;
479 alpha_ref
= rctx
->alpha_ref
;
481 if (rctx
->export_16bpc
)
482 alpha_ref
&= ~0x1FFF;
483 r600_pipe_state_add_reg(&rstate
, R_028438_SX_ALPHA_REF
, alpha_ref
, NULL
, 0);
485 r600_context_pipe_state_set(rctx
, &rstate
);
486 rctx
->alpha_ref_dirty
= false;
489 void r600_set_constant_buffer(struct pipe_context
*ctx
, uint shader
, uint index
,
490 struct pipe_resource
*buffer
)
492 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
493 struct r600_resource
*rbuffer
= r600_resource(buffer
);
494 struct r600_pipe_resource_state
*rstate
;
498 /* Note that the state tracker can unbind constant buffers by
501 if (buffer
== NULL
) {
505 r600_inval_shader_cache(rctx
);
507 r600_upload_const_buffer(rctx
, &rbuffer
, &offset
);
508 va_offset
= r600_resource_va(ctx
->screen
, (void*)rbuffer
);
513 case PIPE_SHADER_VERTEX
:
514 rctx
->vs_const_buffer
.nregs
= 0;
515 r600_pipe_state_add_reg(&rctx
->vs_const_buffer
,
516 R_028180_ALU_CONST_BUFFER_SIZE_VS_0
+ index
* 4,
517 ALIGN_DIVUP(buffer
->width0
>> 4, 16),
519 r600_pipe_state_add_reg(&rctx
->vs_const_buffer
,
520 R_028980_ALU_CONST_CACHE_VS_0
+ index
* 4,
521 va_offset
, rbuffer
, RADEON_USAGE_READ
);
522 r600_context_pipe_state_set(rctx
, &rctx
->vs_const_buffer
);
524 rstate
= &rctx
->vs_const_buffer_resource
[index
];
526 if (rctx
->chip_class
>= EVERGREEN
) {
527 evergreen_pipe_init_buffer_resource(rctx
, rstate
);
529 r600_pipe_init_buffer_resource(rctx
, rstate
);
533 if (rctx
->chip_class
>= EVERGREEN
) {
534 evergreen_pipe_mod_buffer_resource(ctx
, rstate
, rbuffer
, offset
, 16, RADEON_USAGE_READ
);
535 evergreen_context_pipe_state_set_vs_resource(rctx
, rstate
, index
);
537 r600_pipe_mod_buffer_resource(rstate
, rbuffer
, offset
, 16, RADEON_USAGE_READ
);
538 r600_context_pipe_state_set_vs_resource(rctx
, rstate
, index
);
541 case PIPE_SHADER_FRAGMENT
:
542 rctx
->ps_const_buffer
.nregs
= 0;
543 r600_pipe_state_add_reg(&rctx
->ps_const_buffer
,
544 R_028140_ALU_CONST_BUFFER_SIZE_PS_0
,
545 ALIGN_DIVUP(buffer
->width0
>> 4, 16),
547 r600_pipe_state_add_reg(&rctx
->ps_const_buffer
,
548 R_028940_ALU_CONST_CACHE_PS_0
,
549 va_offset
, rbuffer
, RADEON_USAGE_READ
);
550 r600_context_pipe_state_set(rctx
, &rctx
->ps_const_buffer
);
552 rstate
= &rctx
->ps_const_buffer_resource
[index
];
554 if (rctx
->chip_class
>= EVERGREEN
) {
555 evergreen_pipe_init_buffer_resource(rctx
, rstate
);
557 r600_pipe_init_buffer_resource(rctx
, rstate
);
560 if (rctx
->chip_class
>= EVERGREEN
) {
561 evergreen_pipe_mod_buffer_resource(ctx
, rstate
, rbuffer
, offset
, 16, RADEON_USAGE_READ
);
562 evergreen_context_pipe_state_set_ps_resource(rctx
, rstate
, index
);
564 r600_pipe_mod_buffer_resource(rstate
, rbuffer
, offset
, 16, RADEON_USAGE_READ
);
565 r600_context_pipe_state_set_ps_resource(rctx
, rstate
, index
);
569 R600_ERR("unsupported %d\n", shader
);
573 if (buffer
!= &rbuffer
->b
.b
.b
)
574 pipe_resource_reference((struct pipe_resource
**)&rbuffer
, NULL
);
577 struct pipe_stream_output_target
*
578 r600_create_so_target(struct pipe_context
*ctx
,
579 struct pipe_resource
*buffer
,
580 unsigned buffer_offset
,
581 unsigned buffer_size
)
583 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
584 struct r600_so_target
*t
;
587 t
= CALLOC_STRUCT(r600_so_target
);
592 t
->b
.reference
.count
= 1;
594 pipe_resource_reference(&t
->b
.buffer
, buffer
);
595 t
->b
.buffer_offset
= buffer_offset
;
596 t
->b
.buffer_size
= buffer_size
;
598 t
->filled_size
= (struct r600_resource
*)
599 pipe_buffer_create(ctx
->screen
, PIPE_BIND_CUSTOM
, PIPE_USAGE_STATIC
, 4);
600 ptr
= rctx
->ws
->buffer_map(t
->filled_size
->buf
, rctx
->cs
, PIPE_TRANSFER_WRITE
);
601 memset(ptr
, 0, t
->filled_size
->buf
->size
);
602 rctx
->ws
->buffer_unmap(t
->filled_size
->buf
);
607 void r600_so_target_destroy(struct pipe_context
*ctx
,
608 struct pipe_stream_output_target
*target
)
610 struct r600_so_target
*t
= (struct r600_so_target
*)target
;
611 pipe_resource_reference(&t
->b
.buffer
, NULL
);
612 pipe_resource_reference((struct pipe_resource
**)&t
->filled_size
, NULL
);
616 void r600_set_so_targets(struct pipe_context
*ctx
,
617 unsigned num_targets
,
618 struct pipe_stream_output_target
**targets
,
619 unsigned append_bitmask
)
621 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
624 /* Stop streamout. */
625 if (rctx
->num_so_targets
) {
626 r600_context_streamout_end(rctx
);
629 /* Set the new targets. */
630 for (i
= 0; i
< num_targets
; i
++) {
631 pipe_so_target_reference((struct pipe_stream_output_target
**)&rctx
->so_targets
[i
], targets
[i
]);
633 for (; i
< rctx
->num_so_targets
; i
++) {
634 pipe_so_target_reference((struct pipe_stream_output_target
**)&rctx
->so_targets
[i
], NULL
);
637 rctx
->num_so_targets
= num_targets
;
638 rctx
->streamout_start
= num_targets
!= 0;
639 rctx
->streamout_append_bitmask
= append_bitmask
;
642 static void r600_vertex_buffer_update(struct r600_context
*rctx
)
644 struct r600_pipe_resource_state
*rstate
;
645 struct r600_resource
*rbuffer
;
646 struct pipe_vertex_buffer
*vertex_buffer
;
647 unsigned i
, count
, offset
;
649 r600_inval_vertex_cache(rctx
);
651 if (rctx
->vertex_elements
->vbuffer_need_offset
) {
652 /* one resource per vertex elements */
653 count
= rctx
->vertex_elements
->count
;
655 /* bind vertex buffer once */
656 count
= rctx
->vbuf_mgr
->nr_real_vertex_buffers
;
659 for (i
= 0 ; i
< count
; i
++) {
660 rstate
= &rctx
->fs_resource
[i
];
662 if (rctx
->vertex_elements
->vbuffer_need_offset
) {
663 /* one resource per vertex elements */
664 unsigned vbuffer_index
;
665 vbuffer_index
= rctx
->vertex_elements
->elements
[i
].vertex_buffer_index
;
666 vertex_buffer
= &rctx
->vbuf_mgr
->real_vertex_buffer
[vbuffer_index
];
667 rbuffer
= (struct r600_resource
*)vertex_buffer
->buffer
;
668 offset
= rctx
->vertex_elements
->vbuffer_offset
[i
];
670 /* bind vertex buffer once */
671 vertex_buffer
= &rctx
->vbuf_mgr
->real_vertex_buffer
[i
];
672 rbuffer
= (struct r600_resource
*)vertex_buffer
->buffer
;
675 if (vertex_buffer
== NULL
|| rbuffer
== NULL
)
677 offset
+= vertex_buffer
->buffer_offset
;
680 if (rctx
->chip_class
>= EVERGREEN
) {
681 evergreen_pipe_init_buffer_resource(rctx
, rstate
);
683 r600_pipe_init_buffer_resource(rctx
, rstate
);
687 if (rctx
->chip_class
>= EVERGREEN
) {
688 evergreen_pipe_mod_buffer_resource(&rctx
->context
, rstate
, rbuffer
, offset
, vertex_buffer
->stride
, RADEON_USAGE_READ
);
689 evergreen_context_pipe_state_set_fs_resource(rctx
, rstate
, i
);
691 r600_pipe_mod_buffer_resource(rstate
, rbuffer
, offset
, vertex_buffer
->stride
, RADEON_USAGE_READ
);
692 r600_context_pipe_state_set_fs_resource(rctx
, rstate
, i
);
697 static int r600_shader_rebuild(struct pipe_context
* ctx
, struct r600_pipe_shader
* shader
)
699 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
702 r600_pipe_shader_destroy(ctx
, shader
);
703 r
= r600_pipe_shader_create(ctx
, shader
);
707 r600_context_pipe_state_set(rctx
, &shader
->rstate
);
712 static void r600_update_derived_state(struct r600_context
*rctx
)
714 struct pipe_context
* ctx
= (struct pipe_context
*)rctx
;
715 struct r600_pipe_state rstate
;
720 r600_context_pipe_state_set(rctx
, &rstate
);
722 if (!rctx
->blitter
->running
) {
723 if (rctx
->have_depth_fb
|| rctx
->have_depth_texture
)
724 r600_flush_depth_textures(rctx
);
727 if (rctx
->chip_class
< EVERGREEN
) {
728 r600_update_sampler_states(rctx
);
731 if ((rctx
->ps_shader
->shader
.two_side
!= rctx
->two_side
) ||
732 ((rctx
->chip_class
>= EVERGREEN
) && rctx
->ps_shader
->shader
.fs_write_all
&&
733 (rctx
->ps_shader
->shader
.nr_cbufs
!= rctx
->nr_cbufs
))) {
734 r600_shader_rebuild(&rctx
->context
, rctx
->ps_shader
);
737 if (rctx
->alpha_ref_dirty
) {
738 r600_update_alpha_ref(rctx
);
741 if (rctx
->ps_shader
&& ((rctx
->sprite_coord_enable
&&
742 (rctx
->ps_shader
->sprite_coord_enable
!= rctx
->sprite_coord_enable
)) ||
743 (rctx
->rasterizer
&& rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->flatshade
))) {
745 if (rctx
->chip_class
>= EVERGREEN
)
746 evergreen_pipe_shader_ps(ctx
, rctx
->ps_shader
);
748 r600_pipe_shader_ps(ctx
, rctx
->ps_shader
);
750 r600_context_pipe_state_set(rctx
, &rctx
->ps_shader
->rstate
);
755 void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*dinfo
)
757 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
758 struct r600_pipe_dsa
*dsa
= (struct r600_pipe_dsa
*)rctx
->states
[R600_PIPE_STATE_DSA
];
759 struct pipe_draw_info info
= *dinfo
;
760 struct r600_draw rdraw
= {};
761 struct pipe_index_buffer ib
= {};
762 unsigned prim
, mask
, ls_mask
= 0;
763 struct r600_block
*dirty_block
= NULL
, *next_block
= NULL
;
764 struct r600_atom
*state
= NULL
, *next_state
= NULL
;
766 if ((!info
.count
&& (info
.indexed
|| !info
.count_from_stream_output
)) ||
767 (info
.indexed
&& !rctx
->vbuf_mgr
->index_buffer
.buffer
) ||
768 !r600_conv_pipe_prim(info
.mode
, &prim
)) {
772 if (!rctx
->ps_shader
|| !rctx
->vs_shader
)
775 r600_update_derived_state(rctx
);
777 u_vbuf_draw_begin(rctx
->vbuf_mgr
, &info
);
778 r600_vertex_buffer_update(rctx
);
780 rdraw
.vgt_num_indices
= info
.count
;
781 rdraw
.vgt_num_instances
= info
.instance_count
;
784 /* Initialize the index buffer struct. */
785 pipe_resource_reference(&ib
.buffer
, rctx
->vbuf_mgr
->index_buffer
.buffer
);
786 ib
.index_size
= rctx
->vbuf_mgr
->index_buffer
.index_size
;
787 ib
.offset
= rctx
->vbuf_mgr
->index_buffer
.offset
+ info
.start
* ib
.index_size
;
789 /* Translate or upload, if needed. */
790 r600_translate_index_buffer(rctx
, &ib
, info
.count
);
792 if (u_vbuf_resource(ib
.buffer
)->user_ptr
) {
793 r600_upload_index_buffer(rctx
, &ib
, info
.count
);
796 /* Initialize the r600_draw struct with index buffer info. */
797 if (ib
.index_size
== 4) {
798 rdraw
.vgt_index_type
= VGT_INDEX_32
|
799 (R600_BIG_ENDIAN
? VGT_DMA_SWAP_32_BIT
: 0);
801 rdraw
.vgt_index_type
= VGT_INDEX_16
|
802 (R600_BIG_ENDIAN
? VGT_DMA_SWAP_16_BIT
: 0);
804 rdraw
.indices
= (struct r600_resource
*)ib
.buffer
;
805 rdraw
.indices_bo_offset
= ib
.offset
;
806 rdraw
.vgt_draw_initiator
= V_0287F0_DI_SRC_SEL_DMA
;
808 info
.index_bias
= info
.start
;
809 rdraw
.vgt_draw_initiator
= V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
810 if (info
.count_from_stream_output
) {
811 rdraw
.vgt_draw_initiator
|= S_0287F0_USE_OPAQUE(1);
813 r600_context_draw_opaque_count(rctx
, (struct r600_so_target
*)info
.count_from_stream_output
);
817 mask
= (1ULL << ((unsigned)rctx
->framebuffer
.nr_cbufs
* 4)) - 1;
819 if (rctx
->vgt
.id
!= R600_PIPE_STATE_VGT
) {
820 rctx
->vgt
.id
= R600_PIPE_STATE_VGT
;
822 r600_pipe_state_add_reg(&rctx
->vgt
, R_008958_VGT_PRIMITIVE_TYPE
, prim
, NULL
, 0);
823 r600_pipe_state_add_reg(&rctx
->vgt
, R_028238_CB_TARGET_MASK
, rctx
->cb_target_mask
& mask
, NULL
, 0);
824 r600_pipe_state_add_reg(&rctx
->vgt
, R_028400_VGT_MAX_VTX_INDX
, ~0, NULL
, 0);
825 r600_pipe_state_add_reg(&rctx
->vgt
, R_028404_VGT_MIN_VTX_INDX
, 0, NULL
, 0);
826 r600_pipe_state_add_reg(&rctx
->vgt
, R_028408_VGT_INDX_OFFSET
, info
.index_bias
, NULL
, 0);
827 r600_pipe_state_add_reg(&rctx
->vgt
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
, info
.restart_index
, NULL
, 0);
828 r600_pipe_state_add_reg(&rctx
->vgt
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, info
.primitive_restart
, NULL
, 0);
829 r600_pipe_state_add_reg(&rctx
->vgt
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0, NULL
, 0);
830 r600_pipe_state_add_reg(&rctx
->vgt
, R_03CFF4_SQ_VTX_START_INST_LOC
, info
.start_instance
, NULL
, 0);
831 r600_pipe_state_add_reg(&rctx
->vgt
, R_028A0C_PA_SC_LINE_STIPPLE
, 0, NULL
, 0);
832 if (rctx
->chip_class
<= R700
)
833 r600_pipe_state_add_reg(&rctx
->vgt
, R_028808_CB_COLOR_CONTROL
, rctx
->cb_color_control
, NULL
, 0);
834 r600_pipe_state_add_reg(&rctx
->vgt
, R_02881C_PA_CL_VS_OUT_CNTL
, 0, NULL
, 0);
835 r600_pipe_state_add_reg(&rctx
->vgt
, R_028810_PA_CL_CLIP_CNTL
, 0, NULL
, 0);
839 r600_pipe_state_mod_reg(&rctx
->vgt
, prim
);
840 r600_pipe_state_mod_reg(&rctx
->vgt
, rctx
->cb_target_mask
& mask
);
841 r600_pipe_state_mod_reg(&rctx
->vgt
, ~0);
842 r600_pipe_state_mod_reg(&rctx
->vgt
, 0);
843 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.index_bias
);
844 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.restart_index
);
845 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.primitive_restart
);
846 r600_pipe_state_mod_reg(&rctx
->vgt
, 0);
847 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.start_instance
);
849 if (prim
== V_008958_DI_PT_LINELIST
)
851 else if (prim
== V_008958_DI_PT_LINESTRIP
)
853 r600_pipe_state_mod_reg(&rctx
->vgt
, S_028A0C_AUTO_RESET_CNTL(ls_mask
) | rctx
->pa_sc_line_stipple
);
854 if (rctx
->chip_class
<= R700
)
855 r600_pipe_state_mod_reg(&rctx
->vgt
, rctx
->cb_color_control
);
856 r600_pipe_state_mod_reg(&rctx
->vgt
,
857 rctx
->vs_shader
->pa_cl_vs_out_cntl
|
858 (rctx
->rasterizer
->clip_plane_enable
& rctx
->vs_shader
->shader
.clip_dist_write
));
859 r600_pipe_state_mod_reg(&rctx
->vgt
,
860 rctx
->pa_cl_clip_cntl
|
861 (rctx
->vs_shader
->shader
.clip_dist_write
||
862 rctx
->vs_shader
->shader
.vs_prohibit_ucps
?
863 0 : rctx
->rasterizer
->clip_plane_enable
& 0x3F));
865 r600_context_pipe_state_set(rctx
, &rctx
->vgt
);
867 rdraw
.db_render_override
= dsa
->db_render_override
;
868 rdraw
.db_render_control
= dsa
->db_render_control
;
871 r600_need_cs_space(rctx
, 0, TRUE
);
873 LIST_FOR_EACH_ENTRY_SAFE(state
, next_state
, &rctx
->dirty_states
, head
) {
874 r600_emit_atom(rctx
, state
);
876 LIST_FOR_EACH_ENTRY_SAFE(dirty_block
, next_block
, &rctx
->dirty
,list
) {
877 r600_context_block_emit_dirty(rctx
, dirty_block
);
879 LIST_FOR_EACH_ENTRY_SAFE(dirty_block
, next_block
, &rctx
->resource_dirty
,list
) {
880 r600_context_block_resource_emit_dirty(rctx
, dirty_block
);
882 rctx
->pm4_dirty_cdwords
= 0;
884 /* Enable stream out if needed. */
885 if (rctx
->streamout_start
) {
886 r600_context_streamout_begin(rctx
);
887 rctx
->streamout_start
= FALSE
;
890 if (rctx
->chip_class
>= EVERGREEN
) {
891 evergreen_context_draw(rctx
, &rdraw
);
893 r600_context_draw(rctx
, &rdraw
);
896 rctx
->flags
|= R600_CONTEXT_DST_CACHES_DIRTY
| R600_CONTEXT_DRAW_PENDING
;
898 if (rctx
->framebuffer
.zsbuf
)
900 struct pipe_resource
*tex
= rctx
->framebuffer
.zsbuf
->texture
;
901 ((struct r600_resource_texture
*)tex
)->dirty_db
= TRUE
;
904 pipe_resource_reference(&ib
.buffer
, NULL
);
905 u_vbuf_draw_end(rctx
->vbuf_mgr
);
908 void _r600_pipe_state_add_reg(struct r600_context
*ctx
,
909 struct r600_pipe_state
*state
,
910 uint32_t offset
, uint32_t value
,
911 uint32_t range_id
, uint32_t block_id
,
912 struct r600_resource
*bo
,
913 enum radeon_bo_usage usage
)
915 struct r600_range
*range
;
916 struct r600_block
*block
;
918 if (bo
) assert(usage
);
920 range
= &ctx
->range
[range_id
];
921 block
= range
->blocks
[block_id
];
922 state
->regs
[state
->nregs
].block
= block
;
923 state
->regs
[state
->nregs
].id
= (offset
- block
->start_offset
) >> 2;
925 state
->regs
[state
->nregs
].value
= value
;
926 state
->regs
[state
->nregs
].bo
= bo
;
927 state
->regs
[state
->nregs
].bo_usage
= usage
;
930 assert(state
->nregs
< R600_BLOCK_MAX_REG
);
933 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state
*state
,
934 uint32_t offset
, uint32_t value
,
935 struct r600_resource
*bo
,
936 enum radeon_bo_usage usage
)
938 if (bo
) assert(usage
);
940 state
->regs
[state
->nregs
].id
= offset
;
941 state
->regs
[state
->nregs
].block
= NULL
;
942 state
->regs
[state
->nregs
].value
= value
;
943 state
->regs
[state
->nregs
].bo
= bo
;
944 state
->regs
[state
->nregs
].bo_usage
= usage
;
947 assert(state
->nregs
< R600_BLOCK_MAX_REG
);
950 uint32_t r600_translate_stencil_op(int s_op
)
953 case PIPE_STENCIL_OP_KEEP
:
954 return V_028800_STENCIL_KEEP
;
955 case PIPE_STENCIL_OP_ZERO
:
956 return V_028800_STENCIL_ZERO
;
957 case PIPE_STENCIL_OP_REPLACE
:
958 return V_028800_STENCIL_REPLACE
;
959 case PIPE_STENCIL_OP_INCR
:
960 return V_028800_STENCIL_INCR
;
961 case PIPE_STENCIL_OP_DECR
:
962 return V_028800_STENCIL_DECR
;
963 case PIPE_STENCIL_OP_INCR_WRAP
:
964 return V_028800_STENCIL_INCR_WRAP
;
965 case PIPE_STENCIL_OP_DECR_WRAP
:
966 return V_028800_STENCIL_DECR_WRAP
;
967 case PIPE_STENCIL_OP_INVERT
:
968 return V_028800_STENCIL_INVERT
;
970 R600_ERR("Unknown stencil op %d", s_op
);
977 uint32_t r600_translate_fill(uint32_t func
)
980 case PIPE_POLYGON_MODE_FILL
:
982 case PIPE_POLYGON_MODE_LINE
:
984 case PIPE_POLYGON_MODE_POINT
:
992 unsigned r600_tex_wrap(unsigned wrap
)
996 case PIPE_TEX_WRAP_REPEAT
:
997 return V_03C000_SQ_TEX_WRAP
;
998 case PIPE_TEX_WRAP_CLAMP
:
999 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER
;
1000 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1001 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL
;
1002 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1003 return V_03C000_SQ_TEX_CLAMP_BORDER
;
1004 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1005 return V_03C000_SQ_TEX_MIRROR
;
1006 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1007 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1008 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1009 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1010 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1011 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER
;
1015 unsigned r600_tex_filter(unsigned filter
)
1019 case PIPE_TEX_FILTER_NEAREST
:
1020 return V_03C000_SQ_TEX_XY_FILTER_POINT
;
1021 case PIPE_TEX_FILTER_LINEAR
:
1022 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR
;
1026 unsigned r600_tex_mipfilter(unsigned filter
)
1029 case PIPE_TEX_MIPFILTER_NEAREST
:
1030 return V_03C000_SQ_TEX_Z_FILTER_POINT
;
1031 case PIPE_TEX_MIPFILTER_LINEAR
:
1032 return V_03C000_SQ_TEX_Z_FILTER_LINEAR
;
1034 case PIPE_TEX_MIPFILTER_NONE
:
1035 return V_03C000_SQ_TEX_Z_FILTER_NONE
;
1039 unsigned r600_tex_compare(unsigned compare
)
1043 case PIPE_FUNC_NEVER
:
1044 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER
;
1045 case PIPE_FUNC_LESS
:
1046 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS
;
1047 case PIPE_FUNC_EQUAL
:
1048 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1049 case PIPE_FUNC_LEQUAL
:
1050 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1051 case PIPE_FUNC_GREATER
:
1052 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER
;
1053 case PIPE_FUNC_NOTEQUAL
:
1054 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1055 case PIPE_FUNC_GEQUAL
:
1056 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1057 case PIPE_FUNC_ALWAYS
:
1058 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS
;