src/gallium/drivers/r600/r600_state_common.c

   1 /*
   2  * Copyright 2010 Red Hat Inc.
   3  *           2010 Jerome Glisse
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie <airlied@redhat.com>
  25  *          Jerome Glisse <jglisse@redhat.com>
  26  */
  27 #include "util/u_blitter.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_format.h"
  30 #include "pipebuffer/pb_buffer.h"
  31 #include "pipe/p_shader_tokens.h"
  32 #include "tgsi/tgsi_parse.h"
  33 #include "r600_formats.h"
  34 #include "r600_pipe.h"
  35 #include "r600d.h"
  36
  37 static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
  38 {
  39         static const int prim_conv[] = {
  40                 V_008958_DI_PT_POINTLIST,
  41                 V_008958_DI_PT_LINELIST,
  42                 V_008958_DI_PT_LINELOOP,
  43                 V_008958_DI_PT_LINESTRIP,
  44                 V_008958_DI_PT_TRILIST,
  45                 V_008958_DI_PT_TRISTRIP,
  46                 V_008958_DI_PT_TRIFAN,
  47                 V_008958_DI_PT_QUADLIST,
  48                 V_008958_DI_PT_QUADSTRIP,
  49                 V_008958_DI_PT_POLYGON,
  50                 -1,
  51                 -1,
  52                 -1,
  53                 -1
  54         };
  55
  56         *prim = prim_conv[pprim];
  57         if (*prim == -1) {
  58                 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim);
  59                 return false;
  60         }
  61         return true;
  62 }
  63
  64 /* common state between evergreen and r600 */
  65 void r600_bind_blend_state(struct pipe_context *ctx, void *state)
  66 {
  67         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
  68         struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
  69         struct r600_pipe_state *rstate;
  70
  71         if (state == NULL)
  72                 return;
  73         rstate = &blend->rstate;
  74         rctx->states[rstate->id] = rstate;
  75         rctx->cb_target_mask = blend->cb_target_mask;
  76         r600_context_pipe_state_set(&rctx->ctx, rstate);
  77 }
  78
  79 void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
  80 {
  81         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
  82         struct r600_pipe_dsa *dsa = state;
  83         struct r600_pipe_state *rstate;
  84
  85         if (state == NULL)
  86                 return;
  87         rstate = &dsa->rstate;
  88         rctx->states[rstate->id] = rstate;
  89         rctx->alpha_ref = dsa->alpha_ref;
  90         rctx->alpha_ref_dirty = true;
  91         r600_context_pipe_state_set(&rctx->ctx, rstate);
  92 }
  93
  94 void r600_bind_rs_state(struct pipe_context *ctx, void *state)
  95 {
  96         struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
  97         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
  98
  99         if (state == NULL)
 100                 return;
 101
 102         rctx->sprite_coord_enable = rs->sprite_coord_enable;
 103         rctx->two_side = rs->two_side;
 104
 105         rctx->rasterizer = rs;
 106
 107         rctx->states[rs->rstate.id] = &rs->rstate;
 108         r600_context_pipe_state_set(&rctx->ctx, &rs->rstate);
 109
 110         if (rctx->chip_class >= EVERGREEN) {
 111                 evergreen_polygon_offset_update(rctx);
 112         } else {
 113                 r600_polygon_offset_update(rctx);
 114         }
 115 }
 116
 117 void r600_delete_rs_state(struct pipe_context *ctx, void *state)
 118 {
 119         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 120         struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
 121
 122         if (rctx->rasterizer == rs) {
 123                 rctx->rasterizer = NULL;
 124         }
 125         if (rctx->states[rs->rstate.id] == &rs->rstate) {
 126                 rctx->states[rs->rstate.id] = NULL;
 127         }
 128         free(rs);
 129 }
 130
 131 void r600_sampler_view_destroy(struct pipe_context *ctx,
 132                                struct pipe_sampler_view *state)
 133 {
 134         struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
 135
 136         pipe_resource_reference(&state->texture, NULL);
 137         FREE(resource);
 138 }
 139
 140 void r600_delete_state(struct pipe_context *ctx, void *state)
 141 {
 142         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 143         struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
 144
 145         if (rctx->states[rstate->id] == rstate) {
 146                 rctx->states[rstate->id] = NULL;
 147         }
 148         for (int i = 0; i < rstate->nregs; i++) {
 149                 pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL);
 150         }
 151         free(rstate);
 152 }
 153
 154 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
 155 {
 156         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 157         struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 158
 159         rctx->vertex_elements = v;
 160         if (v) {
 161                 u_vbuf_bind_vertex_elements(rctx->vbuf_mgr, state,
 162                                                 v->vmgr_elements);
 163
 164                 rctx->states[v->rstate.id] = &v->rstate;
 165                 r600_context_pipe_state_set(&rctx->ctx, &v->rstate);
 166         }
 167 }
 168
 169 void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
 170 {
 171         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 172         struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 173
 174         if (rctx->states[v->rstate.id] == &v->rstate) {
 175                 rctx->states[v->rstate.id] = NULL;
 176         }
 177         if (rctx->vertex_elements == state)
 178                 rctx->vertex_elements = NULL;
 179
 180         pipe_resource_reference((struct pipe_resource**)&v->fetch_shader, NULL);
 181         u_vbuf_destroy_vertex_elements(rctx->vbuf_mgr, v->vmgr_elements);
 182         FREE(state);
 183 }
 184
 185
 186 void r600_set_index_buffer(struct pipe_context *ctx,
 187                            const struct pipe_index_buffer *ib)
 188 {
 189         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 190
 191         u_vbuf_set_index_buffer(rctx->vbuf_mgr, ib);
 192 }
 193
 194 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
 195                              const struct pipe_vertex_buffer *buffers)
 196 {
 197         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 198         int i;
 199
 200         /* Zero states. */
 201         for (i = 0; i < count; i++) {
 202                 if (!buffers[i].buffer) {
 203                         if (rctx->chip_class >= EVERGREEN) {
 204                                 evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
 205                         } else {
 206                                 r600_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
 207                         }
 208                 }
 209         }
 210         for (; i < rctx->vbuf_mgr->nr_real_vertex_buffers; i++) {
 211                 if (rctx->chip_class >= EVERGREEN) {
 212                         evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
 213                 } else {
 214                         r600_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
 215                 }
 216         }
 217
 218         u_vbuf_set_vertex_buffers(rctx->vbuf_mgr, count, buffers);
 219 }
 220
 221 void *r600_create_vertex_elements(struct pipe_context *ctx,
 222                                   unsigned count,
 223                                   const struct pipe_vertex_element *elements)
 224 {
 225         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 226         struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
 227
 228         assert(count < 32);
 229         if (!v)
 230                 return NULL;
 231
 232         v->count = count;
 233         v->vmgr_elements =
 234                 u_vbuf_create_vertex_elements(rctx->vbuf_mgr, count,
 235                                                   elements, v->elements);
 236
 237         if (r600_vertex_elements_build_fetch_shader(rctx, v)) {
 238                 FREE(v);
 239                 return NULL;
 240         }
 241
 242         return v;
 243 }
 244
 245 void *r600_create_shader_state(struct pipe_context *ctx,
 246                                const struct pipe_shader_state *state)
 247 {
 248         struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader);
 249         int r;
 250
 251         shader->tokens = tgsi_dup_tokens(state->tokens);
 252         shader->so = state->stream_output;
 253
 254         r =  r600_pipe_shader_create(ctx, shader);
 255         if (r) {
 256                 return NULL;
 257         }
 258         return shader;
 259 }
 260
 261 void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
 262 {
 263         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 264
 265         /* TODO delete old shader */
 266         rctx->ps_shader = (struct r600_pipe_shader *)state;
 267         if (state) {
 268                 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_shader->rstate);
 269         }
 270         if (rctx->ps_shader && rctx->vs_shader) {
 271                 r600_adjust_gprs(rctx);
 272         }
 273 }
 274
 275 void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
 276 {
 277         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 278
 279         /* TODO delete old shader */
 280         rctx->vs_shader = (struct r600_pipe_shader *)state;
 281         if (state) {
 282                 r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_shader->rstate);
 283         }
 284         if (rctx->ps_shader && rctx->vs_shader) {
 285                 r600_adjust_gprs(rctx);
 286         }
 287 }
 288
 289 void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
 290 {
 291         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 292         struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
 293
 294         if (rctx->ps_shader == shader) {
 295                 rctx->ps_shader = NULL;
 296         }
 297
 298         free(shader->tokens);
 299         r600_pipe_shader_destroy(ctx, shader);
 300         free(shader);
 301 }
 302
 303 void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
 304 {
 305         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 306         struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
 307
 308         if (rctx->vs_shader == shader) {
 309                 rctx->vs_shader = NULL;
 310         }
 311
 312         free(shader->tokens);
 313         r600_pipe_shader_destroy(ctx, shader);
 314         free(shader);
 315 }
 316
 317 static void r600_update_alpha_ref(struct r600_pipe_context *rctx)
 318 {
 319         unsigned alpha_ref;
 320         struct r600_pipe_state rstate;
 321
 322         alpha_ref = rctx->alpha_ref;
 323         rstate.nregs = 0;
 324         if (rctx->export_16bpc)
 325                 alpha_ref &= ~0x1FFF;
 326         r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL, 0);
 327
 328         r600_context_pipe_state_set(&rctx->ctx, &rstate);
 329         rctx->alpha_ref_dirty = false;
 330 }
 331
 332 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 333                               struct pipe_resource *buffer)
 334 {
 335         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 336         struct r600_resource *rbuffer = r600_resource(buffer);
 337         struct r600_pipe_resource_state *rstate;
 338         uint64_t va_offset;
 339         uint32_t offset;
 340
 341         /* Note that the state tracker can unbind constant buffers by
 342          * passing NULL here.
 343          */
 344         if (buffer == NULL) {
 345                 return;
 346         }
 347
 348         r600_upload_const_buffer(rctx, &rbuffer, &offset);
 349         va_offset = r600_resource_va(ctx->screen, (void*)rbuffer);
 350         va_offset += offset;
 351         va_offset >>= 8;
 352
 353         switch (shader) {
 354         case PIPE_SHADER_VERTEX:
 355                 rctx->vs_const_buffer.nregs = 0;
 356                 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
 357                                         R_028180_ALU_CONST_BUFFER_SIZE_VS_0 + index * 4,
 358                                         ALIGN_DIVUP(buffer->width0 >> 4, 16),
 359                                         0xFFFFFFFF, NULL, 0);
 360                 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
 361                                         R_028980_ALU_CONST_CACHE_VS_0 + index * 4,
 362                                         va_offset, 0xFFFFFFFF, rbuffer, RADEON_USAGE_READ);
 363                 r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_const_buffer);
 364
 365                 rstate = &rctx->vs_const_buffer_resource[index];
 366                 if (!rstate->id) {
 367                         if (rctx->chip_class >= EVERGREEN) {
 368                                 evergreen_pipe_init_buffer_resource(rctx, rstate);
 369                         } else {
 370                                 r600_pipe_init_buffer_resource(rctx, rstate);
 371                         }
 372                 }
 373
 374                 if (rctx->chip_class >= EVERGREEN) {
 375                         evergreen_pipe_mod_buffer_resource(ctx, rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 376                         evergreen_context_pipe_state_set_vs_resource(&rctx->ctx, rstate, index);
 377                 } else {
 378                         r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 379                         r600_context_pipe_state_set_vs_resource(&rctx->ctx, rstate, index);
 380                 }
 381                 break;
 382         case PIPE_SHADER_FRAGMENT:
 383                 rctx->ps_const_buffer.nregs = 0;
 384                 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
 385                                         R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
 386                                         ALIGN_DIVUP(buffer->width0 >> 4, 16),
 387                                         0xFFFFFFFF, NULL, 0);
 388                 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
 389                                         R_028940_ALU_CONST_CACHE_PS_0,
 390                                         va_offset, 0xFFFFFFFF, rbuffer, RADEON_USAGE_READ);
 391                 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_const_buffer);
 392
 393                 rstate = &rctx->ps_const_buffer_resource[index];
 394                 if (!rstate->id) {
 395                         if (rctx->chip_class >= EVERGREEN) {
 396                                 evergreen_pipe_init_buffer_resource(rctx, rstate);
 397                         } else {
 398                                 r600_pipe_init_buffer_resource(rctx, rstate);
 399                         }
 400                 }
 401                 if (rctx->chip_class >= EVERGREEN) {
 402                         evergreen_pipe_mod_buffer_resource(ctx, rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 403                         evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, rstate, index);
 404                 } else {
 405                         r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 406                         r600_context_pipe_state_set_ps_resource(&rctx->ctx, rstate, index);
 407                 }
 408                 break;
 409         default:
 410                 R600_ERR("unsupported %d\n", shader);
 411                 return;
 412         }
 413
 414         if (buffer != &rbuffer->b.b.b)
 415                 pipe_resource_reference((struct pipe_resource**)&rbuffer, NULL);
 416 }
 417
 418 struct pipe_stream_output_target *
 419 r600_create_so_target(struct pipe_context *ctx,
 420                       struct pipe_resource *buffer,
 421                       unsigned buffer_offset,
 422                       unsigned buffer_size)
 423 {
 424         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 425         struct r600_so_target *t;
 426         void *ptr;
 427
 428         t = CALLOC_STRUCT(r600_so_target);
 429         if (!t) {
 430                 return NULL;
 431         }
 432
 433         t->b.reference.count = 1;
 434         t->b.context = ctx;
 435         pipe_resource_reference(&t->b.buffer, buffer);
 436         t->b.buffer_offset = buffer_offset;
 437         t->b.buffer_size = buffer_size;
 438
 439         t->filled_size = (struct r600_resource*)
 440                 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4);
 441         ptr = rctx->ws->buffer_map(t->filled_size->buf, rctx->ctx.cs, PIPE_TRANSFER_WRITE);
 442         memset(ptr, 0, t->filled_size->buf->size);
 443         rctx->ws->buffer_unmap(t->filled_size->buf);
 444
 445         return &t->b;
 446 }
 447
 448 void r600_so_target_destroy(struct pipe_context *ctx,
 449                             struct pipe_stream_output_target *target)
 450 {
 451         struct r600_so_target *t = (struct r600_so_target*)target;
 452         pipe_resource_reference(&t->b.buffer, NULL);
 453         pipe_resource_reference((struct pipe_resource**)&t->filled_size, NULL);
 454         FREE(t);
 455 }
 456
 457 void r600_set_so_targets(struct pipe_context *ctx,
 458                          unsigned num_targets,
 459                          struct pipe_stream_output_target **targets,
 460                          unsigned append_bitmask)
 461 {
 462         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 463         unsigned i;
 464
 465         /* Stop streamout. */
 466         if (rctx->ctx.num_so_targets) {
 467                 r600_context_streamout_end(&rctx->ctx);
 468         }
 469
 470         /* Set the new targets. */
 471         for (i = 0; i < num_targets; i++) {
 472                 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->ctx.so_targets[i], targets[i]);
 473         }
 474         for (; i < rctx->ctx.num_so_targets; i++) {
 475                 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->ctx.so_targets[i], NULL);
 476         }
 477
 478         rctx->ctx.num_so_targets = num_targets;
 479         rctx->ctx.streamout_start = num_targets != 0;
 480         rctx->ctx.streamout_append_bitmask = append_bitmask;
 481 }
 482
 483 static void r600_vertex_buffer_update(struct r600_pipe_context *rctx)
 484 {
 485         struct r600_pipe_resource_state *rstate;
 486         struct r600_resource *rbuffer;
 487         struct pipe_vertex_buffer *vertex_buffer;
 488         unsigned i, count, offset;
 489
 490         if (rctx->vertex_elements->vbuffer_need_offset) {
 491                 /* one resource per vertex elements */
 492                 count = rctx->vertex_elements->count;
 493         } else {
 494                 /* bind vertex buffer once */
 495                 count = rctx->vbuf_mgr->nr_real_vertex_buffers;
 496         }
 497
 498         for (i = 0 ; i < count; i++) {
 499                 rstate = &rctx->fs_resource[i];
 500
 501                 if (rctx->vertex_elements->vbuffer_need_offset) {
 502                         /* one resource per vertex elements */
 503                         unsigned vbuffer_index;
 504                         vbuffer_index = rctx->vertex_elements->elements[i].vertex_buffer_index;
 505                         vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[vbuffer_index];
 506                         rbuffer = (struct r600_resource*)vertex_buffer->buffer;
 507                         offset = rctx->vertex_elements->vbuffer_offset[i];
 508                 } else {
 509                         /* bind vertex buffer once */
 510                         vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[i];
 511                         rbuffer = (struct r600_resource*)vertex_buffer->buffer;
 512                         offset = 0;
 513                 }
 514                 if (vertex_buffer == NULL || rbuffer == NULL)
 515                         continue;
 516                 offset += vertex_buffer->buffer_offset;
 517
 518                 if (!rstate->id) {
 519                         if (rctx->chip_class >= EVERGREEN) {
 520                                 evergreen_pipe_init_buffer_resource(rctx, rstate);
 521                         } else {
 522                                 r600_pipe_init_buffer_resource(rctx, rstate);
 523                         }
 524                 }
 525
 526                 if (rctx->chip_class >= EVERGREEN) {
 527                         evergreen_pipe_mod_buffer_resource(&rctx->context, rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ);
 528                         evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, rstate, i);
 529                 } else {
 530                         r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ);
 531                         r600_context_pipe_state_set_fs_resource(&rctx->ctx, rstate, i);
 532                 }
 533         }
 534 }
 535
 536 static int r600_shader_rebuild(struct pipe_context * ctx, struct r600_pipe_shader * shader)
 537 {
 538         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 539         int r;
 540
 541         r600_pipe_shader_destroy(ctx, shader);
 542         r = r600_pipe_shader_create(ctx, shader);
 543         if (r) {
 544                 return r;
 545         }
 546         r600_context_pipe_state_set(&rctx->ctx, &shader->rstate);
 547
 548         return 0;
 549 }
 550
 551 static void r600_update_derived_state(struct r600_pipe_context *rctx)
 552 {
 553         struct pipe_context * ctx = (struct pipe_context*)rctx;
 554         struct r600_pipe_state rstate;
 555         unsigned user_clip_plane_enable;
 556         unsigned clip_dist_enable;
 557
 558         if (rctx->vs_shader->shader.clip_dist_write || rctx->vs_shader->shader.vs_prohibit_ucps)
 559                 user_clip_plane_enable = 0;
 560         else
 561                 user_clip_plane_enable = rctx->rasterizer->clip_plane_enable & 0x3F;
 562
 563         clip_dist_enable = rctx->rasterizer->clip_plane_enable & rctx->vs_shader->shader.clip_dist_write;
 564         rstate.nregs = 0;
 565
 566         if (user_clip_plane_enable != rctx->user_clip_plane_enable) {
 567                 r600_pipe_state_add_reg(&rstate, R_028810_PA_CL_CLIP_CNTL, user_clip_plane_enable , 0x3F, NULL, 0);
 568                 rctx->user_clip_plane_enable = user_clip_plane_enable;
 569         }
 570
 571         if (clip_dist_enable != rctx->clip_dist_enable) {
 572                 r600_pipe_state_add_reg(&rstate, R_02881C_PA_CL_VS_OUT_CNTL, clip_dist_enable, 0xFF, NULL, 0);
 573                 rctx->clip_dist_enable = clip_dist_enable;
 574         }
 575
 576         if (rstate.nregs)
 577                 r600_context_pipe_state_set(&rctx->ctx, &rstate);
 578
 579         if (!rctx->blitter->running) {
 580                 if (rctx->have_depth_fb || rctx->have_depth_texture)
 581                         r600_flush_depth_textures(rctx);
 582         }
 583
 584         if (rctx->chip_class < EVERGREEN) {
 585                 r600_update_sampler_states(rctx);
 586         }
 587
 588         if ((rctx->ps_shader->shader.two_side != rctx->two_side) ||
 589             ((rctx->chip_class >= EVERGREEN) && rctx->ps_shader->shader.fs_write_all &&
 590              (rctx->ps_shader->shader.nr_cbufs != rctx->nr_cbufs))) {
 591                 r600_shader_rebuild(&rctx->context, rctx->ps_shader);
 592         }
 593
 594         if (rctx->alpha_ref_dirty) {
 595                 r600_update_alpha_ref(rctx);
 596         }
 597
 598         if (rctx->ps_shader && rctx->sprite_coord_enable &&
 599                 (rctx->ps_shader->sprite_coord_enable != rctx->sprite_coord_enable)) {
 600
 601                 if (rctx->chip_class >= EVERGREEN)
 602                         evergreen_pipe_shader_ps(ctx, rctx->ps_shader);
 603                 else
 604                         r600_pipe_shader_ps(ctx, rctx->ps_shader);
 605
 606                 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_shader->rstate);
 607         }
 608
 609 }
 610
 611 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
 612 {
 613         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 614         struct pipe_draw_info info = *dinfo;
 615         struct r600_draw rdraw = {};
 616         struct pipe_index_buffer ib = {};
 617         unsigned prim, mask, ls_mask = 0;
 618
 619         if ((!info.count && (info.indexed || !info.count_from_stream_output)) ||
 620             (info.indexed && !rctx->vbuf_mgr->index_buffer.buffer) ||
 621             !r600_conv_pipe_prim(info.mode, &prim)) {
 622                 return;
 623         }
 624
 625         if (!rctx->ps_shader || !rctx->vs_shader)
 626                 return;
 627
 628         r600_update_derived_state(rctx);
 629
 630         u_vbuf_draw_begin(rctx->vbuf_mgr, &info);
 631         r600_vertex_buffer_update(rctx);
 632
 633         rdraw.vgt_num_indices = info.count;
 634         rdraw.vgt_num_instances = info.instance_count;
 635
 636         if (info.indexed) {
 637                 /* Initialize the index buffer struct. */
 638                 pipe_resource_reference(&ib.buffer, rctx->vbuf_mgr->index_buffer.buffer);
 639                 ib.index_size = rctx->vbuf_mgr->index_buffer.index_size;
 640                 ib.offset = rctx->vbuf_mgr->index_buffer.offset + info.start * ib.index_size;
 641
 642                 /* Translate or upload, if needed. */
 643                 r600_translate_index_buffer(rctx, &ib, info.count);
 644
 645                 if (u_vbuf_resource(ib.buffer)->user_ptr) {
 646                         r600_upload_index_buffer(rctx, &ib, info.count);
 647                 }
 648
 649                 /* Initialize the r600_draw struct with index buffer info. */
 650                 if (ib.index_size == 4) {
 651                         rdraw.vgt_index_type = VGT_INDEX_32 |
 652                                 (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0);
 653                 } else {
 654                         rdraw.vgt_index_type = VGT_INDEX_16 |
 655                                 (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0);
 656                 }
 657                 rdraw.indices = (struct r600_resource*)ib.buffer;
 658                 rdraw.indices_bo_offset = ib.offset;
 659                 rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_DMA;
 660         } else {
 661                 info.index_bias = info.start;
 662                 rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_AUTO_INDEX;
 663                 if (info.count_from_stream_output) {
 664                         rdraw.vgt_draw_initiator |= S_0287F0_USE_OPAQUE(1);
 665
 666                         r600_context_draw_opaque_count(&rctx->ctx, (struct r600_so_target*)info.count_from_stream_output);
 667                 }
 668         }
 669
 670         rctx->ctx.vs_so_stride_in_dw = rctx->vs_shader->so.stride;
 671
 672         mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
 673
 674         if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
 675                 rctx->vgt.id = R600_PIPE_STATE_VGT;
 676                 rctx->vgt.nregs = 0;
 677                 r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL, 0);
 678                 r600_pipe_state_add_reg(&rctx->vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL, 0);
 679                 r600_pipe_state_add_reg(&rctx->vgt, R_028400_VGT_MAX_VTX_INDX, ~0, 0xFFFFFFFF, NULL, 0);
 680                 r600_pipe_state_add_reg(&rctx->vgt, R_028404_VGT_MIN_VTX_INDX, 0, 0xFFFFFFFF, NULL, 0);
 681                 r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias, 0xFFFFFFFF, NULL, 0);
 682                 r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index, 0xFFFFFFFF, NULL, 0);
 683                 r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart, 0xFFFFFFFF, NULL, 0);
 684                 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0xFFFFFFFF, NULL, 0);
 685                 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance, 0xFFFFFFFF, NULL, 0);
 686                 r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE,
 687                                         0,
 688                                         S_028A0C_AUTO_RESET_CNTL(3), NULL, 0);
 689                 r600_pipe_state_add_reg(&rctx->vgt, R_028814_PA_SU_SC_MODE_CNTL,
 690                                         0,
 691                                         S_028814_PROVOKING_VTX_LAST(1), NULL, 0);
 692         }
 693
 694         rctx->vgt.nregs = 0;
 695         r600_pipe_state_mod_reg(&rctx->vgt, prim);
 696         r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_target_mask & mask);
 697         r600_pipe_state_mod_reg(&rctx->vgt, ~0);
 698         r600_pipe_state_mod_reg(&rctx->vgt, 0);
 699         r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
 700         r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
 701         r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart);
 702         r600_pipe_state_mod_reg(&rctx->vgt, 0);
 703         r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance);
 704
 705         if (prim == V_008958_DI_PT_LINELIST)
 706                 ls_mask = 1;
 707         else if (prim == V_008958_DI_PT_LINESTRIP)
 708                 ls_mask = 2;
 709         r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask));
 710
 711         if (info.mode == PIPE_PRIM_QUADS || info.mode == PIPE_PRIM_QUAD_STRIP || info.mode == PIPE_PRIM_POLYGON) {
 712                 r600_pipe_state_mod_reg(&rctx->vgt, S_028814_PROVOKING_VTX_LAST(1));
 713         }
 714
 715         r600_context_pipe_state_set(&rctx->ctx, &rctx->vgt);
 716
 717         if (rctx->chip_class >= EVERGREEN) {
 718                 evergreen_context_draw(&rctx->ctx, &rdraw);
 719         } else {
 720                 r600_context_draw(&rctx->ctx, &rdraw);
 721         }
 722
 723         if (rctx->framebuffer.zsbuf)
 724         {
 725                 struct pipe_resource *tex = rctx->framebuffer.zsbuf->texture;
 726                 ((struct r600_resource_texture *)tex)->dirty_db = TRUE;
 727         }
 728
 729         pipe_resource_reference(&ib.buffer, NULL);
 730         u_vbuf_draw_end(rctx->vbuf_mgr);
 731 }
 732
 733 void _r600_pipe_state_add_reg(struct r600_context *ctx,
 734                               struct r600_pipe_state *state,
 735                               u32 offset, u32 value, u32 mask,
 736                               u32 range_id, u32 block_id,
 737                               struct r600_resource *bo,
 738                               enum radeon_bo_usage usage)
 739 {
 740         struct r600_range *range;
 741         struct r600_block *block;
 742
 743         if (bo) assert(usage);
 744
 745         range = &ctx->range[range_id];
 746         block = range->blocks[block_id];
 747         state->regs[state->nregs].block = block;
 748         state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
 749
 750         state->regs[state->nregs].value = value;
 751         state->regs[state->nregs].mask = mask;
 752         state->regs[state->nregs].bo = bo;
 753         state->regs[state->nregs].bo_usage = usage;
 754
 755         state->nregs++;
 756         assert(state->nregs < R600_BLOCK_MAX_REG);
 757 }
 758
 759 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
 760                                      u32 offset, u32 value, u32 mask,
 761                                      struct r600_resource *bo,
 762                                      enum radeon_bo_usage usage)
 763 {
 764         if (bo) assert(usage);
 765
 766         state->regs[state->nregs].id = offset;
 767         state->regs[state->nregs].block = NULL;
 768         state->regs[state->nregs].value = value;
 769         state->regs[state->nregs].mask = mask;
 770         state->regs[state->nregs].bo = bo;
 771         state->regs[state->nregs].bo_usage = usage;
 772
 773         state->nregs++;
 774         assert(state->nregs < R600_BLOCK_MAX_REG);
 775 }