2 * Copyright 2010 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
27 #include "r600_formats.h"
30 #include "util/u_draw_quad.h"
31 #include "util/u_upload_mgr.h"
32 #include "tgsi/tgsi_parse.h"
35 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
37 static void r600_emit_command_buffer(struct r600_context
*rctx
, struct r600_atom
*atom
)
39 struct radeon_winsys_cs
*cs
= rctx
->cs
;
40 struct r600_command_buffer
*cb
= (struct r600_command_buffer
*)atom
;
42 assert(cs
->cdw
+ cb
->atom
.num_dw
<= RADEON_MAX_CMDBUF_DWORDS
);
43 memcpy(cs
->buf
+ cs
->cdw
, cb
->buf
, 4 * cb
->atom
.num_dw
);
44 cs
->cdw
+= cb
->atom
.num_dw
;
47 void r600_init_command_buffer(struct r600_context
*rctx
, struct r600_command_buffer
*cb
, unsigned id
, unsigned num_dw
)
49 r600_init_atom(rctx
, &cb
->atom
, id
, r600_emit_command_buffer
, 0);
50 cb
->buf
= CALLOC(1, 4 * num_dw
);
51 cb
->max_num_dw
= num_dw
;
54 void r600_release_command_buffer(struct r600_command_buffer
*cb
)
59 void r600_init_atom(struct r600_context
*rctx
,
60 struct r600_atom
*atom
,
62 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
65 assert(id
< R600_NUM_ATOMS
);
66 assert(rctx
->atoms
[id
] == NULL
);
67 rctx
->atoms
[id
] = atom
;
70 atom
->num_dw
= num_dw
;
74 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
76 struct radeon_winsys_cs
*cs
= rctx
->cs
;
77 struct r600_alphatest_state
*a
= (struct r600_alphatest_state
*)atom
;
78 unsigned alpha_ref
= a
->sx_alpha_ref
;
80 if (rctx
->chip_class
>= EVERGREEN
&& a
->cb0_export_16bpc
) {
84 r600_write_context_reg(cs
, R_028410_SX_ALPHA_TEST_CONTROL
,
85 a
->sx_alpha_test_control
|
86 S_028410_ALPHA_TEST_BYPASS(a
->bypass
));
87 r600_write_context_reg(cs
, R_028438_SX_ALPHA_REF
, alpha_ref
);
90 static void r600_texture_barrier(struct pipe_context
*ctx
)
92 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
94 rctx
->flags
|= R600_CONTEXT_CB_FLUSH
| R600_CONTEXT_TEX_FLUSH
;
97 if (rctx
->chip_class
== R600
) {
98 rctx
->flags
|= R600_CONTEXT_FLUSH_AND_INV
;
102 static bool r600_conv_pipe_prim(unsigned pprim
, unsigned *prim
)
104 static const int prim_conv
[] = {
105 V_008958_DI_PT_POINTLIST
,
106 V_008958_DI_PT_LINELIST
,
107 V_008958_DI_PT_LINELOOP
,
108 V_008958_DI_PT_LINESTRIP
,
109 V_008958_DI_PT_TRILIST
,
110 V_008958_DI_PT_TRISTRIP
,
111 V_008958_DI_PT_TRIFAN
,
112 V_008958_DI_PT_QUADLIST
,
113 V_008958_DI_PT_QUADSTRIP
,
114 V_008958_DI_PT_POLYGON
,
119 V_008958_DI_PT_RECTLIST
122 *prim
= prim_conv
[pprim
];
124 fprintf(stderr
, "%s:%d unsupported %d\n", __func__
, __LINE__
, pprim
);
130 /* common state between evergreen and r600 */
132 static void r600_bind_blend_state_internal(struct r600_context
*rctx
,
133 struct r600_pipe_blend
*blend
)
135 struct r600_pipe_state
*rstate
;
136 bool update_cb
= false;
138 rstate
= &blend
->rstate
;
139 rctx
->states
[rstate
->id
] = rstate
;
140 r600_context_pipe_state_set(rctx
, rstate
);
142 if (rctx
->cb_misc_state
.blend_colormask
!= blend
->cb_target_mask
) {
143 rctx
->cb_misc_state
.blend_colormask
= blend
->cb_target_mask
;
146 if (rctx
->chip_class
<= R700
&&
147 rctx
->cb_misc_state
.cb_color_control
!= blend
->cb_color_control
) {
148 rctx
->cb_misc_state
.cb_color_control
= blend
->cb_color_control
;
151 if (rctx
->cb_misc_state
.dual_src_blend
!= blend
->dual_src_blend
) {
152 rctx
->cb_misc_state
.dual_src_blend
= blend
->dual_src_blend
;
156 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
160 static void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
)
162 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
163 struct r600_pipe_blend
*blend
= (struct r600_pipe_blend
*)state
;
169 rctx
->alpha_to_one
= blend
->alpha_to_one
;
170 rctx
->dual_src_blend
= blend
->dual_src_blend
;
172 if (!rctx
->blend_override
)
173 r600_bind_blend_state_internal(rctx
, blend
);
176 static void r600_set_blend_color(struct pipe_context
*ctx
,
177 const struct pipe_blend_color
*state
)
179 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
181 rctx
->blend_color
.state
= *state
;
182 r600_atom_dirty(rctx
, &rctx
->blend_color
.atom
);
185 void r600_emit_blend_color(struct r600_context
*rctx
, struct r600_atom
*atom
)
187 struct radeon_winsys_cs
*cs
= rctx
->cs
;
188 struct pipe_blend_color
*state
= &rctx
->blend_color
.state
;
190 r600_write_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
191 r600_write_value(cs
, fui(state
->color
[0])); /* R_028414_CB_BLEND_RED */
192 r600_write_value(cs
, fui(state
->color
[1])); /* R_028418_CB_BLEND_GREEN */
193 r600_write_value(cs
, fui(state
->color
[2])); /* R_02841C_CB_BLEND_BLUE */
194 r600_write_value(cs
, fui(state
->color
[3])); /* R_028420_CB_BLEND_ALPHA */
197 static void r600_set_clip_state(struct pipe_context
*ctx
,
198 const struct pipe_clip_state
*state
)
200 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
201 struct pipe_constant_buffer cb
;
203 rctx
->clip_state
.state
= *state
;
204 r600_atom_dirty(rctx
, &rctx
->clip_state
.atom
);
207 cb
.user_buffer
= state
->ucp
;
208 cb
.buffer_offset
= 0;
209 cb
.buffer_size
= 4*4*8;
210 ctx
->set_constant_buffer(ctx
, PIPE_SHADER_VERTEX
, 1, &cb
);
211 pipe_resource_reference(&cb
.buffer
, NULL
);
214 static void r600_set_stencil_ref(struct pipe_context
*ctx
,
215 const struct r600_stencil_ref
*state
)
217 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
219 rctx
->stencil_ref
.state
= *state
;
220 r600_atom_dirty(rctx
, &rctx
->stencil_ref
.atom
);
223 void r600_emit_stencil_ref(struct r600_context
*rctx
, struct r600_atom
*atom
)
225 struct radeon_winsys_cs
*cs
= rctx
->cs
;
226 struct r600_stencil_ref_state
*a
= (struct r600_stencil_ref_state
*)atom
;
228 r600_write_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
229 r600_write_value(cs
, /* R_028430_DB_STENCILREFMASK */
230 S_028430_STENCILREF(a
->state
.ref_value
[0]) |
231 S_028430_STENCILMASK(a
->state
.valuemask
[0]) |
232 S_028430_STENCILWRITEMASK(a
->state
.writemask
[0]));
233 r600_write_value(cs
, /* R_028434_DB_STENCILREFMASK_BF */
234 S_028434_STENCILREF_BF(a
->state
.ref_value
[1]) |
235 S_028434_STENCILMASK_BF(a
->state
.valuemask
[1]) |
236 S_028434_STENCILWRITEMASK_BF(a
->state
.writemask
[1]));
239 static void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
240 const struct pipe_stencil_ref
*state
)
242 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
243 struct r600_pipe_dsa
*dsa
= (struct r600_pipe_dsa
*)rctx
->states
[R600_PIPE_STATE_DSA
];
244 struct r600_stencil_ref ref
;
246 rctx
->stencil_ref
.pipe_state
= *state
;
251 ref
.ref_value
[0] = state
->ref_value
[0];
252 ref
.ref_value
[1] = state
->ref_value
[1];
253 ref
.valuemask
[0] = dsa
->valuemask
[0];
254 ref
.valuemask
[1] = dsa
->valuemask
[1];
255 ref
.writemask
[0] = dsa
->writemask
[0];
256 ref
.writemask
[1] = dsa
->writemask
[1];
258 r600_set_stencil_ref(ctx
, &ref
);
261 static void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
263 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
264 struct r600_pipe_dsa
*dsa
= state
;
265 struct r600_pipe_state
*rstate
;
266 struct r600_stencil_ref ref
;
270 rstate
= &dsa
->rstate
;
271 rctx
->states
[rstate
->id
] = rstate
;
272 r600_context_pipe_state_set(rctx
, rstate
);
274 ref
.ref_value
[0] = rctx
->stencil_ref
.pipe_state
.ref_value
[0];
275 ref
.ref_value
[1] = rctx
->stencil_ref
.pipe_state
.ref_value
[1];
276 ref
.valuemask
[0] = dsa
->valuemask
[0];
277 ref
.valuemask
[1] = dsa
->valuemask
[1];
278 ref
.writemask
[0] = dsa
->writemask
[0];
279 ref
.writemask
[1] = dsa
->writemask
[1];
281 r600_set_stencil_ref(ctx
, &ref
);
283 /* Update alphatest state. */
284 if (rctx
->alphatest_state
.sx_alpha_test_control
!= dsa
->sx_alpha_test_control
||
285 rctx
->alphatest_state
.sx_alpha_ref
!= dsa
->alpha_ref
) {
286 rctx
->alphatest_state
.sx_alpha_test_control
= dsa
->sx_alpha_test_control
;
287 rctx
->alphatest_state
.sx_alpha_ref
= dsa
->alpha_ref
;
288 r600_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
292 void r600_set_max_scissor(struct r600_context
*rctx
)
294 /* Set a scissor state such that it doesn't do anything. */
295 struct pipe_scissor_state scissor
;
301 r600_set_scissor_state(rctx
, &scissor
);
304 static void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
)
306 struct r600_pipe_rasterizer
*rs
= (struct r600_pipe_rasterizer
*)state
;
307 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
312 rctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
313 rctx
->two_side
= rs
->two_side
;
314 rctx
->pa_sc_line_stipple
= rs
->pa_sc_line_stipple
;
315 rctx
->multisample_enable
= rs
->multisample_enable
;
317 rctx
->rasterizer
= rs
;
319 rctx
->states
[rs
->rstate
.id
] = &rs
->rstate
;
320 r600_context_pipe_state_set(rctx
, &rs
->rstate
);
322 if (rctx
->chip_class
>= EVERGREEN
) {
323 evergreen_polygon_offset_update(rctx
);
325 r600_polygon_offset_update(rctx
);
328 /* Update clip_misc_state. */
329 if (rctx
->clip_misc_state
.pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
||
330 rctx
->clip_misc_state
.clip_plane_enable
!= rs
->clip_plane_enable
) {
331 rctx
->clip_misc_state
.pa_cl_clip_cntl
= rs
->pa_cl_clip_cntl
;
332 rctx
->clip_misc_state
.clip_plane_enable
= rs
->clip_plane_enable
;
333 r600_atom_dirty(rctx
, &rctx
->clip_misc_state
.atom
);
336 /* Workaround for a missing scissor enable on r600. */
337 if (rctx
->chip_class
== R600
) {
338 if (rs
->scissor_enable
!= rctx
->scissor_enable
) {
339 rctx
->scissor_enable
= rs
->scissor_enable
;
341 if (rs
->scissor_enable
) {
342 r600_set_scissor_state(rctx
, &rctx
->scissor_state
);
344 r600_set_max_scissor(rctx
);
350 static void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
)
352 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
353 struct r600_pipe_rasterizer
*rs
= (struct r600_pipe_rasterizer
*)state
;
355 if (rctx
->rasterizer
== rs
) {
356 rctx
->rasterizer
= NULL
;
358 if (rctx
->states
[rs
->rstate
.id
] == &rs
->rstate
) {
359 rctx
->states
[rs
->rstate
.id
] = NULL
;
364 static void r600_sampler_view_destroy(struct pipe_context
*ctx
,
365 struct pipe_sampler_view
*state
)
367 struct r600_pipe_sampler_view
*resource
= (struct r600_pipe_sampler_view
*)state
;
369 pipe_resource_reference(&state
->texture
, NULL
);
373 void r600_sampler_states_dirty(struct r600_context
*rctx
,
374 struct r600_sampler_states
*state
)
376 if (state
->dirty_mask
) {
377 if (state
->dirty_mask
& state
->has_bordercolor_mask
) {
378 rctx
->flags
|= R600_CONTEXT_PS_PARTIAL_FLUSH
;
381 util_bitcount(state
->dirty_mask
& state
->has_bordercolor_mask
) * 11 +
382 util_bitcount(state
->dirty_mask
& ~state
->has_bordercolor_mask
) * 5;
383 r600_atom_dirty(rctx
, &state
->atom
);
387 static void r600_bind_sampler_states(struct pipe_context
*pipe
,
390 unsigned count
, void **states
)
392 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
393 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
394 struct r600_pipe_sampler_state
**rstates
= (struct r600_pipe_sampler_state
**)states
;
395 int seamless_cube_map
= -1;
397 /* This sets 1-bit for states with index >= count. */
398 uint32_t disable_mask
= ~((1ull << count
) - 1);
399 /* These are the new states set by this function. */
400 uint32_t new_mask
= 0;
402 assert(start
== 0); /* XXX fix below */
404 for (i
= 0; i
< count
; i
++) {
405 struct r600_pipe_sampler_state
*rstate
= rstates
[i
];
407 if (rstate
== dst
->states
.states
[i
]) {
412 if (rstate
->border_color_use
) {
413 dst
->states
.has_bordercolor_mask
|= 1 << i
;
415 dst
->states
.has_bordercolor_mask
&= ~(1 << i
);
417 seamless_cube_map
= rstate
->seamless_cube_map
;
421 disable_mask
|= 1 << i
;
425 memcpy(dst
->states
.states
, rstates
, sizeof(void*) * count
);
426 memset(dst
->states
.states
+ count
, 0, sizeof(void*) * (NUM_TEX_UNITS
- count
));
428 dst
->states
.enabled_mask
&= ~disable_mask
;
429 dst
->states
.dirty_mask
&= dst
->states
.enabled_mask
;
430 dst
->states
.enabled_mask
|= new_mask
;
431 dst
->states
.dirty_mask
|= new_mask
;
432 dst
->states
.has_bordercolor_mask
&= dst
->states
.enabled_mask
;
434 r600_sampler_states_dirty(rctx
, &dst
->states
);
436 /* Seamless cubemap state. */
437 if (rctx
->chip_class
<= R700
&&
438 seamless_cube_map
!= -1 &&
439 seamless_cube_map
!= rctx
->seamless_cube_map
.enabled
) {
440 /* change in TA_CNTL_AUX need a pipeline flush */
441 rctx
->flags
|= R600_CONTEXT_PS_PARTIAL_FLUSH
;
442 rctx
->seamless_cube_map
.enabled
= seamless_cube_map
;
443 r600_atom_dirty(rctx
, &rctx
->seamless_cube_map
.atom
);
447 static void r600_bind_vs_sampler_states(struct pipe_context
*ctx
, unsigned count
, void **states
)
449 r600_bind_sampler_states(ctx
, PIPE_SHADER_VERTEX
, 0, count
, states
);
452 static void r600_bind_ps_sampler_states(struct pipe_context
*ctx
, unsigned count
, void **states
)
454 r600_bind_sampler_states(ctx
, PIPE_SHADER_FRAGMENT
, 0, count
, states
);
457 static void r600_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
462 static void r600_delete_state(struct pipe_context
*ctx
, void *state
)
464 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
465 struct r600_pipe_state
*rstate
= (struct r600_pipe_state
*)state
;
467 if (rctx
->states
[rstate
->id
] == rstate
) {
468 rctx
->states
[rstate
->id
] = NULL
;
470 for (int i
= 0; i
< rstate
->nregs
; i
++) {
471 pipe_resource_reference((struct pipe_resource
**)&rstate
->regs
[i
].bo
, NULL
);
476 static void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
478 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
479 struct r600_vertex_element
*v
= (struct r600_vertex_element
*)state
;
481 rctx
->vertex_elements
= v
;
483 rctx
->states
[v
->rstate
.id
] = &v
->rstate
;
484 r600_context_pipe_state_set(rctx
, &v
->rstate
);
488 static void r600_delete_vertex_elements(struct pipe_context
*ctx
, void *state
)
490 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
491 struct r600_vertex_element
*v
= (struct r600_vertex_element
*)state
;
493 if (rctx
->states
[v
->rstate
.id
] == &v
->rstate
) {
494 rctx
->states
[v
->rstate
.id
] = NULL
;
496 if (rctx
->vertex_elements
== state
)
497 rctx
->vertex_elements
= NULL
;
499 pipe_resource_reference((struct pipe_resource
**)&v
->fetch_shader
, NULL
);
503 static void r600_set_index_buffer(struct pipe_context
*ctx
,
504 const struct pipe_index_buffer
*ib
)
506 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
509 pipe_resource_reference(&rctx
->index_buffer
.buffer
, ib
->buffer
);
510 memcpy(&rctx
->index_buffer
, ib
, sizeof(*ib
));
512 pipe_resource_reference(&rctx
->index_buffer
.buffer
, NULL
);
516 void r600_vertex_buffers_dirty(struct r600_context
*rctx
)
518 if (rctx
->vertex_buffer_state
.dirty_mask
) {
519 rctx
->flags
|= rctx
->has_vertex_cache
? R600_CONTEXT_VTX_FLUSH
: R600_CONTEXT_TEX_FLUSH
;
520 rctx
->vertex_buffer_state
.atom
.num_dw
= (rctx
->chip_class
>= EVERGREEN
? 12 : 11) *
521 util_bitcount(rctx
->vertex_buffer_state
.dirty_mask
);
522 r600_atom_dirty(rctx
, &rctx
->vertex_buffer_state
.atom
);
526 static void r600_set_vertex_buffers(struct pipe_context
*ctx
, unsigned count
,
527 const struct pipe_vertex_buffer
*input
)
529 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
530 struct r600_vertexbuf_state
*state
= &rctx
->vertex_buffer_state
;
531 struct pipe_vertex_buffer
*vb
= state
->vb
;
533 /* This sets 1-bit for buffers with index >= count. */
534 uint32_t disable_mask
= ~((1ull << count
) - 1);
535 /* These are the new buffers set by this function. */
536 uint32_t new_buffer_mask
= 0;
538 /* Set buffers with index >= count to NULL. */
539 uint32_t remaining_buffers_mask
=
540 rctx
->vertex_buffer_state
.enabled_mask
& disable_mask
;
542 while (remaining_buffers_mask
) {
543 i
= u_bit_scan(&remaining_buffers_mask
);
544 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
547 /* Set vertex buffers. */
548 for (i
= 0; i
< count
; i
++) {
549 if (memcmp(&input
[i
], &vb
[i
], sizeof(struct pipe_vertex_buffer
))) {
550 if (input
[i
].buffer
) {
551 vb
[i
].stride
= input
[i
].stride
;
552 vb
[i
].buffer_offset
= input
[i
].buffer_offset
;
553 pipe_resource_reference(&vb
[i
].buffer
, input
[i
].buffer
);
554 new_buffer_mask
|= 1 << i
;
556 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
557 disable_mask
|= 1 << i
;
562 rctx
->vertex_buffer_state
.enabled_mask
&= ~disable_mask
;
563 rctx
->vertex_buffer_state
.dirty_mask
&= rctx
->vertex_buffer_state
.enabled_mask
;
564 rctx
->vertex_buffer_state
.enabled_mask
|= new_buffer_mask
;
565 rctx
->vertex_buffer_state
.dirty_mask
|= new_buffer_mask
;
567 r600_vertex_buffers_dirty(rctx
);
570 void r600_sampler_views_dirty(struct r600_context
*rctx
,
571 struct r600_samplerview_state
*state
)
573 if (state
->dirty_mask
) {
574 rctx
->flags
|= R600_CONTEXT_TEX_FLUSH
;
575 state
->atom
.num_dw
= (rctx
->chip_class
>= EVERGREEN
? 14 : 13) *
576 util_bitcount(state
->dirty_mask
);
577 r600_atom_dirty(rctx
, &state
->atom
);
581 static void r600_set_sampler_views(struct pipe_context
*pipe
, unsigned shader
,
582 unsigned start
, unsigned count
,
583 struct pipe_sampler_view
**views
)
585 struct r600_context
*rctx
= (struct r600_context
*) pipe
;
586 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
587 struct r600_pipe_sampler_view
**rviews
= (struct r600_pipe_sampler_view
**)views
;
588 uint32_t dirty_sampler_states_mask
= 0;
590 /* This sets 1-bit for textures with index >= count. */
591 uint32_t disable_mask
= ~((1ull << count
) - 1);
592 /* These are the new textures set by this function. */
593 uint32_t new_mask
= 0;
595 /* Set textures with index >= count to NULL. */
596 uint32_t remaining_mask
;
598 assert(start
== 0); /* XXX fix below */
600 remaining_mask
= dst
->views
.enabled_mask
& disable_mask
;
602 while (remaining_mask
) {
603 i
= u_bit_scan(&remaining_mask
);
604 assert(dst
->views
.views
[i
]);
606 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
609 for (i
= 0; i
< count
; i
++) {
610 if (rviews
[i
] == dst
->views
.views
[i
]) {
615 struct r600_texture
*rtex
=
616 (struct r600_texture
*)rviews
[i
]->base
.texture
;
618 if (rtex
->is_depth
&& !rtex
->is_flushing_texture
) {
619 dst
->views
.compressed_depthtex_mask
|= 1 << i
;
621 dst
->views
.compressed_depthtex_mask
&= ~(1 << i
);
624 /* Track compressed colorbuffers for Evergreen (Cayman doesn't need this). */
625 if (rctx
->chip_class
!= CAYMAN
&& rtex
->cmask_size
&& rtex
->fmask_size
) {
626 dst
->views
.compressed_colortex_mask
|= 1 << i
;
628 dst
->views
.compressed_colortex_mask
&= ~(1 << i
);
631 /* Changing from array to non-arrays textures and vice versa requires
632 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
633 if (rctx
->chip_class
<= R700
&&
634 (dst
->states
.enabled_mask
& (1 << i
)) &&
635 (rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_1D_ARRAY
||
636 rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_2D_ARRAY
) != dst
->is_array_sampler
[i
]) {
637 dirty_sampler_states_mask
|= 1 << i
;
640 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], views
[i
]);
643 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
644 disable_mask
|= 1 << i
;
648 dst
->views
.enabled_mask
&= ~disable_mask
;
649 dst
->views
.dirty_mask
&= dst
->views
.enabled_mask
;
650 dst
->views
.enabled_mask
|= new_mask
;
651 dst
->views
.dirty_mask
|= new_mask
;
652 dst
->views
.compressed_depthtex_mask
&= dst
->views
.enabled_mask
;
653 dst
->views
.compressed_colortex_mask
&= dst
->views
.enabled_mask
;
655 r600_sampler_views_dirty(rctx
, &dst
->views
);
657 if (dirty_sampler_states_mask
) {
658 dst
->states
.dirty_mask
|= dirty_sampler_states_mask
;
659 r600_sampler_states_dirty(rctx
, &dst
->states
);
663 static void r600_set_vs_sampler_views(struct pipe_context
*ctx
, unsigned count
,
664 struct pipe_sampler_view
**views
)
666 r600_set_sampler_views(ctx
, PIPE_SHADER_VERTEX
, 0, count
, views
);
669 static void r600_set_ps_sampler_views(struct pipe_context
*ctx
, unsigned count
,
670 struct pipe_sampler_view
**views
)
672 r600_set_sampler_views(ctx
, PIPE_SHADER_FRAGMENT
, 0, count
, views
);
675 static void r600_set_viewport_state(struct pipe_context
*ctx
,
676 const struct pipe_viewport_state
*state
)
678 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
680 rctx
->viewport
.state
= *state
;
681 r600_atom_dirty(rctx
, &rctx
->viewport
.atom
);
684 void r600_emit_viewport_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
686 struct radeon_winsys_cs
*cs
= rctx
->cs
;
687 struct pipe_viewport_state
*state
= &rctx
->viewport
.state
;
689 r600_write_context_reg_seq(cs
, R_02843C_PA_CL_VPORT_XSCALE_0
, 6);
690 r600_write_value(cs
, fui(state
->scale
[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
691 r600_write_value(cs
, fui(state
->translate
[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
692 r600_write_value(cs
, fui(state
->scale
[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
693 r600_write_value(cs
, fui(state
->translate
[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
694 r600_write_value(cs
, fui(state
->scale
[2])); /* R_02844C_PA_CL_VPORT_ZSCALE_0 */
695 r600_write_value(cs
, fui(state
->translate
[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
698 static void *r600_create_vertex_elements(struct pipe_context
*ctx
, unsigned count
,
699 const struct pipe_vertex_element
*elements
)
701 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
702 struct r600_vertex_element
*v
= CALLOC_STRUCT(r600_vertex_element
);
709 memcpy(v
->elements
, elements
, sizeof(struct pipe_vertex_element
) * count
);
711 if (r600_vertex_elements_build_fetch_shader(rctx
, v
)) {
719 /* Compute the key for the hw shader variant */
720 static INLINE
unsigned r600_shader_selector_key(struct pipe_context
* ctx
,
721 struct r600_pipe_shader_selector
* sel
)
723 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
726 if (sel
->type
== PIPE_SHADER_FRAGMENT
) {
727 key
= rctx
->two_side
|
728 ((rctx
->alpha_to_one
&& rctx
->multisample_enable
&& !rctx
->cb0_is_integer
) << 1) |
729 (MIN2(sel
->nr_ps_max_color_exports
, rctx
->nr_cbufs
+ rctx
->dual_src_blend
) << 2);
736 /* Select the hw shader variant depending on the current state.
737 * (*dirty) is set to 1 if current variant was changed */
738 static int r600_shader_select(struct pipe_context
*ctx
,
739 struct r600_pipe_shader_selector
* sel
,
743 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
744 struct r600_pipe_shader
* shader
= NULL
;
747 key
= r600_shader_selector_key(ctx
, sel
);
749 /* Check if we don't need to change anything.
750 * This path is also used for most shaders that don't need multiple
751 * variants, it will cost just a computation of the key and this
753 if (likely(sel
->current
&& sel
->current
->key
== key
)) {
757 /* lookup if we have other variants in the list */
758 if (sel
->num_shaders
> 1) {
759 struct r600_pipe_shader
*p
= sel
->current
, *c
= p
->next_variant
;
761 while (c
&& c
->key
!= key
) {
767 p
->next_variant
= c
->next_variant
;
772 if (unlikely(!shader
)) {
773 shader
= CALLOC(1, sizeof(struct r600_pipe_shader
));
774 shader
->selector
= sel
;
776 r
= r600_pipe_shader_create(ctx
, shader
);
778 R600_ERR("Failed to build shader variant (type=%u, key=%u) %d\n",
784 /* We don't know the value of nr_ps_max_color_exports until we built
785 * at least one variant, so we may need to recompute the key after
786 * building first variant. */
787 if (sel
->type
== PIPE_SHADER_FRAGMENT
&&
788 sel
->num_shaders
== 0) {
789 sel
->nr_ps_max_color_exports
= shader
->shader
.nr_ps_max_color_exports
;
790 key
= r600_shader_selector_key(ctx
, sel
);
800 shader
->next_variant
= sel
->current
;
801 sel
->current
= shader
;
803 if (rctx
->chip_class
< EVERGREEN
&& rctx
->ps_shader
&& rctx
->vs_shader
) {
804 r600_adjust_gprs(rctx
);
807 if (rctx
->ps_shader
&&
808 rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
809 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
810 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
815 static void *r600_create_shader_state(struct pipe_context
*ctx
,
816 const struct pipe_shader_state
*state
,
817 unsigned pipe_shader_type
)
819 struct r600_pipe_shader_selector
*sel
= CALLOC_STRUCT(r600_pipe_shader_selector
);
822 sel
->type
= pipe_shader_type
;
823 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
824 sel
->so
= state
->stream_output
;
826 r
= r600_shader_select(ctx
, sel
, NULL
);
833 static void *r600_create_ps_state(struct pipe_context
*ctx
,
834 const struct pipe_shader_state
*state
)
836 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_FRAGMENT
);
839 static void *r600_create_vs_state(struct pipe_context
*ctx
,
840 const struct pipe_shader_state
*state
)
842 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_VERTEX
);
845 static void r600_bind_ps_state(struct pipe_context
*ctx
, void *state
)
847 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
850 state
= rctx
->dummy_pixel_shader
;
852 rctx
->ps_shader
= (struct r600_pipe_shader_selector
*)state
;
853 r600_context_pipe_state_set(rctx
, &rctx
->ps_shader
->current
->rstate
);
855 if (rctx
->chip_class
<= R700
) {
856 bool multiwrite
= rctx
->ps_shader
->current
->shader
.fs_write_all
;
858 if (rctx
->cb_misc_state
.multiwrite
!= multiwrite
) {
859 rctx
->cb_misc_state
.multiwrite
= multiwrite
;
860 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
864 r600_adjust_gprs(rctx
);
867 if (rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
868 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
869 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
873 static void r600_bind_vs_state(struct pipe_context
*ctx
, void *state
)
875 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
877 rctx
->vs_shader
= (struct r600_pipe_shader_selector
*)state
;
879 r600_context_pipe_state_set(rctx
, &rctx
->vs_shader
->current
->rstate
);
881 if (rctx
->chip_class
< EVERGREEN
&& rctx
->ps_shader
)
882 r600_adjust_gprs(rctx
);
884 /* Update clip misc state. */
885 if (rctx
->vs_shader
->current
->pa_cl_vs_out_cntl
!= rctx
->clip_misc_state
.pa_cl_vs_out_cntl
||
886 rctx
->vs_shader
->current
->shader
.clip_dist_write
!= rctx
->clip_misc_state
.clip_dist_write
) {
887 rctx
->clip_misc_state
.pa_cl_vs_out_cntl
= rctx
->vs_shader
->current
->pa_cl_vs_out_cntl
;
888 rctx
->clip_misc_state
.clip_dist_write
= rctx
->vs_shader
->current
->shader
.clip_dist_write
;
889 r600_atom_dirty(rctx
, &rctx
->clip_misc_state
.atom
);
894 static void r600_delete_shader_selector(struct pipe_context
*ctx
,
895 struct r600_pipe_shader_selector
*sel
)
897 struct r600_pipe_shader
*p
= sel
->current
, *c
;
900 r600_pipe_shader_destroy(ctx
, p
);
910 static void r600_delete_ps_state(struct pipe_context
*ctx
, void *state
)
912 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
913 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
915 if (rctx
->ps_shader
== sel
) {
916 rctx
->ps_shader
= NULL
;
919 r600_delete_shader_selector(ctx
, sel
);
922 static void r600_delete_vs_state(struct pipe_context
*ctx
, void *state
)
924 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
925 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
927 if (rctx
->vs_shader
== sel
) {
928 rctx
->vs_shader
= NULL
;
931 r600_delete_shader_selector(ctx
, sel
);
934 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
)
936 if (state
->dirty_mask
) {
937 rctx
->flags
|= R600_CONTEXT_SHADERCONST_FLUSH
;
938 state
->atom
.num_dw
= rctx
->chip_class
>= EVERGREEN
? util_bitcount(state
->dirty_mask
)*20
939 : util_bitcount(state
->dirty_mask
)*19;
940 r600_atom_dirty(rctx
, &state
->atom
);
944 static void r600_set_constant_buffer(struct pipe_context
*ctx
, uint shader
, uint index
,
945 struct pipe_constant_buffer
*input
)
947 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
948 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
949 struct pipe_constant_buffer
*cb
;
952 /* Note that the state tracker can unbind constant buffers by
955 if (unlikely(!input
)) {
956 state
->enabled_mask
&= ~(1 << index
);
957 state
->dirty_mask
&= ~(1 << index
);
958 pipe_resource_reference(&state
->cb
[index
].buffer
, NULL
);
962 cb
= &state
->cb
[index
];
963 cb
->buffer_size
= input
->buffer_size
;
965 ptr
= input
->user_buffer
;
968 /* Upload the user buffer. */
969 if (R600_BIG_ENDIAN
) {
971 unsigned i
, size
= input
->buffer_size
;
973 if (!(tmpPtr
= malloc(size
))) {
974 R600_ERR("Failed to allocate BE swap buffer.\n");
978 for (i
= 0; i
< size
/ 4; ++i
) {
979 tmpPtr
[i
] = bswap_32(((uint32_t *)ptr
)[i
]);
982 u_upload_data(rctx
->uploader
, 0, size
, tmpPtr
, &cb
->buffer_offset
, &cb
->buffer
);
985 u_upload_data(rctx
->uploader
, 0, input
->buffer_size
, ptr
, &cb
->buffer_offset
, &cb
->buffer
);
988 /* Setup the hw buffer. */
989 cb
->buffer_offset
= input
->buffer_offset
;
990 pipe_resource_reference(&cb
->buffer
, input
->buffer
);
993 state
->enabled_mask
|= 1 << index
;
994 state
->dirty_mask
|= 1 << index
;
995 r600_constant_buffers_dirty(rctx
, state
);
998 static struct pipe_stream_output_target
*
999 r600_create_so_target(struct pipe_context
*ctx
,
1000 struct pipe_resource
*buffer
,
1001 unsigned buffer_offset
,
1002 unsigned buffer_size
)
1004 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1005 struct r600_so_target
*t
;
1008 t
= CALLOC_STRUCT(r600_so_target
);
1013 t
->b
.reference
.count
= 1;
1015 pipe_resource_reference(&t
->b
.buffer
, buffer
);
1016 t
->b
.buffer_offset
= buffer_offset
;
1017 t
->b
.buffer_size
= buffer_size
;
1019 t
->filled_size
= (struct r600_resource
*)
1020 pipe_buffer_create(ctx
->screen
, PIPE_BIND_CUSTOM
, PIPE_USAGE_STATIC
, 4);
1021 ptr
= rctx
->ws
->buffer_map(t
->filled_size
->cs_buf
, rctx
->cs
, PIPE_TRANSFER_WRITE
);
1022 memset(ptr
, 0, t
->filled_size
->buf
->size
);
1023 rctx
->ws
->buffer_unmap(t
->filled_size
->cs_buf
);
1028 static void r600_so_target_destroy(struct pipe_context
*ctx
,
1029 struct pipe_stream_output_target
*target
)
1031 struct r600_so_target
*t
= (struct r600_so_target
*)target
;
1032 pipe_resource_reference(&t
->b
.buffer
, NULL
);
1033 pipe_resource_reference((struct pipe_resource
**)&t
->filled_size
, NULL
);
1037 static void r600_set_so_targets(struct pipe_context
*ctx
,
1038 unsigned num_targets
,
1039 struct pipe_stream_output_target
**targets
,
1040 unsigned append_bitmask
)
1042 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1045 /* Stop streamout. */
1046 if (rctx
->num_so_targets
&& !rctx
->streamout_start
) {
1047 r600_context_streamout_end(rctx
);
1050 /* Set the new targets. */
1051 for (i
= 0; i
< num_targets
; i
++) {
1052 pipe_so_target_reference((struct pipe_stream_output_target
**)&rctx
->so_targets
[i
], targets
[i
]);
1054 for (; i
< rctx
->num_so_targets
; i
++) {
1055 pipe_so_target_reference((struct pipe_stream_output_target
**)&rctx
->so_targets
[i
], NULL
);
1058 rctx
->num_so_targets
= num_targets
;
1059 rctx
->streamout_start
= num_targets
!= 0;
1060 rctx
->streamout_append_bitmask
= append_bitmask
;
1063 static void r600_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
1065 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
1067 if (rctx
->sample_mask
.sample_mask
== (uint16_t)sample_mask
)
1070 rctx
->sample_mask
.sample_mask
= sample_mask
;
1071 r600_atom_dirty(rctx
, &rctx
->sample_mask
.atom
);
1074 static void r600_update_derived_state(struct r600_context
*rctx
)
1076 struct pipe_context
* ctx
= (struct pipe_context
*)rctx
;
1077 unsigned ps_dirty
= 0, blend_override
;
1079 if (!rctx
->blitter
->running
) {
1082 /* Decompress textures if needed. */
1083 for (i
= 0; i
< PIPE_SHADER_TYPES
; i
++) {
1084 struct r600_samplerview_state
*views
= &rctx
->samplers
[i
].views
;
1085 if (views
->compressed_depthtex_mask
) {
1086 r600_decompress_depth_textures(rctx
, views
);
1088 if (views
->compressed_colortex_mask
) {
1089 r600_decompress_color_textures(rctx
, views
);
1094 r600_shader_select(ctx
, rctx
->ps_shader
, &ps_dirty
);
1096 if (rctx
->ps_shader
&& ((rctx
->sprite_coord_enable
&&
1097 (rctx
->ps_shader
->current
->sprite_coord_enable
!= rctx
->sprite_coord_enable
)) ||
1098 (rctx
->rasterizer
&& rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
))) {
1100 if (rctx
->chip_class
>= EVERGREEN
)
1101 evergreen_pipe_shader_ps(ctx
, rctx
->ps_shader
->current
);
1103 r600_pipe_shader_ps(ctx
, rctx
->ps_shader
->current
);
1109 r600_context_pipe_state_set(rctx
, &rctx
->ps_shader
->current
->rstate
);
1111 blend_override
= (rctx
->dual_src_blend
&&
1112 rctx
->ps_shader
->current
->nr_ps_color_outputs
< 2);
1114 if (blend_override
!= rctx
->blend_override
) {
1115 rctx
->blend_override
= blend_override
;
1116 r600_bind_blend_state_internal(rctx
,
1117 blend_override
? rctx
->no_blend
: rctx
->blend
);
1120 if (rctx
->chip_class
>= EVERGREEN
) {
1121 evergreen_update_dual_export_state(rctx
);
1123 r600_update_dual_export_state(rctx
);
1127 static unsigned r600_conv_prim_to_gs_out(unsigned mode
)
1129 static const int prim_conv
[] = {
1130 V_028A6C_OUTPRIM_TYPE_POINTLIST
,
1131 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1132 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1133 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1134 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1135 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1136 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1137 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1138 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1139 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1140 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1141 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1142 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1143 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1144 V_028A6C_OUTPRIM_TYPE_TRISTRIP
1146 assert(mode
< Elements(prim_conv
));
1148 return prim_conv
[mode
];
1151 void r600_emit_clip_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1153 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1154 struct r600_clip_misc_state
*state
= &rctx
->clip_misc_state
;
1156 r600_write_context_reg(cs
, R_028810_PA_CL_CLIP_CNTL
,
1157 state
->pa_cl_clip_cntl
|
1158 (state
->clip_dist_write
? 0 : state
->clip_plane_enable
& 0x3F));
1159 r600_write_context_reg(cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
1160 state
->pa_cl_vs_out_cntl
|
1161 (state
->clip_plane_enable
& state
->clip_dist_write
));
1164 static void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*dinfo
)
1166 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1167 struct pipe_draw_info info
= *dinfo
;
1168 struct pipe_index_buffer ib
= {};
1169 unsigned prim
, ls_mask
= 0, i
;
1170 struct r600_block
*dirty_block
= NULL
, *next_block
= NULL
;
1171 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1175 if ((!info
.count
&& (info
.indexed
|| !info
.count_from_stream_output
)) ||
1176 !r600_conv_pipe_prim(info
.mode
, &prim
)) {
1181 if (!rctx
->vs_shader
) {
1186 r600_update_derived_state(rctx
);
1189 /* Initialize the index buffer struct. */
1190 pipe_resource_reference(&ib
.buffer
, rctx
->index_buffer
.buffer
);
1191 ib
.user_buffer
= rctx
->index_buffer
.user_buffer
;
1192 ib
.index_size
= rctx
->index_buffer
.index_size
;
1193 ib
.offset
= rctx
->index_buffer
.offset
+ info
.start
* ib
.index_size
;
1195 /* Translate or upload, if needed. */
1196 r600_translate_index_buffer(rctx
, &ib
, info
.count
);
1198 ptr
= (uint8_t*)ib
.user_buffer
;
1199 if (!ib
.buffer
&& ptr
) {
1200 u_upload_data(rctx
->uploader
, 0, info
.count
* ib
.index_size
,
1201 ptr
, &ib
.offset
, &ib
.buffer
);
1204 info
.index_bias
= info
.start
;
1207 if (rctx
->vgt
.id
!= R600_PIPE_STATE_VGT
) {
1208 rctx
->vgt
.id
= R600_PIPE_STATE_VGT
;
1209 rctx
->vgt
.nregs
= 0;
1210 r600_pipe_state_add_reg(&rctx
->vgt
, R_008958_VGT_PRIMITIVE_TYPE
, prim
);
1211 r600_pipe_state_add_reg(&rctx
->vgt
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, 0);
1212 r600_pipe_state_add_reg(&rctx
->vgt
, R_028408_VGT_INDX_OFFSET
, info
.index_bias
);
1213 r600_pipe_state_add_reg(&rctx
->vgt
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
, info
.restart_index
);
1214 r600_pipe_state_add_reg(&rctx
->vgt
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, info
.primitive_restart
);
1215 r600_pipe_state_add_reg(&rctx
->vgt
, R_03CFF4_SQ_VTX_START_INST_LOC
, info
.start_instance
);
1216 r600_pipe_state_add_reg(&rctx
->vgt
, R_028A0C_PA_SC_LINE_STIPPLE
, 0);
1219 rctx
->vgt
.nregs
= 0;
1220 r600_pipe_state_mod_reg(&rctx
->vgt
, prim
);
1221 r600_pipe_state_mod_reg(&rctx
->vgt
, r600_conv_prim_to_gs_out(info
.mode
));
1222 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.index_bias
);
1223 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.restart_index
);
1224 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.primitive_restart
);
1225 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.start_instance
);
1227 if (prim
== V_008958_DI_PT_LINELIST
)
1229 else if (prim
== V_008958_DI_PT_LINESTRIP
||
1230 prim
== V_008958_DI_PT_LINELOOP
)
1232 r600_pipe_state_mod_reg(&rctx
->vgt
, S_028A0C_AUTO_RESET_CNTL(ls_mask
) | rctx
->pa_sc_line_stipple
);
1234 r600_context_pipe_state_set(rctx
, &rctx
->vgt
);
1236 /* Enable stream out if needed. */
1237 if (rctx
->streamout_start
) {
1238 r600_context_streamout_begin(rctx
);
1239 rctx
->streamout_start
= FALSE
;
1242 /* Emit states (the function expects that we emit at most 17 dwords here). */
1243 r600_need_cs_space(rctx
, 0, TRUE
);
1244 r600_flush_emit(rctx
);
1246 for (i
= 0; i
< R600_NUM_ATOMS
; i
++) {
1247 if (rctx
->atoms
[i
] == NULL
|| !rctx
->atoms
[i
]->dirty
) {
1250 r600_emit_atom(rctx
, rctx
->atoms
[i
]);
1252 LIST_FOR_EACH_ENTRY_SAFE(dirty_block
, next_block
, &rctx
->dirty
,list
) {
1253 r600_context_block_emit_dirty(rctx
, dirty_block
, 0 /* pkt_flags */);
1255 rctx
->pm4_dirty_cdwords
= 0;
1258 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NUM_INSTANCES
, 0, rctx
->predicate_drawing
);
1259 cs
->buf
[cs
->cdw
++] = info
.instance_count
;
1261 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_INDEX_TYPE
, 0, rctx
->predicate_drawing
);
1262 cs
->buf
[cs
->cdw
++] = ib
.index_size
== 4 ?
1263 (VGT_INDEX_32
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_32_BIT
: 0)) :
1264 (VGT_INDEX_16
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_16_BIT
: 0));
1266 va
= r600_resource_va(ctx
->screen
, ib
.buffer
);
1268 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX
, 3, rctx
->predicate_drawing
);
1269 cs
->buf
[cs
->cdw
++] = va
;
1270 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFF;
1271 cs
->buf
[cs
->cdw
++] = info
.count
;
1272 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_DMA
;
1273 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, rctx
->predicate_drawing
);
1274 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(rctx
, (struct r600_resource
*)ib
.buffer
, RADEON_USAGE_READ
);
1276 if (info
.count_from_stream_output
) {
1277 struct r600_so_target
*t
= (struct r600_so_target
*)info
.count_from_stream_output
;
1278 uint64_t va
= r600_resource_va(&rctx
->screen
->screen
, (void*)t
->filled_size
);
1280 r600_write_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
, t
->stride_in_dw
);
1282 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_COPY_DW
, 4, 0);
1283 cs
->buf
[cs
->cdw
++] = COPY_DW_SRC_IS_MEM
| COPY_DW_DST_IS_REG
;
1284 cs
->buf
[cs
->cdw
++] = va
& 0xFFFFFFFFUL
; /* src address lo */
1285 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFFUL
; /* src address hi */
1286 cs
->buf
[cs
->cdw
++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2; /* dst register */
1287 cs
->buf
[cs
->cdw
++] = 0; /* unused */
1289 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
1290 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(rctx
, t
->filled_size
, RADEON_USAGE_READ
);
1293 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX_AUTO
, 1, rctx
->predicate_drawing
);
1294 cs
->buf
[cs
->cdw
++] = info
.count
;
1295 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
1296 (info
.count_from_stream_output
? S_0287F0_USE_OPAQUE(1) : 0);
1299 /* Set the depth buffer as dirty. */
1300 if (rctx
->framebuffer
.zsbuf
) {
1301 struct pipe_surface
*surf
= rctx
->framebuffer
.zsbuf
;
1302 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
1304 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1306 if (rctx
->compressed_cb_mask
) {
1307 struct pipe_surface
*surf
;
1308 struct r600_texture
*rtex
;
1309 unsigned mask
= rctx
->compressed_cb_mask
;
1312 unsigned i
= u_bit_scan(&mask
);
1313 surf
= rctx
->framebuffer
.cbufs
[i
];
1314 rtex
= (struct r600_texture
*)surf
->texture
;
1316 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1321 pipe_resource_reference(&ib
.buffer
, NULL
);
1324 void r600_draw_rectangle(struct blitter_context
*blitter
,
1325 unsigned x1
, unsigned y1
, unsigned x2
, unsigned y2
, float depth
,
1326 enum blitter_attrib_type type
, const union pipe_color_union
*attrib
)
1328 struct r600_context
*rctx
= (struct r600_context
*)util_blitter_get_pipe(blitter
);
1329 struct pipe_viewport_state viewport
;
1330 struct pipe_resource
*buf
= NULL
;
1331 unsigned offset
= 0;
1334 if (type
== UTIL_BLITTER_ATTRIB_TEXCOORD
) {
1335 util_blitter_draw_rectangle(blitter
, x1
, y1
, x2
, y2
, depth
, type
, attrib
);
1339 /* Some operations (like color resolve on r6xx) don't work
1340 * with the conventional primitive types.
1341 * One that works is PT_RECTLIST, which we use here. */
1343 /* setup viewport */
1344 viewport
.scale
[0] = 1.0f
;
1345 viewport
.scale
[1] = 1.0f
;
1346 viewport
.scale
[2] = 1.0f
;
1347 viewport
.scale
[3] = 1.0f
;
1348 viewport
.translate
[0] = 0.0f
;
1349 viewport
.translate
[1] = 0.0f
;
1350 viewport
.translate
[2] = 0.0f
;
1351 viewport
.translate
[3] = 0.0f
;
1352 rctx
->context
.set_viewport_state(&rctx
->context
, &viewport
);
1354 /* Upload vertices. The hw rectangle has only 3 vertices,
1355 * I guess the 4th one is derived from the first 3.
1356 * The vertex specification should match u_blitter's vertex element state. */
1357 u_upload_alloc(rctx
->uploader
, 0, sizeof(float) * 24, &offset
, &buf
, (void**)&vb
);
1374 memcpy(vb
+4, attrib
->f
, sizeof(float)*4);
1375 memcpy(vb
+12, attrib
->f
, sizeof(float)*4);
1376 memcpy(vb
+20, attrib
->f
, sizeof(float)*4);
1380 util_draw_vertex_buffer(&rctx
->context
, NULL
, buf
, offset
,
1381 R600_PRIM_RECTANGLE_LIST
, 3, 2);
1382 pipe_resource_reference(&buf
, NULL
);
1385 void _r600_pipe_state_add_reg_bo(struct r600_context
*ctx
,
1386 struct r600_pipe_state
*state
,
1387 uint32_t offset
, uint32_t value
,
1388 uint32_t range_id
, uint32_t block_id
,
1389 struct r600_resource
*bo
,
1390 enum radeon_bo_usage usage
)
1393 struct r600_range
*range
;
1394 struct r600_block
*block
;
1396 if (bo
) assert(usage
);
1398 range
= &ctx
->range
[range_id
];
1399 block
= range
->blocks
[block_id
];
1400 state
->regs
[state
->nregs
].block
= block
;
1401 state
->regs
[state
->nregs
].id
= (offset
- block
->start_offset
) >> 2;
1403 state
->regs
[state
->nregs
].value
= value
;
1404 state
->regs
[state
->nregs
].bo
= bo
;
1405 state
->regs
[state
->nregs
].bo_usage
= usage
;
1408 assert(state
->nregs
< R600_BLOCK_MAX_REG
);
1411 void _r600_pipe_state_add_reg(struct r600_context
*ctx
,
1412 struct r600_pipe_state
*state
,
1413 uint32_t offset
, uint32_t value
,
1414 uint32_t range_id
, uint32_t block_id
)
1416 _r600_pipe_state_add_reg_bo(ctx
, state
, offset
, value
,
1417 range_id
, block_id
, NULL
, 0);
1420 uint32_t r600_translate_stencil_op(int s_op
)
1423 case PIPE_STENCIL_OP_KEEP
:
1424 return V_028800_STENCIL_KEEP
;
1425 case PIPE_STENCIL_OP_ZERO
:
1426 return V_028800_STENCIL_ZERO
;
1427 case PIPE_STENCIL_OP_REPLACE
:
1428 return V_028800_STENCIL_REPLACE
;
1429 case PIPE_STENCIL_OP_INCR
:
1430 return V_028800_STENCIL_INCR
;
1431 case PIPE_STENCIL_OP_DECR
:
1432 return V_028800_STENCIL_DECR
;
1433 case PIPE_STENCIL_OP_INCR_WRAP
:
1434 return V_028800_STENCIL_INCR_WRAP
;
1435 case PIPE_STENCIL_OP_DECR_WRAP
:
1436 return V_028800_STENCIL_DECR_WRAP
;
1437 case PIPE_STENCIL_OP_INVERT
:
1438 return V_028800_STENCIL_INVERT
;
1440 R600_ERR("Unknown stencil op %d", s_op
);
1447 uint32_t r600_translate_fill(uint32_t func
)
1450 case PIPE_POLYGON_MODE_FILL
:
1452 case PIPE_POLYGON_MODE_LINE
:
1454 case PIPE_POLYGON_MODE_POINT
:
1462 unsigned r600_tex_wrap(unsigned wrap
)
1466 case PIPE_TEX_WRAP_REPEAT
:
1467 return V_03C000_SQ_TEX_WRAP
;
1468 case PIPE_TEX_WRAP_CLAMP
:
1469 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER
;
1470 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1471 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL
;
1472 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1473 return V_03C000_SQ_TEX_CLAMP_BORDER
;
1474 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1475 return V_03C000_SQ_TEX_MIRROR
;
1476 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1477 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1478 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1479 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1480 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1481 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER
;
1485 unsigned r600_tex_filter(unsigned filter
)
1489 case PIPE_TEX_FILTER_NEAREST
:
1490 return V_03C000_SQ_TEX_XY_FILTER_POINT
;
1491 case PIPE_TEX_FILTER_LINEAR
:
1492 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR
;
1496 unsigned r600_tex_mipfilter(unsigned filter
)
1499 case PIPE_TEX_MIPFILTER_NEAREST
:
1500 return V_03C000_SQ_TEX_Z_FILTER_POINT
;
1501 case PIPE_TEX_MIPFILTER_LINEAR
:
1502 return V_03C000_SQ_TEX_Z_FILTER_LINEAR
;
1504 case PIPE_TEX_MIPFILTER_NONE
:
1505 return V_03C000_SQ_TEX_Z_FILTER_NONE
;
1509 unsigned r600_tex_compare(unsigned compare
)
1513 case PIPE_FUNC_NEVER
:
1514 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER
;
1515 case PIPE_FUNC_LESS
:
1516 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS
;
1517 case PIPE_FUNC_EQUAL
:
1518 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1519 case PIPE_FUNC_LEQUAL
:
1520 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1521 case PIPE_FUNC_GREATER
:
1522 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER
;
1523 case PIPE_FUNC_NOTEQUAL
:
1524 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1525 case PIPE_FUNC_GEQUAL
:
1526 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1527 case PIPE_FUNC_ALWAYS
:
1528 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1532 /* keep this at the end of this file, please */
1533 void r600_init_common_state_functions(struct r600_context
*rctx
)
1535 rctx
->context
.create_fs_state
= r600_create_ps_state
;
1536 rctx
->context
.create_vs_state
= r600_create_vs_state
;
1537 rctx
->context
.create_vertex_elements_state
= r600_create_vertex_elements
;
1538 rctx
->context
.bind_blend_state
= r600_bind_blend_state
;
1539 rctx
->context
.bind_depth_stencil_alpha_state
= r600_bind_dsa_state
;
1540 rctx
->context
.bind_fragment_sampler_states
= r600_bind_ps_sampler_states
;
1541 rctx
->context
.bind_fs_state
= r600_bind_ps_state
;
1542 rctx
->context
.bind_rasterizer_state
= r600_bind_rs_state
;
1543 rctx
->context
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
1544 rctx
->context
.bind_vertex_sampler_states
= r600_bind_vs_sampler_states
;
1545 rctx
->context
.bind_vs_state
= r600_bind_vs_state
;
1546 rctx
->context
.delete_blend_state
= r600_delete_state
;
1547 rctx
->context
.delete_depth_stencil_alpha_state
= r600_delete_state
;
1548 rctx
->context
.delete_fs_state
= r600_delete_ps_state
;
1549 rctx
->context
.delete_rasterizer_state
= r600_delete_rs_state
;
1550 rctx
->context
.delete_sampler_state
= r600_delete_sampler_state
;
1551 rctx
->context
.delete_vertex_elements_state
= r600_delete_vertex_elements
;
1552 rctx
->context
.delete_vs_state
= r600_delete_vs_state
;
1553 rctx
->context
.set_blend_color
= r600_set_blend_color
;
1554 rctx
->context
.set_clip_state
= r600_set_clip_state
;
1555 rctx
->context
.set_constant_buffer
= r600_set_constant_buffer
;
1556 rctx
->context
.set_sample_mask
= r600_set_sample_mask
;
1557 rctx
->context
.set_stencil_ref
= r600_set_pipe_stencil_ref
;
1558 rctx
->context
.set_viewport_state
= r600_set_viewport_state
;
1559 rctx
->context
.set_vertex_buffers
= r600_set_vertex_buffers
;
1560 rctx
->context
.set_index_buffer
= r600_set_index_buffer
;
1561 rctx
->context
.set_fragment_sampler_views
= r600_set_ps_sampler_views
;
1562 rctx
->context
.set_vertex_sampler_views
= r600_set_vs_sampler_views
;
1563 rctx
->context
.sampler_view_destroy
= r600_sampler_view_destroy
;
1564 rctx
->context
.texture_barrier
= r600_texture_barrier
;
1565 rctx
->context
.create_stream_output_target
= r600_create_so_target
;
1566 rctx
->context
.stream_output_target_destroy
= r600_so_target_destroy
;
1567 rctx
->context
.set_stream_output_targets
= r600_set_so_targets
;
1568 rctx
->context
.draw_vbo
= r600_draw_vbo
;