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r600g: remove unused flag have_depth_fb
[mesa.git] / src / gallium / drivers / r600 / r600_state_common.c
1 /*
2 * Copyright 2010 Red Hat Inc.
3 * 2010 Jerome Glisse
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
26 */
27 #include "r600_formats.h"
28 #include "r600d.h"
29
30 #include "util/u_blitter.h"
31 #include "util/u_upload_mgr.h"
32 #include "tgsi/tgsi_parse.h"
33 #include <byteswap.h>
34
35 static void r600_emit_command_buffer(struct r600_context *rctx, struct r600_atom *atom)
36 {
37 struct radeon_winsys_cs *cs = rctx->cs;
38 struct r600_command_buffer *cb = (struct r600_command_buffer*)atom;
39
40 assert(cs->cdw + cb->atom.num_dw <= RADEON_MAX_CMDBUF_DWORDS);
41 memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->atom.num_dw);
42 cs->cdw += cb->atom.num_dw;
43 }
44
45 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags)
46 {
47 cb->atom.emit = r600_emit_command_buffer;
48 cb->atom.num_dw = 0;
49 cb->atom.flags = flags;
50 cb->buf = CALLOC(1, 4 * num_dw);
51 cb->max_num_dw = num_dw;
52 }
53
54 void r600_release_command_buffer(struct r600_command_buffer *cb)
55 {
56 FREE(cb->buf);
57 }
58
59 static void r600_emit_surface_sync(struct r600_context *rctx, struct r600_atom *atom)
60 {
61 struct radeon_winsys_cs *cs = rctx->cs;
62 struct r600_surface_sync_cmd *a = (struct r600_surface_sync_cmd*)atom;
63
64 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
65 cs->buf[cs->cdw++] = a->flush_flags; /* CP_COHER_CNTL */
66 cs->buf[cs->cdw++] = 0xffffffff; /* CP_COHER_SIZE */
67 cs->buf[cs->cdw++] = 0; /* CP_COHER_BASE */
68 cs->buf[cs->cdw++] = 0x0000000A; /* POLL_INTERVAL */
69
70 a->flush_flags = 0;
71 }
72
73 static void r600_emit_r6xx_flush_and_inv(struct r600_context *rctx, struct r600_atom *atom)
74 {
75 struct radeon_winsys_cs *cs = rctx->cs;
76 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
77 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
78 }
79
80 void r600_init_atom(struct r600_atom *atom,
81 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
82 unsigned num_dw, enum r600_atom_flags flags)
83 {
84 atom->emit = emit;
85 atom->num_dw = num_dw;
86 atom->flags = flags;
87 }
88
89 void r600_init_common_atoms(struct r600_context *rctx)
90 {
91 r600_init_atom(&rctx->surface_sync_cmd.atom, r600_emit_surface_sync, 5, EMIT_EARLY);
92 r600_init_atom(&rctx->r6xx_flush_and_inv_cmd, r600_emit_r6xx_flush_and_inv, 2, EMIT_EARLY);
93 }
94
95 unsigned r600_get_cb_flush_flags(struct r600_context *rctx)
96 {
97 unsigned flags = 0;
98
99 if (rctx->framebuffer.nr_cbufs) {
100 flags |= S_0085F0_CB_ACTION_ENA(1) |
101 (((1 << rctx->framebuffer.nr_cbufs) - 1) << S_0085F0_CB0_DEST_BASE_ENA_SHIFT);
102 }
103
104 /* Workaround for broken flushing on some R6xx chipsets. */
105 if (rctx->family == CHIP_RV670 ||
106 rctx->family == CHIP_RS780 ||
107 rctx->family == CHIP_RS880) {
108 flags |= S_0085F0_CB1_DEST_BASE_ENA(1) |
109 S_0085F0_DEST_BASE_0_ENA(1);
110 }
111 return flags;
112 }
113
114 void r600_texture_barrier(struct pipe_context *ctx)
115 {
116 struct r600_context *rctx = (struct r600_context *)ctx;
117
118 rctx->surface_sync_cmd.flush_flags |= S_0085F0_TC_ACTION_ENA(1) | r600_get_cb_flush_flags(rctx);
119 r600_atom_dirty(rctx, &rctx->surface_sync_cmd.atom);
120 }
121
122 static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
123 {
124 static const int prim_conv[] = {
125 V_008958_DI_PT_POINTLIST,
126 V_008958_DI_PT_LINELIST,
127 V_008958_DI_PT_LINELOOP,
128 V_008958_DI_PT_LINESTRIP,
129 V_008958_DI_PT_TRILIST,
130 V_008958_DI_PT_TRISTRIP,
131 V_008958_DI_PT_TRIFAN,
132 V_008958_DI_PT_QUADLIST,
133 V_008958_DI_PT_QUADSTRIP,
134 V_008958_DI_PT_POLYGON,
135 -1,
136 -1,
137 -1,
138 -1
139 };
140
141 *prim = prim_conv[pprim];
142 if (*prim == -1) {
143 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim);
144 return false;
145 }
146 return true;
147 }
148
149 /* common state between evergreen and r600 */
150 void r600_bind_blend_state(struct pipe_context *ctx, void *state)
151 {
152 struct r600_context *rctx = (struct r600_context *)ctx;
153 struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
154 struct r600_pipe_state *rstate;
155 bool update_cb = false;
156
157 if (state == NULL)
158 return;
159 rstate = &blend->rstate;
160 rctx->states[rstate->id] = rstate;
161 rctx->dual_src_blend = blend->dual_src_blend;
162 r600_context_pipe_state_set(rctx, rstate);
163
164 if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) {
165 rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
166 update_cb = true;
167 }
168 if (rctx->chip_class <= R700 &&
169 rctx->cb_misc_state.cb_color_control != blend->cb_color_control) {
170 rctx->cb_misc_state.cb_color_control = blend->cb_color_control;
171 update_cb = true;
172 }
173 if (rctx->cb_misc_state.dual_src_blend != blend->dual_src_blend) {
174 rctx->cb_misc_state.dual_src_blend = blend->dual_src_blend;
175 update_cb = true;
176 }
177 if (update_cb) {
178 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
179 }
180 }
181
182 void r600_set_blend_color(struct pipe_context *ctx,
183 const struct pipe_blend_color *state)
184 {
185 struct r600_context *rctx = (struct r600_context *)ctx;
186 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
187
188 if (rstate == NULL)
189 return;
190
191 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
192 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]));
193 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
194 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
195 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
196
197 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
198 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
199 r600_context_pipe_state_set(rctx, rstate);
200 }
201
202 static void r600_set_stencil_ref(struct pipe_context *ctx,
203 const struct r600_stencil_ref *state)
204 {
205 struct r600_context *rctx = (struct r600_context *)ctx;
206 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
207
208 if (rstate == NULL)
209 return;
210
211 rstate->id = R600_PIPE_STATE_STENCIL_REF;
212 r600_pipe_state_add_reg(rstate,
213 R_028430_DB_STENCILREFMASK,
214 S_028430_STENCILREF(state->ref_value[0]) |
215 S_028430_STENCILMASK(state->valuemask[0]) |
216 S_028430_STENCILWRITEMASK(state->writemask[0]));
217 r600_pipe_state_add_reg(rstate,
218 R_028434_DB_STENCILREFMASK_BF,
219 S_028434_STENCILREF_BF(state->ref_value[1]) |
220 S_028434_STENCILMASK_BF(state->valuemask[1]) |
221 S_028434_STENCILWRITEMASK_BF(state->writemask[1]));
222
223 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
224 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
225 r600_context_pipe_state_set(rctx, rstate);
226 }
227
228 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
229 const struct pipe_stencil_ref *state)
230 {
231 struct r600_context *rctx = (struct r600_context *)ctx;
232 struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA];
233 struct r600_stencil_ref ref;
234
235 rctx->stencil_ref = *state;
236
237 if (!dsa)
238 return;
239
240 ref.ref_value[0] = state->ref_value[0];
241 ref.ref_value[1] = state->ref_value[1];
242 ref.valuemask[0] = dsa->valuemask[0];
243 ref.valuemask[1] = dsa->valuemask[1];
244 ref.writemask[0] = dsa->writemask[0];
245 ref.writemask[1] = dsa->writemask[1];
246
247 r600_set_stencil_ref(ctx, &ref);
248 }
249
250 void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
251 {
252 struct r600_context *rctx = (struct r600_context *)ctx;
253 struct r600_pipe_dsa *dsa = state;
254 struct r600_pipe_state *rstate;
255 struct r600_stencil_ref ref;
256
257 if (state == NULL)
258 return;
259 rstate = &dsa->rstate;
260 rctx->states[rstate->id] = rstate;
261 rctx->sx_alpha_test_control &= ~0xff;
262 rctx->sx_alpha_test_control |= dsa->sx_alpha_test_control;
263 rctx->alpha_ref = dsa->alpha_ref;
264 rctx->alpha_ref_dirty = true;
265 r600_context_pipe_state_set(rctx, rstate);
266
267 ref.ref_value[0] = rctx->stencil_ref.ref_value[0];
268 ref.ref_value[1] = rctx->stencil_ref.ref_value[1];
269 ref.valuemask[0] = dsa->valuemask[0];
270 ref.valuemask[1] = dsa->valuemask[1];
271 ref.writemask[0] = dsa->writemask[0];
272 ref.writemask[1] = dsa->writemask[1];
273
274 r600_set_stencil_ref(ctx, &ref);
275 }
276
277 void r600_set_max_scissor(struct r600_context *rctx)
278 {
279 /* Set a scissor state such that it doesn't do anything. */
280 struct pipe_scissor_state scissor;
281 scissor.minx = 0;
282 scissor.miny = 0;
283 scissor.maxx = 8192;
284 scissor.maxy = 8192;
285
286 r600_set_scissor_state(rctx, &scissor);
287 }
288
289 void r600_bind_rs_state(struct pipe_context *ctx, void *state)
290 {
291 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
292 struct r600_context *rctx = (struct r600_context *)ctx;
293
294 if (state == NULL)
295 return;
296
297 rctx->sprite_coord_enable = rs->sprite_coord_enable;
298 rctx->two_side = rs->two_side;
299 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
300 rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
301
302 rctx->rasterizer = rs;
303
304 rctx->states[rs->rstate.id] = &rs->rstate;
305 r600_context_pipe_state_set(rctx, &rs->rstate);
306
307 if (rctx->chip_class >= EVERGREEN) {
308 evergreen_polygon_offset_update(rctx);
309 } else {
310 r600_polygon_offset_update(rctx);
311 }
312
313 /* Workaround for a missing scissor enable on r600. */
314 if (rctx->chip_class == R600) {
315 if (rs->scissor_enable != rctx->scissor_enable) {
316 rctx->scissor_enable = rs->scissor_enable;
317
318 if (rs->scissor_enable) {
319 r600_set_scissor_state(rctx, &rctx->scissor_state);
320 } else {
321 r600_set_max_scissor(rctx);
322 }
323 }
324 }
325 }
326
327 void r600_delete_rs_state(struct pipe_context *ctx, void *state)
328 {
329 struct r600_context *rctx = (struct r600_context *)ctx;
330 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
331
332 if (rctx->rasterizer == rs) {
333 rctx->rasterizer = NULL;
334 }
335 if (rctx->states[rs->rstate.id] == &rs->rstate) {
336 rctx->states[rs->rstate.id] = NULL;
337 }
338 free(rs);
339 }
340
341 void r600_sampler_view_destroy(struct pipe_context *ctx,
342 struct pipe_sampler_view *state)
343 {
344 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
345
346 pipe_resource_reference(&state->texture, NULL);
347 FREE(resource);
348 }
349
350 void r600_delete_state(struct pipe_context *ctx, void *state)
351 {
352 struct r600_context *rctx = (struct r600_context *)ctx;
353 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
354
355 if (rctx->states[rstate->id] == rstate) {
356 rctx->states[rstate->id] = NULL;
357 }
358 for (int i = 0; i < rstate->nregs; i++) {
359 pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL);
360 }
361 free(rstate);
362 }
363
364 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
365 {
366 struct r600_context *rctx = (struct r600_context *)ctx;
367 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
368
369 rctx->vertex_elements = v;
370 if (v) {
371 r600_inval_shader_cache(rctx);
372
373 rctx->states[v->rstate.id] = &v->rstate;
374 r600_context_pipe_state_set(rctx, &v->rstate);
375 }
376 }
377
378 void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
379 {
380 struct r600_context *rctx = (struct r600_context *)ctx;
381 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
382
383 if (rctx->states[v->rstate.id] == &v->rstate) {
384 rctx->states[v->rstate.id] = NULL;
385 }
386 if (rctx->vertex_elements == state)
387 rctx->vertex_elements = NULL;
388
389 pipe_resource_reference((struct pipe_resource**)&v->fetch_shader, NULL);
390 FREE(state);
391 }
392
393 void r600_set_index_buffer(struct pipe_context *ctx,
394 const struct pipe_index_buffer *ib)
395 {
396 struct r600_context *rctx = (struct r600_context *)ctx;
397
398 if (ib) {
399 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
400 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
401 } else {
402 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
403 }
404 }
405
406 void r600_vertex_buffers_dirty(struct r600_context *rctx)
407 {
408 if (rctx->vertex_buffer_state.dirty_mask) {
409 r600_inval_vertex_cache(rctx);
410 rctx->vertex_buffer_state.atom.num_dw = (rctx->chip_class >= EVERGREEN ? 12 : 11) *
411 util_bitcount(rctx->vertex_buffer_state.dirty_mask);
412 r600_atom_dirty(rctx, &rctx->vertex_buffer_state.atom);
413 }
414 }
415
416 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
417 const struct pipe_vertex_buffer *input)
418 {
419 struct r600_context *rctx = (struct r600_context *)ctx;
420 struct r600_vertexbuf_state *state = &rctx->vertex_buffer_state;
421 struct pipe_vertex_buffer *vb = state->vb;
422 unsigned i;
423 /* This sets 1-bit for buffers with index >= count. */
424 uint32_t disable_mask = ~((1ull << count) - 1);
425 /* These are the new buffers set by this function. */
426 uint32_t new_buffer_mask = 0;
427
428 /* Set buffers with index >= count to NULL. */
429 uint32_t remaining_buffers_mask =
430 rctx->vertex_buffer_state.enabled_mask & disable_mask;
431
432 while (remaining_buffers_mask) {
433 i = u_bit_scan(&remaining_buffers_mask);
434 pipe_resource_reference(&vb[i].buffer, NULL);
435 }
436
437 /* Set vertex buffers. */
438 for (i = 0; i < count; i++) {
439 if (memcmp(&input[i], &vb[i], sizeof(struct pipe_vertex_buffer))) {
440 if (input[i].buffer) {
441 vb[i].stride = input[i].stride;
442 vb[i].buffer_offset = input[i].buffer_offset;
443 pipe_resource_reference(&vb[i].buffer, input[i].buffer);
444 new_buffer_mask |= 1 << i;
445 } else {
446 pipe_resource_reference(&vb[i].buffer, NULL);
447 disable_mask |= 1 << i;
448 }
449 }
450 }
451
452 rctx->vertex_buffer_state.enabled_mask &= ~disable_mask;
453 rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask;
454 rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask;
455 rctx->vertex_buffer_state.dirty_mask |= new_buffer_mask;
456
457 r600_vertex_buffers_dirty(rctx);
458 }
459
460 void *r600_create_vertex_elements(struct pipe_context *ctx,
461 unsigned count,
462 const struct pipe_vertex_element *elements)
463 {
464 struct r600_context *rctx = (struct r600_context *)ctx;
465 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
466
467 assert(count < 32);
468 if (!v)
469 return NULL;
470
471 v->count = count;
472 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
473
474 if (r600_vertex_elements_build_fetch_shader(rctx, v)) {
475 FREE(v);
476 return NULL;
477 }
478
479 return v;
480 }
481
482 /* Compute the key for the hw shader variant */
483 static INLINE unsigned r600_shader_selector_key(struct pipe_context * ctx,
484 struct r600_pipe_shader_selector * sel)
485 {
486 struct r600_context *rctx = (struct r600_context *)ctx;
487 unsigned key;
488
489 if (sel->type == PIPE_SHADER_FRAGMENT) {
490 key = rctx->two_side |
491 MIN2(sel->nr_ps_max_color_exports, rctx->nr_cbufs + rctx->dual_src_blend) << 1;
492 } else
493 key = 0;
494
495 return key;
496 }
497
498 /* Select the hw shader variant depending on the current state.
499 * (*dirty) is set to 1 if current variant was changed */
500 static int r600_shader_select(struct pipe_context *ctx,
501 struct r600_pipe_shader_selector* sel,
502 unsigned *dirty)
503 {
504 unsigned key;
505 struct r600_context *rctx = (struct r600_context *)ctx;
506 struct r600_pipe_shader * shader = NULL;
507 int r;
508
509 key = r600_shader_selector_key(ctx, sel);
510
511 /* Check if we don't need to change anything.
512 * This path is also used for most shaders that don't need multiple
513 * variants, it will cost just a computation of the key and this
514 * test. */
515 if (likely(sel->current && sel->current->key == key)) {
516 return 0;
517 }
518
519 /* lookup if we have other variants in the list */
520 if (sel->num_shaders > 1) {
521 struct r600_pipe_shader *p = sel->current, *c = p->next_variant;
522
523 while (c && c->key != key) {
524 p = c;
525 c = c->next_variant;
526 }
527
528 if (c) {
529 p->next_variant = c->next_variant;
530 shader = c;
531 }
532 }
533
534 if (unlikely(!shader)) {
535 shader = CALLOC(1, sizeof(struct r600_pipe_shader));
536 shader->selector = sel;
537
538 r = r600_pipe_shader_create(ctx, shader);
539 if (unlikely(r)) {
540 R600_ERR("Failed to build shader variant (type=%u, key=%u) %d\n",
541 sel->type, key, r);
542 sel->current = NULL;
543 return r;
544 }
545
546 /* We don't know the value of nr_ps_max_color_exports until we built
547 * at least one variant, so we may need to recompute the key after
548 * building first variant. */
549 if (sel->type == PIPE_SHADER_FRAGMENT &&
550 sel->num_shaders == 0) {
551 sel->nr_ps_max_color_exports = shader->shader.nr_ps_max_color_exports;
552 key = r600_shader_selector_key(ctx, sel);
553 }
554
555 shader->key = key;
556 sel->num_shaders++;
557 }
558
559 if (dirty)
560 *dirty = 1;
561
562 shader->next_variant = sel->current;
563 sel->current = shader;
564
565 if (rctx->chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
566 r600_adjust_gprs(rctx);
567 }
568
569 if (rctx->ps_shader &&
570 rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
571 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
572 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
573 }
574 return 0;
575 }
576
577 static void *r600_create_shader_state(struct pipe_context *ctx,
578 const struct pipe_shader_state *state,
579 unsigned pipe_shader_type)
580 {
581 struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector);
582 int r;
583
584 sel->type = pipe_shader_type;
585 sel->tokens = tgsi_dup_tokens(state->tokens);
586 sel->so = state->stream_output;
587
588 r = r600_shader_select(ctx, sel, NULL);
589 if (r)
590 return NULL;
591
592 return sel;
593 }
594
595 void *r600_create_shader_state_ps(struct pipe_context *ctx,
596 const struct pipe_shader_state *state)
597 {
598 return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
599 }
600
601 void *r600_create_shader_state_vs(struct pipe_context *ctx,
602 const struct pipe_shader_state *state)
603 {
604 return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
605 }
606
607 void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
608 {
609 struct r600_context *rctx = (struct r600_context *)ctx;
610
611 if (!state)
612 state = rctx->dummy_pixel_shader;
613
614 rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
615 r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
616
617 if (rctx->chip_class <= R700) {
618 bool multiwrite = rctx->ps_shader->current->shader.fs_write_all;
619
620 if (rctx->cb_misc_state.multiwrite != multiwrite) {
621 rctx->cb_misc_state.multiwrite = multiwrite;
622 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
623 }
624
625 if (rctx->vs_shader)
626 r600_adjust_gprs(rctx);
627 }
628
629 if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
630 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
631 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
632 }
633 }
634
635 void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
636 {
637 struct r600_context *rctx = (struct r600_context *)ctx;
638
639 rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
640 if (state) {
641 r600_context_pipe_state_set(rctx, &rctx->vs_shader->current->rstate);
642
643 if (rctx->chip_class < EVERGREEN && rctx->ps_shader)
644 r600_adjust_gprs(rctx);
645 }
646 }
647
648 static void r600_delete_shader_selector(struct pipe_context *ctx,
649 struct r600_pipe_shader_selector *sel)
650 {
651 struct r600_pipe_shader *p = sel->current, *c;
652 while (p) {
653 c = p->next_variant;
654 r600_pipe_shader_destroy(ctx, p);
655 free(p);
656 p = c;
657 }
658
659 free(sel->tokens);
660 free(sel);
661 }
662
663
664 void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
665 {
666 struct r600_context *rctx = (struct r600_context *)ctx;
667 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
668
669 if (rctx->ps_shader == sel) {
670 rctx->ps_shader = NULL;
671 }
672
673 r600_delete_shader_selector(ctx, sel);
674 }
675
676 void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
677 {
678 struct r600_context *rctx = (struct r600_context *)ctx;
679 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
680
681 if (rctx->vs_shader == sel) {
682 rctx->vs_shader = NULL;
683 }
684
685 r600_delete_shader_selector(ctx, sel);
686 }
687
688 static void r600_update_alpha_ref(struct r600_context *rctx)
689 {
690 unsigned alpha_ref;
691 struct r600_pipe_state rstate;
692
693 alpha_ref = rctx->alpha_ref;
694 rstate.nregs = 0;
695 if (rctx->export_16bpc && rctx->chip_class >= EVERGREEN) {
696 alpha_ref &= ~0x1FFF;
697 }
698 r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref);
699
700 r600_context_pipe_state_set(rctx, &rstate);
701 rctx->alpha_ref_dirty = false;
702 }
703
704 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
705 {
706 r600_inval_shader_cache(rctx);
707 state->atom.num_dw = rctx->chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
708 : util_bitcount(state->dirty_mask)*19;
709 r600_atom_dirty(rctx, &state->atom);
710 }
711
712 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
713 struct pipe_constant_buffer *input)
714 {
715 struct r600_context *rctx = (struct r600_context *)ctx;
716 struct r600_constbuf_state *state;
717 struct pipe_constant_buffer *cb;
718 const uint8_t *ptr;
719
720 switch (shader) {
721 case PIPE_SHADER_VERTEX:
722 state = &rctx->vs_constbuf_state;
723 break;
724 case PIPE_SHADER_FRAGMENT:
725 state = &rctx->ps_constbuf_state;
726 break;
727 default:
728 return;
729 }
730
731 /* Note that the state tracker can unbind constant buffers by
732 * passing NULL here.
733 */
734 if (unlikely(!input)) {
735 state->enabled_mask &= ~(1 << index);
736 state->dirty_mask &= ~(1 << index);
737 pipe_resource_reference(&state->cb[index].buffer, NULL);
738 return;
739 }
740
741 cb = &state->cb[index];
742 cb->buffer_size = input->buffer_size;
743
744 ptr = input->user_buffer;
745
746 if (ptr) {
747 /* Upload the user buffer. */
748 if (R600_BIG_ENDIAN) {
749 uint32_t *tmpPtr;
750 unsigned i, size = input->buffer_size;
751
752 if (!(tmpPtr = malloc(size))) {
753 R600_ERR("Failed to allocate BE swap buffer.\n");
754 return;
755 }
756
757 for (i = 0; i < size / 4; ++i) {
758 tmpPtr[i] = bswap_32(((uint32_t *)ptr)[i]);
759 }
760
761 u_upload_data(rctx->uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer);
762 free(tmpPtr);
763 } else {
764 u_upload_data(rctx->uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer);
765 }
766 } else {
767 /* Setup the hw buffer. */
768 cb->buffer_offset = input->buffer_offset;
769 pipe_resource_reference(&cb->buffer, input->buffer);
770 }
771
772 state->enabled_mask |= 1 << index;
773 state->dirty_mask |= 1 << index;
774 r600_constant_buffers_dirty(rctx, state);
775 }
776
777 struct pipe_stream_output_target *
778 r600_create_so_target(struct pipe_context *ctx,
779 struct pipe_resource *buffer,
780 unsigned buffer_offset,
781 unsigned buffer_size)
782 {
783 struct r600_context *rctx = (struct r600_context *)ctx;
784 struct r600_so_target *t;
785 void *ptr;
786
787 t = CALLOC_STRUCT(r600_so_target);
788 if (!t) {
789 return NULL;
790 }
791
792 t->b.reference.count = 1;
793 t->b.context = ctx;
794 pipe_resource_reference(&t->b.buffer, buffer);
795 t->b.buffer_offset = buffer_offset;
796 t->b.buffer_size = buffer_size;
797
798 t->filled_size = (struct r600_resource*)
799 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4);
800 ptr = rctx->ws->buffer_map(t->filled_size->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
801 memset(ptr, 0, t->filled_size->buf->size);
802 rctx->ws->buffer_unmap(t->filled_size->cs_buf);
803
804 return &t->b;
805 }
806
807 void r600_so_target_destroy(struct pipe_context *ctx,
808 struct pipe_stream_output_target *target)
809 {
810 struct r600_so_target *t = (struct r600_so_target*)target;
811 pipe_resource_reference(&t->b.buffer, NULL);
812 pipe_resource_reference((struct pipe_resource**)&t->filled_size, NULL);
813 FREE(t);
814 }
815
816 void r600_set_so_targets(struct pipe_context *ctx,
817 unsigned num_targets,
818 struct pipe_stream_output_target **targets,
819 unsigned append_bitmask)
820 {
821 struct r600_context *rctx = (struct r600_context *)ctx;
822 unsigned i;
823
824 /* Stop streamout. */
825 if (rctx->num_so_targets && !rctx->streamout_start) {
826 r600_context_streamout_end(rctx);
827 }
828
829 /* Set the new targets. */
830 for (i = 0; i < num_targets; i++) {
831 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]);
832 }
833 for (; i < rctx->num_so_targets; i++) {
834 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL);
835 }
836
837 rctx->num_so_targets = num_targets;
838 rctx->streamout_start = num_targets != 0;
839 rctx->streamout_append_bitmask = append_bitmask;
840 }
841
842 static void r600_update_derived_state(struct r600_context *rctx)
843 {
844 struct pipe_context * ctx = (struct pipe_context*)rctx;
845 unsigned ps_dirty = 0;
846
847 if (!rctx->blitter->running) {
848 if (rctx->have_depth_texture) {
849 r600_flush_all_depth_textures(rctx);
850 }
851 }
852
853 if (rctx->chip_class < EVERGREEN) {
854 r600_update_sampler_states(rctx);
855 }
856
857 r600_shader_select(ctx, rctx->ps_shader, &ps_dirty);
858
859 if (rctx->alpha_ref_dirty) {
860 r600_update_alpha_ref(rctx);
861 }
862
863 if (rctx->ps_shader && ((rctx->sprite_coord_enable &&
864 (rctx->ps_shader->current->sprite_coord_enable != rctx->sprite_coord_enable)) ||
865 (rctx->rasterizer && rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade))) {
866
867 if (rctx->chip_class >= EVERGREEN)
868 evergreen_pipe_shader_ps(ctx, rctx->ps_shader->current);
869 else
870 r600_pipe_shader_ps(ctx, rctx->ps_shader->current);
871
872 ps_dirty = 1;
873 }
874
875 if (ps_dirty)
876 r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
877
878 if (rctx->chip_class >= EVERGREEN) {
879 evergreen_update_dual_export_state(rctx);
880 } else {
881 r600_update_dual_export_state(rctx);
882 }
883 }
884
885 static unsigned r600_conv_prim_to_gs_out(unsigned mode)
886 {
887 static const int prim_conv[] = {
888 V_028A6C_OUTPRIM_TYPE_POINTLIST,
889 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
890 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
891 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
892 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
893 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
894 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
895 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
896 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
897 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
898 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
899 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
900 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
901 V_028A6C_OUTPRIM_TYPE_TRISTRIP
902 };
903 assert(mode < Elements(prim_conv));
904
905 return prim_conv[mode];
906 }
907
908 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
909 {
910 struct r600_context *rctx = (struct r600_context *)ctx;
911 struct pipe_draw_info info = *dinfo;
912 struct pipe_index_buffer ib = {};
913 unsigned prim, ls_mask = 0;
914 struct r600_block *dirty_block = NULL, *next_block = NULL;
915 struct r600_atom *state = NULL, *next_state = NULL;
916 struct radeon_winsys_cs *cs = rctx->cs;
917 uint64_t va;
918 uint8_t *ptr;
919
920 if ((!info.count && (info.indexed || !info.count_from_stream_output)) ||
921 !r600_conv_pipe_prim(info.mode, &prim)) {
922 assert(0);
923 return;
924 }
925
926 if (!rctx->vs_shader) {
927 assert(0);
928 return;
929 }
930
931 r600_update_derived_state(rctx);
932
933 if (info.indexed) {
934 /* Initialize the index buffer struct. */
935 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
936 ib.user_buffer = rctx->index_buffer.user_buffer;
937 ib.index_size = rctx->index_buffer.index_size;
938 ib.offset = rctx->index_buffer.offset + info.start * ib.index_size;
939
940 /* Translate or upload, if needed. */
941 r600_translate_index_buffer(rctx, &ib, info.count);
942
943 ptr = (uint8_t*)ib.user_buffer;
944 if (!ib.buffer && ptr) {
945 u_upload_data(rctx->uploader, 0, info.count * ib.index_size,
946 ptr, &ib.offset, &ib.buffer);
947 }
948 } else {
949 info.index_bias = info.start;
950 if (info.count_from_stream_output) {
951 r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info.count_from_stream_output);
952 }
953 }
954
955 if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
956 rctx->vgt.id = R600_PIPE_STATE_VGT;
957 rctx->vgt.nregs = 0;
958 r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim);
959 r600_pipe_state_add_reg(&rctx->vgt, R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0);
960 r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias);
961 r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index);
962 r600_pipe_state_add_reg(&rctx->vgt, R_028410_SX_ALPHA_TEST_CONTROL, 0);
963 r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart);
964 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
965 r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0);
966 r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0);
967 r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0);
968 }
969
970 rctx->vgt.nregs = 0;
971 r600_pipe_state_mod_reg(&rctx->vgt, prim);
972 r600_pipe_state_mod_reg(&rctx->vgt, r600_conv_prim_to_gs_out(info.mode));
973 r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
974 r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
975 r600_pipe_state_mod_reg(&rctx->vgt, rctx->sx_alpha_test_control);
976 r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart);
977 r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance);
978
979 if (prim == V_008958_DI_PT_LINELIST)
980 ls_mask = 1;
981 else if (prim == V_008958_DI_PT_LINESTRIP)
982 ls_mask = 2;
983 r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask) | rctx->pa_sc_line_stipple);
984 r600_pipe_state_mod_reg(&rctx->vgt,
985 rctx->vs_shader->current->pa_cl_vs_out_cntl |
986 (rctx->rasterizer->clip_plane_enable & rctx->vs_shader->current->shader.clip_dist_write));
987 r600_pipe_state_mod_reg(&rctx->vgt,
988 rctx->pa_cl_clip_cntl |
989 (rctx->vs_shader->current->shader.clip_dist_write ||
990 rctx->vs_shader->current->shader.vs_prohibit_ucps ?
991 0 : rctx->rasterizer->clip_plane_enable & 0x3F));
992
993 r600_context_pipe_state_set(rctx, &rctx->vgt);
994
995 /* Emit states (the function expects that we emit at most 17 dwords here). */
996 r600_need_cs_space(rctx, 0, TRUE);
997
998 LIST_FOR_EACH_ENTRY_SAFE(state, next_state, &rctx->dirty_states, head) {
999 r600_emit_atom(rctx, state);
1000 }
1001 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) {
1002 r600_context_block_emit_dirty(rctx, dirty_block, 0 /* pkt_flags */);
1003 }
1004 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->resource_dirty,list) {
1005 r600_context_block_resource_emit_dirty(rctx, dirty_block);
1006 }
1007 rctx->pm4_dirty_cdwords = 0;
1008
1009 /* Enable stream out if needed. */
1010 if (rctx->streamout_start) {
1011 r600_context_streamout_begin(rctx);
1012 rctx->streamout_start = FALSE;
1013 }
1014
1015 /* draw packet */
1016 cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->predicate_drawing);
1017 cs->buf[cs->cdw++] = ib.index_size == 4 ?
1018 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
1019 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
1020 cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->predicate_drawing);
1021 cs->buf[cs->cdw++] = info.instance_count;
1022 if (info.indexed) {
1023 va = r600_resource_va(ctx->screen, ib.buffer);
1024 va += ib.offset;
1025 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->predicate_drawing);
1026 cs->buf[cs->cdw++] = va;
1027 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
1028 cs->buf[cs->cdw++] = info.count;
1029 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
1030 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->predicate_drawing);
1031 cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
1032 } else {
1033 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->predicate_drawing);
1034 cs->buf[cs->cdw++] = info.count;
1035 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
1036 (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
1037 }
1038
1039 rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING;
1040
1041 /* Set the depth buffer as dirty. */
1042 if (rctx->framebuffer.zsbuf) {
1043 struct pipe_surface *surf = rctx->framebuffer.zsbuf;
1044 struct r600_resource_texture *rtex = (struct r600_resource_texture *)surf->texture;
1045
1046 rtex->dirty_db_mask |= 1 << surf->u.tex.level;
1047 }
1048
1049 pipe_resource_reference(&ib.buffer, NULL);
1050 }
1051
1052 void _r600_pipe_state_add_reg_bo(struct r600_context *ctx,
1053 struct r600_pipe_state *state,
1054 uint32_t offset, uint32_t value,
1055 uint32_t range_id, uint32_t block_id,
1056 struct r600_resource *bo,
1057 enum radeon_bo_usage usage)
1058
1059 {
1060 struct r600_range *range;
1061 struct r600_block *block;
1062
1063 if (bo) assert(usage);
1064
1065 range = &ctx->range[range_id];
1066 block = range->blocks[block_id];
1067 state->regs[state->nregs].block = block;
1068 state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
1069
1070 state->regs[state->nregs].value = value;
1071 state->regs[state->nregs].bo = bo;
1072 state->regs[state->nregs].bo_usage = usage;
1073
1074 state->nregs++;
1075 assert(state->nregs < R600_BLOCK_MAX_REG);
1076 }
1077
1078 void _r600_pipe_state_add_reg(struct r600_context *ctx,
1079 struct r600_pipe_state *state,
1080 uint32_t offset, uint32_t value,
1081 uint32_t range_id, uint32_t block_id)
1082 {
1083 _r600_pipe_state_add_reg_bo(ctx, state, offset, value,
1084 range_id, block_id, NULL, 0);
1085 }
1086
1087 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
1088 uint32_t offset, uint32_t value,
1089 struct r600_resource *bo,
1090 enum radeon_bo_usage usage)
1091 {
1092 if (bo) assert(usage);
1093
1094 state->regs[state->nregs].id = offset;
1095 state->regs[state->nregs].block = NULL;
1096 state->regs[state->nregs].value = value;
1097 state->regs[state->nregs].bo = bo;
1098 state->regs[state->nregs].bo_usage = usage;
1099
1100 state->nregs++;
1101 assert(state->nregs < R600_BLOCK_MAX_REG);
1102 }
1103
1104 uint32_t r600_translate_stencil_op(int s_op)
1105 {
1106 switch (s_op) {
1107 case PIPE_STENCIL_OP_KEEP:
1108 return V_028800_STENCIL_KEEP;
1109 case PIPE_STENCIL_OP_ZERO:
1110 return V_028800_STENCIL_ZERO;
1111 case PIPE_STENCIL_OP_REPLACE:
1112 return V_028800_STENCIL_REPLACE;
1113 case PIPE_STENCIL_OP_INCR:
1114 return V_028800_STENCIL_INCR;
1115 case PIPE_STENCIL_OP_DECR:
1116 return V_028800_STENCIL_DECR;
1117 case PIPE_STENCIL_OP_INCR_WRAP:
1118 return V_028800_STENCIL_INCR_WRAP;
1119 case PIPE_STENCIL_OP_DECR_WRAP:
1120 return V_028800_STENCIL_DECR_WRAP;
1121 case PIPE_STENCIL_OP_INVERT:
1122 return V_028800_STENCIL_INVERT;
1123 default:
1124 R600_ERR("Unknown stencil op %d", s_op);
1125 assert(0);
1126 break;
1127 }
1128 return 0;
1129 }
1130
1131 uint32_t r600_translate_fill(uint32_t func)
1132 {
1133 switch(func) {
1134 case PIPE_POLYGON_MODE_FILL:
1135 return 2;
1136 case PIPE_POLYGON_MODE_LINE:
1137 return 1;
1138 case PIPE_POLYGON_MODE_POINT:
1139 return 0;
1140 default:
1141 assert(0);
1142 return 0;
1143 }
1144 }
1145
1146 unsigned r600_tex_wrap(unsigned wrap)
1147 {
1148 switch (wrap) {
1149 default:
1150 case PIPE_TEX_WRAP_REPEAT:
1151 return V_03C000_SQ_TEX_WRAP;
1152 case PIPE_TEX_WRAP_CLAMP:
1153 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1154 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1155 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1156 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1157 return V_03C000_SQ_TEX_CLAMP_BORDER;
1158 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1159 return V_03C000_SQ_TEX_MIRROR;
1160 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1161 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1162 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1163 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1164 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1165 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1166 }
1167 }
1168
1169 unsigned r600_tex_filter(unsigned filter)
1170 {
1171 switch (filter) {
1172 default:
1173 case PIPE_TEX_FILTER_NEAREST:
1174 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1175 case PIPE_TEX_FILTER_LINEAR:
1176 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1177 }
1178 }
1179
1180 unsigned r600_tex_mipfilter(unsigned filter)
1181 {
1182 switch (filter) {
1183 case PIPE_TEX_MIPFILTER_NEAREST:
1184 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1185 case PIPE_TEX_MIPFILTER_LINEAR:
1186 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1187 default:
1188 case PIPE_TEX_MIPFILTER_NONE:
1189 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1190 }
1191 }
1192
1193 unsigned r600_tex_compare(unsigned compare)
1194 {
1195 switch (compare) {
1196 default:
1197 case PIPE_FUNC_NEVER:
1198 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1199 case PIPE_FUNC_LESS:
1200 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1201 case PIPE_FUNC_EQUAL:
1202 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1203 case PIPE_FUNC_LEQUAL:
1204 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1205 case PIPE_FUNC_GREATER:
1206 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1207 case PIPE_FUNC_NOTEQUAL:
1208 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1209 case PIPE_FUNC_GEQUAL:
1210 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1211 case PIPE_FUNC_ALWAYS:
1212 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1213 }
1214 }