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r600g: suballocate memory for fetch shaders from a large buffer
[mesa.git] / src / gallium / drivers / r600 / r600_state_common.c
1 /*
2 * Copyright 2010 Red Hat Inc.
3 * 2010 Jerome Glisse
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
26 */
27 #include "r600_formats.h"
28 #include "r600_shader.h"
29 #include "r600d.h"
30
31 #include "util/u_draw_quad.h"
32 #include "util/u_index_modify.h"
33 #include "util/u_memory.h"
34 #include "util/u_upload_mgr.h"
35 #include "tgsi/tgsi_parse.h"
36 #include <byteswap.h>
37
38 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
39
40 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw)
41 {
42 cb->buf = CALLOC(1, 4 * num_dw);
43 cb->max_num_dw = num_dw;
44 }
45
46 void r600_release_command_buffer(struct r600_command_buffer *cb)
47 {
48 FREE(cb->buf);
49 }
50
51 void r600_init_atom(struct r600_context *rctx,
52 struct r600_atom *atom,
53 unsigned id,
54 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
55 unsigned num_dw)
56 {
57 assert(id < R600_NUM_ATOMS);
58 assert(rctx->atoms[id] == NULL);
59 rctx->atoms[id] = atom;
60 atom->id = id;
61 atom->emit = emit;
62 atom->num_dw = num_dw;
63 atom->dirty = false;
64 }
65
66 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom)
67 {
68 r600_emit_command_buffer(rctx->cs, ((struct r600_cso_state*)atom)->cb);
69 }
70
71 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom)
72 {
73 struct radeon_winsys_cs *cs = rctx->cs;
74 struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom;
75 unsigned alpha_ref = a->sx_alpha_ref;
76
77 if (rctx->chip_class >= EVERGREEN && a->cb0_export_16bpc) {
78 alpha_ref &= ~0x1FFF;
79 }
80
81 r600_write_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL,
82 a->sx_alpha_test_control |
83 S_028410_ALPHA_TEST_BYPASS(a->bypass));
84 r600_write_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref);
85 }
86
87 static void r600_texture_barrier(struct pipe_context *ctx)
88 {
89 struct r600_context *rctx = (struct r600_context *)ctx;
90
91 rctx->flags |= R600_CONTEXT_CB_FLUSH | R600_CONTEXT_TEX_FLUSH;
92
93 /* R6xx errata */
94 if (rctx->chip_class == R600) {
95 rctx->flags |= R600_CONTEXT_FLUSH_AND_INV;
96 }
97 }
98
99 static unsigned r600_conv_pipe_prim(unsigned prim)
100 {
101 static const unsigned prim_conv[] = {
102 V_008958_DI_PT_POINTLIST,
103 V_008958_DI_PT_LINELIST,
104 V_008958_DI_PT_LINELOOP,
105 V_008958_DI_PT_LINESTRIP,
106 V_008958_DI_PT_TRILIST,
107 V_008958_DI_PT_TRISTRIP,
108 V_008958_DI_PT_TRIFAN,
109 V_008958_DI_PT_QUADLIST,
110 V_008958_DI_PT_QUADSTRIP,
111 V_008958_DI_PT_POLYGON,
112 V_008958_DI_PT_LINELIST_ADJ,
113 V_008958_DI_PT_LINESTRIP_ADJ,
114 V_008958_DI_PT_TRILIST_ADJ,
115 V_008958_DI_PT_TRISTRIP_ADJ,
116 V_008958_DI_PT_RECTLIST
117 };
118 return prim_conv[prim];
119 }
120
121 /* common state between evergreen and r600 */
122
123 static void r600_bind_blend_state_internal(struct r600_context *rctx,
124 struct r600_blend_state *blend, bool blend_disable)
125 {
126 unsigned color_control;
127 bool update_cb = false;
128
129 rctx->alpha_to_one = blend->alpha_to_one;
130 rctx->dual_src_blend = blend->dual_src_blend;
131
132 if (!blend_disable) {
133 r600_set_cso_state_with_cb(&rctx->blend_state, blend, &blend->buffer);
134 color_control = blend->cb_color_control;
135 } else {
136 /* Blending is disabled. */
137 r600_set_cso_state_with_cb(&rctx->blend_state, blend, &blend->buffer_no_blend);
138 color_control = blend->cb_color_control_no_blend;
139 }
140
141 /* Update derived states. */
142 if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) {
143 rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
144 update_cb = true;
145 }
146 if (rctx->chip_class <= R700 &&
147 rctx->cb_misc_state.cb_color_control != color_control) {
148 rctx->cb_misc_state.cb_color_control = color_control;
149 update_cb = true;
150 }
151 if (rctx->cb_misc_state.dual_src_blend != blend->dual_src_blend) {
152 rctx->cb_misc_state.dual_src_blend = blend->dual_src_blend;
153 update_cb = true;
154 }
155 if (update_cb) {
156 rctx->cb_misc_state.atom.dirty = true;
157 }
158 }
159
160 static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
161 {
162 struct r600_context *rctx = (struct r600_context *)ctx;
163 struct r600_blend_state *blend = (struct r600_blend_state *)state;
164
165 if (blend == NULL)
166 return;
167
168 r600_bind_blend_state_internal(rctx, blend, rctx->force_blend_disable);
169 }
170
171 static void r600_set_blend_color(struct pipe_context *ctx,
172 const struct pipe_blend_color *state)
173 {
174 struct r600_context *rctx = (struct r600_context *)ctx;
175
176 rctx->blend_color.state = *state;
177 rctx->blend_color.atom.dirty = true;
178 }
179
180 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom)
181 {
182 struct radeon_winsys_cs *cs = rctx->cs;
183 struct pipe_blend_color *state = &rctx->blend_color.state;
184
185 r600_write_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
186 r600_write_value(cs, fui(state->color[0])); /* R_028414_CB_BLEND_RED */
187 r600_write_value(cs, fui(state->color[1])); /* R_028418_CB_BLEND_GREEN */
188 r600_write_value(cs, fui(state->color[2])); /* R_02841C_CB_BLEND_BLUE */
189 r600_write_value(cs, fui(state->color[3])); /* R_028420_CB_BLEND_ALPHA */
190 }
191
192 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom)
193 {
194 struct radeon_winsys_cs *cs = rctx->cs;
195 struct r600_vgt_state *a = (struct r600_vgt_state *)atom;
196
197 r600_write_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, a->vgt_multi_prim_ib_reset_en);
198 r600_write_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, a->vgt_multi_prim_ib_reset_indx);
199 }
200
201 void r600_emit_vgt2_state(struct r600_context *rctx, struct r600_atom *atom)
202 {
203 struct radeon_winsys_cs *cs = rctx->cs;
204 struct r600_vgt2_state *a = (struct r600_vgt2_state *)atom;
205
206 r600_write_context_reg(cs, R_028408_VGT_INDX_OFFSET, a->vgt_indx_offset);
207 }
208
209 static void r600_set_clip_state(struct pipe_context *ctx,
210 const struct pipe_clip_state *state)
211 {
212 struct r600_context *rctx = (struct r600_context *)ctx;
213 struct pipe_constant_buffer cb;
214
215 rctx->clip_state.state = *state;
216 rctx->clip_state.atom.dirty = true;
217
218 cb.buffer = NULL;
219 cb.user_buffer = state->ucp;
220 cb.buffer_offset = 0;
221 cb.buffer_size = 4*4*8;
222 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, R600_UCP_CONST_BUFFER, &cb);
223 pipe_resource_reference(&cb.buffer, NULL);
224 }
225
226 static void r600_set_stencil_ref(struct pipe_context *ctx,
227 const struct r600_stencil_ref *state)
228 {
229 struct r600_context *rctx = (struct r600_context *)ctx;
230
231 rctx->stencil_ref.state = *state;
232 rctx->stencil_ref.atom.dirty = true;
233 }
234
235 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom)
236 {
237 struct radeon_winsys_cs *cs = rctx->cs;
238 struct r600_stencil_ref_state *a = (struct r600_stencil_ref_state*)atom;
239
240 r600_write_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
241 r600_write_value(cs, /* R_028430_DB_STENCILREFMASK */
242 S_028430_STENCILREF(a->state.ref_value[0]) |
243 S_028430_STENCILMASK(a->state.valuemask[0]) |
244 S_028430_STENCILWRITEMASK(a->state.writemask[0]));
245 r600_write_value(cs, /* R_028434_DB_STENCILREFMASK_BF */
246 S_028434_STENCILREF_BF(a->state.ref_value[1]) |
247 S_028434_STENCILMASK_BF(a->state.valuemask[1]) |
248 S_028434_STENCILWRITEMASK_BF(a->state.writemask[1]));
249 }
250
251 static void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
252 const struct pipe_stencil_ref *state)
253 {
254 struct r600_context *rctx = (struct r600_context *)ctx;
255 struct r600_dsa_state *dsa = (struct r600_dsa_state*)rctx->dsa_state.cso;
256 struct r600_stencil_ref ref;
257
258 rctx->stencil_ref.pipe_state = *state;
259
260 if (!dsa)
261 return;
262
263 ref.ref_value[0] = state->ref_value[0];
264 ref.ref_value[1] = state->ref_value[1];
265 ref.valuemask[0] = dsa->valuemask[0];
266 ref.valuemask[1] = dsa->valuemask[1];
267 ref.writemask[0] = dsa->writemask[0];
268 ref.writemask[1] = dsa->writemask[1];
269
270 r600_set_stencil_ref(ctx, &ref);
271 }
272
273 static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
274 {
275 struct r600_context *rctx = (struct r600_context *)ctx;
276 struct r600_dsa_state *dsa = state;
277 struct r600_stencil_ref ref;
278
279 if (state == NULL)
280 return;
281
282 r600_set_cso_state_with_cb(&rctx->dsa_state, dsa, &dsa->buffer);
283
284 ref.ref_value[0] = rctx->stencil_ref.pipe_state.ref_value[0];
285 ref.ref_value[1] = rctx->stencil_ref.pipe_state.ref_value[1];
286 ref.valuemask[0] = dsa->valuemask[0];
287 ref.valuemask[1] = dsa->valuemask[1];
288 ref.writemask[0] = dsa->writemask[0];
289 ref.writemask[1] = dsa->writemask[1];
290
291 r600_set_stencil_ref(ctx, &ref);
292
293 /* Update alphatest state. */
294 if (rctx->alphatest_state.sx_alpha_test_control != dsa->sx_alpha_test_control ||
295 rctx->alphatest_state.sx_alpha_ref != dsa->alpha_ref) {
296 rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control;
297 rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref;
298 rctx->alphatest_state.atom.dirty = true;
299 }
300 }
301
302 static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
303 {
304 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
305 struct r600_context *rctx = (struct r600_context *)ctx;
306
307 if (state == NULL)
308 return;
309
310 rctx->rasterizer = rs;
311
312 r600_set_cso_state_with_cb(&rctx->rasterizer_state, rs, &rs->buffer);
313
314 if (rs->offset_enable &&
315 (rs->offset_units != rctx->poly_offset_state.offset_units ||
316 rs->offset_scale != rctx->poly_offset_state.offset_scale)) {
317 rctx->poly_offset_state.offset_units = rs->offset_units;
318 rctx->poly_offset_state.offset_scale = rs->offset_scale;
319 rctx->poly_offset_state.atom.dirty = true;
320 }
321
322 /* Update clip_misc_state. */
323 if (rctx->clip_misc_state.pa_cl_clip_cntl != rs->pa_cl_clip_cntl ||
324 rctx->clip_misc_state.clip_plane_enable != rs->clip_plane_enable) {
325 rctx->clip_misc_state.pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
326 rctx->clip_misc_state.clip_plane_enable = rs->clip_plane_enable;
327 rctx->clip_misc_state.atom.dirty = true;
328 }
329
330 /* Workaround for a missing scissor enable on r600. */
331 if (rctx->chip_class == R600 &&
332 rs->scissor_enable != rctx->scissor.enable) {
333 rctx->scissor.enable = rs->scissor_enable;
334 rctx->scissor.atom.dirty = true;
335 }
336
337 /* Re-emit PA_SC_LINE_STIPPLE. */
338 rctx->last_primitive_type = -1;
339 }
340
341 static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
342 {
343 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
344
345 r600_release_command_buffer(&rs->buffer);
346 FREE(rs);
347 }
348
349 static void r600_sampler_view_destroy(struct pipe_context *ctx,
350 struct pipe_sampler_view *state)
351 {
352 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
353
354 pipe_resource_reference(&state->texture, NULL);
355 FREE(resource);
356 }
357
358 void r600_sampler_states_dirty(struct r600_context *rctx,
359 struct r600_sampler_states *state)
360 {
361 if (state->dirty_mask) {
362 if (state->dirty_mask & state->has_bordercolor_mask) {
363 rctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
364 }
365 state->atom.num_dw =
366 util_bitcount(state->dirty_mask & state->has_bordercolor_mask) * 11 +
367 util_bitcount(state->dirty_mask & ~state->has_bordercolor_mask) * 5;
368 state->atom.dirty = true;
369 }
370 }
371
372 static void r600_bind_sampler_states(struct pipe_context *pipe,
373 unsigned shader,
374 unsigned start,
375 unsigned count, void **states)
376 {
377 struct r600_context *rctx = (struct r600_context *)pipe;
378 struct r600_textures_info *dst = &rctx->samplers[shader];
379 struct r600_pipe_sampler_state **rstates = (struct r600_pipe_sampler_state**)states;
380 int seamless_cube_map = -1;
381 unsigned i;
382 /* This sets 1-bit for states with index >= count. */
383 uint32_t disable_mask = ~((1ull << count) - 1);
384 /* These are the new states set by this function. */
385 uint32_t new_mask = 0;
386
387 assert(start == 0); /* XXX fix below */
388
389 for (i = 0; i < count; i++) {
390 struct r600_pipe_sampler_state *rstate = rstates[i];
391
392 if (rstate == dst->states.states[i]) {
393 continue;
394 }
395
396 if (rstate) {
397 if (rstate->border_color_use) {
398 dst->states.has_bordercolor_mask |= 1 << i;
399 } else {
400 dst->states.has_bordercolor_mask &= ~(1 << i);
401 }
402 seamless_cube_map = rstate->seamless_cube_map;
403
404 new_mask |= 1 << i;
405 } else {
406 disable_mask |= 1 << i;
407 }
408 }
409
410 memcpy(dst->states.states, rstates, sizeof(void*) * count);
411 memset(dst->states.states + count, 0, sizeof(void*) * (NUM_TEX_UNITS - count));
412
413 dst->states.enabled_mask &= ~disable_mask;
414 dst->states.dirty_mask &= dst->states.enabled_mask;
415 dst->states.enabled_mask |= new_mask;
416 dst->states.dirty_mask |= new_mask;
417 dst->states.has_bordercolor_mask &= dst->states.enabled_mask;
418
419 r600_sampler_states_dirty(rctx, &dst->states);
420
421 /* Seamless cubemap state. */
422 if (rctx->chip_class <= R700 &&
423 seamless_cube_map != -1 &&
424 seamless_cube_map != rctx->seamless_cube_map.enabled) {
425 /* change in TA_CNTL_AUX need a pipeline flush */
426 rctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
427 rctx->seamless_cube_map.enabled = seamless_cube_map;
428 rctx->seamless_cube_map.atom.dirty = true;
429 }
430 }
431
432 static void r600_bind_vs_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
433 {
434 r600_bind_sampler_states(ctx, PIPE_SHADER_VERTEX, 0, count, states);
435 }
436
437 static void r600_bind_ps_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
438 {
439 r600_bind_sampler_states(ctx, PIPE_SHADER_FRAGMENT, 0, count, states);
440 }
441
442 static void r600_delete_sampler_state(struct pipe_context *ctx, void *state)
443 {
444 free(state);
445 }
446
447 static void r600_delete_blend_state(struct pipe_context *ctx, void *state)
448 {
449 struct r600_blend_state *blend = (struct r600_blend_state*)state;
450
451 r600_release_command_buffer(&blend->buffer);
452 r600_release_command_buffer(&blend->buffer_no_blend);
453 FREE(blend);
454 }
455
456 static void r600_delete_dsa_state(struct pipe_context *ctx, void *state)
457 {
458 struct r600_dsa_state *dsa = (struct r600_dsa_state *)state;
459
460 r600_release_command_buffer(&dsa->buffer);
461 free(dsa);
462 }
463
464 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
465 {
466 struct r600_context *rctx = (struct r600_context *)ctx;
467
468 r600_set_cso_state(&rctx->vertex_fetch_shader, state);
469 }
470
471 static void r600_delete_vertex_elements(struct pipe_context *ctx, void *state)
472 {
473 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state;
474 pipe_resource_reference((struct pipe_resource**)&shader->buffer, NULL);
475 FREE(shader);
476 }
477
478 static void r600_set_index_buffer(struct pipe_context *ctx,
479 const struct pipe_index_buffer *ib)
480 {
481 struct r600_context *rctx = (struct r600_context *)ctx;
482
483 if (ib) {
484 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
485 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
486 } else {
487 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
488 }
489 }
490
491 void r600_vertex_buffers_dirty(struct r600_context *rctx)
492 {
493 if (rctx->vertex_buffer_state.dirty_mask) {
494 rctx->flags |= rctx->has_vertex_cache ? R600_CONTEXT_VTX_FLUSH : R600_CONTEXT_TEX_FLUSH;
495 rctx->vertex_buffer_state.atom.num_dw = (rctx->chip_class >= EVERGREEN ? 12 : 11) *
496 util_bitcount(rctx->vertex_buffer_state.dirty_mask);
497 rctx->vertex_buffer_state.atom.dirty = true;
498 }
499 }
500
501 static void r600_set_vertex_buffers(struct pipe_context *ctx,
502 unsigned start_slot, unsigned count,
503 const struct pipe_vertex_buffer *input)
504 {
505 struct r600_context *rctx = (struct r600_context *)ctx;
506 struct r600_vertexbuf_state *state = &rctx->vertex_buffer_state;
507 struct pipe_vertex_buffer *vb = state->vb + start_slot;
508 unsigned i;
509 uint32_t disable_mask = 0;
510 /* These are the new buffers set by this function. */
511 uint32_t new_buffer_mask = 0;
512
513 /* Set vertex buffers. */
514 if (input) {
515 for (i = 0; i < count; i++) {
516 if (memcmp(&input[i], &vb[i], sizeof(struct pipe_vertex_buffer))) {
517 if (input[i].buffer) {
518 vb[i].stride = input[i].stride;
519 vb[i].buffer_offset = input[i].buffer_offset;
520 pipe_resource_reference(&vb[i].buffer, input[i].buffer);
521 new_buffer_mask |= 1 << i;
522 } else {
523 pipe_resource_reference(&vb[i].buffer, NULL);
524 disable_mask |= 1 << i;
525 }
526 }
527 }
528 } else {
529 for (i = 0; i < count; i++) {
530 pipe_resource_reference(&vb[i].buffer, NULL);
531 }
532 disable_mask = ((1ull << count) - 1);
533 }
534
535 disable_mask <<= start_slot;
536 new_buffer_mask <<= start_slot;
537
538 rctx->vertex_buffer_state.enabled_mask &= ~disable_mask;
539 rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask;
540 rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask;
541 rctx->vertex_buffer_state.dirty_mask |= new_buffer_mask;
542
543 r600_vertex_buffers_dirty(rctx);
544 }
545
546 void r600_sampler_views_dirty(struct r600_context *rctx,
547 struct r600_samplerview_state *state)
548 {
549 if (state->dirty_mask) {
550 rctx->flags |= R600_CONTEXT_TEX_FLUSH;
551 state->atom.num_dw = (rctx->chip_class >= EVERGREEN ? 14 : 13) *
552 util_bitcount(state->dirty_mask);
553 state->atom.dirty = true;
554 }
555 }
556
557 static void r600_set_sampler_views(struct pipe_context *pipe, unsigned shader,
558 unsigned start, unsigned count,
559 struct pipe_sampler_view **views)
560 {
561 struct r600_context *rctx = (struct r600_context *) pipe;
562 struct r600_textures_info *dst = &rctx->samplers[shader];
563 struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
564 uint32_t dirty_sampler_states_mask = 0;
565 unsigned i;
566 /* This sets 1-bit for textures with index >= count. */
567 uint32_t disable_mask = ~((1ull << count) - 1);
568 /* These are the new textures set by this function. */
569 uint32_t new_mask = 0;
570
571 /* Set textures with index >= count to NULL. */
572 uint32_t remaining_mask;
573
574 assert(start == 0); /* XXX fix below */
575
576 remaining_mask = dst->views.enabled_mask & disable_mask;
577
578 while (remaining_mask) {
579 i = u_bit_scan(&remaining_mask);
580 assert(dst->views.views[i]);
581
582 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
583 }
584
585 for (i = 0; i < count; i++) {
586 if (rviews[i] == dst->views.views[i]) {
587 continue;
588 }
589
590 if (rviews[i]) {
591 struct r600_texture *rtex =
592 (struct r600_texture*)rviews[i]->base.texture;
593
594 if (rtex->is_depth && !rtex->is_flushing_texture) {
595 dst->views.compressed_depthtex_mask |= 1 << i;
596 } else {
597 dst->views.compressed_depthtex_mask &= ~(1 << i);
598 }
599
600 /* Track compressed colorbuffers. */
601 if (rtex->cmask_size && rtex->fmask_size) {
602 dst->views.compressed_colortex_mask |= 1 << i;
603 } else {
604 dst->views.compressed_colortex_mask &= ~(1 << i);
605 }
606
607 /* Changing from array to non-arrays textures and vice versa requires
608 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
609 if (rctx->chip_class <= R700 &&
610 (dst->states.enabled_mask & (1 << i)) &&
611 (rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
612 rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) {
613 dirty_sampler_states_mask |= 1 << i;
614 }
615
616 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]);
617 new_mask |= 1 << i;
618 } else {
619 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
620 disable_mask |= 1 << i;
621 }
622 }
623
624 dst->views.enabled_mask &= ~disable_mask;
625 dst->views.dirty_mask &= dst->views.enabled_mask;
626 dst->views.enabled_mask |= new_mask;
627 dst->views.dirty_mask |= new_mask;
628 dst->views.compressed_depthtex_mask &= dst->views.enabled_mask;
629 dst->views.compressed_colortex_mask &= dst->views.enabled_mask;
630 dst->views.dirty_txq_constants = TRUE;
631 r600_sampler_views_dirty(rctx, &dst->views);
632
633 if (dirty_sampler_states_mask) {
634 dst->states.dirty_mask |= dirty_sampler_states_mask;
635 r600_sampler_states_dirty(rctx, &dst->states);
636 }
637 }
638
639 static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
640 struct pipe_sampler_view **views)
641 {
642 r600_set_sampler_views(ctx, PIPE_SHADER_VERTEX, 0, count, views);
643 }
644
645 static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
646 struct pipe_sampler_view **views)
647 {
648 r600_set_sampler_views(ctx, PIPE_SHADER_FRAGMENT, 0, count, views);
649 }
650
651 static void r600_set_viewport_state(struct pipe_context *ctx,
652 const struct pipe_viewport_state *state)
653 {
654 struct r600_context *rctx = (struct r600_context *)ctx;
655
656 rctx->viewport.state = *state;
657 rctx->viewport.atom.dirty = true;
658 }
659
660 void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom)
661 {
662 struct radeon_winsys_cs *cs = rctx->cs;
663 struct pipe_viewport_state *state = &rctx->viewport.state;
664
665 r600_write_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE_0, 6);
666 r600_write_value(cs, fui(state->scale[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
667 r600_write_value(cs, fui(state->translate[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
668 r600_write_value(cs, fui(state->scale[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
669 r600_write_value(cs, fui(state->translate[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
670 r600_write_value(cs, fui(state->scale[2])); /* R_02844C_PA_CL_VPORT_ZSCALE_0 */
671 r600_write_value(cs, fui(state->translate[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
672 }
673
674 /* Compute the key for the hw shader variant */
675 static INLINE struct r600_shader_key r600_shader_selector_key(struct pipe_context * ctx,
676 struct r600_pipe_shader_selector * sel)
677 {
678 struct r600_context *rctx = (struct r600_context *)ctx;
679 struct r600_shader_key key;
680 memset(&key, 0, sizeof(key));
681
682 if (sel->type == PIPE_SHADER_FRAGMENT) {
683 key.color_two_side = rctx->rasterizer && rctx->rasterizer->two_side;
684 key.alpha_to_one = rctx->alpha_to_one &&
685 rctx->rasterizer && rctx->rasterizer->multisample_enable &&
686 !rctx->framebuffer.cb0_is_integer;
687 key.nr_cbufs = rctx->framebuffer.state.nr_cbufs;
688 /* Dual-source blending only makes sense with nr_cbufs == 1. */
689 if (key.nr_cbufs == 1 && rctx->dual_src_blend)
690 key.nr_cbufs = 2;
691 }
692 return key;
693 }
694
695 /* Select the hw shader variant depending on the current state.
696 * (*dirty) is set to 1 if current variant was changed */
697 static int r600_shader_select(struct pipe_context *ctx,
698 struct r600_pipe_shader_selector* sel,
699 unsigned *dirty)
700 {
701 struct r600_shader_key key;
702 struct r600_context *rctx = (struct r600_context *)ctx;
703 struct r600_pipe_shader * shader = NULL;
704 int r;
705
706 key = r600_shader_selector_key(ctx, sel);
707
708 /* Check if we don't need to change anything.
709 * This path is also used for most shaders that don't need multiple
710 * variants, it will cost just a computation of the key and this
711 * test. */
712 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
713 return 0;
714 }
715
716 /* lookup if we have other variants in the list */
717 if (sel->num_shaders > 1) {
718 struct r600_pipe_shader *p = sel->current, *c = p->next_variant;
719
720 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
721 p = c;
722 c = c->next_variant;
723 }
724
725 if (c) {
726 p->next_variant = c->next_variant;
727 shader = c;
728 }
729 }
730
731 if (unlikely(!shader)) {
732 shader = CALLOC(1, sizeof(struct r600_pipe_shader));
733 shader->selector = sel;
734
735 r = r600_pipe_shader_create(ctx, shader, key);
736 if (unlikely(r)) {
737 R600_ERR("Failed to build shader variant (type=%u) %d\n",
738 sel->type, r);
739 sel->current = NULL;
740 return r;
741 }
742
743 /* We don't know the value of nr_ps_max_color_exports until we built
744 * at least one variant, so we may need to recompute the key after
745 * building first variant. */
746 if (sel->type == PIPE_SHADER_FRAGMENT &&
747 sel->num_shaders == 0) {
748 sel->nr_ps_max_color_exports = shader->shader.nr_ps_max_color_exports;
749 key = r600_shader_selector_key(ctx, sel);
750 }
751
752 shader->key = key;
753 sel->num_shaders++;
754 }
755
756 if (dirty)
757 *dirty = 1;
758
759 shader->next_variant = sel->current;
760 sel->current = shader;
761
762 if (rctx->ps_shader &&
763 rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
764 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
765 rctx->cb_misc_state.atom.dirty = true;
766 }
767 return 0;
768 }
769
770 static void *r600_create_shader_state(struct pipe_context *ctx,
771 const struct pipe_shader_state *state,
772 unsigned pipe_shader_type)
773 {
774 struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector);
775 int r;
776
777 sel->type = pipe_shader_type;
778 sel->tokens = tgsi_dup_tokens(state->tokens);
779 sel->so = state->stream_output;
780
781 r = r600_shader_select(ctx, sel, NULL);
782 if (r)
783 return NULL;
784
785 return sel;
786 }
787
788 static void *r600_create_ps_state(struct pipe_context *ctx,
789 const struct pipe_shader_state *state)
790 {
791 return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
792 }
793
794 static void *r600_create_vs_state(struct pipe_context *ctx,
795 const struct pipe_shader_state *state)
796 {
797 return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
798 }
799
800 static void r600_bind_ps_state(struct pipe_context *ctx, void *state)
801 {
802 struct r600_context *rctx = (struct r600_context *)ctx;
803
804 if (!state)
805 state = rctx->dummy_pixel_shader;
806
807 rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
808 r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
809
810 if (rctx->chip_class <= R700) {
811 bool multiwrite = rctx->ps_shader->current->shader.fs_write_all;
812
813 if (rctx->cb_misc_state.multiwrite != multiwrite) {
814 rctx->cb_misc_state.multiwrite = multiwrite;
815 rctx->cb_misc_state.atom.dirty = true;
816 }
817 }
818
819 if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
820 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
821 rctx->cb_misc_state.atom.dirty = true;
822 }
823
824 if (rctx->chip_class >= EVERGREEN) {
825 evergreen_update_db_shader_control(rctx);
826 } else {
827 r600_update_db_shader_control(rctx);
828 }
829 }
830
831 static void r600_bind_vs_state(struct pipe_context *ctx, void *state)
832 {
833 struct r600_context *rctx = (struct r600_context *)ctx;
834
835 rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
836 if (state) {
837 r600_context_pipe_state_set(rctx, &rctx->vs_shader->current->rstate);
838
839 /* Update clip misc state. */
840 if (rctx->vs_shader->current->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
841 rctx->vs_shader->current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write) {
842 rctx->clip_misc_state.pa_cl_vs_out_cntl = rctx->vs_shader->current->pa_cl_vs_out_cntl;
843 rctx->clip_misc_state.clip_dist_write = rctx->vs_shader->current->shader.clip_dist_write;
844 rctx->clip_misc_state.atom.dirty = true;
845 }
846 }
847 }
848
849 static void r600_delete_shader_selector(struct pipe_context *ctx,
850 struct r600_pipe_shader_selector *sel)
851 {
852 struct r600_pipe_shader *p = sel->current, *c;
853 while (p) {
854 c = p->next_variant;
855 r600_pipe_shader_destroy(ctx, p);
856 free(p);
857 p = c;
858 }
859
860 free(sel->tokens);
861 free(sel);
862 }
863
864
865 static void r600_delete_ps_state(struct pipe_context *ctx, void *state)
866 {
867 struct r600_context *rctx = (struct r600_context *)ctx;
868 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
869
870 if (rctx->ps_shader == sel) {
871 rctx->ps_shader = NULL;
872 }
873
874 r600_delete_shader_selector(ctx, sel);
875 }
876
877 static void r600_delete_vs_state(struct pipe_context *ctx, void *state)
878 {
879 struct r600_context *rctx = (struct r600_context *)ctx;
880 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
881
882 if (rctx->vs_shader == sel) {
883 rctx->vs_shader = NULL;
884 }
885
886 r600_delete_shader_selector(ctx, sel);
887 }
888
889 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
890 {
891 if (state->dirty_mask) {
892 rctx->flags |= R600_CONTEXT_SHADERCONST_FLUSH;
893 state->atom.num_dw = rctx->chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
894 : util_bitcount(state->dirty_mask)*19;
895 state->atom.dirty = true;
896 }
897 }
898
899 static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
900 struct pipe_constant_buffer *input)
901 {
902 struct r600_context *rctx = (struct r600_context *)ctx;
903 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
904 struct pipe_constant_buffer *cb;
905 const uint8_t *ptr;
906
907 /* Note that the state tracker can unbind constant buffers by
908 * passing NULL here.
909 */
910 if (unlikely(!input)) {
911 state->enabled_mask &= ~(1 << index);
912 state->dirty_mask &= ~(1 << index);
913 pipe_resource_reference(&state->cb[index].buffer, NULL);
914 return;
915 }
916
917 cb = &state->cb[index];
918 cb->buffer_size = input->buffer_size;
919
920 ptr = input->user_buffer;
921
922 if (ptr) {
923 /* Upload the user buffer. */
924 if (R600_BIG_ENDIAN) {
925 uint32_t *tmpPtr;
926 unsigned i, size = input->buffer_size;
927
928 if (!(tmpPtr = malloc(size))) {
929 R600_ERR("Failed to allocate BE swap buffer.\n");
930 return;
931 }
932
933 for (i = 0; i < size / 4; ++i) {
934 tmpPtr[i] = bswap_32(((uint32_t *)ptr)[i]);
935 }
936
937 u_upload_data(rctx->uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer);
938 free(tmpPtr);
939 } else {
940 u_upload_data(rctx->uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer);
941 }
942 } else {
943 /* Setup the hw buffer. */
944 cb->buffer_offset = input->buffer_offset;
945 pipe_resource_reference(&cb->buffer, input->buffer);
946 }
947
948 state->enabled_mask |= 1 << index;
949 state->dirty_mask |= 1 << index;
950 r600_constant_buffers_dirty(rctx, state);
951 }
952
953 static struct pipe_stream_output_target *
954 r600_create_so_target(struct pipe_context *ctx,
955 struct pipe_resource *buffer,
956 unsigned buffer_offset,
957 unsigned buffer_size)
958 {
959 struct r600_context *rctx = (struct r600_context *)ctx;
960 struct r600_so_target *t;
961
962 t = CALLOC_STRUCT(r600_so_target);
963 if (!t) {
964 return NULL;
965 }
966
967 u_suballocator_alloc(rctx->allocator_so_filled_size, 4,
968 &t->buf_filled_size_offset,
969 (struct pipe_resource**)&t->buf_filled_size);
970 if (!t->buf_filled_size) {
971 FREE(t);
972 return NULL;
973 }
974
975 t->b.reference.count = 1;
976 t->b.context = ctx;
977 pipe_resource_reference(&t->b.buffer, buffer);
978 t->b.buffer_offset = buffer_offset;
979 t->b.buffer_size = buffer_size;
980 return &t->b;
981 }
982
983 static void r600_so_target_destroy(struct pipe_context *ctx,
984 struct pipe_stream_output_target *target)
985 {
986 struct r600_so_target *t = (struct r600_so_target*)target;
987 pipe_resource_reference(&t->b.buffer, NULL);
988 pipe_resource_reference((struct pipe_resource**)&t->buf_filled_size, NULL);
989 FREE(t);
990 }
991
992 static void r600_set_so_targets(struct pipe_context *ctx,
993 unsigned num_targets,
994 struct pipe_stream_output_target **targets,
995 unsigned append_bitmask)
996 {
997 struct r600_context *rctx = (struct r600_context *)ctx;
998 unsigned i;
999
1000 /* Stop streamout. */
1001 if (rctx->num_so_targets && !rctx->streamout_start) {
1002 r600_context_streamout_end(rctx);
1003 }
1004
1005 /* Set the new targets. */
1006 for (i = 0; i < num_targets; i++) {
1007 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]);
1008 }
1009 for (; i < rctx->num_so_targets; i++) {
1010 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL);
1011 }
1012
1013 rctx->num_so_targets = num_targets;
1014 rctx->streamout_start = num_targets != 0;
1015 rctx->streamout_append_bitmask = append_bitmask;
1016 }
1017
1018 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1019 {
1020 struct r600_context *rctx = (struct r600_context*)pipe;
1021
1022 if (rctx->sample_mask.sample_mask == (uint16_t)sample_mask)
1023 return;
1024
1025 rctx->sample_mask.sample_mask = sample_mask;
1026 rctx->sample_mask.atom.dirty = true;
1027 }
1028
1029 static void r600_setup_txq_cube_array_constants(struct r600_context *rctx, int shader_type)
1030 {
1031 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1032 int bits;
1033 uint32_t array_size;
1034 struct pipe_constant_buffer cb;
1035 int i;
1036
1037 if (!samplers->views.dirty_txq_constants)
1038 return;
1039
1040 samplers->views.dirty_txq_constants = FALSE;
1041
1042 bits = util_last_bit(samplers->views.enabled_mask);
1043 array_size = bits * sizeof(uint32_t) * 4;
1044 samplers->txq_constants = realloc(samplers->txq_constants, array_size);
1045 memset(samplers->txq_constants, 0, array_size);
1046 for (i = 0; i < bits; i++)
1047 if (samplers->views.enabled_mask & (1 << i))
1048 samplers->txq_constants[i] = samplers->views.views[i]->base.texture->array_size / 6;
1049
1050 cb.buffer = NULL;
1051 cb.user_buffer = samplers->txq_constants;
1052 cb.buffer_offset = 0;
1053 cb.buffer_size = array_size;
1054 rctx->context.set_constant_buffer(&rctx->context, shader_type, R600_TXQ_CONST_BUFFER, &cb);
1055 pipe_resource_reference(&cb.buffer, NULL);
1056 }
1057
1058 static bool r600_update_derived_state(struct r600_context *rctx)
1059 {
1060 struct pipe_context * ctx = (struct pipe_context*)rctx;
1061 unsigned ps_dirty = 0;
1062 bool blend_disable;
1063
1064 if (!rctx->blitter->running) {
1065 unsigned i;
1066
1067 /* Decompress textures if needed. */
1068 for (i = 0; i < PIPE_SHADER_TYPES; i++) {
1069 struct r600_samplerview_state *views = &rctx->samplers[i].views;
1070 if (views->compressed_depthtex_mask) {
1071 r600_decompress_depth_textures(rctx, views);
1072 }
1073 if (views->compressed_colortex_mask) {
1074 r600_decompress_color_textures(rctx, views);
1075 }
1076 }
1077 }
1078
1079 r600_shader_select(ctx, rctx->ps_shader, &ps_dirty);
1080
1081 if (rctx->ps_shader && rctx->rasterizer &&
1082 ((rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable) ||
1083 (rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade))) {
1084
1085 if (rctx->chip_class >= EVERGREEN)
1086 evergreen_pipe_shader_ps(ctx, rctx->ps_shader->current);
1087 else
1088 r600_pipe_shader_ps(ctx, rctx->ps_shader->current);
1089
1090 ps_dirty = 1;
1091 }
1092
1093 if (ps_dirty)
1094 r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
1095
1096 if (rctx->ps_shader && rctx->ps_shader->current->shader.has_txq_cube_array_z_comp)
1097 r600_setup_txq_cube_array_constants(rctx, PIPE_SHADER_FRAGMENT);
1098 if (rctx->vs_shader && rctx->vs_shader->current->shader.has_txq_cube_array_z_comp)
1099 r600_setup_txq_cube_array_constants(rctx, PIPE_SHADER_VERTEX);
1100
1101 if (rctx->chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
1102 if (!r600_adjust_gprs(rctx)) {
1103 /* discard rendering */
1104 return false;
1105 }
1106 }
1107
1108 blend_disable = (rctx->dual_src_blend &&
1109 rctx->ps_shader->current->nr_ps_color_outputs < 2);
1110
1111 if (blend_disable != rctx->force_blend_disable) {
1112 rctx->force_blend_disable = blend_disable;
1113 r600_bind_blend_state_internal(rctx,
1114 rctx->blend_state.cso,
1115 blend_disable);
1116 }
1117 return true;
1118 }
1119
1120 static unsigned r600_conv_prim_to_gs_out(unsigned mode)
1121 {
1122 static const int prim_conv[] = {
1123 V_028A6C_OUTPRIM_TYPE_POINTLIST,
1124 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1125 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1126 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1127 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1128 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1129 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1130 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1131 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1132 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1133 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1134 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1135 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1136 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1137 V_028A6C_OUTPRIM_TYPE_TRISTRIP
1138 };
1139 assert(mode < Elements(prim_conv));
1140
1141 return prim_conv[mode];
1142 }
1143
1144 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1145 {
1146 struct radeon_winsys_cs *cs = rctx->cs;
1147 struct r600_clip_misc_state *state = &rctx->clip_misc_state;
1148
1149 r600_write_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
1150 state->pa_cl_clip_cntl |
1151 (state->clip_dist_write ? 0 : state->clip_plane_enable & 0x3F));
1152 r600_write_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
1153 state->pa_cl_vs_out_cntl |
1154 (state->clip_plane_enable & state->clip_dist_write));
1155 }
1156
1157 static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
1158 {
1159 struct r600_context *rctx = (struct r600_context *)ctx;
1160 struct pipe_draw_info info = *dinfo;
1161 struct pipe_index_buffer ib = {};
1162 unsigned i;
1163 struct r600_block *dirty_block = NULL, *next_block = NULL;
1164 struct radeon_winsys_cs *cs = rctx->cs;
1165
1166 if (!info.count && (info.indexed || !info.count_from_stream_output)) {
1167 assert(0);
1168 return;
1169 }
1170
1171 if (!rctx->vs_shader) {
1172 assert(0);
1173 return;
1174 }
1175
1176 if (!r600_update_derived_state(rctx)) {
1177 /* useless to render because current rendering command
1178 * can't be achieved
1179 */
1180 return;
1181 }
1182
1183 if (info.indexed) {
1184 /* Initialize the index buffer struct. */
1185 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
1186 ib.user_buffer = rctx->index_buffer.user_buffer;
1187 ib.index_size = rctx->index_buffer.index_size;
1188 ib.offset = rctx->index_buffer.offset + info.start * ib.index_size;
1189
1190 /* Translate 8-bit indices to 16-bit. */
1191 if (ib.index_size == 1) {
1192 struct pipe_resource *out_buffer = NULL;
1193 unsigned out_offset;
1194 void *ptr;
1195
1196 u_upload_alloc(rctx->uploader, 0, info.count * 2,
1197 &out_offset, &out_buffer, &ptr);
1198
1199 util_shorten_ubyte_elts_to_userptr(
1200 &rctx->context, &ib, 0, ib.offset, info.count, ptr);
1201
1202 pipe_resource_reference(&ib.buffer, NULL);
1203 ib.user_buffer = NULL;
1204 ib.buffer = out_buffer;
1205 ib.offset = out_offset;
1206 ib.index_size = 2;
1207 }
1208
1209 /* Upload the index buffer.
1210 * The upload is skipped for small index counts on little-endian machines
1211 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
1212 * Note: Instanced rendering in combination with immediate indices hangs. */
1213 if (ib.user_buffer && (R600_BIG_ENDIAN || info.instance_count > 1 ||
1214 info.count*ib.index_size > 20)) {
1215 u_upload_data(rctx->uploader, 0, info.count * ib.index_size,
1216 ib.user_buffer, &ib.offset, &ib.buffer);
1217 ib.user_buffer = NULL;
1218 }
1219 } else {
1220 info.index_bias = info.start;
1221 }
1222
1223 /* Enable stream out if needed. */
1224 if (rctx->streamout_start) {
1225 r600_context_streamout_begin(rctx);
1226 rctx->streamout_start = FALSE;
1227 }
1228
1229 /* Set the index offset and multi primitive */
1230 if (rctx->vgt2_state.vgt_indx_offset != info.index_bias) {
1231 rctx->vgt2_state.vgt_indx_offset = info.index_bias;
1232 rctx->vgt2_state.atom.dirty = true;
1233 }
1234 if (rctx->vgt_state.vgt_multi_prim_ib_reset_en != info.primitive_restart ||
1235 rctx->vgt_state.vgt_multi_prim_ib_reset_indx != info.restart_index) {
1236 rctx->vgt_state.vgt_multi_prim_ib_reset_en = info.primitive_restart;
1237 rctx->vgt_state.vgt_multi_prim_ib_reset_indx = info.restart_index;
1238 rctx->vgt_state.atom.dirty = true;
1239 }
1240
1241 /* Emit states. */
1242 r600_need_cs_space(rctx, ib.user_buffer ? 5 : 0, TRUE);
1243 r600_flush_emit(rctx);
1244
1245 for (i = 0; i < R600_NUM_ATOMS; i++) {
1246 if (rctx->atoms[i] == NULL || !rctx->atoms[i]->dirty) {
1247 continue;
1248 }
1249 r600_emit_atom(rctx, rctx->atoms[i]);
1250 }
1251 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) {
1252 r600_context_block_emit_dirty(rctx, dirty_block, 0 /* pkt_flags */);
1253 }
1254 rctx->pm4_dirty_cdwords = 0;
1255
1256 /* Update start instance. */
1257 if (rctx->last_start_instance != info.start_instance) {
1258 r600_write_ctl_const(cs, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
1259 rctx->last_start_instance = info.start_instance;
1260 }
1261
1262 /* Update the primitive type. */
1263 if (rctx->last_primitive_type != info.mode) {
1264 unsigned ls_mask = 0;
1265
1266 if (info.mode == PIPE_PRIM_LINES)
1267 ls_mask = 1;
1268 else if (info.mode == PIPE_PRIM_LINE_STRIP ||
1269 info.mode == PIPE_PRIM_LINE_LOOP)
1270 ls_mask = 2;
1271
1272 r600_write_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
1273 S_028A0C_AUTO_RESET_CNTL(ls_mask) |
1274 (rctx->rasterizer ? rctx->rasterizer->pa_sc_line_stipple : 0));
1275 r600_write_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
1276 r600_conv_prim_to_gs_out(info.mode));
1277 r600_write_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE,
1278 r600_conv_pipe_prim(info.mode));
1279
1280 rctx->last_primitive_type = info.mode;
1281 }
1282
1283 /* Draw packets. */
1284 cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->predicate_drawing);
1285 cs->buf[cs->cdw++] = info.instance_count;
1286 if (info.indexed) {
1287 cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->predicate_drawing);
1288 cs->buf[cs->cdw++] = ib.index_size == 4 ?
1289 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
1290 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
1291
1292 if (ib.user_buffer) {
1293 unsigned size_bytes = info.count*ib.index_size;
1294 unsigned size_dw = align(size_bytes, 4) / 4;
1295 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_IMMD, 1 + size_dw, rctx->predicate_drawing);
1296 cs->buf[cs->cdw++] = info.count;
1297 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_IMMEDIATE;
1298 memcpy(cs->buf+cs->cdw, ib.user_buffer, size_bytes);
1299 cs->cdw += size_dw;
1300 } else {
1301 uint64_t va = r600_resource_va(ctx->screen, ib.buffer) + ib.offset;
1302 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->predicate_drawing);
1303 cs->buf[cs->cdw++] = va;
1304 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
1305 cs->buf[cs->cdw++] = info.count;
1306 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
1307 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->predicate_drawing);
1308 cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
1309 }
1310 } else {
1311 if (info.count_from_stream_output) {
1312 struct r600_so_target *t = (struct r600_so_target*)info.count_from_stream_output;
1313 uint64_t va = r600_resource_va(&rctx->screen->screen, (void*)t->buf_filled_size) + t->buf_filled_size_offset;
1314
1315 r600_write_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
1316
1317 cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0);
1318 cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG;
1319 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */
1320 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
1321 cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */
1322 cs->buf[cs->cdw++] = 0; /* unused */
1323
1324 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1325 cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, t->buf_filled_size, RADEON_USAGE_READ);
1326 }
1327
1328 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->predicate_drawing);
1329 cs->buf[cs->cdw++] = info.count;
1330 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
1331 (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
1332 }
1333
1334 /* Set the depth buffer as dirty. */
1335 if (rctx->framebuffer.state.zsbuf) {
1336 struct pipe_surface *surf = rctx->framebuffer.state.zsbuf;
1337 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
1338
1339 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1340 }
1341 if (rctx->framebuffer.compressed_cb_mask) {
1342 struct pipe_surface *surf;
1343 struct r600_texture *rtex;
1344 unsigned mask = rctx->framebuffer.compressed_cb_mask;
1345
1346 do {
1347 unsigned i = u_bit_scan(&mask);
1348 surf = rctx->framebuffer.state.cbufs[i];
1349 rtex = (struct r600_texture*)surf->texture;
1350
1351 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1352
1353 } while (mask);
1354 }
1355
1356 pipe_resource_reference(&ib.buffer, NULL);
1357 }
1358
1359 void r600_draw_rectangle(struct blitter_context *blitter,
1360 int x1, int y1, int x2, int y2, float depth,
1361 enum blitter_attrib_type type, const union pipe_color_union *attrib)
1362 {
1363 struct r600_context *rctx = (struct r600_context*)util_blitter_get_pipe(blitter);
1364 struct pipe_viewport_state viewport;
1365 struct pipe_resource *buf = NULL;
1366 unsigned offset = 0;
1367 float *vb;
1368
1369 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
1370 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
1371 return;
1372 }
1373
1374 /* Some operations (like color resolve on r6xx) don't work
1375 * with the conventional primitive types.
1376 * One that works is PT_RECTLIST, which we use here. */
1377
1378 /* setup viewport */
1379 viewport.scale[0] = 1.0f;
1380 viewport.scale[1] = 1.0f;
1381 viewport.scale[2] = 1.0f;
1382 viewport.scale[3] = 1.0f;
1383 viewport.translate[0] = 0.0f;
1384 viewport.translate[1] = 0.0f;
1385 viewport.translate[2] = 0.0f;
1386 viewport.translate[3] = 0.0f;
1387 rctx->context.set_viewport_state(&rctx->context, &viewport);
1388
1389 /* Upload vertices. The hw rectangle has only 3 vertices,
1390 * I guess the 4th one is derived from the first 3.
1391 * The vertex specification should match u_blitter's vertex element state. */
1392 u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, &offset, &buf, (void**)&vb);
1393 vb[0] = x1;
1394 vb[1] = y1;
1395 vb[2] = depth;
1396 vb[3] = 1;
1397
1398 vb[8] = x1;
1399 vb[9] = y2;
1400 vb[10] = depth;
1401 vb[11] = 1;
1402
1403 vb[16] = x2;
1404 vb[17] = y1;
1405 vb[18] = depth;
1406 vb[19] = 1;
1407
1408 if (attrib) {
1409 memcpy(vb+4, attrib->f, sizeof(float)*4);
1410 memcpy(vb+12, attrib->f, sizeof(float)*4);
1411 memcpy(vb+20, attrib->f, sizeof(float)*4);
1412 }
1413
1414 /* draw */
1415 util_draw_vertex_buffer(&rctx->context, NULL, buf, rctx->blitter->vb_slot, offset,
1416 R600_PRIM_RECTANGLE_LIST, 3, 2);
1417 pipe_resource_reference(&buf, NULL);
1418 }
1419
1420 void _r600_pipe_state_add_reg_bo(struct r600_context *ctx,
1421 struct r600_pipe_state *state,
1422 uint32_t offset, uint32_t value,
1423 uint32_t range_id, uint32_t block_id,
1424 struct r600_resource *bo,
1425 enum radeon_bo_usage usage)
1426
1427 {
1428 struct r600_range *range;
1429 struct r600_block *block;
1430
1431 if (bo) assert(usage);
1432
1433 range = &ctx->range[range_id];
1434 block = range->blocks[block_id];
1435 state->regs[state->nregs].block = block;
1436 state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
1437
1438 state->regs[state->nregs].value = value;
1439 state->regs[state->nregs].bo = bo;
1440 state->regs[state->nregs].bo_usage = usage;
1441
1442 state->nregs++;
1443 assert(state->nregs < R600_BLOCK_MAX_REG);
1444 }
1445
1446 void _r600_pipe_state_add_reg(struct r600_context *ctx,
1447 struct r600_pipe_state *state,
1448 uint32_t offset, uint32_t value,
1449 uint32_t range_id, uint32_t block_id)
1450 {
1451 _r600_pipe_state_add_reg_bo(ctx, state, offset, value,
1452 range_id, block_id, NULL, 0);
1453 }
1454
1455 uint32_t r600_translate_stencil_op(int s_op)
1456 {
1457 switch (s_op) {
1458 case PIPE_STENCIL_OP_KEEP:
1459 return V_028800_STENCIL_KEEP;
1460 case PIPE_STENCIL_OP_ZERO:
1461 return V_028800_STENCIL_ZERO;
1462 case PIPE_STENCIL_OP_REPLACE:
1463 return V_028800_STENCIL_REPLACE;
1464 case PIPE_STENCIL_OP_INCR:
1465 return V_028800_STENCIL_INCR;
1466 case PIPE_STENCIL_OP_DECR:
1467 return V_028800_STENCIL_DECR;
1468 case PIPE_STENCIL_OP_INCR_WRAP:
1469 return V_028800_STENCIL_INCR_WRAP;
1470 case PIPE_STENCIL_OP_DECR_WRAP:
1471 return V_028800_STENCIL_DECR_WRAP;
1472 case PIPE_STENCIL_OP_INVERT:
1473 return V_028800_STENCIL_INVERT;
1474 default:
1475 R600_ERR("Unknown stencil op %d", s_op);
1476 assert(0);
1477 break;
1478 }
1479 return 0;
1480 }
1481
1482 uint32_t r600_translate_fill(uint32_t func)
1483 {
1484 switch(func) {
1485 case PIPE_POLYGON_MODE_FILL:
1486 return 2;
1487 case PIPE_POLYGON_MODE_LINE:
1488 return 1;
1489 case PIPE_POLYGON_MODE_POINT:
1490 return 0;
1491 default:
1492 assert(0);
1493 return 0;
1494 }
1495 }
1496
1497 unsigned r600_tex_wrap(unsigned wrap)
1498 {
1499 switch (wrap) {
1500 default:
1501 case PIPE_TEX_WRAP_REPEAT:
1502 return V_03C000_SQ_TEX_WRAP;
1503 case PIPE_TEX_WRAP_CLAMP:
1504 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1505 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1506 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1507 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1508 return V_03C000_SQ_TEX_CLAMP_BORDER;
1509 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1510 return V_03C000_SQ_TEX_MIRROR;
1511 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1512 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1513 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1514 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1515 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1516 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1517 }
1518 }
1519
1520 unsigned r600_tex_filter(unsigned filter)
1521 {
1522 switch (filter) {
1523 default:
1524 case PIPE_TEX_FILTER_NEAREST:
1525 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1526 case PIPE_TEX_FILTER_LINEAR:
1527 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1528 }
1529 }
1530
1531 unsigned r600_tex_mipfilter(unsigned filter)
1532 {
1533 switch (filter) {
1534 case PIPE_TEX_MIPFILTER_NEAREST:
1535 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1536 case PIPE_TEX_MIPFILTER_LINEAR:
1537 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1538 default:
1539 case PIPE_TEX_MIPFILTER_NONE:
1540 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1541 }
1542 }
1543
1544 unsigned r600_tex_compare(unsigned compare)
1545 {
1546 switch (compare) {
1547 default:
1548 case PIPE_FUNC_NEVER:
1549 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1550 case PIPE_FUNC_LESS:
1551 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1552 case PIPE_FUNC_EQUAL:
1553 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1554 case PIPE_FUNC_LEQUAL:
1555 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1556 case PIPE_FUNC_GREATER:
1557 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1558 case PIPE_FUNC_NOTEQUAL:
1559 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1560 case PIPE_FUNC_GEQUAL:
1561 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1562 case PIPE_FUNC_ALWAYS:
1563 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1564 }
1565 }
1566
1567 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
1568 {
1569 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
1570 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
1571 (linear_filter &&
1572 (wrap == PIPE_TEX_WRAP_CLAMP ||
1573 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
1574 }
1575
1576 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
1577 {
1578 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
1579 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
1580
1581 return (state->border_color.ui[0] || state->border_color.ui[1] ||
1582 state->border_color.ui[2] || state->border_color.ui[3]) &&
1583 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
1584 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
1585 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
1586 }
1587
1588 /* keep this at the end of this file, please */
1589 void r600_init_common_state_functions(struct r600_context *rctx)
1590 {
1591 rctx->context.create_fs_state = r600_create_ps_state;
1592 rctx->context.create_vs_state = r600_create_vs_state;
1593 rctx->context.create_vertex_elements_state = r600_create_vertex_fetch_shader;
1594 rctx->context.bind_blend_state = r600_bind_blend_state;
1595 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1596 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler_states;
1597 rctx->context.bind_fs_state = r600_bind_ps_state;
1598 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1599 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1600 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler_states;
1601 rctx->context.bind_vs_state = r600_bind_vs_state;
1602 rctx->context.delete_blend_state = r600_delete_blend_state;
1603 rctx->context.delete_depth_stencil_alpha_state = r600_delete_dsa_state;
1604 rctx->context.delete_fs_state = r600_delete_ps_state;
1605 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1606 rctx->context.delete_sampler_state = r600_delete_sampler_state;
1607 rctx->context.delete_vertex_elements_state = r600_delete_vertex_elements;
1608 rctx->context.delete_vs_state = r600_delete_vs_state;
1609 rctx->context.set_blend_color = r600_set_blend_color;
1610 rctx->context.set_clip_state = r600_set_clip_state;
1611 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1612 rctx->context.set_sample_mask = r600_set_sample_mask;
1613 rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1614 rctx->context.set_viewport_state = r600_set_viewport_state;
1615 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1616 rctx->context.set_index_buffer = r600_set_index_buffer;
1617 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views;
1618 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views;
1619 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1620 rctx->context.texture_barrier = r600_texture_barrier;
1621 rctx->context.create_stream_output_target = r600_create_so_target;
1622 rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1623 rctx->context.set_stream_output_targets = r600_set_so_targets;
1624 rctx->context.draw_vbo = r600_draw_vbo;
1625 }