src/gallium/drivers/r600/r600_state_common.c

   1 /*
   2  * Copyright 2010 Red Hat Inc.
   3  *           2010 Jerome Glisse
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie <airlied@redhat.com>
  25  *          Jerome Glisse <jglisse@redhat.com>
  26  */
  27 #include "util/u_blitter.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_format.h"
  30 #include "pipebuffer/pb_buffer.h"
  31 #include "pipe/p_shader_tokens.h"
  32 #include "tgsi/tgsi_parse.h"
  33 #include "r600_formats.h"
  34 #include "r600_pipe.h"
  35 #include "r600d.h"
  36 #include "r600_hw_context_priv.h"
  37
  38 static void r600_emit_command_buffer(struct r600_context *rctx, struct r600_atom *atom)
  39 {
  40         struct radeon_winsys_cs *cs = rctx->cs;
  41         struct r600_command_buffer *cb = (struct r600_command_buffer*)atom;
  42
  43         assert(cs->cdw + cb->atom.num_dw <= RADEON_MAX_CMDBUF_DWORDS);
  44         memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->atom.num_dw);
  45         cs->cdw += cb->atom.num_dw;
  46 }
  47
  48 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags)
  49 {
  50         cb->atom.emit = r600_emit_command_buffer;
  51         cb->atom.num_dw = 0;
  52         cb->atom.flags = flags;
  53         cb->buf = CALLOC(1, 4 * num_dw);
  54         cb->max_num_dw = num_dw;
  55 }
  56
  57 void r600_release_command_buffer(struct r600_command_buffer *cb)
  58 {
  59         FREE(cb->buf);
  60 }
  61
  62 static void r600_emit_surface_sync(struct r600_context *rctx, struct r600_atom *atom)
  63 {
  64         struct radeon_winsys_cs *cs = rctx->cs;
  65         struct r600_atom_surface_sync *a = (struct r600_atom_surface_sync*)atom;
  66
  67         cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
  68         cs->buf[cs->cdw++] = a->flush_flags;  /* CP_COHER_CNTL */
  69         cs->buf[cs->cdw++] = 0xffffffff;      /* CP_COHER_SIZE */
  70         cs->buf[cs->cdw++] = 0;               /* CP_COHER_BASE */
  71         cs->buf[cs->cdw++] = 0x0000000A;      /* POLL_INTERVAL */
  72
  73         a->flush_flags = 0;
  74 }
  75
  76 static void r600_emit_r6xx_flush_and_inv(struct r600_context *rctx, struct r600_atom *atom)
  77 {
  78         struct radeon_winsys_cs *cs = rctx->cs;
  79         cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
  80         cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
  81 }
  82
  83 void r600_init_atom(struct r600_atom *atom,
  84                     void (*emit)(struct r600_context *ctx, struct r600_atom *state),
  85                     unsigned num_dw, enum r600_atom_flags flags)
  86 {
  87         atom->emit = emit;
  88         atom->num_dw = num_dw;
  89         atom->flags = flags;
  90 }
  91
  92 void r600_init_common_atoms(struct r600_context *rctx)
  93 {
  94         r600_init_atom(&rctx->atom_surface_sync.atom,   r600_emit_surface_sync,         5, EMIT_EARLY);
  95         r600_init_atom(&rctx->atom_r6xx_flush_and_inv,  r600_emit_r6xx_flush_and_inv,   2, EMIT_EARLY);
  96 }
  97
  98 unsigned r600_get_cb_flush_flags(struct r600_context *rctx)
  99 {
 100         unsigned flags = 0;
 101
 102         if (rctx->framebuffer.nr_cbufs) {
 103                 flags |= S_0085F0_CB_ACTION_ENA(1) |
 104                          (((1 << rctx->framebuffer.nr_cbufs) - 1) << S_0085F0_CB0_DEST_BASE_ENA_SHIFT);
 105         }
 106
 107         /* Workaround for broken flushing on some R6xx chipsets. */
 108         if (rctx->family == CHIP_RV670 ||
 109             rctx->family == CHIP_RS780 ||
 110             rctx->family == CHIP_RS880) {
 111                 flags |=  S_0085F0_CB1_DEST_BASE_ENA(1) |
 112                           S_0085F0_DEST_BASE_0_ENA(1);
 113         }
 114         return flags;
 115 }
 116
 117 void r600_texture_barrier(struct pipe_context *ctx)
 118 {
 119         struct r600_context *rctx = (struct r600_context *)ctx;
 120
 121         rctx->atom_surface_sync.flush_flags |= S_0085F0_TC_ACTION_ENA(1) | r600_get_cb_flush_flags(rctx);
 122         r600_atom_dirty(rctx, &rctx->atom_surface_sync.atom);
 123 }
 124
 125 static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
 126 {
 127         static const int prim_conv[] = {
 128                 V_008958_DI_PT_POINTLIST,
 129                 V_008958_DI_PT_LINELIST,
 130                 V_008958_DI_PT_LINELOOP,
 131                 V_008958_DI_PT_LINESTRIP,
 132                 V_008958_DI_PT_TRILIST,
 133                 V_008958_DI_PT_TRISTRIP,
 134                 V_008958_DI_PT_TRIFAN,
 135                 V_008958_DI_PT_QUADLIST,
 136                 V_008958_DI_PT_QUADSTRIP,
 137                 V_008958_DI_PT_POLYGON,
 138                 -1,
 139                 -1,
 140                 -1,
 141                 -1
 142         };
 143
 144         *prim = prim_conv[pprim];
 145         if (*prim == -1) {
 146                 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim);
 147                 return false;
 148         }
 149         return true;
 150 }
 151
 152 /* common state between evergreen and r600 */
 153 void r600_bind_blend_state(struct pipe_context *ctx, void *state)
 154 {
 155         struct r600_context *rctx = (struct r600_context *)ctx;
 156         struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
 157         struct r600_pipe_state *rstate;
 158
 159         if (state == NULL)
 160                 return;
 161         rstate = &blend->rstate;
 162         rctx->states[rstate->id] = rstate;
 163         rctx->cb_target_mask = blend->cb_target_mask;
 164
 165         /* Replace every bit except MULTIWRITE_ENABLE. */
 166         rctx->cb_color_control &= ~C_028808_MULTIWRITE_ENABLE;
 167         rctx->cb_color_control |= blend->cb_color_control & C_028808_MULTIWRITE_ENABLE;
 168
 169         r600_context_pipe_state_set(rctx, rstate);
 170 }
 171
 172 void r600_set_blend_color(struct pipe_context *ctx,
 173                           const struct pipe_blend_color *state)
 174 {
 175         struct r600_context *rctx = (struct r600_context *)ctx;
 176         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 177
 178         if (rstate == NULL)
 179                 return;
 180
 181         rstate->id = R600_PIPE_STATE_BLEND_COLOR;
 182         r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), NULL, 0);
 183         r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), NULL, 0);
 184         r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), NULL, 0);
 185         r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), NULL, 0);
 186
 187         free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
 188         rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
 189         r600_context_pipe_state_set(rctx, rstate);
 190 }
 191
 192 static void r600_set_stencil_ref(struct pipe_context *ctx,
 193                                  const struct r600_stencil_ref *state)
 194 {
 195         struct r600_context *rctx = (struct r600_context *)ctx;
 196         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 197
 198         if (rstate == NULL)
 199                 return;
 200
 201         rstate->id = R600_PIPE_STATE_STENCIL_REF;
 202         r600_pipe_state_add_reg(rstate,
 203                                 R_028430_DB_STENCILREFMASK,
 204                                 S_028430_STENCILREF(state->ref_value[0]) |
 205                                 S_028430_STENCILMASK(state->valuemask[0]) |
 206                                 S_028430_STENCILWRITEMASK(state->writemask[0]),
 207                                 NULL, 0);
 208         r600_pipe_state_add_reg(rstate,
 209                                 R_028434_DB_STENCILREFMASK_BF,
 210                                 S_028434_STENCILREF_BF(state->ref_value[1]) |
 211                                 S_028434_STENCILMASK_BF(state->valuemask[1]) |
 212                                 S_028434_STENCILWRITEMASK_BF(state->writemask[1]),
 213                                 NULL, 0);
 214
 215         free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
 216         rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
 217         r600_context_pipe_state_set(rctx, rstate);
 218 }
 219
 220 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
 221                                const struct pipe_stencil_ref *state)
 222 {
 223         struct r600_context *rctx = (struct r600_context *)ctx;
 224         struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA];
 225         struct r600_stencil_ref ref;
 226
 227         rctx->stencil_ref = *state;
 228
 229         if (!dsa)
 230                 return;
 231
 232         ref.ref_value[0] = state->ref_value[0];
 233         ref.ref_value[1] = state->ref_value[1];
 234         ref.valuemask[0] = dsa->valuemask[0];
 235         ref.valuemask[1] = dsa->valuemask[1];
 236         ref.writemask[0] = dsa->writemask[0];
 237         ref.writemask[1] = dsa->writemask[1];
 238
 239         r600_set_stencil_ref(ctx, &ref);
 240 }
 241
 242 void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
 243 {
 244         struct r600_context *rctx = (struct r600_context *)ctx;
 245         struct r600_pipe_dsa *dsa = state;
 246         struct r600_pipe_state *rstate;
 247         struct r600_stencil_ref ref;
 248
 249         if (state == NULL)
 250                 return;
 251         rstate = &dsa->rstate;
 252         rctx->states[rstate->id] = rstate;
 253         rctx->alpha_ref = dsa->alpha_ref;
 254         rctx->alpha_ref_dirty = true;
 255         r600_context_pipe_state_set(rctx, rstate);
 256
 257         ref.ref_value[0] = rctx->stencil_ref.ref_value[0];
 258         ref.ref_value[1] = rctx->stencil_ref.ref_value[1];
 259         ref.valuemask[0] = dsa->valuemask[0];
 260         ref.valuemask[1] = dsa->valuemask[1];
 261         ref.writemask[0] = dsa->writemask[0];
 262         ref.writemask[1] = dsa->writemask[1];
 263
 264         r600_set_stencil_ref(ctx, &ref);
 265
 266         if (rctx->atom_db_misc_state.flush_depthstencil_enabled != dsa->is_flush) {
 267                 rctx->atom_db_misc_state.flush_depthstencil_enabled = dsa->is_flush;
 268                 r600_atom_dirty(rctx, &rctx->atom_db_misc_state.atom);
 269         }
 270 }
 271
 272 void r600_bind_rs_state(struct pipe_context *ctx, void *state)
 273 {
 274         struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
 275         struct r600_context *rctx = (struct r600_context *)ctx;
 276
 277         if (state == NULL)
 278                 return;
 279
 280         rctx->sprite_coord_enable = rs->sprite_coord_enable;
 281         rctx->two_side = rs->two_side;
 282         rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
 283         rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
 284
 285         rctx->rasterizer = rs;
 286
 287         rctx->states[rs->rstate.id] = &rs->rstate;
 288         r600_context_pipe_state_set(rctx, &rs->rstate);
 289
 290         if (rctx->chip_class >= EVERGREEN) {
 291                 evergreen_polygon_offset_update(rctx);
 292         } else {
 293                 r600_polygon_offset_update(rctx);
 294         }
 295 }
 296
 297 void r600_delete_rs_state(struct pipe_context *ctx, void *state)
 298 {
 299         struct r600_context *rctx = (struct r600_context *)ctx;
 300         struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
 301
 302         if (rctx->rasterizer == rs) {
 303                 rctx->rasterizer = NULL;
 304         }
 305         if (rctx->states[rs->rstate.id] == &rs->rstate) {
 306                 rctx->states[rs->rstate.id] = NULL;
 307         }
 308         free(rs);
 309 }
 310
 311 void r600_sampler_view_destroy(struct pipe_context *ctx,
 312                                struct pipe_sampler_view *state)
 313 {
 314         struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
 315
 316         pipe_resource_reference(&state->texture, NULL);
 317         FREE(resource);
 318 }
 319
 320 void r600_delete_state(struct pipe_context *ctx, void *state)
 321 {
 322         struct r600_context *rctx = (struct r600_context *)ctx;
 323         struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
 324
 325         if (rctx->states[rstate->id] == rstate) {
 326                 rctx->states[rstate->id] = NULL;
 327         }
 328         for (int i = 0; i < rstate->nregs; i++) {
 329                 pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL);
 330         }
 331         free(rstate);
 332 }
 333
 334 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
 335 {
 336         struct r600_context *rctx = (struct r600_context *)ctx;
 337         struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 338
 339         rctx->vertex_elements = v;
 340         if (v) {
 341                 r600_inval_shader_cache(rctx);
 342                 u_vbuf_bind_vertex_elements(rctx->vbuf_mgr, state,
 343                                                 v->vmgr_elements);
 344
 345                 rctx->states[v->rstate.id] = &v->rstate;
 346                 r600_context_pipe_state_set(rctx, &v->rstate);
 347         }
 348 }
 349
 350 void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
 351 {
 352         struct r600_context *rctx = (struct r600_context *)ctx;
 353         struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 354
 355         if (rctx->states[v->rstate.id] == &v->rstate) {
 356                 rctx->states[v->rstate.id] = NULL;
 357         }
 358         if (rctx->vertex_elements == state)
 359                 rctx->vertex_elements = NULL;
 360
 361         pipe_resource_reference((struct pipe_resource**)&v->fetch_shader, NULL);
 362         u_vbuf_destroy_vertex_elements(rctx->vbuf_mgr, v->vmgr_elements);
 363         FREE(state);
 364 }
 365
 366
 367 void r600_set_index_buffer(struct pipe_context *ctx,
 368                            const struct pipe_index_buffer *ib)
 369 {
 370         struct r600_context *rctx = (struct r600_context *)ctx;
 371
 372         u_vbuf_set_index_buffer(rctx->vbuf_mgr, ib);
 373 }
 374
 375 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
 376                              const struct pipe_vertex_buffer *buffers)
 377 {
 378         struct r600_context *rctx = (struct r600_context *)ctx;
 379         int i;
 380
 381         /* Zero states. */
 382         for (i = 0; i < count; i++) {
 383                 if (!buffers[i].buffer) {
 384                         if (rctx->chip_class >= EVERGREEN) {
 385                                 evergreen_context_pipe_state_set_fs_resource(rctx, NULL, i);
 386                         } else {
 387                                 r600_context_pipe_state_set_fs_resource(rctx, NULL, i);
 388                         }
 389                 }
 390         }
 391         for (; i < rctx->vbuf_mgr->nr_real_vertex_buffers; i++) {
 392                 if (rctx->chip_class >= EVERGREEN) {
 393                         evergreen_context_pipe_state_set_fs_resource(rctx, NULL, i);
 394                 } else {
 395                         r600_context_pipe_state_set_fs_resource(rctx, NULL, i);
 396                 }
 397         }
 398
 399         u_vbuf_set_vertex_buffers(rctx->vbuf_mgr, count, buffers);
 400 }
 401
 402 void *r600_create_vertex_elements(struct pipe_context *ctx,
 403                                   unsigned count,
 404                                   const struct pipe_vertex_element *elements)
 405 {
 406         struct r600_context *rctx = (struct r600_context *)ctx;
 407         struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
 408
 409         assert(count < 32);
 410         if (!v)
 411                 return NULL;
 412
 413         v->count = count;
 414         v->vmgr_elements =
 415                 u_vbuf_create_vertex_elements(rctx->vbuf_mgr, count,
 416                                                   elements, v->elements);
 417
 418         if (r600_vertex_elements_build_fetch_shader(rctx, v)) {
 419                 FREE(v);
 420                 return NULL;
 421         }
 422
 423         return v;
 424 }
 425
 426 void *r600_create_shader_state(struct pipe_context *ctx,
 427                                const struct pipe_shader_state *state)
 428 {
 429         struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader);
 430         int r;
 431
 432         shader->tokens = tgsi_dup_tokens(state->tokens);
 433         shader->so = state->stream_output;
 434
 435         r =  r600_pipe_shader_create(ctx, shader);
 436         if (r) {
 437                 return NULL;
 438         }
 439         return shader;
 440 }
 441
 442 void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
 443 {
 444         struct r600_context *rctx = (struct r600_context *)ctx;
 445
 446         /* TODO delete old shader */
 447         rctx->ps_shader = (struct r600_pipe_shader *)state;
 448         if (state) {
 449                 r600_inval_shader_cache(rctx);
 450                 r600_context_pipe_state_set(rctx, &rctx->ps_shader->rstate);
 451
 452                 rctx->cb_color_control &= C_028808_MULTIWRITE_ENABLE;
 453                 rctx->cb_color_control |= S_028808_MULTIWRITE_ENABLE(!!rctx->ps_shader->shader.fs_write_all);
 454         }
 455         if (rctx->ps_shader && rctx->vs_shader) {
 456                 r600_adjust_gprs(rctx);
 457         }
 458 }
 459
 460 void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
 461 {
 462         struct r600_context *rctx = (struct r600_context *)ctx;
 463
 464         /* TODO delete old shader */
 465         rctx->vs_shader = (struct r600_pipe_shader *)state;
 466         if (state) {
 467                 r600_inval_shader_cache(rctx);
 468                 r600_context_pipe_state_set(rctx, &rctx->vs_shader->rstate);
 469         }
 470         if (rctx->ps_shader && rctx->vs_shader) {
 471                 r600_adjust_gprs(rctx);
 472         }
 473 }
 474
 475 void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
 476 {
 477         struct r600_context *rctx = (struct r600_context *)ctx;
 478         struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
 479
 480         if (rctx->ps_shader == shader) {
 481                 rctx->ps_shader = NULL;
 482         }
 483
 484         free(shader->tokens);
 485         r600_pipe_shader_destroy(ctx, shader);
 486         free(shader);
 487 }
 488
 489 void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
 490 {
 491         struct r600_context *rctx = (struct r600_context *)ctx;
 492         struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
 493
 494         if (rctx->vs_shader == shader) {
 495                 rctx->vs_shader = NULL;
 496         }
 497
 498         free(shader->tokens);
 499         r600_pipe_shader_destroy(ctx, shader);
 500         free(shader);
 501 }
 502
 503 static void r600_update_alpha_ref(struct r600_context *rctx)
 504 {
 505         unsigned alpha_ref;
 506         struct r600_pipe_state rstate;
 507
 508         alpha_ref = rctx->alpha_ref;
 509         rstate.nregs = 0;
 510         if (rctx->export_16bpc)
 511                 alpha_ref &= ~0x1FFF;
 512         r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref, NULL, 0);
 513
 514         r600_context_pipe_state_set(rctx, &rstate);
 515         rctx->alpha_ref_dirty = false;
 516 }
 517
 518 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 519                               struct pipe_resource *buffer)
 520 {
 521         struct r600_context *rctx = (struct r600_context *)ctx;
 522         struct r600_resource *rbuffer = r600_resource(buffer);
 523         struct r600_pipe_resource_state *rstate;
 524         uint64_t va_offset;
 525         uint32_t offset;
 526
 527         /* Note that the state tracker can unbind constant buffers by
 528          * passing NULL here.
 529          */
 530         if (buffer == NULL) {
 531                 return;
 532         }
 533
 534         r600_inval_shader_cache(rctx);
 535
 536         r600_upload_const_buffer(rctx, &rbuffer, &offset);
 537         va_offset = r600_resource_va(ctx->screen, (void*)rbuffer);
 538         va_offset += offset;
 539         va_offset >>= 8;
 540
 541         switch (shader) {
 542         case PIPE_SHADER_VERTEX:
 543                 rctx->vs_const_buffer.nregs = 0;
 544                 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
 545                                         R_028180_ALU_CONST_BUFFER_SIZE_VS_0 + index * 4,
 546                                         ALIGN_DIVUP(buffer->width0 >> 4, 16),
 547                                         NULL, 0);
 548                 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
 549                                         R_028980_ALU_CONST_CACHE_VS_0 + index * 4,
 550                                         va_offset, rbuffer, RADEON_USAGE_READ);
 551                 r600_context_pipe_state_set(rctx, &rctx->vs_const_buffer);
 552
 553                 rstate = &rctx->vs_const_buffer_resource[index];
 554                 if (!rstate->id) {
 555                         if (rctx->chip_class >= EVERGREEN) {
 556                                 evergreen_pipe_init_buffer_resource(rctx, rstate);
 557                         } else {
 558                                 r600_pipe_init_buffer_resource(rctx, rstate);
 559                         }
 560                 }
 561
 562                 if (rctx->chip_class >= EVERGREEN) {
 563                         evergreen_pipe_mod_buffer_resource(ctx, rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 564                         evergreen_context_pipe_state_set_vs_resource(rctx, rstate, index);
 565                 } else {
 566                         r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 567                         r600_context_pipe_state_set_vs_resource(rctx, rstate, index);
 568                 }
 569                 break;
 570         case PIPE_SHADER_FRAGMENT:
 571                 rctx->ps_const_buffer.nregs = 0;
 572                 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
 573                                         R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
 574                                         ALIGN_DIVUP(buffer->width0 >> 4, 16),
 575                                         NULL, 0);
 576                 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
 577                                         R_028940_ALU_CONST_CACHE_PS_0,
 578                                         va_offset, rbuffer, RADEON_USAGE_READ);
 579                 r600_context_pipe_state_set(rctx, &rctx->ps_const_buffer);
 580
 581                 rstate = &rctx->ps_const_buffer_resource[index];
 582                 if (!rstate->id) {
 583                         if (rctx->chip_class >= EVERGREEN) {
 584                                 evergreen_pipe_init_buffer_resource(rctx, rstate);
 585                         } else {
 586                                 r600_pipe_init_buffer_resource(rctx, rstate);
 587                         }
 588                 }
 589                 if (rctx->chip_class >= EVERGREEN) {
 590                         evergreen_pipe_mod_buffer_resource(ctx, rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 591                         evergreen_context_pipe_state_set_ps_resource(rctx, rstate, index);
 592                 } else {
 593                         r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 594                         r600_context_pipe_state_set_ps_resource(rctx, rstate, index);
 595                 }
 596                 break;
 597         default:
 598                 R600_ERR("unsupported %d\n", shader);
 599                 return;
 600         }
 601
 602         if (buffer != &rbuffer->b.b.b)
 603                 pipe_resource_reference((struct pipe_resource**)&rbuffer, NULL);
 604 }
 605
 606 struct pipe_stream_output_target *
 607 r600_create_so_target(struct pipe_context *ctx,
 608                       struct pipe_resource *buffer,
 609                       unsigned buffer_offset,
 610                       unsigned buffer_size)
 611 {
 612         struct r600_context *rctx = (struct r600_context *)ctx;
 613         struct r600_so_target *t;
 614         void *ptr;
 615
 616         t = CALLOC_STRUCT(r600_so_target);
 617         if (!t) {
 618                 return NULL;
 619         }
 620
 621         t->b.reference.count = 1;
 622         t->b.context = ctx;
 623         pipe_resource_reference(&t->b.buffer, buffer);
 624         t->b.buffer_offset = buffer_offset;
 625         t->b.buffer_size = buffer_size;
 626
 627         t->filled_size = (struct r600_resource*)
 628                 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4);
 629         ptr = rctx->ws->buffer_map(t->filled_size->buf, rctx->cs, PIPE_TRANSFER_WRITE);
 630         memset(ptr, 0, t->filled_size->buf->size);
 631         rctx->ws->buffer_unmap(t->filled_size->buf);
 632
 633         return &t->b;
 634 }
 635
 636 void r600_so_target_destroy(struct pipe_context *ctx,
 637                             struct pipe_stream_output_target *target)
 638 {
 639         struct r600_so_target *t = (struct r600_so_target*)target;
 640         pipe_resource_reference(&t->b.buffer, NULL);
 641         pipe_resource_reference((struct pipe_resource**)&t->filled_size, NULL);
 642         FREE(t);
 643 }
 644
 645 void r600_set_so_targets(struct pipe_context *ctx,
 646                          unsigned num_targets,
 647                          struct pipe_stream_output_target **targets,
 648                          unsigned append_bitmask)
 649 {
 650         struct r600_context *rctx = (struct r600_context *)ctx;
 651         unsigned i;
 652
 653         /* Stop streamout. */
 654         if (rctx->num_so_targets) {
 655                 r600_context_streamout_end(rctx);
 656         }
 657
 658         /* Set the new targets. */
 659         for (i = 0; i < num_targets; i++) {
 660                 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]);
 661         }
 662         for (; i < rctx->num_so_targets; i++) {
 663                 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL);
 664         }
 665
 666         rctx->num_so_targets = num_targets;
 667         rctx->streamout_start = num_targets != 0;
 668         rctx->streamout_append_bitmask = append_bitmask;
 669 }
 670
 671 static void r600_vertex_buffer_update(struct r600_context *rctx)
 672 {
 673         struct r600_pipe_resource_state *rstate;
 674         struct r600_resource *rbuffer;
 675         struct pipe_vertex_buffer *vertex_buffer;
 676         unsigned i, count, offset;
 677
 678         r600_inval_vertex_cache(rctx);
 679
 680         if (rctx->vertex_elements->vbuffer_need_offset) {
 681                 /* one resource per vertex elements */
 682                 count = rctx->vertex_elements->count;
 683         } else {
 684                 /* bind vertex buffer once */
 685                 count = rctx->vbuf_mgr->nr_real_vertex_buffers;
 686         }
 687
 688         for (i = 0 ; i < count; i++) {
 689                 rstate = &rctx->fs_resource[i];
 690
 691                 if (rctx->vertex_elements->vbuffer_need_offset) {
 692                         /* one resource per vertex elements */
 693                         unsigned vbuffer_index;
 694                         vbuffer_index = rctx->vertex_elements->elements[i].vertex_buffer_index;
 695                         vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[vbuffer_index];
 696                         rbuffer = (struct r600_resource*)vertex_buffer->buffer;
 697                         offset = rctx->vertex_elements->vbuffer_offset[i];
 698                 } else {
 699                         /* bind vertex buffer once */
 700                         vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[i];
 701                         rbuffer = (struct r600_resource*)vertex_buffer->buffer;
 702                         offset = 0;
 703                 }
 704                 if (vertex_buffer == NULL || rbuffer == NULL)
 705                         continue;
 706                 offset += vertex_buffer->buffer_offset;
 707
 708                 if (!rstate->id) {
 709                         if (rctx->chip_class >= EVERGREEN) {
 710                                 evergreen_pipe_init_buffer_resource(rctx, rstate);
 711                         } else {
 712                                 r600_pipe_init_buffer_resource(rctx, rstate);
 713                         }
 714                 }
 715
 716                 if (rctx->chip_class >= EVERGREEN) {
 717                         evergreen_pipe_mod_buffer_resource(&rctx->context, rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ);
 718                         evergreen_context_pipe_state_set_fs_resource(rctx, rstate, i);
 719                 } else {
 720                         r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ);
 721                         r600_context_pipe_state_set_fs_resource(rctx, rstate, i);
 722                 }
 723         }
 724 }
 725
 726 static int r600_shader_rebuild(struct pipe_context * ctx, struct r600_pipe_shader * shader)
 727 {
 728         struct r600_context *rctx = (struct r600_context *)ctx;
 729         int r;
 730
 731         r600_pipe_shader_destroy(ctx, shader);
 732         r = r600_pipe_shader_create(ctx, shader);
 733         if (r) {
 734                 return r;
 735         }
 736         r600_context_pipe_state_set(rctx, &shader->rstate);
 737
 738         return 0;
 739 }
 740
 741 static void r600_update_derived_state(struct r600_context *rctx)
 742 {
 743         struct pipe_context * ctx = (struct pipe_context*)rctx;
 744         struct r600_pipe_state rstate;
 745
 746         rstate.nregs = 0;
 747
 748         if (rstate.nregs)
 749                 r600_context_pipe_state_set(rctx, &rstate);
 750
 751         if (!rctx->blitter->running) {
 752                 if (rctx->have_depth_fb || rctx->have_depth_texture)
 753                         r600_flush_depth_textures(rctx);
 754         }
 755
 756         if (rctx->chip_class < EVERGREEN) {
 757                 r600_update_sampler_states(rctx);
 758         }
 759
 760         if ((rctx->ps_shader->shader.two_side != rctx->two_side) ||
 761             ((rctx->chip_class >= EVERGREEN) && rctx->ps_shader->shader.fs_write_all &&
 762              (rctx->ps_shader->shader.nr_cbufs != rctx->nr_cbufs))) {
 763                 r600_shader_rebuild(&rctx->context, rctx->ps_shader);
 764         }
 765
 766         if (rctx->alpha_ref_dirty) {
 767                 r600_update_alpha_ref(rctx);
 768         }
 769
 770         if (rctx->ps_shader && ((rctx->sprite_coord_enable &&
 771                 (rctx->ps_shader->sprite_coord_enable != rctx->sprite_coord_enable)) ||
 772                 (rctx->rasterizer && rctx->rasterizer->flatshade != rctx->ps_shader->flatshade))) {
 773
 774                 if (rctx->chip_class >= EVERGREEN)
 775                         evergreen_pipe_shader_ps(ctx, rctx->ps_shader);
 776                 else
 777                         r600_pipe_shader_ps(ctx, rctx->ps_shader);
 778
 779                 r600_context_pipe_state_set(rctx, &rctx->ps_shader->rstate);
 780         }
 781
 782 }
 783
 784 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
 785 {
 786         struct r600_context *rctx = (struct r600_context *)ctx;
 787         struct pipe_draw_info info = *dinfo;
 788         struct pipe_index_buffer ib = {};
 789         unsigned prim, mask, ls_mask = 0;
 790         struct r600_block *dirty_block = NULL, *next_block = NULL;
 791         struct r600_atom *state = NULL, *next_state = NULL;
 792         struct radeon_winsys_cs *cs = rctx->cs;
 793         uint64_t va;
 794
 795         if ((!info.count && (info.indexed || !info.count_from_stream_output)) ||
 796             (info.indexed && !rctx->vbuf_mgr->index_buffer.buffer) ||
 797             !r600_conv_pipe_prim(info.mode, &prim)) {
 798                 return;
 799         }
 800
 801         if (!rctx->ps_shader || !rctx->vs_shader)
 802                 return;
 803
 804         r600_update_derived_state(rctx);
 805
 806         u_vbuf_draw_begin(rctx->vbuf_mgr, &info);
 807         r600_vertex_buffer_update(rctx);
 808
 809         if (info.indexed) {
 810                 /* Initialize the index buffer struct. */
 811                 pipe_resource_reference(&ib.buffer, rctx->vbuf_mgr->index_buffer.buffer);
 812                 ib.index_size = rctx->vbuf_mgr->index_buffer.index_size;
 813                 ib.offset = rctx->vbuf_mgr->index_buffer.offset + info.start * ib.index_size;
 814
 815                 /* Translate or upload, if needed. */
 816                 r600_translate_index_buffer(rctx, &ib, info.count);
 817
 818                 if (u_vbuf_resource(ib.buffer)->user_ptr) {
 819                         r600_upload_index_buffer(rctx, &ib, info.count);
 820                 }
 821         } else {
 822                 info.index_bias = info.start;
 823                 if (info.count_from_stream_output) {
 824                         r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info.count_from_stream_output);
 825                 }
 826         }
 827
 828         mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
 829
 830         if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
 831                 rctx->vgt.id = R600_PIPE_STATE_VGT;
 832                 rctx->vgt.nregs = 0;
 833                 r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, NULL, 0);
 834                 r600_pipe_state_add_reg(&rctx->vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, NULL, 0);
 835                 r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias, NULL, 0);
 836                 r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index, NULL, 0);
 837                 r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart, NULL, 0);
 838                 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance, NULL, 0);
 839                 r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0, NULL, 0);
 840                 if (rctx->chip_class <= R700)
 841                         r600_pipe_state_add_reg(&rctx->vgt, R_028808_CB_COLOR_CONTROL, rctx->cb_color_control, NULL, 0);
 842                 r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0, NULL, 0);
 843                 r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0, NULL, 0);
 844         }
 845
 846         rctx->vgt.nregs = 0;
 847         r600_pipe_state_mod_reg(&rctx->vgt, prim);
 848         r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_target_mask & mask);
 849         r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
 850         r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
 851         r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart);
 852         r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance);
 853
 854         if (prim == V_008958_DI_PT_LINELIST)
 855                 ls_mask = 1;
 856         else if (prim == V_008958_DI_PT_LINESTRIP)
 857                 ls_mask = 2;
 858         r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask) | rctx->pa_sc_line_stipple);
 859         if (rctx->chip_class <= R700)
 860                 r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_color_control);
 861         r600_pipe_state_mod_reg(&rctx->vgt,
 862                                 rctx->vs_shader->pa_cl_vs_out_cntl |
 863                                 (rctx->rasterizer->clip_plane_enable & rctx->vs_shader->shader.clip_dist_write));
 864         r600_pipe_state_mod_reg(&rctx->vgt,
 865                                 rctx->pa_cl_clip_cntl |
 866                                 (rctx->vs_shader->shader.clip_dist_write ||
 867                                  rctx->vs_shader->shader.vs_prohibit_ucps ?
 868                                  0 : rctx->rasterizer->clip_plane_enable & 0x3F));
 869
 870         r600_context_pipe_state_set(rctx, &rctx->vgt);
 871
 872         /* Emit states (the function expects that we emit at most 17 dwords here). */
 873         r600_need_cs_space(rctx, 0, TRUE);
 874
 875         LIST_FOR_EACH_ENTRY_SAFE(state, next_state, &rctx->dirty_states, head) {
 876                 r600_emit_atom(rctx, state);
 877         }
 878         LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) {
 879                 r600_context_block_emit_dirty(rctx, dirty_block);
 880         }
 881         LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->resource_dirty,list) {
 882                 r600_context_block_resource_emit_dirty(rctx, dirty_block);
 883         }
 884         rctx->pm4_dirty_cdwords = 0;
 885
 886         /* Enable stream out if needed. */
 887         if (rctx->streamout_start) {
 888                 r600_context_streamout_begin(rctx);
 889                 rctx->streamout_start = FALSE;
 890         }
 891
 892         /* draw packet */
 893         cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->predicate_drawing);
 894         cs->buf[cs->cdw++] = ib.index_size == 4 ?
 895                                 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
 896                                 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
 897         cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->predicate_drawing);
 898         cs->buf[cs->cdw++] = info.instance_count;
 899         if (info.indexed) {
 900                 va = r600_resource_va(ctx->screen, ib.buffer);
 901                 va += ib.offset;
 902                 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->predicate_drawing);
 903                 cs->buf[cs->cdw++] = va;
 904                 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
 905                 cs->buf[cs->cdw++] = info.count;
 906                 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
 907                 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->predicate_drawing);
 908                 cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
 909         } else {
 910                 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->predicate_drawing);
 911                 cs->buf[cs->cdw++] = info.count;
 912                 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
 913                                         (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
 914         }
 915
 916         rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING;
 917
 918         if (rctx->framebuffer.zsbuf)
 919         {
 920                 struct pipe_resource *tex = rctx->framebuffer.zsbuf->texture;
 921                 ((struct r600_resource_texture *)tex)->dirty_db = TRUE;
 922         }
 923
 924         pipe_resource_reference(&ib.buffer, NULL);
 925         u_vbuf_draw_end(rctx->vbuf_mgr);
 926 }
 927
 928 void _r600_pipe_state_add_reg(struct r600_context *ctx,
 929                               struct r600_pipe_state *state,
 930                               uint32_t offset, uint32_t value,
 931                               uint32_t range_id, uint32_t block_id,
 932                               struct r600_resource *bo,
 933                               enum radeon_bo_usage usage)
 934 {
 935         struct r600_range *range;
 936         struct r600_block *block;
 937
 938         if (bo) assert(usage);
 939
 940         range = &ctx->range[range_id];
 941         block = range->blocks[block_id];
 942         state->regs[state->nregs].block = block;
 943         state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
 944
 945         state->regs[state->nregs].value = value;
 946         state->regs[state->nregs].bo = bo;
 947         state->regs[state->nregs].bo_usage = usage;
 948
 949         state->nregs++;
 950         assert(state->nregs < R600_BLOCK_MAX_REG);
 951 }
 952
 953 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
 954                                      uint32_t offset, uint32_t value,
 955                                      struct r600_resource *bo,
 956                                      enum radeon_bo_usage usage)
 957 {
 958         if (bo) assert(usage);
 959
 960         state->regs[state->nregs].id = offset;
 961         state->regs[state->nregs].block = NULL;
 962         state->regs[state->nregs].value = value;
 963         state->regs[state->nregs].bo = bo;
 964         state->regs[state->nregs].bo_usage = usage;
 965
 966         state->nregs++;
 967         assert(state->nregs < R600_BLOCK_MAX_REG);
 968 }
 969
 970 uint32_t r600_translate_stencil_op(int s_op)
 971 {
 972         switch (s_op) {
 973         case PIPE_STENCIL_OP_KEEP:
 974                 return V_028800_STENCIL_KEEP;
 975         case PIPE_STENCIL_OP_ZERO:
 976                 return V_028800_STENCIL_ZERO;
 977         case PIPE_STENCIL_OP_REPLACE:
 978                 return V_028800_STENCIL_REPLACE;
 979         case PIPE_STENCIL_OP_INCR:
 980                 return V_028800_STENCIL_INCR;
 981         case PIPE_STENCIL_OP_DECR:
 982                 return V_028800_STENCIL_DECR;
 983         case PIPE_STENCIL_OP_INCR_WRAP:
 984                 return V_028800_STENCIL_INCR_WRAP;
 985         case PIPE_STENCIL_OP_DECR_WRAP:
 986                 return V_028800_STENCIL_DECR_WRAP;
 987         case PIPE_STENCIL_OP_INVERT:
 988                 return V_028800_STENCIL_INVERT;
 989         default:
 990                 R600_ERR("Unknown stencil op %d", s_op);
 991                 assert(0);
 992                 break;
 993         }
 994         return 0;
 995 }
 996
 997 uint32_t r600_translate_fill(uint32_t func)
 998 {
 999         switch(func) {
1000         case PIPE_POLYGON_MODE_FILL:
1001                 return 2;
1002         case PIPE_POLYGON_MODE_LINE:
1003                 return 1;
1004         case PIPE_POLYGON_MODE_POINT:
1005                 return 0;
1006         default:
1007                 assert(0);
1008                 return 0;
1009         }
1010 }
1011
1012 unsigned r600_tex_wrap(unsigned wrap)
1013 {
1014         switch (wrap) {
1015         default:
1016         case PIPE_TEX_WRAP_REPEAT:
1017                 return V_03C000_SQ_TEX_WRAP;
1018         case PIPE_TEX_WRAP_CLAMP:
1019                 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1020         case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1021                 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1022         case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1023                 return V_03C000_SQ_TEX_CLAMP_BORDER;
1024         case PIPE_TEX_WRAP_MIRROR_REPEAT:
1025                 return V_03C000_SQ_TEX_MIRROR;
1026         case PIPE_TEX_WRAP_MIRROR_CLAMP:
1027                 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1028         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1029                 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1030         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1031                 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1032         }
1033 }
1034
1035 unsigned r600_tex_filter(unsigned filter)
1036 {
1037         switch (filter) {
1038         default:
1039         case PIPE_TEX_FILTER_NEAREST:
1040                 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1041         case PIPE_TEX_FILTER_LINEAR:
1042                 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1043         }
1044 }
1045
1046 unsigned r600_tex_mipfilter(unsigned filter)
1047 {
1048         switch (filter) {
1049         case PIPE_TEX_MIPFILTER_NEAREST:
1050                 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1051         case PIPE_TEX_MIPFILTER_LINEAR:
1052                 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1053         default:
1054         case PIPE_TEX_MIPFILTER_NONE:
1055                 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1056         }
1057 }
1058
1059 unsigned r600_tex_compare(unsigned compare)
1060 {
1061         switch (compare) {
1062         default:
1063         case PIPE_FUNC_NEVER:
1064                 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1065         case PIPE_FUNC_LESS:
1066                 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1067         case PIPE_FUNC_EQUAL:
1068                 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1069         case PIPE_FUNC_LEQUAL:
1070                 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1071         case PIPE_FUNC_GREATER:
1072                 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1073         case PIPE_FUNC_NOTEQUAL:
1074                 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1075         case PIPE_FUNC_GEQUAL:
1076                 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1077         case PIPE_FUNC_ALWAYS:
1078                 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1079         }
1080 }