2 * Copyright 2010 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
27 #include "r600_formats.h"
28 #include "r600_shader.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_index_modify.h"
33 #include "util/u_memory.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_math.h"
36 #include "tgsi/tgsi_parse.h"
37 #include "tgsi/tgsi_scan.h"
38 #include "tgsi/tgsi_ureg.h"
40 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
)
43 cb
->buf
= CALLOC(1, 4 * num_dw
);
44 cb
->max_num_dw
= num_dw
;
47 void r600_release_command_buffer(struct r600_command_buffer
*cb
)
52 void r600_add_atom(struct r600_context
*rctx
,
53 struct r600_atom
*atom
,
56 assert(id
< R600_NUM_ATOMS
);
57 assert(rctx
->atoms
[id
] == NULL
);
58 rctx
->atoms
[id
] = atom
;
62 void r600_init_atom(struct r600_context
*rctx
,
63 struct r600_atom
*atom
,
65 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
68 atom
->emit
= (void*)emit
;
69 atom
->num_dw
= num_dw
;
70 r600_add_atom(rctx
, atom
, id
);
73 void r600_emit_cso_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
75 r600_emit_command_buffer(rctx
->b
.gfx
.cs
, ((struct r600_cso_state
*)atom
)->cb
);
78 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
80 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
81 struct r600_alphatest_state
*a
= (struct r600_alphatest_state
*)atom
;
82 unsigned alpha_ref
= a
->sx_alpha_ref
;
84 if (rctx
->b
.chip_class
>= EVERGREEN
&& a
->cb0_export_16bpc
) {
88 radeon_set_context_reg(cs
, R_028410_SX_ALPHA_TEST_CONTROL
,
89 a
->sx_alpha_test_control
|
90 S_028410_ALPHA_TEST_BYPASS(a
->bypass
));
91 radeon_set_context_reg(cs
, R_028438_SX_ALPHA_REF
, alpha_ref
);
94 static void r600_texture_barrier(struct pipe_context
*ctx
)
96 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
98 rctx
->b
.flags
|= R600_CONTEXT_INV_TEX_CACHE
|
99 R600_CONTEXT_FLUSH_AND_INV_CB
|
100 R600_CONTEXT_FLUSH_AND_INV
|
101 R600_CONTEXT_WAIT_3D_IDLE
;
104 static unsigned r600_conv_pipe_prim(unsigned prim
)
106 static const unsigned prim_conv
[] = {
107 [PIPE_PRIM_POINTS
] = V_008958_DI_PT_POINTLIST
,
108 [PIPE_PRIM_LINES
] = V_008958_DI_PT_LINELIST
,
109 [PIPE_PRIM_LINE_LOOP
] = V_008958_DI_PT_LINELOOP
,
110 [PIPE_PRIM_LINE_STRIP
] = V_008958_DI_PT_LINESTRIP
,
111 [PIPE_PRIM_TRIANGLES
] = V_008958_DI_PT_TRILIST
,
112 [PIPE_PRIM_TRIANGLE_STRIP
] = V_008958_DI_PT_TRISTRIP
,
113 [PIPE_PRIM_TRIANGLE_FAN
] = V_008958_DI_PT_TRIFAN
,
114 [PIPE_PRIM_QUADS
] = V_008958_DI_PT_QUADLIST
,
115 [PIPE_PRIM_QUAD_STRIP
] = V_008958_DI_PT_QUADSTRIP
,
116 [PIPE_PRIM_POLYGON
] = V_008958_DI_PT_POLYGON
,
117 [PIPE_PRIM_LINES_ADJACENCY
] = V_008958_DI_PT_LINELIST_ADJ
,
118 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_008958_DI_PT_LINESTRIP_ADJ
,
119 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_008958_DI_PT_TRILIST_ADJ
,
120 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_008958_DI_PT_TRISTRIP_ADJ
,
121 [PIPE_PRIM_PATCHES
] = V_008958_DI_PT_PATCH
,
122 [R600_PRIM_RECTANGLE_LIST
] = V_008958_DI_PT_RECTLIST
124 assert(prim
< Elements(prim_conv
));
125 return prim_conv
[prim
];
128 unsigned r600_conv_prim_to_gs_out(unsigned mode
)
130 static const int prim_conv
[] = {
131 [PIPE_PRIM_POINTS
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
132 [PIPE_PRIM_LINES
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
133 [PIPE_PRIM_LINE_LOOP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
134 [PIPE_PRIM_LINE_STRIP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
135 [PIPE_PRIM_TRIANGLES
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
136 [PIPE_PRIM_TRIANGLE_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
137 [PIPE_PRIM_TRIANGLE_FAN
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
138 [PIPE_PRIM_QUADS
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
139 [PIPE_PRIM_QUAD_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
140 [PIPE_PRIM_POLYGON
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
141 [PIPE_PRIM_LINES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
142 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
143 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
144 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
145 [PIPE_PRIM_PATCHES
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
146 [R600_PRIM_RECTANGLE_LIST
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
148 assert(mode
< Elements(prim_conv
));
150 return prim_conv
[mode
];
153 /* common state between evergreen and r600 */
155 static void r600_bind_blend_state_internal(struct r600_context
*rctx
,
156 struct r600_blend_state
*blend
, bool blend_disable
)
158 unsigned color_control
;
159 bool update_cb
= false;
161 rctx
->alpha_to_one
= blend
->alpha_to_one
;
162 rctx
->dual_src_blend
= blend
->dual_src_blend
;
164 if (!blend_disable
) {
165 r600_set_cso_state_with_cb(rctx
, &rctx
->blend_state
, blend
, &blend
->buffer
);
166 color_control
= blend
->cb_color_control
;
168 /* Blending is disabled. */
169 r600_set_cso_state_with_cb(rctx
, &rctx
->blend_state
, blend
, &blend
->buffer_no_blend
);
170 color_control
= blend
->cb_color_control_no_blend
;
173 /* Update derived states. */
174 if (rctx
->cb_misc_state
.blend_colormask
!= blend
->cb_target_mask
) {
175 rctx
->cb_misc_state
.blend_colormask
= blend
->cb_target_mask
;
178 if (rctx
->b
.chip_class
<= R700
&&
179 rctx
->cb_misc_state
.cb_color_control
!= color_control
) {
180 rctx
->cb_misc_state
.cb_color_control
= color_control
;
183 if (rctx
->cb_misc_state
.dual_src_blend
!= blend
->dual_src_blend
) {
184 rctx
->cb_misc_state
.dual_src_blend
= blend
->dual_src_blend
;
188 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
192 static void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
)
194 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
195 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
198 r600_set_cso_state_with_cb(rctx
, &rctx
->blend_state
, NULL
, NULL
);
202 r600_bind_blend_state_internal(rctx
, blend
, rctx
->force_blend_disable
);
205 static void r600_set_blend_color(struct pipe_context
*ctx
,
206 const struct pipe_blend_color
*state
)
208 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
210 rctx
->blend_color
.state
= *state
;
211 r600_mark_atom_dirty(rctx
, &rctx
->blend_color
.atom
);
214 void r600_emit_blend_color(struct r600_context
*rctx
, struct r600_atom
*atom
)
216 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
217 struct pipe_blend_color
*state
= &rctx
->blend_color
.state
;
219 radeon_set_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
220 radeon_emit(cs
, fui(state
->color
[0])); /* R_028414_CB_BLEND_RED */
221 radeon_emit(cs
, fui(state
->color
[1])); /* R_028418_CB_BLEND_GREEN */
222 radeon_emit(cs
, fui(state
->color
[2])); /* R_02841C_CB_BLEND_BLUE */
223 radeon_emit(cs
, fui(state
->color
[3])); /* R_028420_CB_BLEND_ALPHA */
226 void r600_emit_vgt_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
228 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
229 struct r600_vgt_state
*a
= (struct r600_vgt_state
*)atom
;
231 radeon_set_context_reg(cs
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, a
->vgt_multi_prim_ib_reset_en
);
232 radeon_set_context_reg_seq(cs
, R_028408_VGT_INDX_OFFSET
, 2);
233 radeon_emit(cs
, a
->vgt_indx_offset
); /* R_028408_VGT_INDX_OFFSET */
234 radeon_emit(cs
, a
->vgt_multi_prim_ib_reset_indx
); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
235 if (a
->last_draw_was_indirect
) {
236 a
->last_draw_was_indirect
= false;
237 radeon_set_ctl_const(cs
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
241 static void r600_set_clip_state(struct pipe_context
*ctx
,
242 const struct pipe_clip_state
*state
)
244 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
246 rctx
->clip_state
.state
= *state
;
247 r600_mark_atom_dirty(rctx
, &rctx
->clip_state
.atom
);
248 rctx
->driver_consts
[PIPE_SHADER_VERTEX
].vs_ucp_dirty
= true;
251 static void r600_set_stencil_ref(struct pipe_context
*ctx
,
252 const struct r600_stencil_ref
*state
)
254 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
256 rctx
->stencil_ref
.state
= *state
;
257 r600_mark_atom_dirty(rctx
, &rctx
->stencil_ref
.atom
);
260 void r600_emit_stencil_ref(struct r600_context
*rctx
, struct r600_atom
*atom
)
262 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
263 struct r600_stencil_ref_state
*a
= (struct r600_stencil_ref_state
*)atom
;
265 radeon_set_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
266 radeon_emit(cs
, /* R_028430_DB_STENCILREFMASK */
267 S_028430_STENCILREF(a
->state
.ref_value
[0]) |
268 S_028430_STENCILMASK(a
->state
.valuemask
[0]) |
269 S_028430_STENCILWRITEMASK(a
->state
.writemask
[0]));
270 radeon_emit(cs
, /* R_028434_DB_STENCILREFMASK_BF */
271 S_028434_STENCILREF_BF(a
->state
.ref_value
[1]) |
272 S_028434_STENCILMASK_BF(a
->state
.valuemask
[1]) |
273 S_028434_STENCILWRITEMASK_BF(a
->state
.writemask
[1]));
276 static void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
277 const struct pipe_stencil_ref
*state
)
279 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
280 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)rctx
->dsa_state
.cso
;
281 struct r600_stencil_ref ref
;
283 rctx
->stencil_ref
.pipe_state
= *state
;
288 ref
.ref_value
[0] = state
->ref_value
[0];
289 ref
.ref_value
[1] = state
->ref_value
[1];
290 ref
.valuemask
[0] = dsa
->valuemask
[0];
291 ref
.valuemask
[1] = dsa
->valuemask
[1];
292 ref
.writemask
[0] = dsa
->writemask
[0];
293 ref
.writemask
[1] = dsa
->writemask
[1];
295 r600_set_stencil_ref(ctx
, &ref
);
298 static void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
300 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
301 struct r600_dsa_state
*dsa
= state
;
302 struct r600_stencil_ref ref
;
305 r600_set_cso_state_with_cb(rctx
, &rctx
->dsa_state
, NULL
, NULL
);
309 r600_set_cso_state_with_cb(rctx
, &rctx
->dsa_state
, dsa
, &dsa
->buffer
);
311 ref
.ref_value
[0] = rctx
->stencil_ref
.pipe_state
.ref_value
[0];
312 ref
.ref_value
[1] = rctx
->stencil_ref
.pipe_state
.ref_value
[1];
313 ref
.valuemask
[0] = dsa
->valuemask
[0];
314 ref
.valuemask
[1] = dsa
->valuemask
[1];
315 ref
.writemask
[0] = dsa
->writemask
[0];
316 ref
.writemask
[1] = dsa
->writemask
[1];
317 if (rctx
->zwritemask
!= dsa
->zwritemask
) {
318 rctx
->zwritemask
= dsa
->zwritemask
;
319 if (rctx
->b
.chip_class
>= EVERGREEN
) {
320 /* work around some issue when not writing to zbuffer
321 * we are having lockup on evergreen so do not enable
322 * hyperz when not writing zbuffer
324 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
328 r600_set_stencil_ref(ctx
, &ref
);
330 /* Update alphatest state. */
331 if (rctx
->alphatest_state
.sx_alpha_test_control
!= dsa
->sx_alpha_test_control
||
332 rctx
->alphatest_state
.sx_alpha_ref
!= dsa
->alpha_ref
) {
333 rctx
->alphatest_state
.sx_alpha_test_control
= dsa
->sx_alpha_test_control
;
334 rctx
->alphatest_state
.sx_alpha_ref
= dsa
->alpha_ref
;
335 r600_mark_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
339 static void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
)
341 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
342 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
347 rctx
->rasterizer
= rs
;
349 r600_set_cso_state_with_cb(rctx
, &rctx
->rasterizer_state
, rs
, &rs
->buffer
);
351 if (rs
->offset_enable
&&
352 (rs
->offset_units
!= rctx
->poly_offset_state
.offset_units
||
353 rs
->offset_scale
!= rctx
->poly_offset_state
.offset_scale
)) {
354 rctx
->poly_offset_state
.offset_units
= rs
->offset_units
;
355 rctx
->poly_offset_state
.offset_scale
= rs
->offset_scale
;
356 r600_mark_atom_dirty(rctx
, &rctx
->poly_offset_state
.atom
);
359 /* Update clip_misc_state. */
360 if (rctx
->clip_misc_state
.pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
||
361 rctx
->clip_misc_state
.clip_plane_enable
!= rs
->clip_plane_enable
) {
362 rctx
->clip_misc_state
.pa_cl_clip_cntl
= rs
->pa_cl_clip_cntl
;
363 rctx
->clip_misc_state
.clip_plane_enable
= rs
->clip_plane_enable
;
364 r600_mark_atom_dirty(rctx
, &rctx
->clip_misc_state
.atom
);
367 /* Workaround for a missing scissor enable on r600. */
368 if (rctx
->b
.chip_class
== R600
&&
369 rs
->scissor_enable
!= rctx
->scissor
.enable
) {
370 rctx
->scissor
.enable
= rs
->scissor_enable
;
371 rctx
->scissor
.dirty_mask
= (1 << R600_MAX_VIEWPORTS
) - 1;
372 rctx
->scissor
.atom
.num_dw
= R600_MAX_VIEWPORTS
* 4;
373 r600_mark_atom_dirty(rctx
, &rctx
->scissor
.atom
);
376 /* Re-emit PA_SC_LINE_STIPPLE. */
377 rctx
->last_primitive_type
= -1;
380 static void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
)
382 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
384 r600_release_command_buffer(&rs
->buffer
);
388 static void r600_sampler_view_destroy(struct pipe_context
*ctx
,
389 struct pipe_sampler_view
*state
)
391 struct r600_pipe_sampler_view
*view
= (struct r600_pipe_sampler_view
*)state
;
393 if (view
->tex_resource
->gpu_address
&&
394 view
->tex_resource
->b
.b
.target
== PIPE_BUFFER
)
395 LIST_DELINIT(&view
->list
);
397 pipe_resource_reference(&state
->texture
, NULL
);
401 void r600_sampler_states_dirty(struct r600_context
*rctx
,
402 struct r600_sampler_states
*state
)
404 if (state
->dirty_mask
) {
405 if (state
->dirty_mask
& state
->has_bordercolor_mask
) {
406 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
409 util_bitcount(state
->dirty_mask
& state
->has_bordercolor_mask
) * 11 +
410 util_bitcount(state
->dirty_mask
& ~state
->has_bordercolor_mask
) * 5;
411 r600_mark_atom_dirty(rctx
, &state
->atom
);
415 static void r600_bind_sampler_states(struct pipe_context
*pipe
,
418 unsigned count
, void **states
)
420 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
421 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
422 struct r600_pipe_sampler_state
**rstates
= (struct r600_pipe_sampler_state
**)states
;
423 int seamless_cube_map
= -1;
425 /* This sets 1-bit for states with index >= count. */
426 uint32_t disable_mask
= ~((1ull << count
) - 1);
427 /* These are the new states set by this function. */
428 uint32_t new_mask
= 0;
430 assert(start
== 0); /* XXX fix below */
437 for (i
= 0; i
< count
; i
++) {
438 struct r600_pipe_sampler_state
*rstate
= rstates
[i
];
440 if (rstate
== dst
->states
.states
[i
]) {
445 if (rstate
->border_color_use
) {
446 dst
->states
.has_bordercolor_mask
|= 1 << i
;
448 dst
->states
.has_bordercolor_mask
&= ~(1 << i
);
450 seamless_cube_map
= rstate
->seamless_cube_map
;
454 disable_mask
|= 1 << i
;
458 memcpy(dst
->states
.states
, rstates
, sizeof(void*) * count
);
459 memset(dst
->states
.states
+ count
, 0, sizeof(void*) * (NUM_TEX_UNITS
- count
));
461 dst
->states
.enabled_mask
&= ~disable_mask
;
462 dst
->states
.dirty_mask
&= dst
->states
.enabled_mask
;
463 dst
->states
.enabled_mask
|= new_mask
;
464 dst
->states
.dirty_mask
|= new_mask
;
465 dst
->states
.has_bordercolor_mask
&= dst
->states
.enabled_mask
;
467 r600_sampler_states_dirty(rctx
, &dst
->states
);
469 /* Seamless cubemap state. */
470 if (rctx
->b
.chip_class
<= R700
&&
471 seamless_cube_map
!= -1 &&
472 seamless_cube_map
!= rctx
->seamless_cube_map
.enabled
) {
473 /* change in TA_CNTL_AUX need a pipeline flush */
474 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
475 rctx
->seamless_cube_map
.enabled
= seamless_cube_map
;
476 r600_mark_atom_dirty(rctx
, &rctx
->seamless_cube_map
.atom
);
480 static void r600_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
485 static void r600_delete_blend_state(struct pipe_context
*ctx
, void *state
)
487 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
488 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
490 if (rctx
->blend_state
.cso
== state
) {
491 ctx
->bind_blend_state(ctx
, NULL
);
494 r600_release_command_buffer(&blend
->buffer
);
495 r600_release_command_buffer(&blend
->buffer_no_blend
);
499 static void r600_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
501 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
502 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)state
;
504 if (rctx
->dsa_state
.cso
== state
) {
505 ctx
->bind_depth_stencil_alpha_state(ctx
, NULL
);
508 r600_release_command_buffer(&dsa
->buffer
);
512 static void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
514 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
516 r600_set_cso_state(rctx
, &rctx
->vertex_fetch_shader
, state
);
519 static void r600_delete_vertex_elements(struct pipe_context
*ctx
, void *state
)
521 struct r600_fetch_shader
*shader
= (struct r600_fetch_shader
*)state
;
522 pipe_resource_reference((struct pipe_resource
**)&shader
->buffer
, NULL
);
526 static void r600_set_index_buffer(struct pipe_context
*ctx
,
527 const struct pipe_index_buffer
*ib
)
529 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
532 pipe_resource_reference(&rctx
->index_buffer
.buffer
, ib
->buffer
);
533 memcpy(&rctx
->index_buffer
, ib
, sizeof(*ib
));
534 r600_context_add_resource_size(ctx
, ib
->buffer
);
536 pipe_resource_reference(&rctx
->index_buffer
.buffer
, NULL
);
540 void r600_vertex_buffers_dirty(struct r600_context
*rctx
)
542 if (rctx
->vertex_buffer_state
.dirty_mask
) {
543 rctx
->b
.flags
|= R600_CONTEXT_INV_VERTEX_CACHE
;
544 rctx
->vertex_buffer_state
.atom
.num_dw
= (rctx
->b
.chip_class
>= EVERGREEN
? 12 : 11) *
545 util_bitcount(rctx
->vertex_buffer_state
.dirty_mask
);
546 r600_mark_atom_dirty(rctx
, &rctx
->vertex_buffer_state
.atom
);
550 static void r600_set_vertex_buffers(struct pipe_context
*ctx
,
551 unsigned start_slot
, unsigned count
,
552 const struct pipe_vertex_buffer
*input
)
554 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
555 struct r600_vertexbuf_state
*state
= &rctx
->vertex_buffer_state
;
556 struct pipe_vertex_buffer
*vb
= state
->vb
+ start_slot
;
558 uint32_t disable_mask
= 0;
559 /* These are the new buffers set by this function. */
560 uint32_t new_buffer_mask
= 0;
562 /* Set vertex buffers. */
564 for (i
= 0; i
< count
; i
++) {
565 if (memcmp(&input
[i
], &vb
[i
], sizeof(struct pipe_vertex_buffer
))) {
566 if (input
[i
].buffer
) {
567 vb
[i
].stride
= input
[i
].stride
;
568 vb
[i
].buffer_offset
= input
[i
].buffer_offset
;
569 pipe_resource_reference(&vb
[i
].buffer
, input
[i
].buffer
);
570 new_buffer_mask
|= 1 << i
;
571 r600_context_add_resource_size(ctx
, input
[i
].buffer
);
573 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
574 disable_mask
|= 1 << i
;
579 for (i
= 0; i
< count
; i
++) {
580 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
582 disable_mask
= ((1ull << count
) - 1);
585 disable_mask
<<= start_slot
;
586 new_buffer_mask
<<= start_slot
;
588 rctx
->vertex_buffer_state
.enabled_mask
&= ~disable_mask
;
589 rctx
->vertex_buffer_state
.dirty_mask
&= rctx
->vertex_buffer_state
.enabled_mask
;
590 rctx
->vertex_buffer_state
.enabled_mask
|= new_buffer_mask
;
591 rctx
->vertex_buffer_state
.dirty_mask
|= new_buffer_mask
;
593 r600_vertex_buffers_dirty(rctx
);
596 void r600_sampler_views_dirty(struct r600_context
*rctx
,
597 struct r600_samplerview_state
*state
)
599 if (state
->dirty_mask
) {
600 rctx
->b
.flags
|= R600_CONTEXT_INV_TEX_CACHE
;
601 state
->atom
.num_dw
= (rctx
->b
.chip_class
>= EVERGREEN
? 14 : 13) *
602 util_bitcount(state
->dirty_mask
);
603 r600_mark_atom_dirty(rctx
, &state
->atom
);
607 static void r600_set_sampler_views(struct pipe_context
*pipe
, unsigned shader
,
608 unsigned start
, unsigned count
,
609 struct pipe_sampler_view
**views
)
611 struct r600_context
*rctx
= (struct r600_context
*) pipe
;
612 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
613 struct r600_pipe_sampler_view
**rviews
= (struct r600_pipe_sampler_view
**)views
;
614 uint32_t dirty_sampler_states_mask
= 0;
616 /* This sets 1-bit for textures with index >= count. */
617 uint32_t disable_mask
= ~((1ull << count
) - 1);
618 /* These are the new textures set by this function. */
619 uint32_t new_mask
= 0;
621 /* Set textures with index >= count to NULL. */
622 uint32_t remaining_mask
;
624 assert(start
== 0); /* XXX fix below */
631 remaining_mask
= dst
->views
.enabled_mask
& disable_mask
;
633 while (remaining_mask
) {
634 i
= u_bit_scan(&remaining_mask
);
635 assert(dst
->views
.views
[i
]);
637 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
640 for (i
= 0; i
< count
; i
++) {
641 if (rviews
[i
] == dst
->views
.views
[i
]) {
646 struct r600_texture
*rtex
=
647 (struct r600_texture
*)rviews
[i
]->base
.texture
;
649 if (rviews
[i
]->base
.texture
->target
!= PIPE_BUFFER
) {
650 if (rtex
->is_depth
&& !rtex
->is_flushing_texture
) {
651 dst
->views
.compressed_depthtex_mask
|= 1 << i
;
653 dst
->views
.compressed_depthtex_mask
&= ~(1 << i
);
656 /* Track compressed colorbuffers. */
657 if (rtex
->cmask
.size
) {
658 dst
->views
.compressed_colortex_mask
|= 1 << i
;
660 dst
->views
.compressed_colortex_mask
&= ~(1 << i
);
663 /* Changing from array to non-arrays textures and vice versa requires
664 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
665 if (rctx
->b
.chip_class
<= R700
&&
666 (dst
->states
.enabled_mask
& (1 << i
)) &&
667 (rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_1D_ARRAY
||
668 rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_2D_ARRAY
) != dst
->is_array_sampler
[i
]) {
669 dirty_sampler_states_mask
|= 1 << i
;
672 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], views
[i
]);
674 r600_context_add_resource_size(pipe
, views
[i
]->texture
);
676 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
677 disable_mask
|= 1 << i
;
681 dst
->views
.enabled_mask
&= ~disable_mask
;
682 dst
->views
.dirty_mask
&= dst
->views
.enabled_mask
;
683 dst
->views
.enabled_mask
|= new_mask
;
684 dst
->views
.dirty_mask
|= new_mask
;
685 dst
->views
.compressed_depthtex_mask
&= dst
->views
.enabled_mask
;
686 dst
->views
.compressed_colortex_mask
&= dst
->views
.enabled_mask
;
687 dst
->views
.dirty_buffer_constants
= TRUE
;
688 r600_sampler_views_dirty(rctx
, &dst
->views
);
690 if (dirty_sampler_states_mask
) {
691 dst
->states
.dirty_mask
|= dirty_sampler_states_mask
;
692 r600_sampler_states_dirty(rctx
, &dst
->states
);
696 static void r600_set_viewport_states(struct pipe_context
*ctx
,
698 unsigned num_viewports
,
699 const struct pipe_viewport_state
*state
)
701 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
702 struct r600_viewport_state
*rstate
= &rctx
->viewport
;
705 for (i
= start_slot
; i
< start_slot
+ num_viewports
; i
++)
706 rstate
->state
[i
] = state
[i
- start_slot
];
707 rstate
->dirty_mask
|= ((1 << num_viewports
) - 1) << start_slot
;
708 rstate
->atom
.num_dw
= util_bitcount(rstate
->dirty_mask
) * 8;
709 r600_mark_atom_dirty(rctx
, &rctx
->viewport
.atom
);
712 void r600_emit_viewport_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
714 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
715 struct r600_viewport_state
*rstate
= &rctx
->viewport
;
716 struct pipe_viewport_state
*state
;
720 dirty_mask
= rstate
->dirty_mask
;
721 while (dirty_mask
!= 0) {
722 i
= u_bit_scan(&dirty_mask
);
724 radeon_set_context_reg_seq(cs
, R_02843C_PA_CL_VPORT_XSCALE_0
+ offset
, 6);
725 state
= &rstate
->state
[i
];
726 radeon_emit(cs
, fui(state
->scale
[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
727 radeon_emit(cs
, fui(state
->translate
[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
728 radeon_emit(cs
, fui(state
->scale
[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
729 radeon_emit(cs
, fui(state
->translate
[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
730 radeon_emit(cs
, fui(state
->scale
[2])); /* R_02844C_PA_CL_VPORT_ZSCALE_0 */
731 radeon_emit(cs
, fui(state
->translate
[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
733 rstate
->dirty_mask
= 0;
734 rstate
->atom
.num_dw
= 0;
737 /* Compute the key for the hw shader variant */
738 static inline union r600_shader_key
r600_shader_selector_key(struct pipe_context
* ctx
,
739 struct r600_pipe_shader_selector
* sel
)
741 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
742 union r600_shader_key key
;
743 memset(&key
, 0, sizeof(key
));
746 case PIPE_SHADER_VERTEX
: {
747 key
.vs
.as_ls
= (rctx
->tes_shader
!= NULL
);
749 key
.vs
.as_es
= (rctx
->gs_shader
!= NULL
);
751 if (rctx
->ps_shader
->current
->shader
.gs_prim_id_input
&& !rctx
->gs_shader
) {
752 key
.vs
.as_gs_a
= true;
753 key
.vs
.prim_id_out
= rctx
->ps_shader
->current
->shader
.input
[rctx
->ps_shader
->current
->shader
.ps_prim_id_input
].spi_sid
;
757 case PIPE_SHADER_GEOMETRY
:
759 case PIPE_SHADER_FRAGMENT
: {
760 key
.ps
.color_two_side
= rctx
->rasterizer
&& rctx
->rasterizer
->two_side
;
761 key
.ps
.alpha_to_one
= rctx
->alpha_to_one
&&
762 rctx
->rasterizer
&& rctx
->rasterizer
->multisample_enable
&&
763 !rctx
->framebuffer
.cb0_is_integer
;
764 key
.ps
.nr_cbufs
= rctx
->framebuffer
.state
.nr_cbufs
;
765 /* Dual-source blending only makes sense with nr_cbufs == 1. */
766 if (key
.ps
.nr_cbufs
== 1 && rctx
->dual_src_blend
)
770 case PIPE_SHADER_TESS_EVAL
:
771 key
.tes
.as_es
= (rctx
->gs_shader
!= NULL
);
773 case PIPE_SHADER_TESS_CTRL
:
774 key
.tcs
.prim_mode
= rctx
->tes_shader
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
783 /* Select the hw shader variant depending on the current state.
784 * (*dirty) is set to 1 if current variant was changed */
785 static int r600_shader_select(struct pipe_context
*ctx
,
786 struct r600_pipe_shader_selector
* sel
,
789 union r600_shader_key key
;
790 struct r600_pipe_shader
* shader
= NULL
;
793 memset(&key
, 0, sizeof(key
));
794 key
= r600_shader_selector_key(ctx
, sel
);
796 /* Check if we don't need to change anything.
797 * This path is also used for most shaders that don't need multiple
798 * variants, it will cost just a computation of the key and this
800 if (likely(sel
->current
&& memcmp(&sel
->current
->key
, &key
, sizeof(key
)) == 0)) {
804 /* lookup if we have other variants in the list */
805 if (sel
->num_shaders
> 1) {
806 struct r600_pipe_shader
*p
= sel
->current
, *c
= p
->next_variant
;
808 while (c
&& memcmp(&c
->key
, &key
, sizeof(key
)) != 0) {
814 p
->next_variant
= c
->next_variant
;
819 if (unlikely(!shader
)) {
820 shader
= CALLOC(1, sizeof(struct r600_pipe_shader
));
821 shader
->selector
= sel
;
823 r
= r600_pipe_shader_create(ctx
, shader
, key
);
825 R600_ERR("Failed to build shader variant (type=%u) %d\n",
832 /* We don't know the value of nr_ps_max_color_exports until we built
833 * at least one variant, so we may need to recompute the key after
834 * building first variant. */
835 if (sel
->type
== PIPE_SHADER_FRAGMENT
&&
836 sel
->num_shaders
== 0) {
837 sel
->nr_ps_max_color_exports
= shader
->shader
.nr_ps_max_color_exports
;
838 key
= r600_shader_selector_key(ctx
, sel
);
841 memcpy(&shader
->key
, &key
, sizeof(key
));
848 shader
->next_variant
= sel
->current
;
849 sel
->current
= shader
;
854 static void *r600_create_shader_state(struct pipe_context
*ctx
,
855 const struct pipe_shader_state
*state
,
856 unsigned pipe_shader_type
)
858 struct r600_pipe_shader_selector
*sel
= CALLOC_STRUCT(r600_pipe_shader_selector
);
861 sel
->type
= pipe_shader_type
;
862 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
863 sel
->so
= state
->stream_output
;
864 tgsi_scan_shader(state
->tokens
, &sel
->info
);
866 switch (pipe_shader_type
) {
867 case PIPE_SHADER_GEOMETRY
:
868 sel
->gs_output_prim
=
869 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
870 sel
->gs_max_out_vertices
=
871 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
872 sel
->gs_num_invocations
=
873 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
875 case PIPE_SHADER_VERTEX
:
876 case PIPE_SHADER_TESS_CTRL
:
877 sel
->lds_patch_outputs_written_mask
= 0;
878 sel
->lds_outputs_written_mask
= 0;
880 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
881 unsigned name
= sel
->info
.output_semantic_name
[i
];
882 unsigned index
= sel
->info
.output_semantic_index
[i
];
885 case TGSI_SEMANTIC_TESSINNER
:
886 case TGSI_SEMANTIC_TESSOUTER
:
887 case TGSI_SEMANTIC_PATCH
:
888 sel
->lds_patch_outputs_written_mask
|=
889 1llu << r600_get_lds_unique_index(name
, index
);
892 sel
->lds_outputs_written_mask
|=
893 1llu << r600_get_lds_unique_index(name
, index
);
904 static void *r600_create_ps_state(struct pipe_context
*ctx
,
905 const struct pipe_shader_state
*state
)
907 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_FRAGMENT
);
910 static void *r600_create_vs_state(struct pipe_context
*ctx
,
911 const struct pipe_shader_state
*state
)
913 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_VERTEX
);
916 static void *r600_create_gs_state(struct pipe_context
*ctx
,
917 const struct pipe_shader_state
*state
)
919 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_GEOMETRY
);
922 static void *r600_create_tcs_state(struct pipe_context
*ctx
,
923 const struct pipe_shader_state
*state
)
925 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_TESS_CTRL
);
928 static void *r600_create_tes_state(struct pipe_context
*ctx
,
929 const struct pipe_shader_state
*state
)
931 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_TESS_EVAL
);
934 static void r600_bind_ps_state(struct pipe_context
*ctx
, void *state
)
936 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
939 state
= rctx
->dummy_pixel_shader
;
941 rctx
->ps_shader
= (struct r600_pipe_shader_selector
*)state
;
944 static void r600_bind_vs_state(struct pipe_context
*ctx
, void *state
)
946 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
951 rctx
->vs_shader
= (struct r600_pipe_shader_selector
*)state
;
952 rctx
->b
.streamout
.stride_in_dw
= rctx
->vs_shader
->so
.stride
;
955 static void r600_bind_gs_state(struct pipe_context
*ctx
, void *state
)
957 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
959 rctx
->gs_shader
= (struct r600_pipe_shader_selector
*)state
;
963 rctx
->b
.streamout
.stride_in_dw
= rctx
->gs_shader
->so
.stride
;
966 static void r600_bind_tcs_state(struct pipe_context
*ctx
, void *state
)
968 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
970 rctx
->tcs_shader
= (struct r600_pipe_shader_selector
*)state
;
973 static void r600_bind_tes_state(struct pipe_context
*ctx
, void *state
)
975 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
977 rctx
->tes_shader
= (struct r600_pipe_shader_selector
*)state
;
981 rctx
->b
.streamout
.stride_in_dw
= rctx
->tes_shader
->so
.stride
;
984 static void r600_delete_shader_selector(struct pipe_context
*ctx
,
985 struct r600_pipe_shader_selector
*sel
)
987 struct r600_pipe_shader
*p
= sel
->current
, *c
;
990 r600_pipe_shader_destroy(ctx
, p
);
1000 static void r600_delete_ps_state(struct pipe_context
*ctx
, void *state
)
1002 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1003 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1005 if (rctx
->ps_shader
== sel
) {
1006 rctx
->ps_shader
= NULL
;
1009 r600_delete_shader_selector(ctx
, sel
);
1012 static void r600_delete_vs_state(struct pipe_context
*ctx
, void *state
)
1014 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1015 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1017 if (rctx
->vs_shader
== sel
) {
1018 rctx
->vs_shader
= NULL
;
1021 r600_delete_shader_selector(ctx
, sel
);
1025 static void r600_delete_gs_state(struct pipe_context
*ctx
, void *state
)
1027 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1028 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1030 if (rctx
->gs_shader
== sel
) {
1031 rctx
->gs_shader
= NULL
;
1034 r600_delete_shader_selector(ctx
, sel
);
1037 static void r600_delete_tcs_state(struct pipe_context
*ctx
, void *state
)
1039 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1040 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1042 if (rctx
->tcs_shader
== sel
) {
1043 rctx
->tcs_shader
= NULL
;
1046 r600_delete_shader_selector(ctx
, sel
);
1049 static void r600_delete_tes_state(struct pipe_context
*ctx
, void *state
)
1051 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1052 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1054 if (rctx
->tes_shader
== sel
) {
1055 rctx
->tes_shader
= NULL
;
1058 r600_delete_shader_selector(ctx
, sel
);
1061 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
)
1063 if (state
->dirty_mask
) {
1064 rctx
->b
.flags
|= R600_CONTEXT_INV_CONST_CACHE
;
1065 state
->atom
.num_dw
= rctx
->b
.chip_class
>= EVERGREEN
? util_bitcount(state
->dirty_mask
)*20
1066 : util_bitcount(state
->dirty_mask
)*19;
1067 r600_mark_atom_dirty(rctx
, &state
->atom
);
1071 static void r600_set_constant_buffer(struct pipe_context
*ctx
, uint shader
, uint index
,
1072 struct pipe_constant_buffer
*input
)
1074 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1075 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
1076 struct pipe_constant_buffer
*cb
;
1079 /* Note that the state tracker can unbind constant buffers by
1080 * passing NULL here.
1082 if (unlikely(!input
|| (!input
->buffer
&& !input
->user_buffer
))) {
1083 state
->enabled_mask
&= ~(1 << index
);
1084 state
->dirty_mask
&= ~(1 << index
);
1085 pipe_resource_reference(&state
->cb
[index
].buffer
, NULL
);
1089 cb
= &state
->cb
[index
];
1090 cb
->buffer_size
= input
->buffer_size
;
1092 ptr
= input
->user_buffer
;
1095 /* Upload the user buffer. */
1096 if (R600_BIG_ENDIAN
) {
1098 unsigned i
, size
= input
->buffer_size
;
1100 if (!(tmpPtr
= malloc(size
))) {
1101 R600_ERR("Failed to allocate BE swap buffer.\n");
1105 for (i
= 0; i
< size
/ 4; ++i
) {
1106 tmpPtr
[i
] = util_cpu_to_le32(((uint32_t *)ptr
)[i
]);
1109 u_upload_data(rctx
->b
.uploader
, 0, size
, tmpPtr
, &cb
->buffer_offset
, &cb
->buffer
);
1112 u_upload_data(rctx
->b
.uploader
, 0, input
->buffer_size
, ptr
, &cb
->buffer_offset
, &cb
->buffer
);
1114 /* account it in gtt */
1115 rctx
->b
.gtt
+= input
->buffer_size
;
1117 /* Setup the hw buffer. */
1118 cb
->buffer_offset
= input
->buffer_offset
;
1119 pipe_resource_reference(&cb
->buffer
, input
->buffer
);
1120 r600_context_add_resource_size(ctx
, input
->buffer
);
1123 state
->enabled_mask
|= 1 << index
;
1124 state
->dirty_mask
|= 1 << index
;
1125 r600_constant_buffers_dirty(rctx
, state
);
1128 static void r600_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
1130 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
1132 if (rctx
->sample_mask
.sample_mask
== (uint16_t)sample_mask
)
1135 rctx
->sample_mask
.sample_mask
= sample_mask
;
1136 r600_mark_atom_dirty(rctx
, &rctx
->sample_mask
.atom
);
1139 static void r600_update_driver_const_buffers(struct r600_context
*rctx
)
1143 struct pipe_constant_buffer cb
;
1144 for (sh
= 0; sh
< PIPE_SHADER_TYPES
; sh
++) {
1145 struct r600_shader_driver_constants_info
*info
= &rctx
->driver_consts
[sh
];
1146 if (!info
->vs_ucp_dirty
&&
1147 !info
->texture_const_dirty
&&
1148 !info
->ps_sample_pos_dirty
)
1151 ptr
= info
->constants
;
1152 size
= info
->alloc_size
;
1153 if (info
->vs_ucp_dirty
) {
1154 assert(sh
== PIPE_SHADER_VERTEX
);
1156 ptr
= rctx
->clip_state
.state
.ucp
;
1157 size
= R600_UCP_SIZE
;
1159 memcpy(ptr
, rctx
->clip_state
.state
.ucp
, R600_UCP_SIZE
);
1161 info
->vs_ucp_dirty
= false;
1164 if (info
->ps_sample_pos_dirty
) {
1165 assert(sh
== PIPE_SHADER_FRAGMENT
);
1167 ptr
= rctx
->sample_positions
;
1168 size
= R600_UCP_SIZE
;
1170 memcpy(ptr
, rctx
->sample_positions
, R600_UCP_SIZE
);
1172 info
->ps_sample_pos_dirty
= false;
1175 if (info
->texture_const_dirty
) {
1178 if (sh
== PIPE_SHADER_VERTEX
)
1179 memcpy(ptr
, rctx
->clip_state
.state
.ucp
, R600_UCP_SIZE
);
1180 if (sh
== PIPE_SHADER_FRAGMENT
)
1181 memcpy(ptr
, rctx
->sample_positions
, R600_UCP_SIZE
);
1183 info
->texture_const_dirty
= false;
1186 cb
.user_buffer
= ptr
;
1187 cb
.buffer_offset
= 0;
1188 cb
.buffer_size
= size
;
1189 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, sh
, R600_BUFFER_INFO_CONST_BUFFER
, &cb
);
1190 pipe_resource_reference(&cb
.buffer
, NULL
);
1194 static void *r600_alloc_buf_consts(struct r600_context
*rctx
, int shader_type
,
1195 int array_size
, uint32_t *base_offset
)
1197 struct r600_shader_driver_constants_info
*info
= &rctx
->driver_consts
[shader_type
];
1198 if (array_size
+ R600_UCP_SIZE
> info
->alloc_size
) {
1199 info
->constants
= realloc(info
->constants
, array_size
+ R600_UCP_SIZE
);
1200 info
->alloc_size
= array_size
+ R600_UCP_SIZE
;
1202 memset(info
->constants
+ (R600_UCP_SIZE
/ 4), 0, array_size
);
1203 info
->texture_const_dirty
= true;
1204 *base_offset
= R600_UCP_SIZE
;
1205 return info
->constants
;
1208 * On r600/700 hw we don't have vertex fetch swizzle, though TBO
1209 * doesn't require full swizzles it does need masking and setting alpha
1210 * to one, so we setup a set of 5 constants with the masks + alpha value
1211 * then in the shader, we AND the 4 components with 0xffffffff or 0,
1212 * then OR the alpha with the value given here.
1213 * We use a 6th constant to store the txq buffer size in
1214 * we use 7th slot for number of cube layers in a cube map array.
1216 static void r600_setup_buffer_constants(struct r600_context
*rctx
, int shader_type
)
1218 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1220 uint32_t array_size
;
1222 uint32_t *constants
;
1223 uint32_t base_offset
;
1224 if (!samplers
->views
.dirty_buffer_constants
)
1227 samplers
->views
.dirty_buffer_constants
= FALSE
;
1229 bits
= util_last_bit(samplers
->views
.enabled_mask
);
1230 array_size
= bits
* 8 * sizeof(uint32_t) * 4;
1232 constants
= r600_alloc_buf_consts(rctx
, shader_type
, array_size
, &base_offset
);
1234 for (i
= 0; i
< bits
; i
++) {
1235 if (samplers
->views
.enabled_mask
& (1 << i
)) {
1236 int offset
= (base_offset
/ 4) + i
* 8;
1237 const struct util_format_description
*desc
;
1238 desc
= util_format_description(samplers
->views
.views
[i
]->base
.format
);
1240 for (j
= 0; j
< 4; j
++)
1241 if (j
< desc
->nr_channels
)
1242 constants
[offset
+j
] = 0xffffffff;
1244 constants
[offset
+j
] = 0x0;
1245 if (desc
->nr_channels
< 4) {
1246 if (desc
->channel
[0].pure_integer
)
1247 constants
[offset
+4] = 1;
1249 constants
[offset
+4] = fui(1.0);
1251 constants
[offset
+ 4] = 0;
1253 constants
[offset
+ 5] = samplers
->views
.views
[i
]->base
.texture
->width0
/ util_format_get_blocksize(samplers
->views
.views
[i
]->base
.format
);
1254 constants
[offset
+ 6] = samplers
->views
.views
[i
]->base
.texture
->array_size
/ 6;
1260 /* On evergreen we store two values
1261 * 1. buffer size for TXQ
1262 * 2. number of cube layers in a cube map array.
1264 static void eg_setup_buffer_constants(struct r600_context
*rctx
, int shader_type
)
1266 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1268 uint32_t array_size
;
1270 uint32_t *constants
;
1271 uint32_t base_offset
;
1272 if (!samplers
->views
.dirty_buffer_constants
)
1275 samplers
->views
.dirty_buffer_constants
= FALSE
;
1277 bits
= util_last_bit(samplers
->views
.enabled_mask
);
1278 array_size
= bits
* 2 * sizeof(uint32_t) * 4;
1280 constants
= r600_alloc_buf_consts(rctx
, shader_type
, array_size
,
1283 for (i
= 0; i
< bits
; i
++) {
1284 if (samplers
->views
.enabled_mask
& (1 << i
)) {
1285 uint32_t offset
= (base_offset
/ 4) + i
* 2;
1286 constants
[offset
] = samplers
->views
.views
[i
]->base
.texture
->width0
/ util_format_get_blocksize(samplers
->views
.views
[i
]->base
.format
);
1287 constants
[offset
+ 1] = samplers
->views
.views
[i
]->base
.texture
->array_size
/ 6;
1292 /* set sample xy locations as array of fragment shader constants */
1293 void r600_set_sample_locations_constant_buffer(struct r600_context
*rctx
)
1296 struct pipe_context
*ctx
= &rctx
->b
.b
;
1298 assert(rctx
->framebuffer
.nr_samples
< R600_UCP_SIZE
);
1299 assert(rctx
->framebuffer
.nr_samples
<= Elements(rctx
->sample_positions
)/4);
1301 memset(rctx
->sample_positions
, 0, 4 * 4 * 16);
1302 for (i
= 0; i
< rctx
->framebuffer
.nr_samples
; i
++) {
1303 ctx
->get_sample_position(ctx
, rctx
->framebuffer
.nr_samples
, i
, &rctx
->sample_positions
[4*i
]);
1304 /* Also fill in center-zeroed positions used for interpolateAtSample */
1305 rctx
->sample_positions
[4*i
+ 2] = rctx
->sample_positions
[4*i
+ 0] - 0.5f
;
1306 rctx
->sample_positions
[4*i
+ 3] = rctx
->sample_positions
[4*i
+ 1] - 0.5f
;
1309 rctx
->driver_consts
[PIPE_SHADER_FRAGMENT
].ps_sample_pos_dirty
= true;
1312 static void update_shader_atom(struct pipe_context
*ctx
,
1313 struct r600_shader_state
*state
,
1314 struct r600_pipe_shader
*shader
)
1316 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1318 state
->shader
= shader
;
1320 state
->atom
.num_dw
= shader
->command_buffer
.num_dw
;
1321 r600_context_add_resource_size(ctx
, (struct pipe_resource
*)shader
->bo
);
1323 state
->atom
.num_dw
= 0;
1325 r600_mark_atom_dirty(rctx
, &state
->atom
);
1328 static void update_gs_block_state(struct r600_context
*rctx
, unsigned enable
)
1330 if (rctx
->shader_stages
.geom_enable
!= enable
) {
1331 rctx
->shader_stages
.geom_enable
= enable
;
1332 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1335 if (rctx
->gs_rings
.enable
!= enable
) {
1336 rctx
->gs_rings
.enable
= enable
;
1337 r600_mark_atom_dirty(rctx
, &rctx
->gs_rings
.atom
);
1339 if (enable
&& !rctx
->gs_rings
.esgs_ring
.buffer
) {
1340 unsigned size
= 0x1C000;
1341 rctx
->gs_rings
.esgs_ring
.buffer
=
1342 pipe_buffer_create(rctx
->b
.b
.screen
, PIPE_BIND_CUSTOM
,
1343 PIPE_USAGE_DEFAULT
, size
);
1344 rctx
->gs_rings
.esgs_ring
.buffer_size
= size
;
1348 rctx
->gs_rings
.gsvs_ring
.buffer
=
1349 pipe_buffer_create(rctx
->b
.b
.screen
, PIPE_BIND_CUSTOM
,
1350 PIPE_USAGE_DEFAULT
, size
);
1351 rctx
->gs_rings
.gsvs_ring
.buffer_size
= size
;
1355 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_GEOMETRY
,
1356 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.esgs_ring
);
1357 if (rctx
->tes_shader
) {
1358 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_TESS_EVAL
,
1359 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.gsvs_ring
);
1361 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_VERTEX
,
1362 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.gsvs_ring
);
1365 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_GEOMETRY
,
1366 R600_GS_RING_CONST_BUFFER
, NULL
);
1367 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_VERTEX
,
1368 R600_GS_RING_CONST_BUFFER
, NULL
);
1369 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_TESS_EVAL
,
1370 R600_GS_RING_CONST_BUFFER
, NULL
);
1375 static void r600_update_clip_state(struct r600_context
*rctx
,
1376 struct r600_pipe_shader
*current
)
1378 if (current
->pa_cl_vs_out_cntl
!= rctx
->clip_misc_state
.pa_cl_vs_out_cntl
||
1379 current
->shader
.clip_dist_write
!= rctx
->clip_misc_state
.clip_dist_write
||
1380 current
->shader
.vs_position_window_space
!= rctx
->clip_misc_state
.clip_disable
||
1381 current
->shader
.vs_out_viewport
!= rctx
->clip_misc_state
.vs_out_viewport
) {
1382 rctx
->clip_misc_state
.pa_cl_vs_out_cntl
= current
->pa_cl_vs_out_cntl
;
1383 rctx
->clip_misc_state
.clip_dist_write
= current
->shader
.clip_dist_write
;
1384 rctx
->clip_misc_state
.clip_disable
= current
->shader
.vs_position_window_space
;
1385 rctx
->clip_misc_state
.vs_out_viewport
= current
->shader
.vs_out_viewport
;
1386 r600_mark_atom_dirty(rctx
, &rctx
->clip_misc_state
.atom
);
1390 static void r600_generate_fixed_func_tcs(struct r600_context
*rctx
)
1392 struct ureg_src const0
, const1
;
1393 struct ureg_dst tessouter
, tessinner
;
1394 struct ureg_program
*ureg
= ureg_create(TGSI_PROCESSOR_TESS_CTRL
);
1397 return; /* if we get here, we're screwed */
1399 assert(!rctx
->fixed_func_tcs_shader
);
1401 ureg_DECL_constant2D(ureg
, 0, 3, R600_LDS_INFO_CONST_BUFFER
);
1402 const0
= ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT
, 2),
1403 R600_LDS_INFO_CONST_BUFFER
);
1404 const1
= ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT
, 3),
1405 R600_LDS_INFO_CONST_BUFFER
);
1407 tessouter
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSOUTER
, 0);
1408 tessinner
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSINNER
, 0);
1410 ureg_MOV(ureg
, tessouter
, const0
);
1411 ureg_MOV(ureg
, tessinner
, const1
);
1414 rctx
->fixed_func_tcs_shader
=
1415 ureg_create_shader_and_destroy(ureg
, &rctx
->b
.b
);
1418 #define SELECT_SHADER_OR_FAIL(x) do { \
1419 r600_shader_select(ctx, rctx->x##_shader, &x##_dirty); \
1420 if (unlikely(!rctx->x##_shader->current)) \
1424 #define UPDATE_SHADER(hw, sw) do { \
1425 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) \
1426 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1429 #define UPDATE_SHADER_CLIP(hw, sw) do { \
1430 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1431 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1432 clip_so_current = rctx->sw##_shader->current; \
1436 #define UPDATE_SHADER_GS(hw, hw2, sw) do { \
1437 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1438 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1439 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw2)], rctx->sw##_shader->current->gs_copy_shader); \
1440 clip_so_current = rctx->sw##_shader->current->gs_copy_shader; \
1444 #define SET_NULL_SHADER(hw) do { \
1445 if (rctx->hw_shader_stages[(hw)].shader) \
1446 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], NULL); \
1449 static bool r600_update_derived_state(struct r600_context
*rctx
)
1451 struct pipe_context
* ctx
= (struct pipe_context
*)rctx
;
1452 bool ps_dirty
= false, vs_dirty
= false, gs_dirty
= false;
1453 bool tcs_dirty
= false, tes_dirty
= false, fixed_func_tcs_dirty
= false;
1455 bool need_buf_const
;
1456 struct r600_pipe_shader
*clip_so_current
= NULL
;
1458 if (!rctx
->blitter
->running
) {
1461 /* Decompress textures if needed. */
1462 for (i
= 0; i
< PIPE_SHADER_TYPES
; i
++) {
1463 struct r600_samplerview_state
*views
= &rctx
->samplers
[i
].views
;
1464 if (views
->compressed_depthtex_mask
) {
1465 r600_decompress_depth_textures(rctx
, views
);
1467 if (views
->compressed_colortex_mask
) {
1468 r600_decompress_color_textures(rctx
, views
);
1473 SELECT_SHADER_OR_FAIL(ps
);
1475 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1477 update_gs_block_state(rctx
, rctx
->gs_shader
!= NULL
);
1479 if (rctx
->gs_shader
)
1480 SELECT_SHADER_OR_FAIL(gs
);
1483 if (rctx
->tcs_shader
) {
1484 SELECT_SHADER_OR_FAIL(tcs
);
1486 UPDATE_SHADER(EG_HW_STAGE_HS
, tcs
);
1487 } else if (rctx
->tes_shader
) {
1488 if (!rctx
->fixed_func_tcs_shader
) {
1489 r600_generate_fixed_func_tcs(rctx
);
1490 if (!rctx
->fixed_func_tcs_shader
)
1494 SELECT_SHADER_OR_FAIL(fixed_func_tcs
);
1496 UPDATE_SHADER(EG_HW_STAGE_HS
, fixed_func_tcs
);
1498 SET_NULL_SHADER(EG_HW_STAGE_HS
);
1500 if (rctx
->tes_shader
) {
1501 SELECT_SHADER_OR_FAIL(tes
);
1504 SELECT_SHADER_OR_FAIL(vs
);
1506 if (rctx
->gs_shader
) {
1507 if (!rctx
->shader_stages
.geom_enable
) {
1508 rctx
->shader_stages
.geom_enable
= true;
1509 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1512 /* gs_shader provides GS and VS (copy shader) */
1513 UPDATE_SHADER_GS(R600_HW_STAGE_GS
, R600_HW_STAGE_VS
, gs
);
1515 /* vs_shader is used as ES */
1517 if (rctx
->tes_shader
) {
1518 /* VS goes to LS, TES goes to ES */
1519 UPDATE_SHADER(R600_HW_STAGE_ES
, tes
);
1520 UPDATE_SHADER(EG_HW_STAGE_LS
, vs
);
1522 /* vs_shader is used as ES */
1523 UPDATE_SHADER(R600_HW_STAGE_ES
, vs
);
1524 SET_NULL_SHADER(EG_HW_STAGE_LS
);
1527 if (unlikely(rctx
->hw_shader_stages
[R600_HW_STAGE_GS
].shader
)) {
1528 SET_NULL_SHADER(R600_HW_STAGE_GS
);
1529 SET_NULL_SHADER(R600_HW_STAGE_ES
);
1530 rctx
->shader_stages
.geom_enable
= false;
1531 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1534 if (rctx
->tes_shader
) {
1535 /* if TES is loaded and no geometry, TES runs on hw VS, VS runs on hw LS */
1536 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS
, tes
);
1537 UPDATE_SHADER(EG_HW_STAGE_LS
, vs
);
1539 SET_NULL_SHADER(EG_HW_STAGE_LS
);
1540 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS
, vs
);
1544 /* Update clip misc state. */
1545 if (clip_so_current
) {
1546 r600_update_clip_state(rctx
, clip_so_current
);
1547 rctx
->b
.streamout
.enabled_stream_buffers_mask
= clip_so_current
->enabled_stream_buffers_mask
;
1550 if (unlikely(ps_dirty
|| rctx
->hw_shader_stages
[R600_HW_STAGE_PS
].shader
!= rctx
->ps_shader
->current
||
1551 rctx
->rasterizer
->sprite_coord_enable
!= rctx
->ps_shader
->current
->sprite_coord_enable
||
1552 rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
)) {
1554 if (rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
1555 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
1556 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1559 if (rctx
->b
.chip_class
<= R700
) {
1560 bool multiwrite
= rctx
->ps_shader
->current
->shader
.fs_write_all
;
1562 if (rctx
->cb_misc_state
.multiwrite
!= multiwrite
) {
1563 rctx
->cb_misc_state
.multiwrite
= multiwrite
;
1564 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1568 if (unlikely(!ps_dirty
&& rctx
->ps_shader
&& rctx
->rasterizer
&&
1569 ((rctx
->rasterizer
->sprite_coord_enable
!= rctx
->ps_shader
->current
->sprite_coord_enable
) ||
1570 (rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
)))) {
1572 if (rctx
->b
.chip_class
>= EVERGREEN
)
1573 evergreen_update_ps_state(ctx
, rctx
->ps_shader
->current
);
1575 r600_update_ps_state(ctx
, rctx
->ps_shader
->current
);
1578 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1580 UPDATE_SHADER(R600_HW_STAGE_PS
, ps
);
1582 if (rctx
->b
.chip_class
>= EVERGREEN
) {
1583 evergreen_update_db_shader_control(rctx
);
1585 r600_update_db_shader_control(rctx
);
1588 /* on R600 we stuff masks + txq info into one constant buffer */
1589 /* on evergreen we only need a txq info one */
1590 if (rctx
->ps_shader
) {
1591 need_buf_const
= rctx
->ps_shader
->current
->shader
.uses_tex_buffers
|| rctx
->ps_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1592 if (need_buf_const
) {
1593 if (rctx
->b
.chip_class
< EVERGREEN
)
1594 r600_setup_buffer_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1596 eg_setup_buffer_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1600 if (rctx
->vs_shader
) {
1601 need_buf_const
= rctx
->vs_shader
->current
->shader
.uses_tex_buffers
|| rctx
->vs_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1602 if (need_buf_const
) {
1603 if (rctx
->b
.chip_class
< EVERGREEN
)
1604 r600_setup_buffer_constants(rctx
, PIPE_SHADER_VERTEX
);
1606 eg_setup_buffer_constants(rctx
, PIPE_SHADER_VERTEX
);
1610 if (rctx
->gs_shader
) {
1611 need_buf_const
= rctx
->gs_shader
->current
->shader
.uses_tex_buffers
|| rctx
->gs_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1612 if (need_buf_const
) {
1613 if (rctx
->b
.chip_class
< EVERGREEN
)
1614 r600_setup_buffer_constants(rctx
, PIPE_SHADER_GEOMETRY
);
1616 eg_setup_buffer_constants(rctx
, PIPE_SHADER_GEOMETRY
);
1620 r600_update_driver_const_buffers(rctx
);
1622 if (rctx
->b
.chip_class
< EVERGREEN
&& rctx
->ps_shader
&& rctx
->vs_shader
) {
1623 if (!r600_adjust_gprs(rctx
)) {
1624 /* discard rendering */
1629 if (rctx
->b
.chip_class
== EVERGREEN
) {
1630 if (!evergreen_adjust_gprs(rctx
)) {
1631 /* discard rendering */
1636 blend_disable
= (rctx
->dual_src_blend
&&
1637 rctx
->ps_shader
->current
->nr_ps_color_outputs
< 2);
1639 if (blend_disable
!= rctx
->force_blend_disable
) {
1640 rctx
->force_blend_disable
= blend_disable
;
1641 r600_bind_blend_state_internal(rctx
,
1642 rctx
->blend_state
.cso
,
1649 void r600_emit_clip_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1651 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1652 struct r600_clip_misc_state
*state
= &rctx
->clip_misc_state
;
1654 radeon_set_context_reg(cs
, R_028810_PA_CL_CLIP_CNTL
,
1655 state
->pa_cl_clip_cntl
|
1656 (state
->clip_dist_write
? 0 : state
->clip_plane_enable
& 0x3F) |
1657 S_028810_CLIP_DISABLE(state
->clip_disable
));
1658 radeon_set_context_reg(cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
1659 state
->pa_cl_vs_out_cntl
|
1660 (state
->clip_plane_enable
& state
->clip_dist_write
));
1661 /* reuse needs to be set off if we write oViewport */
1662 if (rctx
->b
.chip_class
>= EVERGREEN
)
1663 radeon_set_context_reg(cs
, R_028AB4_VGT_REUSE_OFF
,
1664 S_028AB4_REUSE_OFF(state
->vs_out_viewport
));
1667 static void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*dinfo
)
1669 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1670 struct pipe_draw_info info
= *dinfo
;
1671 struct pipe_index_buffer ib
= {};
1672 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1673 bool render_cond_bit
= rctx
->b
.render_cond
&& !rctx
->b
.render_cond_force_off
;
1675 unsigned num_patches
;
1677 if (!info
.indirect
&& !info
.count
&& (info
.indexed
|| !info
.count_from_stream_output
)) {
1681 if (!rctx
->vs_shader
|| !rctx
->ps_shader
) {
1686 /* make sure that the gfx ring is only one active */
1687 if (rctx
->b
.dma
.cs
&& rctx
->b
.dma
.cs
->cdw
) {
1688 rctx
->b
.dma
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
1691 if (!r600_update_derived_state(rctx
)) {
1692 /* useless to render because current rendering command
1699 /* Initialize the index buffer struct. */
1700 pipe_resource_reference(&ib
.buffer
, rctx
->index_buffer
.buffer
);
1701 ib
.user_buffer
= rctx
->index_buffer
.user_buffer
;
1702 ib
.index_size
= rctx
->index_buffer
.index_size
;
1703 ib
.offset
= rctx
->index_buffer
.offset
;
1704 if (!info
.indirect
) {
1705 ib
.offset
+= info
.start
* ib
.index_size
;
1708 /* Translate 8-bit indices to 16-bit. */
1709 if (unlikely(ib
.index_size
== 1)) {
1710 struct pipe_resource
*out_buffer
= NULL
;
1711 unsigned out_offset
;
1713 unsigned start
, count
;
1715 if (likely(!info
.indirect
)) {
1720 /* Have to get start/count from indirect buffer, slow path ahead... */
1721 struct r600_resource
*indirect_resource
= (struct r600_resource
*)info
.indirect
;
1722 unsigned *data
= r600_buffer_map_sync_with_rings(&rctx
->b
, indirect_resource
,
1723 PIPE_TRANSFER_READ
);
1725 data
+= info
.indirect_offset
/ sizeof(unsigned);
1726 start
= data
[2] * ib
.index_size
;
1735 u_upload_alloc(rctx
->b
.uploader
, start
, count
* 2,
1736 &out_offset
, &out_buffer
, &ptr
);
1738 util_shorten_ubyte_elts_to_userptr(
1739 &rctx
->b
.b
, &ib
, 0, ib
.offset
+ start
, count
, ptr
);
1741 pipe_resource_reference(&ib
.buffer
, NULL
);
1742 ib
.user_buffer
= NULL
;
1743 ib
.buffer
= out_buffer
;
1744 ib
.offset
= out_offset
;
1748 /* Upload the index buffer.
1749 * The upload is skipped for small index counts on little-endian machines
1750 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
1751 * Indirect draws never use immediate indices.
1752 * Note: Instanced rendering in combination with immediate indices hangs. */
1753 if (ib
.user_buffer
&& (R600_BIG_ENDIAN
|| info
.indirect
||
1754 info
.instance_count
> 1 ||
1755 info
.count
*ib
.index_size
> 20)) {
1756 u_upload_data(rctx
->b
.uploader
, 0, info
.count
* ib
.index_size
,
1757 ib
.user_buffer
, &ib
.offset
, &ib
.buffer
);
1758 ib
.user_buffer
= NULL
;
1761 info
.index_bias
= info
.start
;
1764 /* Set the index offset and primitive restart. */
1765 if (rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
!= info
.primitive_restart
||
1766 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
!= info
.restart_index
||
1767 rctx
->vgt_state
.vgt_indx_offset
!= info
.index_bias
||
1768 (rctx
->vgt_state
.last_draw_was_indirect
&& !info
.indirect
)) {
1769 rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
= info
.primitive_restart
;
1770 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
= info
.restart_index
;
1771 rctx
->vgt_state
.vgt_indx_offset
= info
.index_bias
;
1772 r600_mark_atom_dirty(rctx
, &rctx
->vgt_state
.atom
);
1775 /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
1776 if (rctx
->b
.chip_class
== R600
) {
1777 rctx
->b
.flags
|= R600_CONTEXT_PS_PARTIAL_FLUSH
;
1778 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1781 if (rctx
->b
.chip_class
>= EVERGREEN
)
1782 evergreen_setup_tess_constants(rctx
, &info
, &num_patches
);
1785 r600_need_cs_space(rctx
, ib
.user_buffer
? 5 : 0, TRUE
);
1786 r600_flush_emit(rctx
);
1788 mask
= rctx
->dirty_atoms
;
1790 r600_emit_atom(rctx
, rctx
->atoms
[u_bit_scan64(&mask
)]);
1793 if (rctx
->b
.chip_class
== CAYMAN
) {
1794 /* Copied from radeonsi. */
1795 unsigned primgroup_size
= 128; /* recommended without a GS */
1796 bool ia_switch_on_eop
= false;
1797 bool partial_vs_wave
= false;
1799 if (rctx
->gs_shader
)
1800 primgroup_size
= 64; /* recommended with a GS */
1802 if ((rctx
->rasterizer
&& rctx
->rasterizer
->pa_sc_line_stipple
) ||
1803 (rctx
->b
.screen
->debug_flags
& DBG_SWITCH_ON_EOP
)) {
1804 ia_switch_on_eop
= true;
1807 if (rctx
->b
.streamout
.streamout_enabled
||
1808 rctx
->b
.streamout
.prims_gen_query_enabled
)
1809 partial_vs_wave
= true;
1811 radeon_set_context_reg(cs
, CM_R_028AA8_IA_MULTI_VGT_PARAM
,
1812 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop
) |
1813 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave
) |
1814 S_028AA8_PRIMGROUP_SIZE(primgroup_size
- 1));
1817 if (rctx
->b
.chip_class
>= EVERGREEN
) {
1818 uint32_t ls_hs_config
= evergreen_get_ls_hs_config(rctx
, &info
,
1821 evergreen_set_ls_hs_config(rctx
, cs
, ls_hs_config
);
1822 evergreen_set_lds_alloc(rctx
, cs
, rctx
->lds_alloc
);
1825 /* On R6xx, CULL_FRONT=1 culls all points, lines, and rectangles,
1826 * even though it should have no effect on those. */
1827 if (rctx
->b
.chip_class
== R600
&& rctx
->rasterizer
) {
1828 unsigned su_sc_mode_cntl
= rctx
->rasterizer
->pa_su_sc_mode_cntl
;
1829 unsigned prim
= info
.mode
;
1831 if (rctx
->gs_shader
) {
1832 prim
= rctx
->gs_shader
->gs_output_prim
;
1834 prim
= r600_conv_prim_to_gs_out(prim
); /* decrease the number of types to 3 */
1836 if (prim
== V_028A6C_OUTPRIM_TYPE_POINTLIST
||
1837 prim
== V_028A6C_OUTPRIM_TYPE_LINESTRIP
||
1838 info
.mode
== R600_PRIM_RECTANGLE_LIST
) {
1839 su_sc_mode_cntl
&= C_028814_CULL_FRONT
;
1841 radeon_set_context_reg(cs
, R_028814_PA_SU_SC_MODE_CNTL
, su_sc_mode_cntl
);
1844 /* Update start instance. */
1845 if (!info
.indirect
&& rctx
->last_start_instance
!= info
.start_instance
) {
1846 radeon_set_ctl_const(cs
, R_03CFF4_SQ_VTX_START_INST_LOC
, info
.start_instance
);
1847 rctx
->last_start_instance
= info
.start_instance
;
1850 /* Update the primitive type. */
1851 if (rctx
->last_primitive_type
!= info
.mode
) {
1852 unsigned ls_mask
= 0;
1854 if (info
.mode
== PIPE_PRIM_LINES
)
1856 else if (info
.mode
== PIPE_PRIM_LINE_STRIP
||
1857 info
.mode
== PIPE_PRIM_LINE_LOOP
)
1860 radeon_set_context_reg(cs
, R_028A0C_PA_SC_LINE_STIPPLE
,
1861 S_028A0C_AUTO_RESET_CNTL(ls_mask
) |
1862 (rctx
->rasterizer
? rctx
->rasterizer
->pa_sc_line_stipple
: 0));
1863 radeon_set_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
,
1864 r600_conv_pipe_prim(info
.mode
));
1866 rctx
->last_primitive_type
= info
.mode
;
1870 if (!info
.indirect
) {
1871 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NUM_INSTANCES
, 0, 0);
1872 cs
->buf
[cs
->cdw
++] = info
.instance_count
;
1875 if (unlikely(info
.indirect
)) {
1876 uint64_t va
= r600_resource(info
.indirect
)->gpu_address
;
1877 assert(rctx
->b
.chip_class
>= EVERGREEN
);
1879 // Invalidate so non-indirect draw calls reset this state
1880 rctx
->vgt_state
.last_draw_was_indirect
= true;
1881 rctx
->last_start_instance
= -1;
1883 cs
->buf
[cs
->cdw
++] = PKT3(EG_PKT3_SET_BASE
, 2, 0);
1884 cs
->buf
[cs
->cdw
++] = EG_DRAW_INDEX_INDIRECT_PATCH_TABLE_BASE
;
1885 cs
->buf
[cs
->cdw
++] = va
;
1886 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFF;
1888 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
1889 cs
->buf
[cs
->cdw
++] = radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
1890 (struct r600_resource
*)info
.indirect
,
1892 RADEON_PRIO_DRAW_INDIRECT
);
1896 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_INDEX_TYPE
, 0, 0);
1897 cs
->buf
[cs
->cdw
++] = ib
.index_size
== 4 ?
1898 (VGT_INDEX_32
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_32_BIT
: 0)) :
1899 (VGT_INDEX_16
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_16_BIT
: 0));
1901 if (ib
.user_buffer
) {
1902 unsigned size_bytes
= info
.count
*ib
.index_size
;
1903 unsigned size_dw
= align(size_bytes
, 4) / 4;
1904 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX_IMMD
, 1 + size_dw
, render_cond_bit
);
1905 cs
->buf
[cs
->cdw
++] = info
.count
;
1906 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_IMMEDIATE
;
1907 memcpy(cs
->buf
+cs
->cdw
, ib
.user_buffer
, size_bytes
);
1910 uint64_t va
= r600_resource(ib
.buffer
)->gpu_address
+ ib
.offset
;
1912 if (likely(!info
.indirect
)) {
1913 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX
, 3, render_cond_bit
);
1914 cs
->buf
[cs
->cdw
++] = va
;
1915 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFF;
1916 cs
->buf
[cs
->cdw
++] = info
.count
;
1917 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_DMA
;
1918 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
1919 cs
->buf
[cs
->cdw
++] = radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
1920 (struct r600_resource
*)ib
.buffer
,
1922 RADEON_PRIO_INDEX_BUFFER
);
1925 uint32_t max_size
= (ib
.buffer
->width0
- ib
.offset
) / ib
.index_size
;
1927 cs
->buf
[cs
->cdw
++] = PKT3(EG_PKT3_INDEX_BASE
, 1, 0);
1928 cs
->buf
[cs
->cdw
++] = va
;
1929 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFF;
1931 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
1932 cs
->buf
[cs
->cdw
++] = radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
1933 (struct r600_resource
*)ib
.buffer
,
1935 RADEON_PRIO_INDEX_BUFFER
);
1937 cs
->buf
[cs
->cdw
++] = PKT3(EG_PKT3_INDEX_BUFFER_SIZE
, 0, 0);
1938 cs
->buf
[cs
->cdw
++] = max_size
;
1940 cs
->buf
[cs
->cdw
++] = PKT3(EG_PKT3_DRAW_INDEX_INDIRECT
, 1, render_cond_bit
);
1941 cs
->buf
[cs
->cdw
++] = info
.indirect_offset
;
1942 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_DMA
;
1946 if (unlikely(info
.count_from_stream_output
)) {
1947 struct r600_so_target
*t
= (struct r600_so_target
*)info
.count_from_stream_output
;
1948 uint64_t va
= t
->buf_filled_size
->gpu_address
+ t
->buf_filled_size_offset
;
1950 radeon_set_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
, t
->stride_in_dw
);
1952 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_COPY_DW
, 4, 0);
1953 cs
->buf
[cs
->cdw
++] = COPY_DW_SRC_IS_MEM
| COPY_DW_DST_IS_REG
;
1954 cs
->buf
[cs
->cdw
++] = va
& 0xFFFFFFFFUL
; /* src address lo */
1955 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFFUL
; /* src address hi */
1956 cs
->buf
[cs
->cdw
++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2; /* dst register */
1957 cs
->buf
[cs
->cdw
++] = 0; /* unused */
1959 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
1960 cs
->buf
[cs
->cdw
++] = radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
1961 t
->buf_filled_size
, RADEON_USAGE_READ
,
1962 RADEON_PRIO_SO_FILLED_SIZE
);
1965 if (likely(!info
.indirect
)) {
1966 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX_AUTO
, 1, render_cond_bit
);
1967 cs
->buf
[cs
->cdw
++] = info
.count
;
1970 cs
->buf
[cs
->cdw
++] = PKT3(EG_PKT3_DRAW_INDIRECT
, 1, render_cond_bit
);
1971 cs
->buf
[cs
->cdw
++] = info
.indirect_offset
;
1973 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
1974 (info
.count_from_stream_output
? S_0287F0_USE_OPAQUE(1) : 0);
1977 /* SMX returns CONTEXT_DONE too early workaround */
1978 if (rctx
->b
.family
== CHIP_R600
||
1979 rctx
->b
.family
== CHIP_RV610
||
1980 rctx
->b
.family
== CHIP_RV630
||
1981 rctx
->b
.family
== CHIP_RV635
) {
1982 /* if we have gs shader or streamout
1983 we need to do a wait idle after every draw */
1984 if (rctx
->gs_shader
|| rctx
->b
.streamout
.streamout_enabled
) {
1985 radeon_set_config_reg(cs
, R_008040_WAIT_UNTIL
, S_008040_WAIT_3D_IDLE(1));
1989 /* ES ring rolling over at EOP - workaround */
1990 if (rctx
->b
.chip_class
== R600
) {
1991 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_EVENT_WRITE
, 0, 0);
1992 cs
->buf
[cs
->cdw
++] = EVENT_TYPE(EVENT_TYPE_SQ_NON_EVENT
);
1995 if (rctx
->screen
->b
.trace_bo
) {
1996 r600_trace_emit(rctx
);
1999 /* Set the depth buffer as dirty. */
2000 if (rctx
->framebuffer
.state
.zsbuf
) {
2001 struct pipe_surface
*surf
= rctx
->framebuffer
.state
.zsbuf
;
2002 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
2004 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2006 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
)
2007 rtex
->stencil_dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2009 if (rctx
->framebuffer
.compressed_cb_mask
) {
2010 struct pipe_surface
*surf
;
2011 struct r600_texture
*rtex
;
2012 unsigned mask
= rctx
->framebuffer
.compressed_cb_mask
;
2015 unsigned i
= u_bit_scan(&mask
);
2016 surf
= rctx
->framebuffer
.state
.cbufs
[i
];
2017 rtex
= (struct r600_texture
*)surf
->texture
;
2019 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2024 pipe_resource_reference(&ib
.buffer
, NULL
);
2025 rctx
->b
.num_draw_calls
++;
2028 uint32_t r600_translate_stencil_op(int s_op
)
2031 case PIPE_STENCIL_OP_KEEP
:
2032 return V_028800_STENCIL_KEEP
;
2033 case PIPE_STENCIL_OP_ZERO
:
2034 return V_028800_STENCIL_ZERO
;
2035 case PIPE_STENCIL_OP_REPLACE
:
2036 return V_028800_STENCIL_REPLACE
;
2037 case PIPE_STENCIL_OP_INCR
:
2038 return V_028800_STENCIL_INCR
;
2039 case PIPE_STENCIL_OP_DECR
:
2040 return V_028800_STENCIL_DECR
;
2041 case PIPE_STENCIL_OP_INCR_WRAP
:
2042 return V_028800_STENCIL_INCR_WRAP
;
2043 case PIPE_STENCIL_OP_DECR_WRAP
:
2044 return V_028800_STENCIL_DECR_WRAP
;
2045 case PIPE_STENCIL_OP_INVERT
:
2046 return V_028800_STENCIL_INVERT
;
2048 R600_ERR("Unknown stencil op %d", s_op
);
2055 uint32_t r600_translate_fill(uint32_t func
)
2058 case PIPE_POLYGON_MODE_FILL
:
2060 case PIPE_POLYGON_MODE_LINE
:
2062 case PIPE_POLYGON_MODE_POINT
:
2070 unsigned r600_tex_wrap(unsigned wrap
)
2074 case PIPE_TEX_WRAP_REPEAT
:
2075 return V_03C000_SQ_TEX_WRAP
;
2076 case PIPE_TEX_WRAP_CLAMP
:
2077 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER
;
2078 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
2079 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL
;
2080 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
2081 return V_03C000_SQ_TEX_CLAMP_BORDER
;
2082 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
2083 return V_03C000_SQ_TEX_MIRROR
;
2084 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
2085 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
2086 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
2087 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
2088 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
2089 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER
;
2093 unsigned r600_tex_filter(unsigned filter
)
2097 case PIPE_TEX_FILTER_NEAREST
:
2098 return V_03C000_SQ_TEX_XY_FILTER_POINT
;
2099 case PIPE_TEX_FILTER_LINEAR
:
2100 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR
;
2104 unsigned r600_tex_mipfilter(unsigned filter
)
2107 case PIPE_TEX_MIPFILTER_NEAREST
:
2108 return V_03C000_SQ_TEX_Z_FILTER_POINT
;
2109 case PIPE_TEX_MIPFILTER_LINEAR
:
2110 return V_03C000_SQ_TEX_Z_FILTER_LINEAR
;
2112 case PIPE_TEX_MIPFILTER_NONE
:
2113 return V_03C000_SQ_TEX_Z_FILTER_NONE
;
2117 unsigned r600_tex_compare(unsigned compare
)
2121 case PIPE_FUNC_NEVER
:
2122 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER
;
2123 case PIPE_FUNC_LESS
:
2124 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS
;
2125 case PIPE_FUNC_EQUAL
:
2126 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL
;
2127 case PIPE_FUNC_LEQUAL
:
2128 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
2129 case PIPE_FUNC_GREATER
:
2130 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER
;
2131 case PIPE_FUNC_NOTEQUAL
:
2132 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
2133 case PIPE_FUNC_GEQUAL
:
2134 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
2135 case PIPE_FUNC_ALWAYS
:
2136 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
2140 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
2142 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
2143 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
2145 (wrap
== PIPE_TEX_WRAP_CLAMP
||
2146 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
2149 bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
)
2151 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
2152 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
2154 return (state
->border_color
.ui
[0] || state
->border_color
.ui
[1] ||
2155 state
->border_color
.ui
[2] || state
->border_color
.ui
[3]) &&
2156 (wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) ||
2157 wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) ||
2158 wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
));
2161 void r600_emit_shader(struct r600_context
*rctx
, struct r600_atom
*a
)
2164 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2165 struct r600_pipe_shader
*shader
= ((struct r600_shader_state
*)a
)->shader
;
2170 r600_emit_command_buffer(cs
, &shader
->command_buffer
);
2171 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2172 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, shader
->bo
,
2173 RADEON_USAGE_READ
, RADEON_PRIO_USER_SHADER
));
2176 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
2177 const unsigned char *swizzle_view
,
2181 unsigned char swizzle
[4];
2182 unsigned result
= 0;
2183 const uint32_t tex_swizzle_shift
[4] = {
2186 const uint32_t vtx_swizzle_shift
[4] = {
2189 const uint32_t swizzle_bit
[4] = {
2192 const uint32_t *swizzle_shift
= tex_swizzle_shift
;
2195 swizzle_shift
= vtx_swizzle_shift
;
2198 util_format_compose_swizzles(swizzle_format
, swizzle_view
, swizzle
);
2200 memcpy(swizzle
, swizzle_format
, 4);
2204 for (i
= 0; i
< 4; i
++) {
2205 switch (swizzle
[i
]) {
2206 case UTIL_FORMAT_SWIZZLE_Y
:
2207 result
|= swizzle_bit
[1] << swizzle_shift
[i
];
2209 case UTIL_FORMAT_SWIZZLE_Z
:
2210 result
|= swizzle_bit
[2] << swizzle_shift
[i
];
2212 case UTIL_FORMAT_SWIZZLE_W
:
2213 result
|= swizzle_bit
[3] << swizzle_shift
[i
];
2215 case UTIL_FORMAT_SWIZZLE_0
:
2216 result
|= V_038010_SQ_SEL_0
<< swizzle_shift
[i
];
2218 case UTIL_FORMAT_SWIZZLE_1
:
2219 result
|= V_038010_SQ_SEL_1
<< swizzle_shift
[i
];
2221 default: /* UTIL_FORMAT_SWIZZLE_X */
2222 result
|= swizzle_bit
[0] << swizzle_shift
[i
];
2228 /* texture format translate */
2229 uint32_t r600_translate_texformat(struct pipe_screen
*screen
,
2230 enum pipe_format format
,
2231 const unsigned char *swizzle_view
,
2232 uint32_t *word4_p
, uint32_t *yuv_format_p
)
2234 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
2235 uint32_t result
= 0, word4
= 0, yuv_format
= 0;
2236 const struct util_format_description
*desc
;
2237 boolean uniform
= TRUE
;
2238 bool enable_s3tc
= rscreen
->b
.info
.drm_minor
>= 9;
2239 bool is_srgb_valid
= FALSE
;
2240 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
2241 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
2244 const uint32_t sign_bit
[4] = {
2245 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED
),
2246 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED
),
2247 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED
),
2248 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED
)
2250 desc
= util_format_description(format
);
2252 /* Depth and stencil swizzling is handled separately. */
2253 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
) {
2254 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
, FALSE
);
2257 /* Colorspace (return non-RGB formats directly). */
2258 switch (desc
->colorspace
) {
2259 /* Depth stencil formats */
2260 case UTIL_FORMAT_COLORSPACE_ZS
:
2262 /* Depth sampler formats. */
2263 case PIPE_FORMAT_Z16_UNORM
:
2264 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2267 case PIPE_FORMAT_Z24X8_UNORM
:
2268 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
2269 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2272 case PIPE_FORMAT_X8Z24_UNORM
:
2273 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2274 if (rscreen
->b
.chip_class
< EVERGREEN
)
2276 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
2279 case PIPE_FORMAT_Z32_FLOAT
:
2280 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2281 result
= FMT_32_FLOAT
;
2283 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
2284 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2285 result
= FMT_X24_8_32_FLOAT
;
2287 /* Stencil sampler formats. */
2288 case PIPE_FORMAT_S8_UINT
:
2289 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2290 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2293 case PIPE_FORMAT_X24S8_UINT
:
2294 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2295 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
2298 case PIPE_FORMAT_S8X24_UINT
:
2299 if (rscreen
->b
.chip_class
< EVERGREEN
)
2301 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2302 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2305 case PIPE_FORMAT_X32_S8X24_UINT
:
2306 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2307 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
2308 result
= FMT_X24_8_32_FLOAT
;
2314 case UTIL_FORMAT_COLORSPACE_YUV
:
2315 yuv_format
|= (1 << 30);
2317 case PIPE_FORMAT_UYVY
:
2318 case PIPE_FORMAT_YUYV
:
2322 goto out_unknown
; /* XXX */
2324 case UTIL_FORMAT_COLORSPACE_SRGB
:
2325 word4
|= S_038010_FORCE_DEGAMMA(1);
2332 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
2337 case PIPE_FORMAT_RGTC1_SNORM
:
2338 case PIPE_FORMAT_LATC1_SNORM
:
2339 word4
|= sign_bit
[0];
2340 case PIPE_FORMAT_RGTC1_UNORM
:
2341 case PIPE_FORMAT_LATC1_UNORM
:
2344 case PIPE_FORMAT_RGTC2_SNORM
:
2345 case PIPE_FORMAT_LATC2_SNORM
:
2346 word4
|= sign_bit
[0] | sign_bit
[1];
2347 case PIPE_FORMAT_RGTC2_UNORM
:
2348 case PIPE_FORMAT_LATC2_UNORM
:
2356 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
2361 if (!util_format_s3tc_enabled
) {
2366 case PIPE_FORMAT_DXT1_RGB
:
2367 case PIPE_FORMAT_DXT1_RGBA
:
2368 case PIPE_FORMAT_DXT1_SRGB
:
2369 case PIPE_FORMAT_DXT1_SRGBA
:
2371 is_srgb_valid
= TRUE
;
2373 case PIPE_FORMAT_DXT3_RGBA
:
2374 case PIPE_FORMAT_DXT3_SRGBA
:
2376 is_srgb_valid
= TRUE
;
2378 case PIPE_FORMAT_DXT5_RGBA
:
2379 case PIPE_FORMAT_DXT5_SRGBA
:
2381 is_srgb_valid
= TRUE
;
2388 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
2392 if (rscreen
->b
.chip_class
< EVERGREEN
)
2396 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
2397 case PIPE_FORMAT_BPTC_SRGBA
:
2399 is_srgb_valid
= TRUE
;
2401 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
2402 word4
|= sign_bit
[0] | sign_bit
[1] | sign_bit
[2];
2404 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
2412 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
2414 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
2415 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
2418 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
2419 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
2427 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
2428 result
= FMT_5_9_9_9_SHAREDEXP
;
2430 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
2431 result
= FMT_10_11_11_FLOAT
;
2436 for (i
= 0; i
< desc
->nr_channels
; i
++) {
2437 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2438 word4
|= sign_bit
[i
];
2442 /* R8G8Bx_SNORM - XXX CxV8U8 */
2444 /* See whether the components are of the same size. */
2445 for (i
= 1; i
< desc
->nr_channels
; i
++) {
2446 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
2449 /* Non-uniform formats. */
2451 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
2452 desc
->channel
[0].pure_integer
)
2453 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2454 switch(desc
->nr_channels
) {
2456 if (desc
->channel
[0].size
== 5 &&
2457 desc
->channel
[1].size
== 6 &&
2458 desc
->channel
[2].size
== 5) {
2464 if (desc
->channel
[0].size
== 5 &&
2465 desc
->channel
[1].size
== 5 &&
2466 desc
->channel
[2].size
== 5 &&
2467 desc
->channel
[3].size
== 1) {
2468 result
= FMT_1_5_5_5
;
2471 if (desc
->channel
[0].size
== 10 &&
2472 desc
->channel
[1].size
== 10 &&
2473 desc
->channel
[2].size
== 10 &&
2474 desc
->channel
[3].size
== 2) {
2475 result
= FMT_2_10_10_10
;
2483 /* Find the first non-VOID channel. */
2484 for (i
= 0; i
< 4; i
++) {
2485 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2493 /* uniform formats */
2494 switch (desc
->channel
[i
].type
) {
2495 case UTIL_FORMAT_TYPE_UNSIGNED
:
2496 case UTIL_FORMAT_TYPE_SIGNED
:
2498 if (!desc
->channel
[i
].normalized
&&
2499 desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
) {
2503 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
2504 desc
->channel
[i
].pure_integer
)
2505 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2507 switch (desc
->channel
[i
].size
) {
2509 switch (desc
->nr_channels
) {
2514 result
= FMT_4_4_4_4
;
2519 switch (desc
->nr_channels
) {
2527 result
= FMT_8_8_8_8
;
2528 is_srgb_valid
= TRUE
;
2533 switch (desc
->nr_channels
) {
2541 result
= FMT_16_16_16_16
;
2546 switch (desc
->nr_channels
) {
2554 result
= FMT_32_32_32_32
;
2560 case UTIL_FORMAT_TYPE_FLOAT
:
2561 switch (desc
->channel
[i
].size
) {
2563 switch (desc
->nr_channels
) {
2565 result
= FMT_16_FLOAT
;
2568 result
= FMT_16_16_FLOAT
;
2571 result
= FMT_16_16_16_16_FLOAT
;
2576 switch (desc
->nr_channels
) {
2578 result
= FMT_32_FLOAT
;
2581 result
= FMT_32_32_FLOAT
;
2584 result
= FMT_32_32_32_32_FLOAT
;
2593 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
&& !is_srgb_valid
)
2598 *yuv_format_p
= yuv_format
;
2601 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
2605 uint32_t r600_translate_colorformat(enum chip_class chip
, enum pipe_format format
)
2607 const struct util_format_description
*desc
= util_format_description(format
);
2608 int channel
= util_format_get_first_non_void_channel(format
);
2611 #define HAS_SIZE(x,y,z,w) \
2612 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
2613 desc->channel[2].size == (z) && desc->channel[3].size == (w))
2615 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2616 return V_0280A0_COLOR_10_11_11_FLOAT
;
2618 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
||
2622 is_float
= desc
->channel
[channel
].type
== UTIL_FORMAT_TYPE_FLOAT
;
2624 switch (desc
->nr_channels
) {
2626 switch (desc
->channel
[0].size
) {
2628 return V_0280A0_COLOR_8
;
2631 return V_0280A0_COLOR_16_FLOAT
;
2633 return V_0280A0_COLOR_16
;
2636 return V_0280A0_COLOR_32_FLOAT
;
2638 return V_0280A0_COLOR_32
;
2642 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
2643 switch (desc
->channel
[0].size
) {
2646 return V_0280A0_COLOR_4_4
;
2648 return ~0U; /* removed on Evergreen */
2650 return V_0280A0_COLOR_8_8
;
2653 return V_0280A0_COLOR_16_16_FLOAT
;
2655 return V_0280A0_COLOR_16_16
;
2658 return V_0280A0_COLOR_32_32_FLOAT
;
2660 return V_0280A0_COLOR_32_32
;
2662 } else if (HAS_SIZE(8,24,0,0)) {
2663 return V_0280A0_COLOR_24_8
;
2664 } else if (HAS_SIZE(24,8,0,0)) {
2665 return V_0280A0_COLOR_8_24
;
2669 if (HAS_SIZE(5,6,5,0)) {
2670 return V_0280A0_COLOR_5_6_5
;
2671 } else if (HAS_SIZE(32,8,24,0)) {
2672 return V_0280A0_COLOR_X24_8_32_FLOAT
;
2676 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
2677 desc
->channel
[0].size
== desc
->channel
[2].size
&&
2678 desc
->channel
[0].size
== desc
->channel
[3].size
) {
2679 switch (desc
->channel
[0].size
) {
2681 return V_0280A0_COLOR_4_4_4_4
;
2683 return V_0280A0_COLOR_8_8_8_8
;
2686 return V_0280A0_COLOR_16_16_16_16_FLOAT
;
2688 return V_0280A0_COLOR_16_16_16_16
;
2691 return V_0280A0_COLOR_32_32_32_32_FLOAT
;
2693 return V_0280A0_COLOR_32_32_32_32
;
2695 } else if (HAS_SIZE(5,5,5,1)) {
2696 return V_0280A0_COLOR_1_5_5_5
;
2697 } else if (HAS_SIZE(10,10,10,2)) {
2698 return V_0280A0_COLOR_2_10_10_10
;
2705 uint32_t r600_colorformat_endian_swap(uint32_t colorformat
)
2707 if (R600_BIG_ENDIAN
) {
2708 switch(colorformat
) {
2709 /* 8-bit buffers. */
2710 case V_0280A0_COLOR_4_4
:
2711 case V_0280A0_COLOR_8
:
2714 /* 16-bit buffers. */
2715 case V_0280A0_COLOR_5_6_5
:
2716 case V_0280A0_COLOR_1_5_5_5
:
2717 case V_0280A0_COLOR_4_4_4_4
:
2718 case V_0280A0_COLOR_16
:
2719 case V_0280A0_COLOR_8_8
:
2720 return ENDIAN_8IN16
;
2722 /* 32-bit buffers. */
2723 case V_0280A0_COLOR_8_8_8_8
:
2724 case V_0280A0_COLOR_2_10_10_10
:
2725 case V_0280A0_COLOR_8_24
:
2726 case V_0280A0_COLOR_24_8
:
2727 case V_0280A0_COLOR_32_FLOAT
:
2728 case V_0280A0_COLOR_16_16_FLOAT
:
2729 case V_0280A0_COLOR_16_16
:
2730 return ENDIAN_8IN32
;
2732 /* 64-bit buffers. */
2733 case V_0280A0_COLOR_16_16_16_16
:
2734 case V_0280A0_COLOR_16_16_16_16_FLOAT
:
2735 return ENDIAN_8IN16
;
2737 case V_0280A0_COLOR_32_32_FLOAT
:
2738 case V_0280A0_COLOR_32_32
:
2739 case V_0280A0_COLOR_X24_8_32_FLOAT
:
2740 return ENDIAN_8IN32
;
2742 /* 128-bit buffers. */
2743 case V_0280A0_COLOR_32_32_32_32_FLOAT
:
2744 case V_0280A0_COLOR_32_32_32_32
:
2745 return ENDIAN_8IN32
;
2747 return ENDIAN_NONE
; /* Unsupported. */
2754 static void r600_invalidate_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
)
2756 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2757 struct r600_resource
*rbuffer
= r600_resource(buf
);
2758 unsigned i
, shader
, mask
, alignment
= rbuffer
->buf
->alignment
;
2759 struct r600_pipe_sampler_view
*view
;
2761 /* Reallocate the buffer in the same pipe_resource. */
2762 r600_init_resource(&rctx
->screen
->b
, rbuffer
, rbuffer
->b
.b
.width0
,
2765 /* We changed the buffer, now we need to bind it where the old one was bound. */
2766 /* Vertex buffers. */
2767 mask
= rctx
->vertex_buffer_state
.enabled_mask
;
2769 i
= u_bit_scan(&mask
);
2770 if (rctx
->vertex_buffer_state
.vb
[i
].buffer
== &rbuffer
->b
.b
) {
2771 rctx
->vertex_buffer_state
.dirty_mask
|= 1 << i
;
2772 r600_vertex_buffers_dirty(rctx
);
2775 /* Streamout buffers. */
2776 for (i
= 0; i
< rctx
->b
.streamout
.num_targets
; i
++) {
2777 if (rctx
->b
.streamout
.targets
[i
]->b
.buffer
== &rbuffer
->b
.b
) {
2778 if (rctx
->b
.streamout
.begin_emitted
) {
2779 r600_emit_streamout_end(&rctx
->b
);
2781 rctx
->b
.streamout
.append_bitmask
= rctx
->b
.streamout
.enabled_mask
;
2782 r600_streamout_buffers_dirty(&rctx
->b
);
2786 /* Constant buffers. */
2787 for (shader
= 0; shader
< PIPE_SHADER_TYPES
; shader
++) {
2788 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
2790 uint32_t mask
= state
->enabled_mask
;
2793 unsigned i
= u_bit_scan(&mask
);
2794 if (state
->cb
[i
].buffer
== &rbuffer
->b
.b
) {
2796 state
->dirty_mask
|= 1 << i
;
2800 r600_constant_buffers_dirty(rctx
, state
);
2804 /* Texture buffer objects - update the virtual addresses in descriptors. */
2805 LIST_FOR_EACH_ENTRY(view
, &rctx
->b
.texture_buffers
, list
) {
2806 if (view
->base
.texture
== &rbuffer
->b
.b
) {
2807 unsigned stride
= util_format_get_blocksize(view
->base
.format
);
2808 uint64_t offset
= (uint64_t)view
->base
.u
.buf
.first_element
* stride
;
2809 uint64_t va
= rbuffer
->gpu_address
+ offset
;
2811 view
->tex_resource_words
[0] = va
;
2812 view
->tex_resource_words
[2] &= C_038008_BASE_ADDRESS_HI
;
2813 view
->tex_resource_words
[2] |= S_038008_BASE_ADDRESS_HI(va
>> 32);
2816 /* Texture buffer objects - make bindings dirty if needed. */
2817 for (shader
= 0; shader
< PIPE_SHADER_TYPES
; shader
++) {
2818 struct r600_samplerview_state
*state
= &rctx
->samplers
[shader
].views
;
2820 uint32_t mask
= state
->enabled_mask
;
2823 unsigned i
= u_bit_scan(&mask
);
2824 if (state
->views
[i
]->base
.texture
== &rbuffer
->b
.b
) {
2826 state
->dirty_mask
|= 1 << i
;
2830 r600_sampler_views_dirty(rctx
, state
);
2835 static void r600_set_occlusion_query_state(struct pipe_context
*ctx
, bool enable
)
2837 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2839 if (rctx
->db_misc_state
.occlusion_query_enabled
!= enable
) {
2840 rctx
->db_misc_state
.occlusion_query_enabled
= enable
;
2841 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
2845 static void r600_need_gfx_cs_space(struct pipe_context
*ctx
, unsigned num_dw
,
2846 bool include_draw_vbo
)
2848 r600_need_cs_space((struct r600_context
*)ctx
, num_dw
, include_draw_vbo
);
2851 /* keep this at the end of this file, please */
2852 void r600_init_common_state_functions(struct r600_context
*rctx
)
2854 rctx
->b
.b
.create_fs_state
= r600_create_ps_state
;
2855 rctx
->b
.b
.create_vs_state
= r600_create_vs_state
;
2856 rctx
->b
.b
.create_gs_state
= r600_create_gs_state
;
2857 rctx
->b
.b
.create_tcs_state
= r600_create_tcs_state
;
2858 rctx
->b
.b
.create_tes_state
= r600_create_tes_state
;
2859 rctx
->b
.b
.create_vertex_elements_state
= r600_create_vertex_fetch_shader
;
2860 rctx
->b
.b
.bind_blend_state
= r600_bind_blend_state
;
2861 rctx
->b
.b
.bind_depth_stencil_alpha_state
= r600_bind_dsa_state
;
2862 rctx
->b
.b
.bind_sampler_states
= r600_bind_sampler_states
;
2863 rctx
->b
.b
.bind_fs_state
= r600_bind_ps_state
;
2864 rctx
->b
.b
.bind_rasterizer_state
= r600_bind_rs_state
;
2865 rctx
->b
.b
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
2866 rctx
->b
.b
.bind_vs_state
= r600_bind_vs_state
;
2867 rctx
->b
.b
.bind_gs_state
= r600_bind_gs_state
;
2868 rctx
->b
.b
.bind_tcs_state
= r600_bind_tcs_state
;
2869 rctx
->b
.b
.bind_tes_state
= r600_bind_tes_state
;
2870 rctx
->b
.b
.delete_blend_state
= r600_delete_blend_state
;
2871 rctx
->b
.b
.delete_depth_stencil_alpha_state
= r600_delete_dsa_state
;
2872 rctx
->b
.b
.delete_fs_state
= r600_delete_ps_state
;
2873 rctx
->b
.b
.delete_rasterizer_state
= r600_delete_rs_state
;
2874 rctx
->b
.b
.delete_sampler_state
= r600_delete_sampler_state
;
2875 rctx
->b
.b
.delete_vertex_elements_state
= r600_delete_vertex_elements
;
2876 rctx
->b
.b
.delete_vs_state
= r600_delete_vs_state
;
2877 rctx
->b
.b
.delete_gs_state
= r600_delete_gs_state
;
2878 rctx
->b
.b
.delete_tcs_state
= r600_delete_tcs_state
;
2879 rctx
->b
.b
.delete_tes_state
= r600_delete_tes_state
;
2880 rctx
->b
.b
.set_blend_color
= r600_set_blend_color
;
2881 rctx
->b
.b
.set_clip_state
= r600_set_clip_state
;
2882 rctx
->b
.b
.set_constant_buffer
= r600_set_constant_buffer
;
2883 rctx
->b
.b
.set_sample_mask
= r600_set_sample_mask
;
2884 rctx
->b
.b
.set_stencil_ref
= r600_set_pipe_stencil_ref
;
2885 rctx
->b
.b
.set_viewport_states
= r600_set_viewport_states
;
2886 rctx
->b
.b
.set_vertex_buffers
= r600_set_vertex_buffers
;
2887 rctx
->b
.b
.set_index_buffer
= r600_set_index_buffer
;
2888 rctx
->b
.b
.set_sampler_views
= r600_set_sampler_views
;
2889 rctx
->b
.b
.sampler_view_destroy
= r600_sampler_view_destroy
;
2890 rctx
->b
.b
.texture_barrier
= r600_texture_barrier
;
2891 rctx
->b
.b
.set_stream_output_targets
= r600_set_streamout_targets
;
2892 rctx
->b
.b
.draw_vbo
= r600_draw_vbo
;
2893 rctx
->b
.invalidate_buffer
= r600_invalidate_buffer
;
2894 rctx
->b
.set_occlusion_query_state
= r600_set_occlusion_query_state
;
2895 rctx
->b
.need_gfx_cs_space
= r600_need_gfx_cs_space
;
2898 void r600_trace_emit(struct r600_context
*rctx
)
2900 struct r600_screen
*rscreen
= rctx
->screen
;
2901 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2905 va
= rscreen
->b
.trace_bo
->gpu_address
;
2906 reloc
= radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rscreen
->b
.trace_bo
,
2907 RADEON_USAGE_READWRITE
, RADEON_PRIO_TRACE
);
2908 radeon_emit(cs
, PKT3(PKT3_MEM_WRITE
, 3, 0));
2909 radeon_emit(cs
, va
& 0xFFFFFFFFUL
);
2910 radeon_emit(cs
, (va
>> 32UL) & 0xFFUL
);
2911 radeon_emit(cs
, cs
->cdw
);
2912 radeon_emit(cs
, rscreen
->b
.cs_count
);
2913 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2914 radeon_emit(cs
, reloc
);