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r600g: remove duplicated set_xx_resource functions
[mesa.git] / src / gallium / drivers / r600 / r600_state_common.c
1 /*
2 * Copyright 2010 Red Hat Inc.
3 * 2010 Jerome Glisse
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
26 */
27 #include "util/u_blitter.h"
28 #include "util/u_memory.h"
29 #include "util/u_format.h"
30 #include "pipebuffer/pb_buffer.h"
31 #include "pipe/p_shader_tokens.h"
32 #include "tgsi/tgsi_parse.h"
33 #include "r600_formats.h"
34 #include "r600_pipe.h"
35 #include "r600d.h"
36 #include "r600_hw_context_priv.h"
37
38 static void r600_emit_command_buffer(struct r600_context *rctx, struct r600_atom *atom)
39 {
40 struct radeon_winsys_cs *cs = rctx->cs;
41 struct r600_command_buffer *cb = (struct r600_command_buffer*)atom;
42
43 assert(cs->cdw + cb->atom.num_dw <= RADEON_MAX_CMDBUF_DWORDS);
44 memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->atom.num_dw);
45 cs->cdw += cb->atom.num_dw;
46 }
47
48 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags)
49 {
50 cb->atom.emit = r600_emit_command_buffer;
51 cb->atom.num_dw = 0;
52 cb->atom.flags = flags;
53 cb->buf = CALLOC(1, 4 * num_dw);
54 cb->max_num_dw = num_dw;
55 }
56
57 void r600_release_command_buffer(struct r600_command_buffer *cb)
58 {
59 FREE(cb->buf);
60 }
61
62 static void r600_emit_surface_sync(struct r600_context *rctx, struct r600_atom *atom)
63 {
64 struct radeon_winsys_cs *cs = rctx->cs;
65 struct r600_atom_surface_sync *a = (struct r600_atom_surface_sync*)atom;
66
67 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
68 cs->buf[cs->cdw++] = a->flush_flags; /* CP_COHER_CNTL */
69 cs->buf[cs->cdw++] = 0xffffffff; /* CP_COHER_SIZE */
70 cs->buf[cs->cdw++] = 0; /* CP_COHER_BASE */
71 cs->buf[cs->cdw++] = 0x0000000A; /* POLL_INTERVAL */
72
73 a->flush_flags = 0;
74 }
75
76 static void r600_emit_r6xx_flush_and_inv(struct r600_context *rctx, struct r600_atom *atom)
77 {
78 struct radeon_winsys_cs *cs = rctx->cs;
79 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
80 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
81 }
82
83 void r600_init_atom(struct r600_atom *atom,
84 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
85 unsigned num_dw, enum r600_atom_flags flags)
86 {
87 atom->emit = emit;
88 atom->num_dw = num_dw;
89 atom->flags = flags;
90 }
91
92 void r600_init_common_atoms(struct r600_context *rctx)
93 {
94 r600_init_atom(&rctx->atom_surface_sync.atom, r600_emit_surface_sync, 5, EMIT_EARLY);
95 r600_init_atom(&rctx->atom_r6xx_flush_and_inv, r600_emit_r6xx_flush_and_inv, 2, EMIT_EARLY);
96 }
97
98 unsigned r600_get_cb_flush_flags(struct r600_context *rctx)
99 {
100 unsigned flags = 0;
101
102 if (rctx->framebuffer.nr_cbufs) {
103 flags |= S_0085F0_CB_ACTION_ENA(1) |
104 (((1 << rctx->framebuffer.nr_cbufs) - 1) << S_0085F0_CB0_DEST_BASE_ENA_SHIFT);
105 }
106
107 /* Workaround for broken flushing on some R6xx chipsets. */
108 if (rctx->family == CHIP_RV670 ||
109 rctx->family == CHIP_RS780 ||
110 rctx->family == CHIP_RS880) {
111 flags |= S_0085F0_CB1_DEST_BASE_ENA(1) |
112 S_0085F0_DEST_BASE_0_ENA(1);
113 }
114 return flags;
115 }
116
117 void r600_texture_barrier(struct pipe_context *ctx)
118 {
119 struct r600_context *rctx = (struct r600_context *)ctx;
120
121 rctx->atom_surface_sync.flush_flags |= S_0085F0_TC_ACTION_ENA(1) | r600_get_cb_flush_flags(rctx);
122 r600_atom_dirty(rctx, &rctx->atom_surface_sync.atom);
123 }
124
125 static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
126 {
127 static const int prim_conv[] = {
128 V_008958_DI_PT_POINTLIST,
129 V_008958_DI_PT_LINELIST,
130 V_008958_DI_PT_LINELOOP,
131 V_008958_DI_PT_LINESTRIP,
132 V_008958_DI_PT_TRILIST,
133 V_008958_DI_PT_TRISTRIP,
134 V_008958_DI_PT_TRIFAN,
135 V_008958_DI_PT_QUADLIST,
136 V_008958_DI_PT_QUADSTRIP,
137 V_008958_DI_PT_POLYGON,
138 -1,
139 -1,
140 -1,
141 -1
142 };
143
144 *prim = prim_conv[pprim];
145 if (*prim == -1) {
146 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim);
147 return false;
148 }
149 return true;
150 }
151
152 /* common state between evergreen and r600 */
153 void r600_bind_blend_state(struct pipe_context *ctx, void *state)
154 {
155 struct r600_context *rctx = (struct r600_context *)ctx;
156 struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
157 struct r600_pipe_state *rstate;
158
159 if (state == NULL)
160 return;
161 rstate = &blend->rstate;
162 rctx->states[rstate->id] = rstate;
163 rctx->cb_target_mask = blend->cb_target_mask;
164
165 /* Replace every bit except MULTIWRITE_ENABLE. */
166 rctx->cb_color_control &= ~C_028808_MULTIWRITE_ENABLE;
167 rctx->cb_color_control |= blend->cb_color_control & C_028808_MULTIWRITE_ENABLE;
168
169 r600_context_pipe_state_set(rctx, rstate);
170 }
171
172 void r600_set_blend_color(struct pipe_context *ctx,
173 const struct pipe_blend_color *state)
174 {
175 struct r600_context *rctx = (struct r600_context *)ctx;
176 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
177
178 if (rstate == NULL)
179 return;
180
181 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
182 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), NULL, 0);
183 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), NULL, 0);
184 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), NULL, 0);
185 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), NULL, 0);
186
187 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
188 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
189 r600_context_pipe_state_set(rctx, rstate);
190 }
191
192 static void r600_set_stencil_ref(struct pipe_context *ctx,
193 const struct r600_stencil_ref *state)
194 {
195 struct r600_context *rctx = (struct r600_context *)ctx;
196 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
197
198 if (rstate == NULL)
199 return;
200
201 rstate->id = R600_PIPE_STATE_STENCIL_REF;
202 r600_pipe_state_add_reg(rstate,
203 R_028430_DB_STENCILREFMASK,
204 S_028430_STENCILREF(state->ref_value[0]) |
205 S_028430_STENCILMASK(state->valuemask[0]) |
206 S_028430_STENCILWRITEMASK(state->writemask[0]),
207 NULL, 0);
208 r600_pipe_state_add_reg(rstate,
209 R_028434_DB_STENCILREFMASK_BF,
210 S_028434_STENCILREF_BF(state->ref_value[1]) |
211 S_028434_STENCILMASK_BF(state->valuemask[1]) |
212 S_028434_STENCILWRITEMASK_BF(state->writemask[1]),
213 NULL, 0);
214
215 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
216 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
217 r600_context_pipe_state_set(rctx, rstate);
218 }
219
220 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
221 const struct pipe_stencil_ref *state)
222 {
223 struct r600_context *rctx = (struct r600_context *)ctx;
224 struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA];
225 struct r600_stencil_ref ref;
226
227 rctx->stencil_ref = *state;
228
229 if (!dsa)
230 return;
231
232 ref.ref_value[0] = state->ref_value[0];
233 ref.ref_value[1] = state->ref_value[1];
234 ref.valuemask[0] = dsa->valuemask[0];
235 ref.valuemask[1] = dsa->valuemask[1];
236 ref.writemask[0] = dsa->writemask[0];
237 ref.writemask[1] = dsa->writemask[1];
238
239 r600_set_stencil_ref(ctx, &ref);
240 }
241
242 void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
243 {
244 struct r600_context *rctx = (struct r600_context *)ctx;
245 struct r600_pipe_dsa *dsa = state;
246 struct r600_pipe_state *rstate;
247 struct r600_stencil_ref ref;
248
249 if (state == NULL)
250 return;
251 rstate = &dsa->rstate;
252 rctx->states[rstate->id] = rstate;
253 rctx->alpha_ref = dsa->alpha_ref;
254 rctx->alpha_ref_dirty = true;
255 r600_context_pipe_state_set(rctx, rstate);
256
257 ref.ref_value[0] = rctx->stencil_ref.ref_value[0];
258 ref.ref_value[1] = rctx->stencil_ref.ref_value[1];
259 ref.valuemask[0] = dsa->valuemask[0];
260 ref.valuemask[1] = dsa->valuemask[1];
261 ref.writemask[0] = dsa->writemask[0];
262 ref.writemask[1] = dsa->writemask[1];
263
264 r600_set_stencil_ref(ctx, &ref);
265
266 if (rctx->atom_db_misc_state.flush_depthstencil_enabled != dsa->is_flush) {
267 rctx->atom_db_misc_state.flush_depthstencil_enabled = dsa->is_flush;
268 r600_atom_dirty(rctx, &rctx->atom_db_misc_state.atom);
269 }
270 }
271
272 void r600_bind_rs_state(struct pipe_context *ctx, void *state)
273 {
274 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
275 struct r600_context *rctx = (struct r600_context *)ctx;
276
277 if (state == NULL)
278 return;
279
280 rctx->sprite_coord_enable = rs->sprite_coord_enable;
281 rctx->two_side = rs->two_side;
282 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
283 rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
284
285 rctx->rasterizer = rs;
286
287 rctx->states[rs->rstate.id] = &rs->rstate;
288 r600_context_pipe_state_set(rctx, &rs->rstate);
289
290 if (rctx->chip_class >= EVERGREEN) {
291 evergreen_polygon_offset_update(rctx);
292 } else {
293 r600_polygon_offset_update(rctx);
294 }
295 }
296
297 void r600_delete_rs_state(struct pipe_context *ctx, void *state)
298 {
299 struct r600_context *rctx = (struct r600_context *)ctx;
300 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
301
302 if (rctx->rasterizer == rs) {
303 rctx->rasterizer = NULL;
304 }
305 if (rctx->states[rs->rstate.id] == &rs->rstate) {
306 rctx->states[rs->rstate.id] = NULL;
307 }
308 free(rs);
309 }
310
311 void r600_sampler_view_destroy(struct pipe_context *ctx,
312 struct pipe_sampler_view *state)
313 {
314 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
315
316 pipe_resource_reference(&state->texture, NULL);
317 FREE(resource);
318 }
319
320 void r600_delete_state(struct pipe_context *ctx, void *state)
321 {
322 struct r600_context *rctx = (struct r600_context *)ctx;
323 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
324
325 if (rctx->states[rstate->id] == rstate) {
326 rctx->states[rstate->id] = NULL;
327 }
328 for (int i = 0; i < rstate->nregs; i++) {
329 pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL);
330 }
331 free(rstate);
332 }
333
334 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
335 {
336 struct r600_context *rctx = (struct r600_context *)ctx;
337 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
338
339 rctx->vertex_elements = v;
340 if (v) {
341 r600_inval_shader_cache(rctx);
342 u_vbuf_bind_vertex_elements(rctx->vbuf_mgr, state,
343 v->vmgr_elements);
344
345 rctx->states[v->rstate.id] = &v->rstate;
346 r600_context_pipe_state_set(rctx, &v->rstate);
347 }
348 }
349
350 void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
351 {
352 struct r600_context *rctx = (struct r600_context *)ctx;
353 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
354
355 if (rctx->states[v->rstate.id] == &v->rstate) {
356 rctx->states[v->rstate.id] = NULL;
357 }
358 if (rctx->vertex_elements == state)
359 rctx->vertex_elements = NULL;
360
361 pipe_resource_reference((struct pipe_resource**)&v->fetch_shader, NULL);
362 u_vbuf_destroy_vertex_elements(rctx->vbuf_mgr, v->vmgr_elements);
363 FREE(state);
364 }
365
366
367 void r600_set_index_buffer(struct pipe_context *ctx,
368 const struct pipe_index_buffer *ib)
369 {
370 struct r600_context *rctx = (struct r600_context *)ctx;
371
372 u_vbuf_set_index_buffer(rctx->vbuf_mgr, ib);
373 }
374
375 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
376 const struct pipe_vertex_buffer *buffers)
377 {
378 struct r600_context *rctx = (struct r600_context *)ctx;
379 int i;
380
381 /* Zero states. */
382 for (i = 0; i < count; i++) {
383 if (!buffers[i].buffer) {
384 r600_context_pipe_state_set_fs_resource(rctx, NULL, i);
385 }
386 }
387 for (; i < rctx->vbuf_mgr->nr_real_vertex_buffers; i++) {
388 r600_context_pipe_state_set_fs_resource(rctx, NULL, i);
389 }
390
391 u_vbuf_set_vertex_buffers(rctx->vbuf_mgr, count, buffers);
392 }
393
394 void *r600_create_vertex_elements(struct pipe_context *ctx,
395 unsigned count,
396 const struct pipe_vertex_element *elements)
397 {
398 struct r600_context *rctx = (struct r600_context *)ctx;
399 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
400
401 assert(count < 32);
402 if (!v)
403 return NULL;
404
405 v->count = count;
406 v->vmgr_elements =
407 u_vbuf_create_vertex_elements(rctx->vbuf_mgr, count,
408 elements, v->elements);
409
410 if (r600_vertex_elements_build_fetch_shader(rctx, v)) {
411 FREE(v);
412 return NULL;
413 }
414
415 return v;
416 }
417
418 void *r600_create_shader_state(struct pipe_context *ctx,
419 const struct pipe_shader_state *state)
420 {
421 struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader);
422 int r;
423
424 shader->tokens = tgsi_dup_tokens(state->tokens);
425 shader->so = state->stream_output;
426
427 r = r600_pipe_shader_create(ctx, shader);
428 if (r) {
429 return NULL;
430 }
431 return shader;
432 }
433
434 void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
435 {
436 struct r600_context *rctx = (struct r600_context *)ctx;
437
438 /* TODO delete old shader */
439 rctx->ps_shader = (struct r600_pipe_shader *)state;
440 if (state) {
441 r600_inval_shader_cache(rctx);
442 r600_context_pipe_state_set(rctx, &rctx->ps_shader->rstate);
443
444 rctx->cb_color_control &= C_028808_MULTIWRITE_ENABLE;
445 rctx->cb_color_control |= S_028808_MULTIWRITE_ENABLE(!!rctx->ps_shader->shader.fs_write_all);
446 }
447 if (rctx->ps_shader && rctx->vs_shader) {
448 r600_adjust_gprs(rctx);
449 }
450 }
451
452 void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
453 {
454 struct r600_context *rctx = (struct r600_context *)ctx;
455
456 /* TODO delete old shader */
457 rctx->vs_shader = (struct r600_pipe_shader *)state;
458 if (state) {
459 r600_inval_shader_cache(rctx);
460 r600_context_pipe_state_set(rctx, &rctx->vs_shader->rstate);
461 }
462 if (rctx->ps_shader && rctx->vs_shader) {
463 r600_adjust_gprs(rctx);
464 }
465 }
466
467 void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
468 {
469 struct r600_context *rctx = (struct r600_context *)ctx;
470 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
471
472 if (rctx->ps_shader == shader) {
473 rctx->ps_shader = NULL;
474 }
475
476 free(shader->tokens);
477 r600_pipe_shader_destroy(ctx, shader);
478 free(shader);
479 }
480
481 void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
482 {
483 struct r600_context *rctx = (struct r600_context *)ctx;
484 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
485
486 if (rctx->vs_shader == shader) {
487 rctx->vs_shader = NULL;
488 }
489
490 free(shader->tokens);
491 r600_pipe_shader_destroy(ctx, shader);
492 free(shader);
493 }
494
495 static void r600_update_alpha_ref(struct r600_context *rctx)
496 {
497 unsigned alpha_ref;
498 struct r600_pipe_state rstate;
499
500 alpha_ref = rctx->alpha_ref;
501 rstate.nregs = 0;
502 if (rctx->export_16bpc)
503 alpha_ref &= ~0x1FFF;
504 r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref, NULL, 0);
505
506 r600_context_pipe_state_set(rctx, &rstate);
507 rctx->alpha_ref_dirty = false;
508 }
509
510 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
511 struct pipe_resource *buffer)
512 {
513 struct r600_context *rctx = (struct r600_context *)ctx;
514 struct r600_resource *rbuffer = r600_resource(buffer);
515 struct r600_pipe_resource_state *rstate;
516 uint64_t va_offset;
517 uint32_t offset;
518
519 /* Note that the state tracker can unbind constant buffers by
520 * passing NULL here.
521 */
522 if (buffer == NULL) {
523 return;
524 }
525
526 r600_inval_shader_cache(rctx);
527
528 r600_upload_const_buffer(rctx, &rbuffer, &offset);
529 va_offset = r600_resource_va(ctx->screen, (void*)rbuffer);
530 va_offset += offset;
531 va_offset >>= 8;
532
533 switch (shader) {
534 case PIPE_SHADER_VERTEX:
535 rctx->vs_const_buffer.nregs = 0;
536 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
537 R_028180_ALU_CONST_BUFFER_SIZE_VS_0 + index * 4,
538 ALIGN_DIVUP(buffer->width0 >> 4, 16),
539 NULL, 0);
540 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
541 R_028980_ALU_CONST_CACHE_VS_0 + index * 4,
542 va_offset, rbuffer, RADEON_USAGE_READ);
543 r600_context_pipe_state_set(rctx, &rctx->vs_const_buffer);
544
545 rstate = &rctx->vs_const_buffer_resource[index];
546 if (!rstate->id) {
547 if (rctx->chip_class >= EVERGREEN) {
548 evergreen_pipe_init_buffer_resource(rctx, rstate);
549 } else {
550 r600_pipe_init_buffer_resource(rctx, rstate);
551 }
552 }
553
554 if (rctx->chip_class >= EVERGREEN) {
555 evergreen_pipe_mod_buffer_resource(ctx, rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
556 } else {
557 r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
558 }
559 r600_context_pipe_state_set_vs_resource(rctx, rstate, index);
560 break;
561 case PIPE_SHADER_FRAGMENT:
562 rctx->ps_const_buffer.nregs = 0;
563 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
564 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
565 ALIGN_DIVUP(buffer->width0 >> 4, 16),
566 NULL, 0);
567 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
568 R_028940_ALU_CONST_CACHE_PS_0,
569 va_offset, rbuffer, RADEON_USAGE_READ);
570 r600_context_pipe_state_set(rctx, &rctx->ps_const_buffer);
571
572 rstate = &rctx->ps_const_buffer_resource[index];
573 if (!rstate->id) {
574 if (rctx->chip_class >= EVERGREEN) {
575 evergreen_pipe_init_buffer_resource(rctx, rstate);
576 } else {
577 r600_pipe_init_buffer_resource(rctx, rstate);
578 }
579 }
580 if (rctx->chip_class >= EVERGREEN) {
581 evergreen_pipe_mod_buffer_resource(ctx, rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
582 } else {
583 r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
584 }
585 r600_context_pipe_state_set_ps_resource(rctx, rstate, index);
586 break;
587 default:
588 R600_ERR("unsupported %d\n", shader);
589 return;
590 }
591
592 if (buffer != &rbuffer->b.b.b)
593 pipe_resource_reference((struct pipe_resource**)&rbuffer, NULL);
594 }
595
596 struct pipe_stream_output_target *
597 r600_create_so_target(struct pipe_context *ctx,
598 struct pipe_resource *buffer,
599 unsigned buffer_offset,
600 unsigned buffer_size)
601 {
602 struct r600_context *rctx = (struct r600_context *)ctx;
603 struct r600_so_target *t;
604 void *ptr;
605
606 t = CALLOC_STRUCT(r600_so_target);
607 if (!t) {
608 return NULL;
609 }
610
611 t->b.reference.count = 1;
612 t->b.context = ctx;
613 pipe_resource_reference(&t->b.buffer, buffer);
614 t->b.buffer_offset = buffer_offset;
615 t->b.buffer_size = buffer_size;
616
617 t->filled_size = (struct r600_resource*)
618 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4);
619 ptr = rctx->ws->buffer_map(t->filled_size->buf, rctx->cs, PIPE_TRANSFER_WRITE);
620 memset(ptr, 0, t->filled_size->buf->size);
621 rctx->ws->buffer_unmap(t->filled_size->buf);
622
623 return &t->b;
624 }
625
626 void r600_so_target_destroy(struct pipe_context *ctx,
627 struct pipe_stream_output_target *target)
628 {
629 struct r600_so_target *t = (struct r600_so_target*)target;
630 pipe_resource_reference(&t->b.buffer, NULL);
631 pipe_resource_reference((struct pipe_resource**)&t->filled_size, NULL);
632 FREE(t);
633 }
634
635 void r600_set_so_targets(struct pipe_context *ctx,
636 unsigned num_targets,
637 struct pipe_stream_output_target **targets,
638 unsigned append_bitmask)
639 {
640 struct r600_context *rctx = (struct r600_context *)ctx;
641 unsigned i;
642
643 /* Stop streamout. */
644 if (rctx->num_so_targets) {
645 r600_context_streamout_end(rctx);
646 }
647
648 /* Set the new targets. */
649 for (i = 0; i < num_targets; i++) {
650 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]);
651 }
652 for (; i < rctx->num_so_targets; i++) {
653 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL);
654 }
655
656 rctx->num_so_targets = num_targets;
657 rctx->streamout_start = num_targets != 0;
658 rctx->streamout_append_bitmask = append_bitmask;
659 }
660
661 static void r600_vertex_buffer_update(struct r600_context *rctx)
662 {
663 struct r600_pipe_resource_state *rstate;
664 struct r600_resource *rbuffer;
665 struct pipe_vertex_buffer *vertex_buffer;
666 unsigned i, count, offset;
667
668 r600_inval_vertex_cache(rctx);
669
670 if (rctx->vertex_elements->vbuffer_need_offset) {
671 /* one resource per vertex elements */
672 count = rctx->vertex_elements->count;
673 } else {
674 /* bind vertex buffer once */
675 count = rctx->vbuf_mgr->nr_real_vertex_buffers;
676 }
677
678 for (i = 0 ; i < count; i++) {
679 rstate = &rctx->fs_resource[i];
680
681 if (rctx->vertex_elements->vbuffer_need_offset) {
682 /* one resource per vertex elements */
683 unsigned vbuffer_index;
684 vbuffer_index = rctx->vertex_elements->elements[i].vertex_buffer_index;
685 vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[vbuffer_index];
686 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
687 offset = rctx->vertex_elements->vbuffer_offset[i];
688 } else {
689 /* bind vertex buffer once */
690 vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[i];
691 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
692 offset = 0;
693 }
694 if (vertex_buffer == NULL || rbuffer == NULL)
695 continue;
696 offset += vertex_buffer->buffer_offset;
697
698 if (!rstate->id) {
699 if (rctx->chip_class >= EVERGREEN) {
700 evergreen_pipe_init_buffer_resource(rctx, rstate);
701 } else {
702 r600_pipe_init_buffer_resource(rctx, rstate);
703 }
704 }
705
706 if (rctx->chip_class >= EVERGREEN) {
707 evergreen_pipe_mod_buffer_resource(&rctx->context, rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ);
708 } else {
709 r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ);
710 }
711 r600_context_pipe_state_set_fs_resource(rctx, rstate, i);
712 }
713 }
714
715 static int r600_shader_rebuild(struct pipe_context * ctx, struct r600_pipe_shader * shader)
716 {
717 struct r600_context *rctx = (struct r600_context *)ctx;
718 int r;
719
720 r600_pipe_shader_destroy(ctx, shader);
721 r = r600_pipe_shader_create(ctx, shader);
722 if (r) {
723 return r;
724 }
725 r600_context_pipe_state_set(rctx, &shader->rstate);
726
727 return 0;
728 }
729
730 static void r600_update_derived_state(struct r600_context *rctx)
731 {
732 struct pipe_context * ctx = (struct pipe_context*)rctx;
733 struct r600_pipe_state rstate;
734
735 rstate.nregs = 0;
736
737 if (rstate.nregs)
738 r600_context_pipe_state_set(rctx, &rstate);
739
740 if (!rctx->blitter->running) {
741 if (rctx->have_depth_fb || rctx->have_depth_texture)
742 r600_flush_depth_textures(rctx);
743 }
744
745 if (rctx->chip_class < EVERGREEN) {
746 r600_update_sampler_states(rctx);
747 }
748
749 if ((rctx->ps_shader->shader.two_side != rctx->two_side) ||
750 ((rctx->chip_class >= EVERGREEN) && rctx->ps_shader->shader.fs_write_all &&
751 (rctx->ps_shader->shader.nr_cbufs != rctx->nr_cbufs))) {
752 r600_shader_rebuild(&rctx->context, rctx->ps_shader);
753 }
754
755 if (rctx->alpha_ref_dirty) {
756 r600_update_alpha_ref(rctx);
757 }
758
759 if (rctx->ps_shader && ((rctx->sprite_coord_enable &&
760 (rctx->ps_shader->sprite_coord_enable != rctx->sprite_coord_enable)) ||
761 (rctx->rasterizer && rctx->rasterizer->flatshade != rctx->ps_shader->flatshade))) {
762
763 if (rctx->chip_class >= EVERGREEN)
764 evergreen_pipe_shader_ps(ctx, rctx->ps_shader);
765 else
766 r600_pipe_shader_ps(ctx, rctx->ps_shader);
767
768 r600_context_pipe_state_set(rctx, &rctx->ps_shader->rstate);
769 }
770
771 }
772
773 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
774 {
775 struct r600_context *rctx = (struct r600_context *)ctx;
776 struct pipe_draw_info info = *dinfo;
777 struct pipe_index_buffer ib = {};
778 unsigned prim, mask, ls_mask = 0;
779 struct r600_block *dirty_block = NULL, *next_block = NULL;
780 struct r600_atom *state = NULL, *next_state = NULL;
781 struct radeon_winsys_cs *cs = rctx->cs;
782 uint64_t va;
783
784 if ((!info.count && (info.indexed || !info.count_from_stream_output)) ||
785 (info.indexed && !rctx->vbuf_mgr->index_buffer.buffer) ||
786 !r600_conv_pipe_prim(info.mode, &prim)) {
787 return;
788 }
789
790 if (!rctx->ps_shader || !rctx->vs_shader)
791 return;
792
793 r600_update_derived_state(rctx);
794
795 u_vbuf_draw_begin(rctx->vbuf_mgr, &info);
796 r600_vertex_buffer_update(rctx);
797
798 if (info.indexed) {
799 /* Initialize the index buffer struct. */
800 pipe_resource_reference(&ib.buffer, rctx->vbuf_mgr->index_buffer.buffer);
801 ib.index_size = rctx->vbuf_mgr->index_buffer.index_size;
802 ib.offset = rctx->vbuf_mgr->index_buffer.offset + info.start * ib.index_size;
803
804 /* Translate or upload, if needed. */
805 r600_translate_index_buffer(rctx, &ib, info.count);
806
807 if (u_vbuf_resource(ib.buffer)->user_ptr) {
808 r600_upload_index_buffer(rctx, &ib, info.count);
809 }
810 } else {
811 info.index_bias = info.start;
812 if (info.count_from_stream_output) {
813 r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info.count_from_stream_output);
814 }
815 }
816
817 mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
818
819 if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
820 rctx->vgt.id = R600_PIPE_STATE_VGT;
821 rctx->vgt.nregs = 0;
822 r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, NULL, 0);
823 r600_pipe_state_add_reg(&rctx->vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, NULL, 0);
824 r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias, NULL, 0);
825 r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index, NULL, 0);
826 r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart, NULL, 0);
827 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance, NULL, 0);
828 r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0, NULL, 0);
829 if (rctx->chip_class <= R700)
830 r600_pipe_state_add_reg(&rctx->vgt, R_028808_CB_COLOR_CONTROL, rctx->cb_color_control, NULL, 0);
831 r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0, NULL, 0);
832 r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0, NULL, 0);
833 }
834
835 rctx->vgt.nregs = 0;
836 r600_pipe_state_mod_reg(&rctx->vgt, prim);
837 r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_target_mask & mask);
838 r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
839 r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
840 r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart);
841 r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance);
842
843 if (prim == V_008958_DI_PT_LINELIST)
844 ls_mask = 1;
845 else if (prim == V_008958_DI_PT_LINESTRIP)
846 ls_mask = 2;
847 r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask) | rctx->pa_sc_line_stipple);
848 if (rctx->chip_class <= R700)
849 r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_color_control);
850 r600_pipe_state_mod_reg(&rctx->vgt,
851 rctx->vs_shader->pa_cl_vs_out_cntl |
852 (rctx->rasterizer->clip_plane_enable & rctx->vs_shader->shader.clip_dist_write));
853 r600_pipe_state_mod_reg(&rctx->vgt,
854 rctx->pa_cl_clip_cntl |
855 (rctx->vs_shader->shader.clip_dist_write ||
856 rctx->vs_shader->shader.vs_prohibit_ucps ?
857 0 : rctx->rasterizer->clip_plane_enable & 0x3F));
858
859 r600_context_pipe_state_set(rctx, &rctx->vgt);
860
861 /* Emit states (the function expects that we emit at most 17 dwords here). */
862 r600_need_cs_space(rctx, 0, TRUE);
863
864 LIST_FOR_EACH_ENTRY_SAFE(state, next_state, &rctx->dirty_states, head) {
865 r600_emit_atom(rctx, state);
866 }
867 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) {
868 r600_context_block_emit_dirty(rctx, dirty_block);
869 }
870 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->resource_dirty,list) {
871 r600_context_block_resource_emit_dirty(rctx, dirty_block);
872 }
873 rctx->pm4_dirty_cdwords = 0;
874
875 /* Enable stream out if needed. */
876 if (rctx->streamout_start) {
877 r600_context_streamout_begin(rctx);
878 rctx->streamout_start = FALSE;
879 }
880
881 /* draw packet */
882 cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->predicate_drawing);
883 cs->buf[cs->cdw++] = ib.index_size == 4 ?
884 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
885 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
886 cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->predicate_drawing);
887 cs->buf[cs->cdw++] = info.instance_count;
888 if (info.indexed) {
889 va = r600_resource_va(ctx->screen, ib.buffer);
890 va += ib.offset;
891 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->predicate_drawing);
892 cs->buf[cs->cdw++] = va;
893 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
894 cs->buf[cs->cdw++] = info.count;
895 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
896 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->predicate_drawing);
897 cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
898 } else {
899 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->predicate_drawing);
900 cs->buf[cs->cdw++] = info.count;
901 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
902 (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
903 }
904
905 rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING;
906
907 if (rctx->framebuffer.zsbuf)
908 {
909 struct pipe_resource *tex = rctx->framebuffer.zsbuf->texture;
910 ((struct r600_resource_texture *)tex)->dirty_db = TRUE;
911 }
912
913 pipe_resource_reference(&ib.buffer, NULL);
914 u_vbuf_draw_end(rctx->vbuf_mgr);
915 }
916
917 void _r600_pipe_state_add_reg(struct r600_context *ctx,
918 struct r600_pipe_state *state,
919 uint32_t offset, uint32_t value,
920 uint32_t range_id, uint32_t block_id,
921 struct r600_resource *bo,
922 enum radeon_bo_usage usage)
923 {
924 struct r600_range *range;
925 struct r600_block *block;
926
927 if (bo) assert(usage);
928
929 range = &ctx->range[range_id];
930 block = range->blocks[block_id];
931 state->regs[state->nregs].block = block;
932 state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
933
934 state->regs[state->nregs].value = value;
935 state->regs[state->nregs].bo = bo;
936 state->regs[state->nregs].bo_usage = usage;
937
938 state->nregs++;
939 assert(state->nregs < R600_BLOCK_MAX_REG);
940 }
941
942 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
943 uint32_t offset, uint32_t value,
944 struct r600_resource *bo,
945 enum radeon_bo_usage usage)
946 {
947 if (bo) assert(usage);
948
949 state->regs[state->nregs].id = offset;
950 state->regs[state->nregs].block = NULL;
951 state->regs[state->nregs].value = value;
952 state->regs[state->nregs].bo = bo;
953 state->regs[state->nregs].bo_usage = usage;
954
955 state->nregs++;
956 assert(state->nregs < R600_BLOCK_MAX_REG);
957 }
958
959 uint32_t r600_translate_stencil_op(int s_op)
960 {
961 switch (s_op) {
962 case PIPE_STENCIL_OP_KEEP:
963 return V_028800_STENCIL_KEEP;
964 case PIPE_STENCIL_OP_ZERO:
965 return V_028800_STENCIL_ZERO;
966 case PIPE_STENCIL_OP_REPLACE:
967 return V_028800_STENCIL_REPLACE;
968 case PIPE_STENCIL_OP_INCR:
969 return V_028800_STENCIL_INCR;
970 case PIPE_STENCIL_OP_DECR:
971 return V_028800_STENCIL_DECR;
972 case PIPE_STENCIL_OP_INCR_WRAP:
973 return V_028800_STENCIL_INCR_WRAP;
974 case PIPE_STENCIL_OP_DECR_WRAP:
975 return V_028800_STENCIL_DECR_WRAP;
976 case PIPE_STENCIL_OP_INVERT:
977 return V_028800_STENCIL_INVERT;
978 default:
979 R600_ERR("Unknown stencil op %d", s_op);
980 assert(0);
981 break;
982 }
983 return 0;
984 }
985
986 uint32_t r600_translate_fill(uint32_t func)
987 {
988 switch(func) {
989 case PIPE_POLYGON_MODE_FILL:
990 return 2;
991 case PIPE_POLYGON_MODE_LINE:
992 return 1;
993 case PIPE_POLYGON_MODE_POINT:
994 return 0;
995 default:
996 assert(0);
997 return 0;
998 }
999 }
1000
1001 unsigned r600_tex_wrap(unsigned wrap)
1002 {
1003 switch (wrap) {
1004 default:
1005 case PIPE_TEX_WRAP_REPEAT:
1006 return V_03C000_SQ_TEX_WRAP;
1007 case PIPE_TEX_WRAP_CLAMP:
1008 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1009 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1010 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1011 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1012 return V_03C000_SQ_TEX_CLAMP_BORDER;
1013 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1014 return V_03C000_SQ_TEX_MIRROR;
1015 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1016 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1017 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1018 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1019 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1020 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1021 }
1022 }
1023
1024 unsigned r600_tex_filter(unsigned filter)
1025 {
1026 switch (filter) {
1027 default:
1028 case PIPE_TEX_FILTER_NEAREST:
1029 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1030 case PIPE_TEX_FILTER_LINEAR:
1031 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1032 }
1033 }
1034
1035 unsigned r600_tex_mipfilter(unsigned filter)
1036 {
1037 switch (filter) {
1038 case PIPE_TEX_MIPFILTER_NEAREST:
1039 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1040 case PIPE_TEX_MIPFILTER_LINEAR:
1041 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1042 default:
1043 case PIPE_TEX_MIPFILTER_NONE:
1044 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1045 }
1046 }
1047
1048 unsigned r600_tex_compare(unsigned compare)
1049 {
1050 switch (compare) {
1051 default:
1052 case PIPE_FUNC_NEVER:
1053 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1054 case PIPE_FUNC_LESS:
1055 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1056 case PIPE_FUNC_EQUAL:
1057 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1058 case PIPE_FUNC_LEQUAL:
1059 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1060 case PIPE_FUNC_GREATER:
1061 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1062 case PIPE_FUNC_NOTEQUAL:
1063 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1064 case PIPE_FUNC_GEQUAL:
1065 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1066 case PIPE_FUNC_ALWAYS:
1067 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1068 }
1069 }