2 * Copyright 2010 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
27 #include "r600_formats.h"
30 #include "util/u_draw_quad.h"
31 #include "util/u_upload_mgr.h"
32 #include "tgsi/tgsi_parse.h"
35 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
37 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
)
39 cb
->buf
= CALLOC(1, 4 * num_dw
);
40 cb
->max_num_dw
= num_dw
;
43 void r600_release_command_buffer(struct r600_command_buffer
*cb
)
48 void r600_init_atom(struct r600_context
*rctx
,
49 struct r600_atom
*atom
,
51 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
54 assert(id
< R600_NUM_ATOMS
);
55 assert(rctx
->atoms
[id
] == NULL
);
56 rctx
->atoms
[id
] = atom
;
59 atom
->num_dw
= num_dw
;
63 void r600_emit_cso_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
65 r600_emit_command_buffer(rctx
->cs
, ((struct r600_cso_state
*)atom
)->cb
);
68 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
70 struct radeon_winsys_cs
*cs
= rctx
->cs
;
71 struct r600_alphatest_state
*a
= (struct r600_alphatest_state
*)atom
;
72 unsigned alpha_ref
= a
->sx_alpha_ref
;
74 if (rctx
->chip_class
>= EVERGREEN
&& a
->cb0_export_16bpc
) {
78 r600_write_context_reg(cs
, R_028410_SX_ALPHA_TEST_CONTROL
,
79 a
->sx_alpha_test_control
|
80 S_028410_ALPHA_TEST_BYPASS(a
->bypass
));
81 r600_write_context_reg(cs
, R_028438_SX_ALPHA_REF
, alpha_ref
);
84 static void r600_texture_barrier(struct pipe_context
*ctx
)
86 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
88 rctx
->flags
|= R600_CONTEXT_CB_FLUSH
| R600_CONTEXT_TEX_FLUSH
;
91 if (rctx
->chip_class
== R600
) {
92 rctx
->flags
|= R600_CONTEXT_FLUSH_AND_INV
;
96 static unsigned r600_conv_pipe_prim(unsigned prim
)
98 static const unsigned prim_conv
[] = {
99 V_008958_DI_PT_POINTLIST
,
100 V_008958_DI_PT_LINELIST
,
101 V_008958_DI_PT_LINELOOP
,
102 V_008958_DI_PT_LINESTRIP
,
103 V_008958_DI_PT_TRILIST
,
104 V_008958_DI_PT_TRISTRIP
,
105 V_008958_DI_PT_TRIFAN
,
106 V_008958_DI_PT_QUADLIST
,
107 V_008958_DI_PT_QUADSTRIP
,
108 V_008958_DI_PT_POLYGON
,
109 V_008958_DI_PT_LINELIST_ADJ
,
110 V_008958_DI_PT_LINESTRIP_ADJ
,
111 V_008958_DI_PT_TRILIST_ADJ
,
112 V_008958_DI_PT_TRISTRIP_ADJ
,
113 V_008958_DI_PT_RECTLIST
115 return prim_conv
[prim
];
118 /* common state between evergreen and r600 */
120 static void r600_bind_blend_state_internal(struct r600_context
*rctx
,
121 struct r600_blend_state
*blend
, bool blend_disable
)
123 unsigned color_control
;
124 bool update_cb
= false;
126 rctx
->alpha_to_one
= blend
->alpha_to_one
;
127 rctx
->dual_src_blend
= blend
->dual_src_blend
;
129 if (!blend_disable
) {
130 r600_set_cso_state_with_cb(&rctx
->blend_state
, blend
, &blend
->buffer
);
131 color_control
= blend
->cb_color_control
;
133 /* Blending is disabled. */
134 r600_set_cso_state_with_cb(&rctx
->blend_state
, blend
, &blend
->buffer_no_blend
);
135 color_control
= blend
->cb_color_control_no_blend
;
138 /* Update derived states. */
139 if (rctx
->cb_misc_state
.blend_colormask
!= blend
->cb_target_mask
) {
140 rctx
->cb_misc_state
.blend_colormask
= blend
->cb_target_mask
;
143 if (rctx
->chip_class
<= R700
&&
144 rctx
->cb_misc_state
.cb_color_control
!= color_control
) {
145 rctx
->cb_misc_state
.cb_color_control
= color_control
;
148 if (rctx
->cb_misc_state
.dual_src_blend
!= blend
->dual_src_blend
) {
149 rctx
->cb_misc_state
.dual_src_blend
= blend
->dual_src_blend
;
153 rctx
->cb_misc_state
.atom
.dirty
= true;
157 static void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
)
159 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
160 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
165 r600_bind_blend_state_internal(rctx
, blend
, rctx
->force_blend_disable
);
168 static void r600_set_blend_color(struct pipe_context
*ctx
,
169 const struct pipe_blend_color
*state
)
171 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
173 rctx
->blend_color
.state
= *state
;
174 rctx
->blend_color
.atom
.dirty
= true;
177 void r600_emit_blend_color(struct r600_context
*rctx
, struct r600_atom
*atom
)
179 struct radeon_winsys_cs
*cs
= rctx
->cs
;
180 struct pipe_blend_color
*state
= &rctx
->blend_color
.state
;
182 r600_write_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
183 r600_write_value(cs
, fui(state
->color
[0])); /* R_028414_CB_BLEND_RED */
184 r600_write_value(cs
, fui(state
->color
[1])); /* R_028418_CB_BLEND_GREEN */
185 r600_write_value(cs
, fui(state
->color
[2])); /* R_02841C_CB_BLEND_BLUE */
186 r600_write_value(cs
, fui(state
->color
[3])); /* R_028420_CB_BLEND_ALPHA */
189 void r600_emit_vgt_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
191 struct radeon_winsys_cs
*cs
= rctx
->cs
;
192 struct r600_vgt_state
*a
= (struct r600_vgt_state
*)atom
;
194 r600_write_context_reg(cs
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, a
->vgt_multi_prim_ib_reset_en
);
195 r600_write_context_reg(cs
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
, a
->vgt_multi_prim_ib_reset_indx
);
198 void r600_emit_vgt2_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
200 struct radeon_winsys_cs
*cs
= rctx
->cs
;
201 struct r600_vgt2_state
*a
= (struct r600_vgt2_state
*)atom
;
203 r600_write_context_reg(cs
, R_028408_VGT_INDX_OFFSET
, a
->vgt_indx_offset
);
206 static void r600_set_clip_state(struct pipe_context
*ctx
,
207 const struct pipe_clip_state
*state
)
209 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
210 struct pipe_constant_buffer cb
;
212 rctx
->clip_state
.state
= *state
;
213 rctx
->clip_state
.atom
.dirty
= true;
216 cb
.user_buffer
= state
->ucp
;
217 cb
.buffer_offset
= 0;
218 cb
.buffer_size
= 4*4*8;
219 ctx
->set_constant_buffer(ctx
, PIPE_SHADER_VERTEX
, 1, &cb
);
220 pipe_resource_reference(&cb
.buffer
, NULL
);
223 static void r600_set_stencil_ref(struct pipe_context
*ctx
,
224 const struct r600_stencil_ref
*state
)
226 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
228 rctx
->stencil_ref
.state
= *state
;
229 rctx
->stencil_ref
.atom
.dirty
= true;
232 void r600_emit_stencil_ref(struct r600_context
*rctx
, struct r600_atom
*atom
)
234 struct radeon_winsys_cs
*cs
= rctx
->cs
;
235 struct r600_stencil_ref_state
*a
= (struct r600_stencil_ref_state
*)atom
;
237 r600_write_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
238 r600_write_value(cs
, /* R_028430_DB_STENCILREFMASK */
239 S_028430_STENCILREF(a
->state
.ref_value
[0]) |
240 S_028430_STENCILMASK(a
->state
.valuemask
[0]) |
241 S_028430_STENCILWRITEMASK(a
->state
.writemask
[0]));
242 r600_write_value(cs
, /* R_028434_DB_STENCILREFMASK_BF */
243 S_028434_STENCILREF_BF(a
->state
.ref_value
[1]) |
244 S_028434_STENCILMASK_BF(a
->state
.valuemask
[1]) |
245 S_028434_STENCILWRITEMASK_BF(a
->state
.writemask
[1]));
248 static void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
249 const struct pipe_stencil_ref
*state
)
251 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
252 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)rctx
->dsa_state
.cso
;
253 struct r600_stencil_ref ref
;
255 rctx
->stencil_ref
.pipe_state
= *state
;
260 ref
.ref_value
[0] = state
->ref_value
[0];
261 ref
.ref_value
[1] = state
->ref_value
[1];
262 ref
.valuemask
[0] = dsa
->valuemask
[0];
263 ref
.valuemask
[1] = dsa
->valuemask
[1];
264 ref
.writemask
[0] = dsa
->writemask
[0];
265 ref
.writemask
[1] = dsa
->writemask
[1];
267 r600_set_stencil_ref(ctx
, &ref
);
270 static void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
272 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
273 struct r600_dsa_state
*dsa
= state
;
274 struct r600_stencil_ref ref
;
279 r600_set_cso_state_with_cb(&rctx
->dsa_state
, dsa
, &dsa
->buffer
);
281 ref
.ref_value
[0] = rctx
->stencil_ref
.pipe_state
.ref_value
[0];
282 ref
.ref_value
[1] = rctx
->stencil_ref
.pipe_state
.ref_value
[1];
283 ref
.valuemask
[0] = dsa
->valuemask
[0];
284 ref
.valuemask
[1] = dsa
->valuemask
[1];
285 ref
.writemask
[0] = dsa
->writemask
[0];
286 ref
.writemask
[1] = dsa
->writemask
[1];
288 r600_set_stencil_ref(ctx
, &ref
);
290 /* Update alphatest state. */
291 if (rctx
->alphatest_state
.sx_alpha_test_control
!= dsa
->sx_alpha_test_control
||
292 rctx
->alphatest_state
.sx_alpha_ref
!= dsa
->alpha_ref
) {
293 rctx
->alphatest_state
.sx_alpha_test_control
= dsa
->sx_alpha_test_control
;
294 rctx
->alphatest_state
.sx_alpha_ref
= dsa
->alpha_ref
;
295 rctx
->alphatest_state
.atom
.dirty
= true;
299 static void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
)
301 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
302 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
307 rctx
->rasterizer
= rs
;
309 r600_set_cso_state_with_cb(&rctx
->rasterizer_state
, rs
, &rs
->buffer
);
311 if (rs
->offset_enable
&&
312 (rs
->offset_units
!= rctx
->poly_offset_state
.offset_units
||
313 rs
->offset_scale
!= rctx
->poly_offset_state
.offset_scale
)) {
314 rctx
->poly_offset_state
.offset_units
= rs
->offset_units
;
315 rctx
->poly_offset_state
.offset_scale
= rs
->offset_scale
;
316 rctx
->poly_offset_state
.atom
.dirty
= true;
319 /* Update clip_misc_state. */
320 if (rctx
->clip_misc_state
.pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
||
321 rctx
->clip_misc_state
.clip_plane_enable
!= rs
->clip_plane_enable
) {
322 rctx
->clip_misc_state
.pa_cl_clip_cntl
= rs
->pa_cl_clip_cntl
;
323 rctx
->clip_misc_state
.clip_plane_enable
= rs
->clip_plane_enable
;
324 rctx
->clip_misc_state
.atom
.dirty
= true;
327 /* Workaround for a missing scissor enable on r600. */
328 if (rctx
->chip_class
== R600
&&
329 rs
->scissor_enable
!= rctx
->scissor
.enable
) {
330 rctx
->scissor
.enable
= rs
->scissor_enable
;
331 rctx
->scissor
.atom
.dirty
= true;
334 /* Re-emit PA_SC_LINE_STIPPLE. */
335 rctx
->last_primitive_type
= -1;
338 static void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
)
340 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
342 r600_release_command_buffer(&rs
->buffer
);
346 static void r600_sampler_view_destroy(struct pipe_context
*ctx
,
347 struct pipe_sampler_view
*state
)
349 struct r600_pipe_sampler_view
*resource
= (struct r600_pipe_sampler_view
*)state
;
351 pipe_resource_reference(&state
->texture
, NULL
);
355 void r600_sampler_states_dirty(struct r600_context
*rctx
,
356 struct r600_sampler_states
*state
)
358 if (state
->dirty_mask
) {
359 if (state
->dirty_mask
& state
->has_bordercolor_mask
) {
360 rctx
->flags
|= R600_CONTEXT_PS_PARTIAL_FLUSH
;
363 util_bitcount(state
->dirty_mask
& state
->has_bordercolor_mask
) * 11 +
364 util_bitcount(state
->dirty_mask
& ~state
->has_bordercolor_mask
) * 5;
365 state
->atom
.dirty
= true;
369 static void r600_bind_sampler_states(struct pipe_context
*pipe
,
372 unsigned count
, void **states
)
374 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
375 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
376 struct r600_pipe_sampler_state
**rstates
= (struct r600_pipe_sampler_state
**)states
;
377 int seamless_cube_map
= -1;
379 /* This sets 1-bit for states with index >= count. */
380 uint32_t disable_mask
= ~((1ull << count
) - 1);
381 /* These are the new states set by this function. */
382 uint32_t new_mask
= 0;
384 assert(start
== 0); /* XXX fix below */
386 for (i
= 0; i
< count
; i
++) {
387 struct r600_pipe_sampler_state
*rstate
= rstates
[i
];
389 if (rstate
== dst
->states
.states
[i
]) {
394 if (rstate
->border_color_use
) {
395 dst
->states
.has_bordercolor_mask
|= 1 << i
;
397 dst
->states
.has_bordercolor_mask
&= ~(1 << i
);
399 seamless_cube_map
= rstate
->seamless_cube_map
;
403 disable_mask
|= 1 << i
;
407 memcpy(dst
->states
.states
, rstates
, sizeof(void*) * count
);
408 memset(dst
->states
.states
+ count
, 0, sizeof(void*) * (NUM_TEX_UNITS
- count
));
410 dst
->states
.enabled_mask
&= ~disable_mask
;
411 dst
->states
.dirty_mask
&= dst
->states
.enabled_mask
;
412 dst
->states
.enabled_mask
|= new_mask
;
413 dst
->states
.dirty_mask
|= new_mask
;
414 dst
->states
.has_bordercolor_mask
&= dst
->states
.enabled_mask
;
416 r600_sampler_states_dirty(rctx
, &dst
->states
);
418 /* Seamless cubemap state. */
419 if (rctx
->chip_class
<= R700
&&
420 seamless_cube_map
!= -1 &&
421 seamless_cube_map
!= rctx
->seamless_cube_map
.enabled
) {
422 /* change in TA_CNTL_AUX need a pipeline flush */
423 rctx
->flags
|= R600_CONTEXT_PS_PARTIAL_FLUSH
;
424 rctx
->seamless_cube_map
.enabled
= seamless_cube_map
;
425 rctx
->seamless_cube_map
.atom
.dirty
= true;
429 static void r600_bind_vs_sampler_states(struct pipe_context
*ctx
, unsigned count
, void **states
)
431 r600_bind_sampler_states(ctx
, PIPE_SHADER_VERTEX
, 0, count
, states
);
434 static void r600_bind_ps_sampler_states(struct pipe_context
*ctx
, unsigned count
, void **states
)
436 r600_bind_sampler_states(ctx
, PIPE_SHADER_FRAGMENT
, 0, count
, states
);
439 static void r600_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
444 static void r600_delete_blend_state(struct pipe_context
*ctx
, void *state
)
446 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
448 r600_release_command_buffer(&blend
->buffer
);
449 r600_release_command_buffer(&blend
->buffer_no_blend
);
453 static void r600_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
455 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)state
;
457 r600_release_command_buffer(&dsa
->buffer
);
461 static void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
463 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
465 r600_set_cso_state(&rctx
->vertex_fetch_shader
, state
);
468 static void r600_delete_vertex_elements(struct pipe_context
*ctx
, void *state
)
470 pipe_resource_reference((struct pipe_resource
**)&state
, NULL
);
473 static void r600_set_index_buffer(struct pipe_context
*ctx
,
474 const struct pipe_index_buffer
*ib
)
476 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
479 pipe_resource_reference(&rctx
->index_buffer
.buffer
, ib
->buffer
);
480 memcpy(&rctx
->index_buffer
, ib
, sizeof(*ib
));
482 pipe_resource_reference(&rctx
->index_buffer
.buffer
, NULL
);
486 void r600_vertex_buffers_dirty(struct r600_context
*rctx
)
488 if (rctx
->vertex_buffer_state
.dirty_mask
) {
489 rctx
->flags
|= rctx
->has_vertex_cache
? R600_CONTEXT_VTX_FLUSH
: R600_CONTEXT_TEX_FLUSH
;
490 rctx
->vertex_buffer_state
.atom
.num_dw
= (rctx
->chip_class
>= EVERGREEN
? 12 : 11) *
491 util_bitcount(rctx
->vertex_buffer_state
.dirty_mask
);
492 rctx
->vertex_buffer_state
.atom
.dirty
= true;
496 static void r600_set_vertex_buffers(struct pipe_context
*ctx
, unsigned count
,
497 const struct pipe_vertex_buffer
*input
)
499 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
500 struct r600_vertexbuf_state
*state
= &rctx
->vertex_buffer_state
;
501 struct pipe_vertex_buffer
*vb
= state
->vb
;
503 /* This sets 1-bit for buffers with index >= count. */
504 uint32_t disable_mask
= ~((1ull << count
) - 1);
505 /* These are the new buffers set by this function. */
506 uint32_t new_buffer_mask
= 0;
508 /* Set buffers with index >= count to NULL. */
509 uint32_t remaining_buffers_mask
=
510 rctx
->vertex_buffer_state
.enabled_mask
& disable_mask
;
512 while (remaining_buffers_mask
) {
513 i
= u_bit_scan(&remaining_buffers_mask
);
514 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
517 /* Set vertex buffers. */
518 for (i
= 0; i
< count
; i
++) {
519 if (memcmp(&input
[i
], &vb
[i
], sizeof(struct pipe_vertex_buffer
))) {
520 if (input
[i
].buffer
) {
521 vb
[i
].stride
= input
[i
].stride
;
522 vb
[i
].buffer_offset
= input
[i
].buffer_offset
;
523 pipe_resource_reference(&vb
[i
].buffer
, input
[i
].buffer
);
524 new_buffer_mask
|= 1 << i
;
526 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
527 disable_mask
|= 1 << i
;
532 rctx
->vertex_buffer_state
.enabled_mask
&= ~disable_mask
;
533 rctx
->vertex_buffer_state
.dirty_mask
&= rctx
->vertex_buffer_state
.enabled_mask
;
534 rctx
->vertex_buffer_state
.enabled_mask
|= new_buffer_mask
;
535 rctx
->vertex_buffer_state
.dirty_mask
|= new_buffer_mask
;
537 r600_vertex_buffers_dirty(rctx
);
540 void r600_sampler_views_dirty(struct r600_context
*rctx
,
541 struct r600_samplerview_state
*state
)
543 if (state
->dirty_mask
) {
544 rctx
->flags
|= R600_CONTEXT_TEX_FLUSH
;
545 state
->atom
.num_dw
= (rctx
->chip_class
>= EVERGREEN
? 14 : 13) *
546 util_bitcount(state
->dirty_mask
);
547 state
->atom
.dirty
= true;
551 static void r600_set_sampler_views(struct pipe_context
*pipe
, unsigned shader
,
552 unsigned start
, unsigned count
,
553 struct pipe_sampler_view
**views
)
555 struct r600_context
*rctx
= (struct r600_context
*) pipe
;
556 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
557 struct r600_pipe_sampler_view
**rviews
= (struct r600_pipe_sampler_view
**)views
;
558 uint32_t dirty_sampler_states_mask
= 0;
560 /* This sets 1-bit for textures with index >= count. */
561 uint32_t disable_mask
= ~((1ull << count
) - 1);
562 /* These are the new textures set by this function. */
563 uint32_t new_mask
= 0;
565 /* Set textures with index >= count to NULL. */
566 uint32_t remaining_mask
;
568 assert(start
== 0); /* XXX fix below */
570 remaining_mask
= dst
->views
.enabled_mask
& disable_mask
;
572 while (remaining_mask
) {
573 i
= u_bit_scan(&remaining_mask
);
574 assert(dst
->views
.views
[i
]);
576 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
579 for (i
= 0; i
< count
; i
++) {
580 if (rviews
[i
] == dst
->views
.views
[i
]) {
585 struct r600_texture
*rtex
=
586 (struct r600_texture
*)rviews
[i
]->base
.texture
;
588 if (rtex
->is_depth
&& !rtex
->is_flushing_texture
) {
589 dst
->views
.compressed_depthtex_mask
|= 1 << i
;
591 dst
->views
.compressed_depthtex_mask
&= ~(1 << i
);
594 /* Track compressed colorbuffers for Evergreen (Cayman doesn't need this). */
595 if (rctx
->chip_class
!= CAYMAN
&& rtex
->cmask_size
&& rtex
->fmask_size
) {
596 dst
->views
.compressed_colortex_mask
|= 1 << i
;
598 dst
->views
.compressed_colortex_mask
&= ~(1 << i
);
601 /* Changing from array to non-arrays textures and vice versa requires
602 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
603 if (rctx
->chip_class
<= R700
&&
604 (dst
->states
.enabled_mask
& (1 << i
)) &&
605 (rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_1D_ARRAY
||
606 rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_2D_ARRAY
) != dst
->is_array_sampler
[i
]) {
607 dirty_sampler_states_mask
|= 1 << i
;
610 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], views
[i
]);
613 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
614 disable_mask
|= 1 << i
;
618 dst
->views
.enabled_mask
&= ~disable_mask
;
619 dst
->views
.dirty_mask
&= dst
->views
.enabled_mask
;
620 dst
->views
.enabled_mask
|= new_mask
;
621 dst
->views
.dirty_mask
|= new_mask
;
622 dst
->views
.compressed_depthtex_mask
&= dst
->views
.enabled_mask
;
623 dst
->views
.compressed_colortex_mask
&= dst
->views
.enabled_mask
;
625 r600_sampler_views_dirty(rctx
, &dst
->views
);
627 if (dirty_sampler_states_mask
) {
628 dst
->states
.dirty_mask
|= dirty_sampler_states_mask
;
629 r600_sampler_states_dirty(rctx
, &dst
->states
);
633 static void r600_set_vs_sampler_views(struct pipe_context
*ctx
, unsigned count
,
634 struct pipe_sampler_view
**views
)
636 r600_set_sampler_views(ctx
, PIPE_SHADER_VERTEX
, 0, count
, views
);
639 static void r600_set_ps_sampler_views(struct pipe_context
*ctx
, unsigned count
,
640 struct pipe_sampler_view
**views
)
642 r600_set_sampler_views(ctx
, PIPE_SHADER_FRAGMENT
, 0, count
, views
);
645 static void r600_set_viewport_state(struct pipe_context
*ctx
,
646 const struct pipe_viewport_state
*state
)
648 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
650 rctx
->viewport
.state
= *state
;
651 rctx
->viewport
.atom
.dirty
= true;
654 void r600_emit_viewport_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
656 struct radeon_winsys_cs
*cs
= rctx
->cs
;
657 struct pipe_viewport_state
*state
= &rctx
->viewport
.state
;
659 r600_write_context_reg_seq(cs
, R_02843C_PA_CL_VPORT_XSCALE_0
, 6);
660 r600_write_value(cs
, fui(state
->scale
[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
661 r600_write_value(cs
, fui(state
->translate
[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
662 r600_write_value(cs
, fui(state
->scale
[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
663 r600_write_value(cs
, fui(state
->translate
[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
664 r600_write_value(cs
, fui(state
->scale
[2])); /* R_02844C_PA_CL_VPORT_ZSCALE_0 */
665 r600_write_value(cs
, fui(state
->translate
[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
668 /* Compute the key for the hw shader variant */
669 static INLINE
struct r600_shader_key
r600_shader_selector_key(struct pipe_context
* ctx
,
670 struct r600_pipe_shader_selector
* sel
)
672 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
673 struct r600_shader_key key
;
674 memset(&key
, 0, sizeof(key
));
676 if (sel
->type
== PIPE_SHADER_FRAGMENT
) {
677 key
.color_two_side
= rctx
->rasterizer
&& rctx
->rasterizer
->two_side
;
678 key
.alpha_to_one
= rctx
->alpha_to_one
&&
679 rctx
->rasterizer
&& rctx
->rasterizer
->multisample_enable
&&
680 !rctx
->framebuffer
.cb0_is_integer
;
681 key
.nr_cbufs
= rctx
->framebuffer
.state
.nr_cbufs
;
682 /* Dual-source blending only makes sense with nr_cbufs == 1. */
683 if (key
.nr_cbufs
== 1 && rctx
->dual_src_blend
)
689 /* Select the hw shader variant depending on the current state.
690 * (*dirty) is set to 1 if current variant was changed */
691 static int r600_shader_select(struct pipe_context
*ctx
,
692 struct r600_pipe_shader_selector
* sel
,
695 struct r600_shader_key key
;
696 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
697 struct r600_pipe_shader
* shader
= NULL
;
700 key
= r600_shader_selector_key(ctx
, sel
);
702 /* Check if we don't need to change anything.
703 * This path is also used for most shaders that don't need multiple
704 * variants, it will cost just a computation of the key and this
706 if (likely(sel
->current
&& memcmp(&sel
->current
->key
, &key
, sizeof(key
)) == 0)) {
710 /* lookup if we have other variants in the list */
711 if (sel
->num_shaders
> 1) {
712 struct r600_pipe_shader
*p
= sel
->current
, *c
= p
->next_variant
;
714 while (c
&& memcmp(&c
->key
, &key
, sizeof(key
)) != 0) {
720 p
->next_variant
= c
->next_variant
;
725 if (unlikely(!shader
)) {
726 shader
= CALLOC(1, sizeof(struct r600_pipe_shader
));
727 shader
->selector
= sel
;
729 r
= r600_pipe_shader_create(ctx
, shader
, key
);
731 R600_ERR("Failed to build shader variant (type=%u) %d\n",
737 /* We don't know the value of nr_ps_max_color_exports until we built
738 * at least one variant, so we may need to recompute the key after
739 * building first variant. */
740 if (sel
->type
== PIPE_SHADER_FRAGMENT
&&
741 sel
->num_shaders
== 0) {
742 sel
->nr_ps_max_color_exports
= shader
->shader
.nr_ps_max_color_exports
;
743 key
= r600_shader_selector_key(ctx
, sel
);
753 shader
->next_variant
= sel
->current
;
754 sel
->current
= shader
;
756 if (rctx
->chip_class
< EVERGREEN
&& rctx
->ps_shader
&& rctx
->vs_shader
) {
757 r600_adjust_gprs(rctx
);
760 if (rctx
->ps_shader
&&
761 rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
762 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
763 rctx
->cb_misc_state
.atom
.dirty
= true;
768 static void *r600_create_shader_state(struct pipe_context
*ctx
,
769 const struct pipe_shader_state
*state
,
770 unsigned pipe_shader_type
)
772 struct r600_pipe_shader_selector
*sel
= CALLOC_STRUCT(r600_pipe_shader_selector
);
775 sel
->type
= pipe_shader_type
;
776 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
777 sel
->so
= state
->stream_output
;
779 r
= r600_shader_select(ctx
, sel
, NULL
);
786 static void *r600_create_ps_state(struct pipe_context
*ctx
,
787 const struct pipe_shader_state
*state
)
789 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_FRAGMENT
);
792 static void *r600_create_vs_state(struct pipe_context
*ctx
,
793 const struct pipe_shader_state
*state
)
795 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_VERTEX
);
798 static void r600_bind_ps_state(struct pipe_context
*ctx
, void *state
)
800 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
803 state
= rctx
->dummy_pixel_shader
;
805 rctx
->ps_shader
= (struct r600_pipe_shader_selector
*)state
;
806 r600_context_pipe_state_set(rctx
, &rctx
->ps_shader
->current
->rstate
);
808 if (rctx
->chip_class
<= R700
) {
809 bool multiwrite
= rctx
->ps_shader
->current
->shader
.fs_write_all
;
811 if (rctx
->cb_misc_state
.multiwrite
!= multiwrite
) {
812 rctx
->cb_misc_state
.multiwrite
= multiwrite
;
813 rctx
->cb_misc_state
.atom
.dirty
= true;
817 r600_adjust_gprs(rctx
);
820 if (rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
821 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
822 rctx
->cb_misc_state
.atom
.dirty
= true;
826 static void r600_bind_vs_state(struct pipe_context
*ctx
, void *state
)
828 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
830 rctx
->vs_shader
= (struct r600_pipe_shader_selector
*)state
;
832 r600_context_pipe_state_set(rctx
, &rctx
->vs_shader
->current
->rstate
);
834 if (rctx
->chip_class
< EVERGREEN
&& rctx
->ps_shader
)
835 r600_adjust_gprs(rctx
);
837 /* Update clip misc state. */
838 if (rctx
->vs_shader
->current
->pa_cl_vs_out_cntl
!= rctx
->clip_misc_state
.pa_cl_vs_out_cntl
||
839 rctx
->vs_shader
->current
->shader
.clip_dist_write
!= rctx
->clip_misc_state
.clip_dist_write
) {
840 rctx
->clip_misc_state
.pa_cl_vs_out_cntl
= rctx
->vs_shader
->current
->pa_cl_vs_out_cntl
;
841 rctx
->clip_misc_state
.clip_dist_write
= rctx
->vs_shader
->current
->shader
.clip_dist_write
;
842 rctx
->clip_misc_state
.atom
.dirty
= true;
847 static void r600_delete_shader_selector(struct pipe_context
*ctx
,
848 struct r600_pipe_shader_selector
*sel
)
850 struct r600_pipe_shader
*p
= sel
->current
, *c
;
853 r600_pipe_shader_destroy(ctx
, p
);
863 static void r600_delete_ps_state(struct pipe_context
*ctx
, void *state
)
865 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
866 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
868 if (rctx
->ps_shader
== sel
) {
869 rctx
->ps_shader
= NULL
;
872 r600_delete_shader_selector(ctx
, sel
);
875 static void r600_delete_vs_state(struct pipe_context
*ctx
, void *state
)
877 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
878 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
880 if (rctx
->vs_shader
== sel
) {
881 rctx
->vs_shader
= NULL
;
884 r600_delete_shader_selector(ctx
, sel
);
887 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
)
889 if (state
->dirty_mask
) {
890 rctx
->flags
|= R600_CONTEXT_SHADERCONST_FLUSH
;
891 state
->atom
.num_dw
= rctx
->chip_class
>= EVERGREEN
? util_bitcount(state
->dirty_mask
)*20
892 : util_bitcount(state
->dirty_mask
)*19;
893 state
->atom
.dirty
= true;
897 static void r600_set_constant_buffer(struct pipe_context
*ctx
, uint shader
, uint index
,
898 struct pipe_constant_buffer
*input
)
900 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
901 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
902 struct pipe_constant_buffer
*cb
;
905 /* Note that the state tracker can unbind constant buffers by
908 if (unlikely(!input
)) {
909 state
->enabled_mask
&= ~(1 << index
);
910 state
->dirty_mask
&= ~(1 << index
);
911 pipe_resource_reference(&state
->cb
[index
].buffer
, NULL
);
915 cb
= &state
->cb
[index
];
916 cb
->buffer_size
= input
->buffer_size
;
918 ptr
= input
->user_buffer
;
921 /* Upload the user buffer. */
922 if (R600_BIG_ENDIAN
) {
924 unsigned i
, size
= input
->buffer_size
;
926 if (!(tmpPtr
= malloc(size
))) {
927 R600_ERR("Failed to allocate BE swap buffer.\n");
931 for (i
= 0; i
< size
/ 4; ++i
) {
932 tmpPtr
[i
] = bswap_32(((uint32_t *)ptr
)[i
]);
935 u_upload_data(rctx
->uploader
, 0, size
, tmpPtr
, &cb
->buffer_offset
, &cb
->buffer
);
938 u_upload_data(rctx
->uploader
, 0, input
->buffer_size
, ptr
, &cb
->buffer_offset
, &cb
->buffer
);
941 /* Setup the hw buffer. */
942 cb
->buffer_offset
= input
->buffer_offset
;
943 pipe_resource_reference(&cb
->buffer
, input
->buffer
);
946 state
->enabled_mask
|= 1 << index
;
947 state
->dirty_mask
|= 1 << index
;
948 r600_constant_buffers_dirty(rctx
, state
);
951 static struct pipe_stream_output_target
*
952 r600_create_so_target(struct pipe_context
*ctx
,
953 struct pipe_resource
*buffer
,
954 unsigned buffer_offset
,
955 unsigned buffer_size
)
957 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
958 struct r600_so_target
*t
;
961 t
= CALLOC_STRUCT(r600_so_target
);
966 t
->b
.reference
.count
= 1;
968 pipe_resource_reference(&t
->b
.buffer
, buffer
);
969 t
->b
.buffer_offset
= buffer_offset
;
970 t
->b
.buffer_size
= buffer_size
;
972 t
->filled_size
= (struct r600_resource
*)
973 pipe_buffer_create(ctx
->screen
, PIPE_BIND_CUSTOM
, PIPE_USAGE_STATIC
, 4);
974 ptr
= rctx
->ws
->buffer_map(t
->filled_size
->cs_buf
, rctx
->cs
, PIPE_TRANSFER_WRITE
);
975 memset(ptr
, 0, t
->filled_size
->buf
->size
);
976 rctx
->ws
->buffer_unmap(t
->filled_size
->cs_buf
);
981 static void r600_so_target_destroy(struct pipe_context
*ctx
,
982 struct pipe_stream_output_target
*target
)
984 struct r600_so_target
*t
= (struct r600_so_target
*)target
;
985 pipe_resource_reference(&t
->b
.buffer
, NULL
);
986 pipe_resource_reference((struct pipe_resource
**)&t
->filled_size
, NULL
);
990 static void r600_set_so_targets(struct pipe_context
*ctx
,
991 unsigned num_targets
,
992 struct pipe_stream_output_target
**targets
,
993 unsigned append_bitmask
)
995 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
998 /* Stop streamout. */
999 if (rctx
->num_so_targets
&& !rctx
->streamout_start
) {
1000 r600_context_streamout_end(rctx
);
1003 /* Set the new targets. */
1004 for (i
= 0; i
< num_targets
; i
++) {
1005 pipe_so_target_reference((struct pipe_stream_output_target
**)&rctx
->so_targets
[i
], targets
[i
]);
1007 for (; i
< rctx
->num_so_targets
; i
++) {
1008 pipe_so_target_reference((struct pipe_stream_output_target
**)&rctx
->so_targets
[i
], NULL
);
1011 rctx
->num_so_targets
= num_targets
;
1012 rctx
->streamout_start
= num_targets
!= 0;
1013 rctx
->streamout_append_bitmask
= append_bitmask
;
1016 static void r600_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
1018 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
1020 if (rctx
->sample_mask
.sample_mask
== (uint16_t)sample_mask
)
1023 rctx
->sample_mask
.sample_mask
= sample_mask
;
1024 rctx
->sample_mask
.atom
.dirty
= true;
1027 static void r600_update_derived_state(struct r600_context
*rctx
)
1029 struct pipe_context
* ctx
= (struct pipe_context
*)rctx
;
1030 unsigned ps_dirty
= 0;
1033 if (!rctx
->blitter
->running
) {
1036 /* Decompress textures if needed. */
1037 for (i
= 0; i
< PIPE_SHADER_TYPES
; i
++) {
1038 struct r600_samplerview_state
*views
= &rctx
->samplers
[i
].views
;
1039 if (views
->compressed_depthtex_mask
) {
1040 r600_decompress_depth_textures(rctx
, views
);
1042 if (views
->compressed_colortex_mask
) {
1043 r600_decompress_color_textures(rctx
, views
);
1048 r600_shader_select(ctx
, rctx
->ps_shader
, &ps_dirty
);
1050 if (rctx
->ps_shader
&& rctx
->rasterizer
&&
1051 ((rctx
->rasterizer
->sprite_coord_enable
!= rctx
->ps_shader
->current
->sprite_coord_enable
) ||
1052 (rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
))) {
1054 if (rctx
->chip_class
>= EVERGREEN
)
1055 evergreen_pipe_shader_ps(ctx
, rctx
->ps_shader
->current
);
1057 r600_pipe_shader_ps(ctx
, rctx
->ps_shader
->current
);
1063 r600_context_pipe_state_set(rctx
, &rctx
->ps_shader
->current
->rstate
);
1065 blend_disable
= (rctx
->dual_src_blend
&&
1066 rctx
->ps_shader
->current
->nr_ps_color_outputs
< 2);
1068 if (blend_disable
!= rctx
->force_blend_disable
) {
1069 rctx
->force_blend_disable
= blend_disable
;
1070 r600_bind_blend_state_internal(rctx
,
1071 rctx
->blend_state
.cso
,
1075 if (rctx
->chip_class
>= EVERGREEN
) {
1076 evergreen_update_dual_export_state(rctx
);
1078 r600_update_dual_export_state(rctx
);
1082 static unsigned r600_conv_prim_to_gs_out(unsigned mode
)
1084 static const int prim_conv
[] = {
1085 V_028A6C_OUTPRIM_TYPE_POINTLIST
,
1086 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1087 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1088 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1089 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1090 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1091 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1092 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1093 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1094 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1095 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1096 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1097 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1098 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1099 V_028A6C_OUTPRIM_TYPE_TRISTRIP
1101 assert(mode
< Elements(prim_conv
));
1103 return prim_conv
[mode
];
1106 void r600_emit_clip_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1108 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1109 struct r600_clip_misc_state
*state
= &rctx
->clip_misc_state
;
1111 r600_write_context_reg(cs
, R_028810_PA_CL_CLIP_CNTL
,
1112 state
->pa_cl_clip_cntl
|
1113 (state
->clip_dist_write
? 0 : state
->clip_plane_enable
& 0x3F));
1114 r600_write_context_reg(cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
1115 state
->pa_cl_vs_out_cntl
|
1116 (state
->clip_plane_enable
& state
->clip_dist_write
));
1119 static void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*dinfo
)
1121 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1122 struct pipe_draw_info info
= *dinfo
;
1123 struct pipe_index_buffer ib
= {};
1125 struct r600_block
*dirty_block
= NULL
, *next_block
= NULL
;
1126 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1130 if (!info
.count
&& (info
.indexed
|| !info
.count_from_stream_output
)) {
1135 if (!rctx
->vs_shader
) {
1140 r600_update_derived_state(rctx
);
1143 /* Initialize the index buffer struct. */
1144 pipe_resource_reference(&ib
.buffer
, rctx
->index_buffer
.buffer
);
1145 ib
.user_buffer
= rctx
->index_buffer
.user_buffer
;
1146 ib
.index_size
= rctx
->index_buffer
.index_size
;
1147 ib
.offset
= rctx
->index_buffer
.offset
+ info
.start
* ib
.index_size
;
1149 /* Translate or upload, if needed. */
1150 r600_translate_index_buffer(rctx
, &ib
, info
.count
);
1152 ptr
= (uint8_t*)ib
.user_buffer
;
1153 if (!ib
.buffer
&& ptr
) {
1154 u_upload_data(rctx
->uploader
, 0, info
.count
* ib
.index_size
,
1155 ptr
, &ib
.offset
, &ib
.buffer
);
1158 info
.index_bias
= info
.start
;
1161 /* Enable stream out if needed. */
1162 if (rctx
->streamout_start
) {
1163 r600_context_streamout_begin(rctx
);
1164 rctx
->streamout_start
= FALSE
;
1167 /* Set the index offset and multi primitive */
1168 if (rctx
->vgt2_state
.vgt_indx_offset
!= info
.index_bias
) {
1169 rctx
->vgt2_state
.vgt_indx_offset
= info
.index_bias
;
1170 rctx
->vgt2_state
.atom
.dirty
= true;
1172 if (rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
!= info
.primitive_restart
||
1173 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
!= info
.restart_index
) {
1174 rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
= info
.primitive_restart
;
1175 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
= info
.restart_index
;
1176 rctx
->vgt_state
.atom
.dirty
= true;
1179 /* Emit states (the function expects that we emit at most 17 dwords here). */
1180 r600_need_cs_space(rctx
, 0, TRUE
);
1181 r600_flush_emit(rctx
);
1183 for (i
= 0; i
< R600_NUM_ATOMS
; i
++) {
1184 if (rctx
->atoms
[i
] == NULL
|| !rctx
->atoms
[i
]->dirty
) {
1187 r600_emit_atom(rctx
, rctx
->atoms
[i
]);
1189 LIST_FOR_EACH_ENTRY_SAFE(dirty_block
, next_block
, &rctx
->dirty
,list
) {
1190 r600_context_block_emit_dirty(rctx
, dirty_block
, 0 /* pkt_flags */);
1192 rctx
->pm4_dirty_cdwords
= 0;
1194 /* Update start instance. */
1195 if (rctx
->last_start_instance
!= info
.start_instance
) {
1196 r600_write_ctl_const(cs
, R_03CFF4_SQ_VTX_START_INST_LOC
, info
.start_instance
);
1197 rctx
->last_start_instance
= info
.start_instance
;
1200 /* Update the primitive type. */
1201 if (rctx
->last_primitive_type
!= info
.mode
) {
1202 unsigned ls_mask
= 0;
1204 if (info
.mode
== PIPE_PRIM_LINES
)
1206 else if (info
.mode
== PIPE_PRIM_LINE_STRIP
||
1207 info
.mode
== PIPE_PRIM_LINE_LOOP
)
1210 r600_write_context_reg(cs
, R_028A0C_PA_SC_LINE_STIPPLE
,
1211 S_028A0C_AUTO_RESET_CNTL(ls_mask
) |
1212 (rctx
->rasterizer
? rctx
->rasterizer
->pa_sc_line_stipple
: 0));
1213 r600_write_context_reg(cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
,
1214 r600_conv_prim_to_gs_out(info
.mode
));
1215 r600_write_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
,
1216 r600_conv_pipe_prim(info
.mode
));
1218 rctx
->last_primitive_type
= info
.mode
;
1222 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NUM_INSTANCES
, 0, rctx
->predicate_drawing
);
1223 cs
->buf
[cs
->cdw
++] = info
.instance_count
;
1225 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_INDEX_TYPE
, 0, rctx
->predicate_drawing
);
1226 cs
->buf
[cs
->cdw
++] = ib
.index_size
== 4 ?
1227 (VGT_INDEX_32
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_32_BIT
: 0)) :
1228 (VGT_INDEX_16
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_16_BIT
: 0));
1230 va
= r600_resource_va(ctx
->screen
, ib
.buffer
);
1232 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX
, 3, rctx
->predicate_drawing
);
1233 cs
->buf
[cs
->cdw
++] = va
;
1234 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFF;
1235 cs
->buf
[cs
->cdw
++] = info
.count
;
1236 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_DMA
;
1237 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, rctx
->predicate_drawing
);
1238 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(rctx
, (struct r600_resource
*)ib
.buffer
, RADEON_USAGE_READ
);
1240 if (info
.count_from_stream_output
) {
1241 struct r600_so_target
*t
= (struct r600_so_target
*)info
.count_from_stream_output
;
1242 uint64_t va
= r600_resource_va(&rctx
->screen
->screen
, (void*)t
->filled_size
);
1244 r600_write_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
, t
->stride_in_dw
);
1246 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_COPY_DW
, 4, 0);
1247 cs
->buf
[cs
->cdw
++] = COPY_DW_SRC_IS_MEM
| COPY_DW_DST_IS_REG
;
1248 cs
->buf
[cs
->cdw
++] = va
& 0xFFFFFFFFUL
; /* src address lo */
1249 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFFUL
; /* src address hi */
1250 cs
->buf
[cs
->cdw
++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2; /* dst register */
1251 cs
->buf
[cs
->cdw
++] = 0; /* unused */
1253 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
1254 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(rctx
, t
->filled_size
, RADEON_USAGE_READ
);
1257 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX_AUTO
, 1, rctx
->predicate_drawing
);
1258 cs
->buf
[cs
->cdw
++] = info
.count
;
1259 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
1260 (info
.count_from_stream_output
? S_0287F0_USE_OPAQUE(1) : 0);
1263 /* Set the depth buffer as dirty. */
1264 if (rctx
->framebuffer
.state
.zsbuf
) {
1265 struct pipe_surface
*surf
= rctx
->framebuffer
.state
.zsbuf
;
1266 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
1268 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1270 if (rctx
->framebuffer
.compressed_cb_mask
) {
1271 struct pipe_surface
*surf
;
1272 struct r600_texture
*rtex
;
1273 unsigned mask
= rctx
->framebuffer
.compressed_cb_mask
;
1276 unsigned i
= u_bit_scan(&mask
);
1277 surf
= rctx
->framebuffer
.state
.cbufs
[i
];
1278 rtex
= (struct r600_texture
*)surf
->texture
;
1280 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1285 pipe_resource_reference(&ib
.buffer
, NULL
);
1288 void r600_draw_rectangle(struct blitter_context
*blitter
,
1289 int x1
, int y1
, int x2
, int y2
, float depth
,
1290 enum blitter_attrib_type type
, const union pipe_color_union
*attrib
)
1292 struct r600_context
*rctx
= (struct r600_context
*)util_blitter_get_pipe(blitter
);
1293 struct pipe_viewport_state viewport
;
1294 struct pipe_resource
*buf
= NULL
;
1295 unsigned offset
= 0;
1298 if (type
== UTIL_BLITTER_ATTRIB_TEXCOORD
) {
1299 util_blitter_draw_rectangle(blitter
, x1
, y1
, x2
, y2
, depth
, type
, attrib
);
1303 /* Some operations (like color resolve on r6xx) don't work
1304 * with the conventional primitive types.
1305 * One that works is PT_RECTLIST, which we use here. */
1307 /* setup viewport */
1308 viewport
.scale
[0] = 1.0f
;
1309 viewport
.scale
[1] = 1.0f
;
1310 viewport
.scale
[2] = 1.0f
;
1311 viewport
.scale
[3] = 1.0f
;
1312 viewport
.translate
[0] = 0.0f
;
1313 viewport
.translate
[1] = 0.0f
;
1314 viewport
.translate
[2] = 0.0f
;
1315 viewport
.translate
[3] = 0.0f
;
1316 rctx
->context
.set_viewport_state(&rctx
->context
, &viewport
);
1318 /* Upload vertices. The hw rectangle has only 3 vertices,
1319 * I guess the 4th one is derived from the first 3.
1320 * The vertex specification should match u_blitter's vertex element state. */
1321 u_upload_alloc(rctx
->uploader
, 0, sizeof(float) * 24, &offset
, &buf
, (void**)&vb
);
1338 memcpy(vb
+4, attrib
->f
, sizeof(float)*4);
1339 memcpy(vb
+12, attrib
->f
, sizeof(float)*4);
1340 memcpy(vb
+20, attrib
->f
, sizeof(float)*4);
1344 util_draw_vertex_buffer(&rctx
->context
, NULL
, buf
, offset
,
1345 R600_PRIM_RECTANGLE_LIST
, 3, 2);
1346 pipe_resource_reference(&buf
, NULL
);
1349 void _r600_pipe_state_add_reg_bo(struct r600_context
*ctx
,
1350 struct r600_pipe_state
*state
,
1351 uint32_t offset
, uint32_t value
,
1352 uint32_t range_id
, uint32_t block_id
,
1353 struct r600_resource
*bo
,
1354 enum radeon_bo_usage usage
)
1357 struct r600_range
*range
;
1358 struct r600_block
*block
;
1360 if (bo
) assert(usage
);
1362 range
= &ctx
->range
[range_id
];
1363 block
= range
->blocks
[block_id
];
1364 state
->regs
[state
->nregs
].block
= block
;
1365 state
->regs
[state
->nregs
].id
= (offset
- block
->start_offset
) >> 2;
1367 state
->regs
[state
->nregs
].value
= value
;
1368 state
->regs
[state
->nregs
].bo
= bo
;
1369 state
->regs
[state
->nregs
].bo_usage
= usage
;
1372 assert(state
->nregs
< R600_BLOCK_MAX_REG
);
1375 void _r600_pipe_state_add_reg(struct r600_context
*ctx
,
1376 struct r600_pipe_state
*state
,
1377 uint32_t offset
, uint32_t value
,
1378 uint32_t range_id
, uint32_t block_id
)
1380 _r600_pipe_state_add_reg_bo(ctx
, state
, offset
, value
,
1381 range_id
, block_id
, NULL
, 0);
1384 uint32_t r600_translate_stencil_op(int s_op
)
1387 case PIPE_STENCIL_OP_KEEP
:
1388 return V_028800_STENCIL_KEEP
;
1389 case PIPE_STENCIL_OP_ZERO
:
1390 return V_028800_STENCIL_ZERO
;
1391 case PIPE_STENCIL_OP_REPLACE
:
1392 return V_028800_STENCIL_REPLACE
;
1393 case PIPE_STENCIL_OP_INCR
:
1394 return V_028800_STENCIL_INCR
;
1395 case PIPE_STENCIL_OP_DECR
:
1396 return V_028800_STENCIL_DECR
;
1397 case PIPE_STENCIL_OP_INCR_WRAP
:
1398 return V_028800_STENCIL_INCR_WRAP
;
1399 case PIPE_STENCIL_OP_DECR_WRAP
:
1400 return V_028800_STENCIL_DECR_WRAP
;
1401 case PIPE_STENCIL_OP_INVERT
:
1402 return V_028800_STENCIL_INVERT
;
1404 R600_ERR("Unknown stencil op %d", s_op
);
1411 uint32_t r600_translate_fill(uint32_t func
)
1414 case PIPE_POLYGON_MODE_FILL
:
1416 case PIPE_POLYGON_MODE_LINE
:
1418 case PIPE_POLYGON_MODE_POINT
:
1426 unsigned r600_tex_wrap(unsigned wrap
)
1430 case PIPE_TEX_WRAP_REPEAT
:
1431 return V_03C000_SQ_TEX_WRAP
;
1432 case PIPE_TEX_WRAP_CLAMP
:
1433 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER
;
1434 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1435 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL
;
1436 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1437 return V_03C000_SQ_TEX_CLAMP_BORDER
;
1438 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1439 return V_03C000_SQ_TEX_MIRROR
;
1440 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1441 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1442 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1443 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1444 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1445 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER
;
1449 unsigned r600_tex_filter(unsigned filter
)
1453 case PIPE_TEX_FILTER_NEAREST
:
1454 return V_03C000_SQ_TEX_XY_FILTER_POINT
;
1455 case PIPE_TEX_FILTER_LINEAR
:
1456 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR
;
1460 unsigned r600_tex_mipfilter(unsigned filter
)
1463 case PIPE_TEX_MIPFILTER_NEAREST
:
1464 return V_03C000_SQ_TEX_Z_FILTER_POINT
;
1465 case PIPE_TEX_MIPFILTER_LINEAR
:
1466 return V_03C000_SQ_TEX_Z_FILTER_LINEAR
;
1468 case PIPE_TEX_MIPFILTER_NONE
:
1469 return V_03C000_SQ_TEX_Z_FILTER_NONE
;
1473 unsigned r600_tex_compare(unsigned compare
)
1477 case PIPE_FUNC_NEVER
:
1478 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER
;
1479 case PIPE_FUNC_LESS
:
1480 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS
;
1481 case PIPE_FUNC_EQUAL
:
1482 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1483 case PIPE_FUNC_LEQUAL
:
1484 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1485 case PIPE_FUNC_GREATER
:
1486 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER
;
1487 case PIPE_FUNC_NOTEQUAL
:
1488 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1489 case PIPE_FUNC_GEQUAL
:
1490 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1491 case PIPE_FUNC_ALWAYS
:
1492 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1496 /* keep this at the end of this file, please */
1497 void r600_init_common_state_functions(struct r600_context
*rctx
)
1499 rctx
->context
.create_fs_state
= r600_create_ps_state
;
1500 rctx
->context
.create_vs_state
= r600_create_vs_state
;
1501 rctx
->context
.create_vertex_elements_state
= r600_create_vertex_fetch_shader
;
1502 rctx
->context
.bind_blend_state
= r600_bind_blend_state
;
1503 rctx
->context
.bind_depth_stencil_alpha_state
= r600_bind_dsa_state
;
1504 rctx
->context
.bind_fragment_sampler_states
= r600_bind_ps_sampler_states
;
1505 rctx
->context
.bind_fs_state
= r600_bind_ps_state
;
1506 rctx
->context
.bind_rasterizer_state
= r600_bind_rs_state
;
1507 rctx
->context
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
1508 rctx
->context
.bind_vertex_sampler_states
= r600_bind_vs_sampler_states
;
1509 rctx
->context
.bind_vs_state
= r600_bind_vs_state
;
1510 rctx
->context
.delete_blend_state
= r600_delete_blend_state
;
1511 rctx
->context
.delete_depth_stencil_alpha_state
= r600_delete_dsa_state
;
1512 rctx
->context
.delete_fs_state
= r600_delete_ps_state
;
1513 rctx
->context
.delete_rasterizer_state
= r600_delete_rs_state
;
1514 rctx
->context
.delete_sampler_state
= r600_delete_sampler_state
;
1515 rctx
->context
.delete_vertex_elements_state
= r600_delete_vertex_elements
;
1516 rctx
->context
.delete_vs_state
= r600_delete_vs_state
;
1517 rctx
->context
.set_blend_color
= r600_set_blend_color
;
1518 rctx
->context
.set_clip_state
= r600_set_clip_state
;
1519 rctx
->context
.set_constant_buffer
= r600_set_constant_buffer
;
1520 rctx
->context
.set_sample_mask
= r600_set_sample_mask
;
1521 rctx
->context
.set_stencil_ref
= r600_set_pipe_stencil_ref
;
1522 rctx
->context
.set_viewport_state
= r600_set_viewport_state
;
1523 rctx
->context
.set_vertex_buffers
= r600_set_vertex_buffers
;
1524 rctx
->context
.set_index_buffer
= r600_set_index_buffer
;
1525 rctx
->context
.set_fragment_sampler_views
= r600_set_ps_sampler_views
;
1526 rctx
->context
.set_vertex_sampler_views
= r600_set_vs_sampler_views
;
1527 rctx
->context
.sampler_view_destroy
= r600_sampler_view_destroy
;
1528 rctx
->context
.texture_barrier
= r600_texture_barrier
;
1529 rctx
->context
.create_stream_output_target
= r600_create_so_target
;
1530 rctx
->context
.stream_output_target_destroy
= r600_so_target_destroy
;
1531 rctx
->context
.set_stream_output_targets
= r600_set_so_targets
;
1532 rctx
->context
.draw_vbo
= r600_draw_vbo
;