src/gallium/drivers/r600/r600_state_common.c

   1 /*
   2  * Copyright 2010 Red Hat Inc.
   3  *           2010 Jerome Glisse
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie <airlied@redhat.com>
  25  *          Jerome Glisse <jglisse@redhat.com>
  26  */
  27 #include "util/u_blitter.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_format.h"
  30 #include "pipebuffer/pb_buffer.h"
  31 #include "pipe/p_shader_tokens.h"
  32 #include "tgsi/tgsi_parse.h"
  33 #include "r600_formats.h"
  34 #include "r600_pipe.h"
  35 #include "r600d.h"
  36
  37 static void r600_emit_command_buffer(struct r600_context *rctx, struct r600_atom *atom)
  38 {
  39         struct radeon_winsys_cs *cs = rctx->cs;
  40         struct r600_command_buffer *cb = (struct r600_command_buffer*)atom;
  41
  42         assert(cs->cdw + cb->atom.num_dw <= RADEON_MAX_CMDBUF_DWORDS);
  43         memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->atom.num_dw);
  44         cs->cdw += cb->atom.num_dw;
  45 }
  46
  47 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags)
  48 {
  49         cb->atom.emit = r600_emit_command_buffer;
  50         cb->atom.num_dw = 0;
  51         cb->atom.flags = flags;
  52         cb->buf = CALLOC(1, 4 * num_dw);
  53         cb->max_num_dw = num_dw;
  54 }
  55
  56 void r600_release_command_buffer(struct r600_command_buffer *cb)
  57 {
  58         FREE(cb->buf);
  59 }
  60
  61 static void r600_emit_surface_sync(struct r600_context *rctx, struct r600_atom *atom)
  62 {
  63         struct radeon_winsys_cs *cs = rctx->cs;
  64         struct r600_atom_surface_sync *a = (struct r600_atom_surface_sync*)atom;
  65
  66         cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
  67         cs->buf[cs->cdw++] = a->flush_flags;  /* CP_COHER_CNTL */
  68         cs->buf[cs->cdw++] = 0xffffffff;      /* CP_COHER_SIZE */
  69         cs->buf[cs->cdw++] = 0;               /* CP_COHER_BASE */
  70         cs->buf[cs->cdw++] = 0x0000000A;      /* POLL_INTERVAL */
  71
  72         a->flush_flags = 0;
  73 }
  74
  75 static void r600_emit_r6xx_flush_and_inv(struct r600_context *rctx, struct r600_atom *atom)
  76 {
  77         struct radeon_winsys_cs *cs = rctx->cs;
  78         cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
  79         cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
  80 }
  81
  82 static void r600_init_atom(struct r600_atom *atom,
  83                            void (*emit)(struct r600_context *ctx, struct r600_atom *state),
  84                            unsigned num_dw,
  85                            enum r600_atom_flags flags)
  86 {
  87         atom->emit = emit;
  88         atom->num_dw = num_dw;
  89         atom->flags = flags;
  90 }
  91
  92 void r600_init_common_atoms(struct r600_context *rctx)
  93 {
  94         r600_init_atom(&rctx->atom_surface_sync.atom,   r600_emit_surface_sync,         5, EMIT_EARLY);
  95         r600_init_atom(&rctx->atom_r6xx_flush_and_inv,  r600_emit_r6xx_flush_and_inv,   2, EMIT_EARLY);
  96 }
  97
  98 unsigned r600_get_cb_flush_flags(struct r600_context *rctx)
  99 {
 100         unsigned flags = 0;
 101
 102         if (rctx->framebuffer.nr_cbufs) {
 103                 flags |= S_0085F0_CB_ACTION_ENA(1) |
 104                          (((1 << rctx->framebuffer.nr_cbufs) - 1) << S_0085F0_CB0_DEST_BASE_ENA_SHIFT);
 105         }
 106
 107         /* Workaround for broken flushing on some R6xx chipsets. */
 108         if (rctx->family == CHIP_RV670 ||
 109             rctx->family == CHIP_RS780 ||
 110             rctx->family == CHIP_RS880) {
 111                 flags |=  S_0085F0_CB1_DEST_BASE_ENA(1) |
 112                           S_0085F0_DEST_BASE_0_ENA(1);
 113         }
 114         return flags;
 115 }
 116
 117 void r600_texture_barrier(struct pipe_context *ctx)
 118 {
 119         struct r600_context *rctx = (struct r600_context *)ctx;
 120
 121         rctx->atom_surface_sync.flush_flags |= S_0085F0_TC_ACTION_ENA(1) | r600_get_cb_flush_flags(rctx);
 122         r600_atom_dirty(rctx, &rctx->atom_surface_sync.atom);
 123 }
 124
 125 static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
 126 {
 127         static const int prim_conv[] = {
 128                 V_008958_DI_PT_POINTLIST,
 129                 V_008958_DI_PT_LINELIST,
 130                 V_008958_DI_PT_LINELOOP,
 131                 V_008958_DI_PT_LINESTRIP,
 132                 V_008958_DI_PT_TRILIST,
 133                 V_008958_DI_PT_TRISTRIP,
 134                 V_008958_DI_PT_TRIFAN,
 135                 V_008958_DI_PT_QUADLIST,
 136                 V_008958_DI_PT_QUADSTRIP,
 137                 V_008958_DI_PT_POLYGON,
 138                 -1,
 139                 -1,
 140                 -1,
 141                 -1
 142         };
 143
 144         *prim = prim_conv[pprim];
 145         if (*prim == -1) {
 146                 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim);
 147                 return false;
 148         }
 149         return true;
 150 }
 151
 152 /* common state between evergreen and r600 */
 153 void r600_bind_blend_state(struct pipe_context *ctx, void *state)
 154 {
 155         struct r600_context *rctx = (struct r600_context *)ctx;
 156         struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
 157         struct r600_pipe_state *rstate;
 158
 159         if (state == NULL)
 160                 return;
 161         rstate = &blend->rstate;
 162         rctx->states[rstate->id] = rstate;
 163         rctx->cb_target_mask = blend->cb_target_mask;
 164
 165         /* Replace every bit except MULTIWRITE_ENABLE. */
 166         rctx->cb_color_control &= ~C_028808_MULTIWRITE_ENABLE;
 167         rctx->cb_color_control |= blend->cb_color_control & C_028808_MULTIWRITE_ENABLE;
 168
 169         r600_context_pipe_state_set(rctx, rstate);
 170 }
 171
 172 void r600_set_blend_color(struct pipe_context *ctx,
 173                           const struct pipe_blend_color *state)
 174 {
 175         struct r600_context *rctx = (struct r600_context *)ctx;
 176         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 177
 178         if (rstate == NULL)
 179                 return;
 180
 181         rstate->id = R600_PIPE_STATE_BLEND_COLOR;
 182         r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), NULL, 0);
 183         r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), NULL, 0);
 184         r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), NULL, 0);
 185         r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), NULL, 0);
 186
 187         free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
 188         rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
 189         r600_context_pipe_state_set(rctx, rstate);
 190 }
 191
 192 static void r600_set_stencil_ref(struct pipe_context *ctx,
 193                                  const struct r600_stencil_ref *state)
 194 {
 195         struct r600_context *rctx = (struct r600_context *)ctx;
 196         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 197
 198         if (rstate == NULL)
 199                 return;
 200
 201         rstate->id = R600_PIPE_STATE_STENCIL_REF;
 202         r600_pipe_state_add_reg(rstate,
 203                                 R_028430_DB_STENCILREFMASK,
 204                                 S_028430_STENCILREF(state->ref_value[0]) |
 205                                 S_028430_STENCILMASK(state->valuemask[0]) |
 206                                 S_028430_STENCILWRITEMASK(state->writemask[0]),
 207                                 NULL, 0);
 208         r600_pipe_state_add_reg(rstate,
 209                                 R_028434_DB_STENCILREFMASK_BF,
 210                                 S_028434_STENCILREF_BF(state->ref_value[1]) |
 211                                 S_028434_STENCILMASK_BF(state->valuemask[1]) |
 212                                 S_028434_STENCILWRITEMASK_BF(state->writemask[1]),
 213                                 NULL, 0);
 214
 215         free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
 216         rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
 217         r600_context_pipe_state_set(rctx, rstate);
 218 }
 219
 220 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
 221                                const struct pipe_stencil_ref *state)
 222 {
 223         struct r600_context *rctx = (struct r600_context *)ctx;
 224         struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA];
 225         struct r600_stencil_ref ref;
 226
 227         rctx->stencil_ref = *state;
 228
 229         if (!dsa)
 230                 return;
 231
 232         ref.ref_value[0] = state->ref_value[0];
 233         ref.ref_value[1] = state->ref_value[1];
 234         ref.valuemask[0] = dsa->valuemask[0];
 235         ref.valuemask[1] = dsa->valuemask[1];
 236         ref.writemask[0] = dsa->writemask[0];
 237         ref.writemask[1] = dsa->writemask[1];
 238
 239         r600_set_stencil_ref(ctx, &ref);
 240 }
 241
 242 void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
 243 {
 244         struct r600_context *rctx = (struct r600_context *)ctx;
 245         struct r600_pipe_dsa *dsa = state;
 246         struct r600_pipe_state *rstate;
 247         struct r600_stencil_ref ref;
 248
 249         if (state == NULL)
 250                 return;
 251         rstate = &dsa->rstate;
 252         rctx->states[rstate->id] = rstate;
 253         rctx->alpha_ref = dsa->alpha_ref;
 254         rctx->alpha_ref_dirty = true;
 255         r600_context_pipe_state_set(rctx, rstate);
 256
 257         ref.ref_value[0] = rctx->stencil_ref.ref_value[0];
 258         ref.ref_value[1] = rctx->stencil_ref.ref_value[1];
 259         ref.valuemask[0] = dsa->valuemask[0];
 260         ref.valuemask[1] = dsa->valuemask[1];
 261         ref.writemask[0] = dsa->writemask[0];
 262         ref.writemask[1] = dsa->writemask[1];
 263
 264         r600_set_stencil_ref(ctx, &ref);
 265 }
 266
 267 void r600_bind_rs_state(struct pipe_context *ctx, void *state)
 268 {
 269         struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
 270         struct r600_context *rctx = (struct r600_context *)ctx;
 271
 272         if (state == NULL)
 273                 return;
 274
 275         rctx->sprite_coord_enable = rs->sprite_coord_enable;
 276         rctx->two_side = rs->two_side;
 277         rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
 278         rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
 279
 280         rctx->rasterizer = rs;
 281
 282         rctx->states[rs->rstate.id] = &rs->rstate;
 283         r600_context_pipe_state_set(rctx, &rs->rstate);
 284
 285         if (rctx->chip_class >= EVERGREEN) {
 286                 evergreen_polygon_offset_update(rctx);
 287         } else {
 288                 r600_polygon_offset_update(rctx);
 289         }
 290 }
 291
 292 void r600_delete_rs_state(struct pipe_context *ctx, void *state)
 293 {
 294         struct r600_context *rctx = (struct r600_context *)ctx;
 295         struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
 296
 297         if (rctx->rasterizer == rs) {
 298                 rctx->rasterizer = NULL;
 299         }
 300         if (rctx->states[rs->rstate.id] == &rs->rstate) {
 301                 rctx->states[rs->rstate.id] = NULL;
 302         }
 303         free(rs);
 304 }
 305
 306 void r600_sampler_view_destroy(struct pipe_context *ctx,
 307                                struct pipe_sampler_view *state)
 308 {
 309         struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
 310
 311         pipe_resource_reference(&state->texture, NULL);
 312         FREE(resource);
 313 }
 314
 315 void r600_delete_state(struct pipe_context *ctx, void *state)
 316 {
 317         struct r600_context *rctx = (struct r600_context *)ctx;
 318         struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
 319
 320         if (rctx->states[rstate->id] == rstate) {
 321                 rctx->states[rstate->id] = NULL;
 322         }
 323         for (int i = 0; i < rstate->nregs; i++) {
 324                 pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL);
 325         }
 326         free(rstate);
 327 }
 328
 329 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
 330 {
 331         struct r600_context *rctx = (struct r600_context *)ctx;
 332         struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 333
 334         rctx->vertex_elements = v;
 335         if (v) {
 336                 r600_inval_shader_cache(rctx);
 337                 u_vbuf_bind_vertex_elements(rctx->vbuf_mgr, state,
 338                                                 v->vmgr_elements);
 339
 340                 rctx->states[v->rstate.id] = &v->rstate;
 341                 r600_context_pipe_state_set(rctx, &v->rstate);
 342         }
 343 }
 344
 345 void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
 346 {
 347         struct r600_context *rctx = (struct r600_context *)ctx;
 348         struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 349
 350         if (rctx->states[v->rstate.id] == &v->rstate) {
 351                 rctx->states[v->rstate.id] = NULL;
 352         }
 353         if (rctx->vertex_elements == state)
 354                 rctx->vertex_elements = NULL;
 355
 356         pipe_resource_reference((struct pipe_resource**)&v->fetch_shader, NULL);
 357         u_vbuf_destroy_vertex_elements(rctx->vbuf_mgr, v->vmgr_elements);
 358         FREE(state);
 359 }
 360
 361
 362 void r600_set_index_buffer(struct pipe_context *ctx,
 363                            const struct pipe_index_buffer *ib)
 364 {
 365         struct r600_context *rctx = (struct r600_context *)ctx;
 366
 367         u_vbuf_set_index_buffer(rctx->vbuf_mgr, ib);
 368 }
 369
 370 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
 371                              const struct pipe_vertex_buffer *buffers)
 372 {
 373         struct r600_context *rctx = (struct r600_context *)ctx;
 374         int i;
 375
 376         /* Zero states. */
 377         for (i = 0; i < count; i++) {
 378                 if (!buffers[i].buffer) {
 379                         if (rctx->chip_class >= EVERGREEN) {
 380                                 evergreen_context_pipe_state_set_fs_resource(rctx, NULL, i);
 381                         } else {
 382                                 r600_context_pipe_state_set_fs_resource(rctx, NULL, i);
 383                         }
 384                 }
 385         }
 386         for (; i < rctx->vbuf_mgr->nr_real_vertex_buffers; i++) {
 387                 if (rctx->chip_class >= EVERGREEN) {
 388                         evergreen_context_pipe_state_set_fs_resource(rctx, NULL, i);
 389                 } else {
 390                         r600_context_pipe_state_set_fs_resource(rctx, NULL, i);
 391                 }
 392         }
 393
 394         u_vbuf_set_vertex_buffers(rctx->vbuf_mgr, count, buffers);
 395 }
 396
 397 void *r600_create_vertex_elements(struct pipe_context *ctx,
 398                                   unsigned count,
 399                                   const struct pipe_vertex_element *elements)
 400 {
 401         struct r600_context *rctx = (struct r600_context *)ctx;
 402         struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
 403
 404         assert(count < 32);
 405         if (!v)
 406                 return NULL;
 407
 408         v->count = count;
 409         v->vmgr_elements =
 410                 u_vbuf_create_vertex_elements(rctx->vbuf_mgr, count,
 411                                                   elements, v->elements);
 412
 413         if (r600_vertex_elements_build_fetch_shader(rctx, v)) {
 414                 FREE(v);
 415                 return NULL;
 416         }
 417
 418         return v;
 419 }
 420
 421 void *r600_create_shader_state(struct pipe_context *ctx,
 422                                const struct pipe_shader_state *state)
 423 {
 424         struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader);
 425         int r;
 426
 427         shader->tokens = tgsi_dup_tokens(state->tokens);
 428         shader->so = state->stream_output;
 429
 430         r =  r600_pipe_shader_create(ctx, shader);
 431         if (r) {
 432                 return NULL;
 433         }
 434         return shader;
 435 }
 436
 437 void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
 438 {
 439         struct r600_context *rctx = (struct r600_context *)ctx;
 440
 441         /* TODO delete old shader */
 442         rctx->ps_shader = (struct r600_pipe_shader *)state;
 443         if (state) {
 444                 r600_inval_shader_cache(rctx);
 445                 r600_context_pipe_state_set(rctx, &rctx->ps_shader->rstate);
 446
 447                 rctx->cb_color_control &= C_028808_MULTIWRITE_ENABLE;
 448                 rctx->cb_color_control |= S_028808_MULTIWRITE_ENABLE(!!rctx->ps_shader->shader.fs_write_all);
 449         }
 450         if (rctx->ps_shader && rctx->vs_shader) {
 451                 r600_adjust_gprs(rctx);
 452         }
 453 }
 454
 455 void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
 456 {
 457         struct r600_context *rctx = (struct r600_context *)ctx;
 458
 459         /* TODO delete old shader */
 460         rctx->vs_shader = (struct r600_pipe_shader *)state;
 461         if (state) {
 462                 r600_inval_shader_cache(rctx);
 463                 r600_context_pipe_state_set(rctx, &rctx->vs_shader->rstate);
 464         }
 465         if (rctx->ps_shader && rctx->vs_shader) {
 466                 r600_adjust_gprs(rctx);
 467         }
 468 }
 469
 470 void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
 471 {
 472         struct r600_context *rctx = (struct r600_context *)ctx;
 473         struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
 474
 475         if (rctx->ps_shader == shader) {
 476                 rctx->ps_shader = NULL;
 477         }
 478
 479         free(shader->tokens);
 480         r600_pipe_shader_destroy(ctx, shader);
 481         free(shader);
 482 }
 483
 484 void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
 485 {
 486         struct r600_context *rctx = (struct r600_context *)ctx;
 487         struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
 488
 489         if (rctx->vs_shader == shader) {
 490                 rctx->vs_shader = NULL;
 491         }
 492
 493         free(shader->tokens);
 494         r600_pipe_shader_destroy(ctx, shader);
 495         free(shader);
 496 }
 497
 498 static void r600_update_alpha_ref(struct r600_context *rctx)
 499 {
 500         unsigned alpha_ref;
 501         struct r600_pipe_state rstate;
 502
 503         alpha_ref = rctx->alpha_ref;
 504         rstate.nregs = 0;
 505         if (rctx->export_16bpc)
 506                 alpha_ref &= ~0x1FFF;
 507         r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref, NULL, 0);
 508
 509         r600_context_pipe_state_set(rctx, &rstate);
 510         rctx->alpha_ref_dirty = false;
 511 }
 512
 513 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 514                               struct pipe_resource *buffer)
 515 {
 516         struct r600_context *rctx = (struct r600_context *)ctx;
 517         struct r600_resource *rbuffer = r600_resource(buffer);
 518         struct r600_pipe_resource_state *rstate;
 519         uint64_t va_offset;
 520         uint32_t offset;
 521
 522         /* Note that the state tracker can unbind constant buffers by
 523          * passing NULL here.
 524          */
 525         if (buffer == NULL) {
 526                 return;
 527         }
 528
 529         r600_inval_shader_cache(rctx);
 530
 531         r600_upload_const_buffer(rctx, &rbuffer, &offset);
 532         va_offset = r600_resource_va(ctx->screen, (void*)rbuffer);
 533         va_offset += offset;
 534         va_offset >>= 8;
 535
 536         switch (shader) {
 537         case PIPE_SHADER_VERTEX:
 538                 rctx->vs_const_buffer.nregs = 0;
 539                 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
 540                                         R_028180_ALU_CONST_BUFFER_SIZE_VS_0 + index * 4,
 541                                         ALIGN_DIVUP(buffer->width0 >> 4, 16),
 542                                         NULL, 0);
 543                 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
 544                                         R_028980_ALU_CONST_CACHE_VS_0 + index * 4,
 545                                         va_offset, rbuffer, RADEON_USAGE_READ);
 546                 r600_context_pipe_state_set(rctx, &rctx->vs_const_buffer);
 547
 548                 rstate = &rctx->vs_const_buffer_resource[index];
 549                 if (!rstate->id) {
 550                         if (rctx->chip_class >= EVERGREEN) {
 551                                 evergreen_pipe_init_buffer_resource(rctx, rstate);
 552                         } else {
 553                                 r600_pipe_init_buffer_resource(rctx, rstate);
 554                         }
 555                 }
 556
 557                 if (rctx->chip_class >= EVERGREEN) {
 558                         evergreen_pipe_mod_buffer_resource(ctx, rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 559                         evergreen_context_pipe_state_set_vs_resource(rctx, rstate, index);
 560                 } else {
 561                         r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 562                         r600_context_pipe_state_set_vs_resource(rctx, rstate, index);
 563                 }
 564                 break;
 565         case PIPE_SHADER_FRAGMENT:
 566                 rctx->ps_const_buffer.nregs = 0;
 567                 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
 568                                         R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
 569                                         ALIGN_DIVUP(buffer->width0 >> 4, 16),
 570                                         NULL, 0);
 571                 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
 572                                         R_028940_ALU_CONST_CACHE_PS_0,
 573                                         va_offset, rbuffer, RADEON_USAGE_READ);
 574                 r600_context_pipe_state_set(rctx, &rctx->ps_const_buffer);
 575
 576                 rstate = &rctx->ps_const_buffer_resource[index];
 577                 if (!rstate->id) {
 578                         if (rctx->chip_class >= EVERGREEN) {
 579                                 evergreen_pipe_init_buffer_resource(rctx, rstate);
 580                         } else {
 581                                 r600_pipe_init_buffer_resource(rctx, rstate);
 582                         }
 583                 }
 584                 if (rctx->chip_class >= EVERGREEN) {
 585                         evergreen_pipe_mod_buffer_resource(ctx, rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 586                         evergreen_context_pipe_state_set_ps_resource(rctx, rstate, index);
 587                 } else {
 588                         r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 589                         r600_context_pipe_state_set_ps_resource(rctx, rstate, index);
 590                 }
 591                 break;
 592         default:
 593                 R600_ERR("unsupported %d\n", shader);
 594                 return;
 595         }
 596
 597         if (buffer != &rbuffer->b.b.b)
 598                 pipe_resource_reference((struct pipe_resource**)&rbuffer, NULL);
 599 }
 600
 601 struct pipe_stream_output_target *
 602 r600_create_so_target(struct pipe_context *ctx,
 603                       struct pipe_resource *buffer,
 604                       unsigned buffer_offset,
 605                       unsigned buffer_size)
 606 {
 607         struct r600_context *rctx = (struct r600_context *)ctx;
 608         struct r600_so_target *t;
 609         void *ptr;
 610
 611         t = CALLOC_STRUCT(r600_so_target);
 612         if (!t) {
 613                 return NULL;
 614         }
 615
 616         t->b.reference.count = 1;
 617         t->b.context = ctx;
 618         pipe_resource_reference(&t->b.buffer, buffer);
 619         t->b.buffer_offset = buffer_offset;
 620         t->b.buffer_size = buffer_size;
 621
 622         t->filled_size = (struct r600_resource*)
 623                 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4);
 624         ptr = rctx->ws->buffer_map(t->filled_size->buf, rctx->cs, PIPE_TRANSFER_WRITE);
 625         memset(ptr, 0, t->filled_size->buf->size);
 626         rctx->ws->buffer_unmap(t->filled_size->buf);
 627
 628         return &t->b;
 629 }
 630
 631 void r600_so_target_destroy(struct pipe_context *ctx,
 632                             struct pipe_stream_output_target *target)
 633 {
 634         struct r600_so_target *t = (struct r600_so_target*)target;
 635         pipe_resource_reference(&t->b.buffer, NULL);
 636         pipe_resource_reference((struct pipe_resource**)&t->filled_size, NULL);
 637         FREE(t);
 638 }
 639
 640 void r600_set_so_targets(struct pipe_context *ctx,
 641                          unsigned num_targets,
 642                          struct pipe_stream_output_target **targets,
 643                          unsigned append_bitmask)
 644 {
 645         struct r600_context *rctx = (struct r600_context *)ctx;
 646         unsigned i;
 647
 648         /* Stop streamout. */
 649         if (rctx->num_so_targets) {
 650                 r600_context_streamout_end(rctx);
 651         }
 652
 653         /* Set the new targets. */
 654         for (i = 0; i < num_targets; i++) {
 655                 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]);
 656         }
 657         for (; i < rctx->num_so_targets; i++) {
 658                 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL);
 659         }
 660
 661         rctx->num_so_targets = num_targets;
 662         rctx->streamout_start = num_targets != 0;
 663         rctx->streamout_append_bitmask = append_bitmask;
 664 }
 665
 666 static void r600_vertex_buffer_update(struct r600_context *rctx)
 667 {
 668         struct r600_pipe_resource_state *rstate;
 669         struct r600_resource *rbuffer;
 670         struct pipe_vertex_buffer *vertex_buffer;
 671         unsigned i, count, offset;
 672
 673         r600_inval_vertex_cache(rctx);
 674
 675         if (rctx->vertex_elements->vbuffer_need_offset) {
 676                 /* one resource per vertex elements */
 677                 count = rctx->vertex_elements->count;
 678         } else {
 679                 /* bind vertex buffer once */
 680                 count = rctx->vbuf_mgr->nr_real_vertex_buffers;
 681         }
 682
 683         for (i = 0 ; i < count; i++) {
 684                 rstate = &rctx->fs_resource[i];
 685
 686                 if (rctx->vertex_elements->vbuffer_need_offset) {
 687                         /* one resource per vertex elements */
 688                         unsigned vbuffer_index;
 689                         vbuffer_index = rctx->vertex_elements->elements[i].vertex_buffer_index;
 690                         vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[vbuffer_index];
 691                         rbuffer = (struct r600_resource*)vertex_buffer->buffer;
 692                         offset = rctx->vertex_elements->vbuffer_offset[i];
 693                 } else {
 694                         /* bind vertex buffer once */
 695                         vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[i];
 696                         rbuffer = (struct r600_resource*)vertex_buffer->buffer;
 697                         offset = 0;
 698                 }
 699                 if (vertex_buffer == NULL || rbuffer == NULL)
 700                         continue;
 701                 offset += vertex_buffer->buffer_offset;
 702
 703                 if (!rstate->id) {
 704                         if (rctx->chip_class >= EVERGREEN) {
 705                                 evergreen_pipe_init_buffer_resource(rctx, rstate);
 706                         } else {
 707                                 r600_pipe_init_buffer_resource(rctx, rstate);
 708                         }
 709                 }
 710
 711                 if (rctx->chip_class >= EVERGREEN) {
 712                         evergreen_pipe_mod_buffer_resource(&rctx->context, rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ);
 713                         evergreen_context_pipe_state_set_fs_resource(rctx, rstate, i);
 714                 } else {
 715                         r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ);
 716                         r600_context_pipe_state_set_fs_resource(rctx, rstate, i);
 717                 }
 718         }
 719 }
 720
 721 static int r600_shader_rebuild(struct pipe_context * ctx, struct r600_pipe_shader * shader)
 722 {
 723         struct r600_context *rctx = (struct r600_context *)ctx;
 724         int r;
 725
 726         r600_pipe_shader_destroy(ctx, shader);
 727         r = r600_pipe_shader_create(ctx, shader);
 728         if (r) {
 729                 return r;
 730         }
 731         r600_context_pipe_state_set(rctx, &shader->rstate);
 732
 733         return 0;
 734 }
 735
 736 static void r600_update_derived_state(struct r600_context *rctx)
 737 {
 738         struct pipe_context * ctx = (struct pipe_context*)rctx;
 739         struct r600_pipe_state rstate;
 740
 741         rstate.nregs = 0;
 742
 743         if (rstate.nregs)
 744                 r600_context_pipe_state_set(rctx, &rstate);
 745
 746         if (!rctx->blitter->running) {
 747                 if (rctx->have_depth_fb || rctx->have_depth_texture)
 748                         r600_flush_depth_textures(rctx);
 749         }
 750
 751         if (rctx->chip_class < EVERGREEN) {
 752                 r600_update_sampler_states(rctx);
 753         }
 754
 755         if ((rctx->ps_shader->shader.two_side != rctx->two_side) ||
 756             ((rctx->chip_class >= EVERGREEN) && rctx->ps_shader->shader.fs_write_all &&
 757              (rctx->ps_shader->shader.nr_cbufs != rctx->nr_cbufs))) {
 758                 r600_shader_rebuild(&rctx->context, rctx->ps_shader);
 759         }
 760
 761         if (rctx->alpha_ref_dirty) {
 762                 r600_update_alpha_ref(rctx);
 763         }
 764
 765         if (rctx->ps_shader && ((rctx->sprite_coord_enable &&
 766                 (rctx->ps_shader->sprite_coord_enable != rctx->sprite_coord_enable)) ||
 767                 (rctx->rasterizer && rctx->rasterizer->flatshade != rctx->ps_shader->flatshade))) {
 768
 769                 if (rctx->chip_class >= EVERGREEN)
 770                         evergreen_pipe_shader_ps(ctx, rctx->ps_shader);
 771                 else
 772                         r600_pipe_shader_ps(ctx, rctx->ps_shader);
 773
 774                 r600_context_pipe_state_set(rctx, &rctx->ps_shader->rstate);
 775         }
 776
 777 }
 778
 779 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
 780 {
 781         struct r600_context *rctx = (struct r600_context *)ctx;
 782         struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA];
 783         struct pipe_draw_info info = *dinfo;
 784         struct r600_draw rdraw = {};
 785         struct pipe_index_buffer ib = {};
 786         unsigned prim, mask, ls_mask = 0;
 787         struct r600_block *dirty_block = NULL, *next_block = NULL;
 788         struct r600_atom *state = NULL, *next_state = NULL;
 789
 790         if ((!info.count && (info.indexed || !info.count_from_stream_output)) ||
 791             (info.indexed && !rctx->vbuf_mgr->index_buffer.buffer) ||
 792             !r600_conv_pipe_prim(info.mode, &prim)) {
 793                 return;
 794         }
 795
 796         if (!rctx->ps_shader || !rctx->vs_shader)
 797                 return;
 798
 799         r600_update_derived_state(rctx);
 800
 801         u_vbuf_draw_begin(rctx->vbuf_mgr, &info);
 802         r600_vertex_buffer_update(rctx);
 803
 804         rdraw.vgt_num_indices = info.count;
 805         rdraw.vgt_num_instances = info.instance_count;
 806
 807         if (info.indexed) {
 808                 /* Initialize the index buffer struct. */
 809                 pipe_resource_reference(&ib.buffer, rctx->vbuf_mgr->index_buffer.buffer);
 810                 ib.index_size = rctx->vbuf_mgr->index_buffer.index_size;
 811                 ib.offset = rctx->vbuf_mgr->index_buffer.offset + info.start * ib.index_size;
 812
 813                 /* Translate or upload, if needed. */
 814                 r600_translate_index_buffer(rctx, &ib, info.count);
 815
 816                 if (u_vbuf_resource(ib.buffer)->user_ptr) {
 817                         r600_upload_index_buffer(rctx, &ib, info.count);
 818                 }
 819
 820                 /* Initialize the r600_draw struct with index buffer info. */
 821                 if (ib.index_size == 4) {
 822                         rdraw.vgt_index_type = VGT_INDEX_32 |
 823                                 (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0);
 824                 } else {
 825                         rdraw.vgt_index_type = VGT_INDEX_16 |
 826                                 (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0);
 827                 }
 828                 rdraw.indices = (struct r600_resource*)ib.buffer;
 829                 rdraw.indices_bo_offset = ib.offset;
 830                 rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_DMA;
 831         } else {
 832                 info.index_bias = info.start;
 833                 rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_AUTO_INDEX;
 834                 if (info.count_from_stream_output) {
 835                         rdraw.vgt_draw_initiator |= S_0287F0_USE_OPAQUE(1);
 836
 837                         r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info.count_from_stream_output);
 838                 }
 839         }
 840
 841         mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
 842
 843         if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
 844                 rctx->vgt.id = R600_PIPE_STATE_VGT;
 845                 rctx->vgt.nregs = 0;
 846                 r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, NULL, 0);
 847                 r600_pipe_state_add_reg(&rctx->vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, NULL, 0);
 848                 r600_pipe_state_add_reg(&rctx->vgt, R_028400_VGT_MAX_VTX_INDX, ~0, NULL, 0);
 849                 r600_pipe_state_add_reg(&rctx->vgt, R_028404_VGT_MIN_VTX_INDX, 0, NULL, 0);
 850                 r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias, NULL, 0);
 851                 r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index, NULL, 0);
 852                 r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart, NULL, 0);
 853                 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, NULL, 0);
 854                 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance, NULL, 0);
 855                 r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0, NULL, 0);
 856                 if (rctx->chip_class <= R700)
 857                         r600_pipe_state_add_reg(&rctx->vgt, R_028808_CB_COLOR_CONTROL, rctx->cb_color_control, NULL, 0);
 858                 r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0, NULL, 0);
 859                 r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0, NULL, 0);
 860         }
 861
 862         rctx->vgt.nregs = 0;
 863         r600_pipe_state_mod_reg(&rctx->vgt, prim);
 864         r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_target_mask & mask);
 865         r600_pipe_state_mod_reg(&rctx->vgt, ~0);
 866         r600_pipe_state_mod_reg(&rctx->vgt, 0);
 867         r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
 868         r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
 869         r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart);
 870         r600_pipe_state_mod_reg(&rctx->vgt, 0);
 871         r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance);
 872
 873         if (prim == V_008958_DI_PT_LINELIST)
 874                 ls_mask = 1;
 875         else if (prim == V_008958_DI_PT_LINESTRIP)
 876                 ls_mask = 2;
 877         r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask) | rctx->pa_sc_line_stipple);
 878         if (rctx->chip_class <= R700)
 879                 r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_color_control);
 880         r600_pipe_state_mod_reg(&rctx->vgt,
 881                                 rctx->vs_shader->pa_cl_vs_out_cntl |
 882                                 (rctx->rasterizer->clip_plane_enable & rctx->vs_shader->shader.clip_dist_write));
 883         r600_pipe_state_mod_reg(&rctx->vgt,
 884                                 rctx->pa_cl_clip_cntl |
 885                                 (rctx->vs_shader->shader.clip_dist_write ||
 886                                  rctx->vs_shader->shader.vs_prohibit_ucps ?
 887                                  0 : rctx->rasterizer->clip_plane_enable & 0x3F));
 888
 889         r600_context_pipe_state_set(rctx, &rctx->vgt);
 890
 891         rdraw.db_render_override = dsa->db_render_override;
 892         rdraw.db_render_control = dsa->db_render_control;
 893
 894         /* Emit states. */
 895         r600_need_cs_space(rctx, 0, TRUE);
 896
 897         LIST_FOR_EACH_ENTRY_SAFE(state, next_state, &rctx->dirty_states, head) {
 898                 r600_emit_atom(rctx, state);
 899         }
 900         LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) {
 901                 r600_context_block_emit_dirty(rctx, dirty_block);
 902         }
 903         LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->resource_dirty,list) {
 904                 r600_context_block_resource_emit_dirty(rctx, dirty_block);
 905         }
 906         rctx->pm4_dirty_cdwords = 0;
 907
 908         /* Enable stream out if needed. */
 909         if (rctx->streamout_start) {
 910                 r600_context_streamout_begin(rctx);
 911                 rctx->streamout_start = FALSE;
 912         }
 913
 914         if (rctx->chip_class >= EVERGREEN) {
 915                 evergreen_context_draw(rctx, &rdraw);
 916         } else {
 917                 r600_context_draw(rctx, &rdraw);
 918         }
 919
 920         rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING;
 921
 922         if (rctx->framebuffer.zsbuf)
 923         {
 924                 struct pipe_resource *tex = rctx->framebuffer.zsbuf->texture;
 925                 ((struct r600_resource_texture *)tex)->dirty_db = TRUE;
 926         }
 927
 928         pipe_resource_reference(&ib.buffer, NULL);
 929         u_vbuf_draw_end(rctx->vbuf_mgr);
 930 }
 931
 932 void _r600_pipe_state_add_reg(struct r600_context *ctx,
 933                               struct r600_pipe_state *state,
 934                               uint32_t offset, uint32_t value,
 935                               uint32_t range_id, uint32_t block_id,
 936                               struct r600_resource *bo,
 937                               enum radeon_bo_usage usage)
 938 {
 939         struct r600_range *range;
 940         struct r600_block *block;
 941
 942         if (bo) assert(usage);
 943
 944         range = &ctx->range[range_id];
 945         block = range->blocks[block_id];
 946         state->regs[state->nregs].block = block;
 947         state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
 948
 949         state->regs[state->nregs].value = value;
 950         state->regs[state->nregs].bo = bo;
 951         state->regs[state->nregs].bo_usage = usage;
 952
 953         state->nregs++;
 954         assert(state->nregs < R600_BLOCK_MAX_REG);
 955 }
 956
 957 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
 958                                      uint32_t offset, uint32_t value,
 959                                      struct r600_resource *bo,
 960                                      enum radeon_bo_usage usage)
 961 {
 962         if (bo) assert(usage);
 963
 964         state->regs[state->nregs].id = offset;
 965         state->regs[state->nregs].block = NULL;
 966         state->regs[state->nregs].value = value;
 967         state->regs[state->nregs].bo = bo;
 968         state->regs[state->nregs].bo_usage = usage;
 969
 970         state->nregs++;
 971         assert(state->nregs < R600_BLOCK_MAX_REG);
 972 }
 973
 974 uint32_t r600_translate_stencil_op(int s_op)
 975 {
 976         switch (s_op) {
 977         case PIPE_STENCIL_OP_KEEP:
 978                 return V_028800_STENCIL_KEEP;
 979         case PIPE_STENCIL_OP_ZERO:
 980                 return V_028800_STENCIL_ZERO;
 981         case PIPE_STENCIL_OP_REPLACE:
 982                 return V_028800_STENCIL_REPLACE;
 983         case PIPE_STENCIL_OP_INCR:
 984                 return V_028800_STENCIL_INCR;
 985         case PIPE_STENCIL_OP_DECR:
 986                 return V_028800_STENCIL_DECR;
 987         case PIPE_STENCIL_OP_INCR_WRAP:
 988                 return V_028800_STENCIL_INCR_WRAP;
 989         case PIPE_STENCIL_OP_DECR_WRAP:
 990                 return V_028800_STENCIL_DECR_WRAP;
 991         case PIPE_STENCIL_OP_INVERT:
 992                 return V_028800_STENCIL_INVERT;
 993         default:
 994                 R600_ERR("Unknown stencil op %d", s_op);
 995                 assert(0);
 996                 break;
 997         }
 998         return 0;
 999 }
1000
1001 uint32_t r600_translate_fill(uint32_t func)
1002 {
1003         switch(func) {
1004         case PIPE_POLYGON_MODE_FILL:
1005                 return 2;
1006         case PIPE_POLYGON_MODE_LINE:
1007                 return 1;
1008         case PIPE_POLYGON_MODE_POINT:
1009                 return 0;
1010         default:
1011                 assert(0);
1012                 return 0;
1013         }
1014 }
1015
1016 unsigned r600_tex_wrap(unsigned wrap)
1017 {
1018         switch (wrap) {
1019         default:
1020         case PIPE_TEX_WRAP_REPEAT:
1021                 return V_03C000_SQ_TEX_WRAP;
1022         case PIPE_TEX_WRAP_CLAMP:
1023                 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1024         case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1025                 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1026         case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1027                 return V_03C000_SQ_TEX_CLAMP_BORDER;
1028         case PIPE_TEX_WRAP_MIRROR_REPEAT:
1029                 return V_03C000_SQ_TEX_MIRROR;
1030         case PIPE_TEX_WRAP_MIRROR_CLAMP:
1031                 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1032         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1033                 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1034         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1035                 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1036         }
1037 }
1038
1039 unsigned r600_tex_filter(unsigned filter)
1040 {
1041         switch (filter) {
1042         default:
1043         case PIPE_TEX_FILTER_NEAREST:
1044                 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1045         case PIPE_TEX_FILTER_LINEAR:
1046                 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1047         }
1048 }
1049
1050 unsigned r600_tex_mipfilter(unsigned filter)
1051 {
1052         switch (filter) {
1053         case PIPE_TEX_MIPFILTER_NEAREST:
1054                 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1055         case PIPE_TEX_MIPFILTER_LINEAR:
1056                 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1057         default:
1058         case PIPE_TEX_MIPFILTER_NONE:
1059                 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1060         }
1061 }
1062
1063 unsigned r600_tex_compare(unsigned compare)
1064 {
1065         switch (compare) {
1066         default:
1067         case PIPE_FUNC_NEVER:
1068                 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1069         case PIPE_FUNC_LESS:
1070                 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1071         case PIPE_FUNC_EQUAL:
1072                 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1073         case PIPE_FUNC_LEQUAL:
1074                 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1075         case PIPE_FUNC_GREATER:
1076                 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1077         case PIPE_FUNC_NOTEQUAL:
1078                 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1079         case PIPE_FUNC_GEQUAL:
1080                 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1081         case PIPE_FUNC_ALWAYS:
1082                 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1083         }
1084 }