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r600g: put sampler states and views into an array indexed by shader type
[mesa.git] / src / gallium / drivers / r600 / r600_state_common.c
1 /*
2 * Copyright 2010 Red Hat Inc.
3 * 2010 Jerome Glisse
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
26 */
27 #include "r600_formats.h"
28 #include "r600d.h"
29
30 #include "util/u_draw_quad.h"
31 #include "util/u_upload_mgr.h"
32 #include "tgsi/tgsi_parse.h"
33 #include <byteswap.h>
34
35 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
36
37 static void r600_emit_command_buffer(struct r600_context *rctx, struct r600_atom *atom)
38 {
39 struct radeon_winsys_cs *cs = rctx->cs;
40 struct r600_command_buffer *cb = (struct r600_command_buffer*)atom;
41
42 assert(cs->cdw + cb->atom.num_dw <= RADEON_MAX_CMDBUF_DWORDS);
43 memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->atom.num_dw);
44 cs->cdw += cb->atom.num_dw;
45 }
46
47 void r600_init_command_buffer(struct r600_context *rctx, struct r600_command_buffer *cb, unsigned id, unsigned num_dw)
48 {
49 r600_init_atom(rctx, &cb->atom, id, r600_emit_command_buffer, 0);
50 cb->buf = CALLOC(1, 4 * num_dw);
51 cb->max_num_dw = num_dw;
52 }
53
54 void r600_release_command_buffer(struct r600_command_buffer *cb)
55 {
56 FREE(cb->buf);
57 }
58
59 void r600_init_atom(struct r600_context *rctx,
60 struct r600_atom *atom,
61 unsigned id,
62 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
63 unsigned num_dw)
64 {
65 assert(id < R600_MAX_ATOM);
66 assert(rctx->atoms[id] == NULL);
67 rctx->atoms[id] = atom;
68 atom->id = id;
69 atom->emit = emit;
70 atom->num_dw = num_dw;
71 atom->dirty = false;
72 }
73
74 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom)
75 {
76 struct radeon_winsys_cs *cs = rctx->cs;
77 struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom;
78 unsigned alpha_ref = a->sx_alpha_ref;
79
80 if (rctx->chip_class >= EVERGREEN && a->cb0_export_16bpc) {
81 alpha_ref &= ~0x1FFF;
82 }
83
84 r600_write_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL,
85 a->sx_alpha_test_control |
86 S_028410_ALPHA_TEST_BYPASS(a->bypass));
87 r600_write_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref);
88 }
89
90 static void r600_texture_barrier(struct pipe_context *ctx)
91 {
92 struct r600_context *rctx = (struct r600_context *)ctx;
93
94 rctx->flags |= R600_CONTEXT_CB_FLUSH | R600_CONTEXT_TEX_FLUSH;
95
96 /* R6xx errata */
97 if (rctx->chip_class == R600) {
98 rctx->flags |= R600_CONTEXT_FLUSH_AND_INV;
99 }
100 }
101
102 static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
103 {
104 static const int prim_conv[] = {
105 V_008958_DI_PT_POINTLIST,
106 V_008958_DI_PT_LINELIST,
107 V_008958_DI_PT_LINELOOP,
108 V_008958_DI_PT_LINESTRIP,
109 V_008958_DI_PT_TRILIST,
110 V_008958_DI_PT_TRISTRIP,
111 V_008958_DI_PT_TRIFAN,
112 V_008958_DI_PT_QUADLIST,
113 V_008958_DI_PT_QUADSTRIP,
114 V_008958_DI_PT_POLYGON,
115 -1,
116 -1,
117 -1,
118 -1,
119 V_008958_DI_PT_RECTLIST
120 };
121
122 *prim = prim_conv[pprim];
123 if (*prim == -1) {
124 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim);
125 return false;
126 }
127 return true;
128 }
129
130 /* common state between evergreen and r600 */
131
132 static void r600_bind_blend_state_internal(struct r600_context *rctx,
133 struct r600_pipe_blend *blend)
134 {
135 struct r600_pipe_state *rstate;
136 bool update_cb = false;
137
138 rstate = &blend->rstate;
139 rctx->states[rstate->id] = rstate;
140 r600_context_pipe_state_set(rctx, rstate);
141
142 if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) {
143 rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
144 update_cb = true;
145 }
146 if (rctx->chip_class <= R700 &&
147 rctx->cb_misc_state.cb_color_control != blend->cb_color_control) {
148 rctx->cb_misc_state.cb_color_control = blend->cb_color_control;
149 update_cb = true;
150 }
151 if (rctx->cb_misc_state.dual_src_blend != blend->dual_src_blend) {
152 rctx->cb_misc_state.dual_src_blend = blend->dual_src_blend;
153 update_cb = true;
154 }
155 if (update_cb) {
156 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
157 }
158 }
159
160 static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
161 {
162 struct r600_context *rctx = (struct r600_context *)ctx;
163 struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
164
165 if (blend == NULL)
166 return;
167
168 rctx->blend = blend;
169 rctx->alpha_to_one = blend->alpha_to_one;
170 rctx->dual_src_blend = blend->dual_src_blend;
171
172 if (!rctx->blend_override)
173 r600_bind_blend_state_internal(rctx, blend);
174 }
175
176 static void r600_set_blend_color(struct pipe_context *ctx,
177 const struct pipe_blend_color *state)
178 {
179 struct r600_context *rctx = (struct r600_context *)ctx;
180 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
181
182 if (rstate == NULL)
183 return;
184
185 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
186 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]));
187 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
188 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
189 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
190
191 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
192 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
193 r600_context_pipe_state_set(rctx, rstate);
194 }
195
196 static void r600_set_stencil_ref(struct pipe_context *ctx,
197 const struct r600_stencil_ref *state)
198 {
199 struct r600_context *rctx = (struct r600_context *)ctx;
200 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
201
202 if (rstate == NULL)
203 return;
204
205 rstate->id = R600_PIPE_STATE_STENCIL_REF;
206 r600_pipe_state_add_reg(rstate,
207 R_028430_DB_STENCILREFMASK,
208 S_028430_STENCILREF(state->ref_value[0]) |
209 S_028430_STENCILMASK(state->valuemask[0]) |
210 S_028430_STENCILWRITEMASK(state->writemask[0]));
211 r600_pipe_state_add_reg(rstate,
212 R_028434_DB_STENCILREFMASK_BF,
213 S_028434_STENCILREF_BF(state->ref_value[1]) |
214 S_028434_STENCILMASK_BF(state->valuemask[1]) |
215 S_028434_STENCILWRITEMASK_BF(state->writemask[1]));
216
217 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
218 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
219 r600_context_pipe_state_set(rctx, rstate);
220 }
221
222 static void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
223 const struct pipe_stencil_ref *state)
224 {
225 struct r600_context *rctx = (struct r600_context *)ctx;
226 struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA];
227 struct r600_stencil_ref ref;
228
229 rctx->stencil_ref = *state;
230
231 if (!dsa)
232 return;
233
234 ref.ref_value[0] = state->ref_value[0];
235 ref.ref_value[1] = state->ref_value[1];
236 ref.valuemask[0] = dsa->valuemask[0];
237 ref.valuemask[1] = dsa->valuemask[1];
238 ref.writemask[0] = dsa->writemask[0];
239 ref.writemask[1] = dsa->writemask[1];
240
241 r600_set_stencil_ref(ctx, &ref);
242 }
243
244 static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
245 {
246 struct r600_context *rctx = (struct r600_context *)ctx;
247 struct r600_pipe_dsa *dsa = state;
248 struct r600_pipe_state *rstate;
249 struct r600_stencil_ref ref;
250
251 if (state == NULL)
252 return;
253 rstate = &dsa->rstate;
254 rctx->states[rstate->id] = rstate;
255 r600_context_pipe_state_set(rctx, rstate);
256
257 ref.ref_value[0] = rctx->stencil_ref.ref_value[0];
258 ref.ref_value[1] = rctx->stencil_ref.ref_value[1];
259 ref.valuemask[0] = dsa->valuemask[0];
260 ref.valuemask[1] = dsa->valuemask[1];
261 ref.writemask[0] = dsa->writemask[0];
262 ref.writemask[1] = dsa->writemask[1];
263
264 r600_set_stencil_ref(ctx, &ref);
265
266 /* Update alphatest state. */
267 if (rctx->alphatest_state.sx_alpha_test_control != dsa->sx_alpha_test_control ||
268 rctx->alphatest_state.sx_alpha_ref != dsa->alpha_ref) {
269 rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control;
270 rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref;
271 r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
272 }
273 }
274
275 void r600_set_max_scissor(struct r600_context *rctx)
276 {
277 /* Set a scissor state such that it doesn't do anything. */
278 struct pipe_scissor_state scissor;
279 scissor.minx = 0;
280 scissor.miny = 0;
281 scissor.maxx = 8192;
282 scissor.maxy = 8192;
283
284 r600_set_scissor_state(rctx, &scissor);
285 }
286
287 static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
288 {
289 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
290 struct r600_context *rctx = (struct r600_context *)ctx;
291
292 if (state == NULL)
293 return;
294
295 rctx->sprite_coord_enable = rs->sprite_coord_enable;
296 rctx->two_side = rs->two_side;
297 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
298 rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
299 rctx->multisample_enable = rs->multisample_enable;
300
301 rctx->rasterizer = rs;
302
303 rctx->states[rs->rstate.id] = &rs->rstate;
304 r600_context_pipe_state_set(rctx, &rs->rstate);
305
306 if (rctx->chip_class >= EVERGREEN) {
307 evergreen_polygon_offset_update(rctx);
308 } else {
309 r600_polygon_offset_update(rctx);
310 }
311
312 /* Workaround for a missing scissor enable on r600. */
313 if (rctx->chip_class == R600) {
314 if (rs->scissor_enable != rctx->scissor_enable) {
315 rctx->scissor_enable = rs->scissor_enable;
316
317 if (rs->scissor_enable) {
318 r600_set_scissor_state(rctx, &rctx->scissor_state);
319 } else {
320 r600_set_max_scissor(rctx);
321 }
322 }
323 }
324 }
325
326 static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
327 {
328 struct r600_context *rctx = (struct r600_context *)ctx;
329 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
330
331 if (rctx->rasterizer == rs) {
332 rctx->rasterizer = NULL;
333 }
334 if (rctx->states[rs->rstate.id] == &rs->rstate) {
335 rctx->states[rs->rstate.id] = NULL;
336 }
337 free(rs);
338 }
339
340 static void r600_sampler_view_destroy(struct pipe_context *ctx,
341 struct pipe_sampler_view *state)
342 {
343 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
344
345 pipe_resource_reference(&state->texture, NULL);
346 FREE(resource);
347 }
348
349 void r600_sampler_states_dirty(struct r600_context *rctx,
350 struct r600_sampler_states *state)
351 {
352 if (state->dirty_mask) {
353 if (state->dirty_mask & state->has_bordercolor_mask) {
354 rctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
355 }
356 state->atom.num_dw =
357 util_bitcount(state->dirty_mask & state->has_bordercolor_mask) * 11 +
358 util_bitcount(state->dirty_mask & ~state->has_bordercolor_mask) * 5;
359 r600_atom_dirty(rctx, &state->atom);
360 }
361 }
362
363 static void r600_bind_sampler_states(struct pipe_context *pipe,
364 unsigned shader,
365 unsigned start,
366 unsigned count, void **states)
367 {
368 struct r600_context *rctx = (struct r600_context *)pipe;
369 struct r600_textures_info *dst = &rctx->samplers[shader];
370 struct r600_pipe_sampler_state **rstates = (struct r600_pipe_sampler_state**)states;
371 int seamless_cube_map = -1;
372 unsigned i;
373 /* This sets 1-bit for states with index >= count. */
374 uint32_t disable_mask = ~((1ull << count) - 1);
375 /* These are the new states set by this function. */
376 uint32_t new_mask = 0;
377
378 assert(start == 0); /* XXX fix below */
379
380 for (i = 0; i < count; i++) {
381 struct r600_pipe_sampler_state *rstate = rstates[i];
382
383 if (rstate == dst->states.states[i]) {
384 continue;
385 }
386
387 if (rstate) {
388 if (rstate->border_color_use) {
389 dst->states.has_bordercolor_mask |= 1 << i;
390 } else {
391 dst->states.has_bordercolor_mask &= ~(1 << i);
392 }
393 seamless_cube_map = rstate->seamless_cube_map;
394
395 new_mask |= 1 << i;
396 } else {
397 disable_mask |= 1 << i;
398 }
399 }
400
401 memcpy(dst->states.states, rstates, sizeof(void*) * count);
402 memset(dst->states.states + count, 0, sizeof(void*) * (NUM_TEX_UNITS - count));
403
404 dst->states.enabled_mask &= ~disable_mask;
405 dst->states.dirty_mask &= dst->states.enabled_mask;
406 dst->states.enabled_mask |= new_mask;
407 dst->states.dirty_mask |= new_mask;
408 dst->states.has_bordercolor_mask &= dst->states.enabled_mask;
409
410 r600_sampler_states_dirty(rctx, &dst->states);
411
412 /* Seamless cubemap state. */
413 if (rctx->chip_class <= R700 &&
414 seamless_cube_map != -1 &&
415 seamless_cube_map != rctx->seamless_cube_map.enabled) {
416 /* change in TA_CNTL_AUX need a pipeline flush */
417 rctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
418 rctx->seamless_cube_map.enabled = seamless_cube_map;
419 r600_atom_dirty(rctx, &rctx->seamless_cube_map.atom);
420 }
421 }
422
423 static void r600_bind_vs_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
424 {
425 r600_bind_sampler_states(ctx, PIPE_SHADER_VERTEX, 0, count, states);
426 }
427
428 static void r600_bind_ps_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
429 {
430 r600_bind_sampler_states(ctx, PIPE_SHADER_FRAGMENT, 0, count, states);
431 }
432
433 static void r600_delete_sampler_state(struct pipe_context *ctx, void *state)
434 {
435 free(state);
436 }
437
438 static void r600_delete_state(struct pipe_context *ctx, void *state)
439 {
440 struct r600_context *rctx = (struct r600_context *)ctx;
441 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
442
443 if (rctx->states[rstate->id] == rstate) {
444 rctx->states[rstate->id] = NULL;
445 }
446 for (int i = 0; i < rstate->nregs; i++) {
447 pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL);
448 }
449 free(rstate);
450 }
451
452 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
453 {
454 struct r600_context *rctx = (struct r600_context *)ctx;
455 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
456
457 rctx->vertex_elements = v;
458 if (v) {
459 rctx->states[v->rstate.id] = &v->rstate;
460 r600_context_pipe_state_set(rctx, &v->rstate);
461 }
462 }
463
464 static void r600_delete_vertex_elements(struct pipe_context *ctx, void *state)
465 {
466 struct r600_context *rctx = (struct r600_context *)ctx;
467 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
468
469 if (rctx->states[v->rstate.id] == &v->rstate) {
470 rctx->states[v->rstate.id] = NULL;
471 }
472 if (rctx->vertex_elements == state)
473 rctx->vertex_elements = NULL;
474
475 pipe_resource_reference((struct pipe_resource**)&v->fetch_shader, NULL);
476 FREE(state);
477 }
478
479 static void r600_set_index_buffer(struct pipe_context *ctx,
480 const struct pipe_index_buffer *ib)
481 {
482 struct r600_context *rctx = (struct r600_context *)ctx;
483
484 if (ib) {
485 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
486 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
487 } else {
488 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
489 }
490 }
491
492 void r600_vertex_buffers_dirty(struct r600_context *rctx)
493 {
494 if (rctx->vertex_buffer_state.dirty_mask) {
495 rctx->flags |= rctx->has_vertex_cache ? R600_CONTEXT_VTX_FLUSH : R600_CONTEXT_TEX_FLUSH;
496 rctx->vertex_buffer_state.atom.num_dw = (rctx->chip_class >= EVERGREEN ? 12 : 11) *
497 util_bitcount(rctx->vertex_buffer_state.dirty_mask);
498 r600_atom_dirty(rctx, &rctx->vertex_buffer_state.atom);
499 }
500 }
501
502 static void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
503 const struct pipe_vertex_buffer *input)
504 {
505 struct r600_context *rctx = (struct r600_context *)ctx;
506 struct r600_vertexbuf_state *state = &rctx->vertex_buffer_state;
507 struct pipe_vertex_buffer *vb = state->vb;
508 unsigned i;
509 /* This sets 1-bit for buffers with index >= count. */
510 uint32_t disable_mask = ~((1ull << count) - 1);
511 /* These are the new buffers set by this function. */
512 uint32_t new_buffer_mask = 0;
513
514 /* Set buffers with index >= count to NULL. */
515 uint32_t remaining_buffers_mask =
516 rctx->vertex_buffer_state.enabled_mask & disable_mask;
517
518 while (remaining_buffers_mask) {
519 i = u_bit_scan(&remaining_buffers_mask);
520 pipe_resource_reference(&vb[i].buffer, NULL);
521 }
522
523 /* Set vertex buffers. */
524 for (i = 0; i < count; i++) {
525 if (memcmp(&input[i], &vb[i], sizeof(struct pipe_vertex_buffer))) {
526 if (input[i].buffer) {
527 vb[i].stride = input[i].stride;
528 vb[i].buffer_offset = input[i].buffer_offset;
529 pipe_resource_reference(&vb[i].buffer, input[i].buffer);
530 new_buffer_mask |= 1 << i;
531 } else {
532 pipe_resource_reference(&vb[i].buffer, NULL);
533 disable_mask |= 1 << i;
534 }
535 }
536 }
537
538 rctx->vertex_buffer_state.enabled_mask &= ~disable_mask;
539 rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask;
540 rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask;
541 rctx->vertex_buffer_state.dirty_mask |= new_buffer_mask;
542
543 r600_vertex_buffers_dirty(rctx);
544 }
545
546 void r600_sampler_views_dirty(struct r600_context *rctx,
547 struct r600_samplerview_state *state)
548 {
549 if (state->dirty_mask) {
550 rctx->flags |= R600_CONTEXT_TEX_FLUSH;
551 state->atom.num_dw = (rctx->chip_class >= EVERGREEN ? 14 : 13) *
552 util_bitcount(state->dirty_mask);
553 r600_atom_dirty(rctx, &state->atom);
554 }
555 }
556
557 static void r600_set_sampler_views(struct pipe_context *pipe, unsigned shader,
558 unsigned start, unsigned count,
559 struct pipe_sampler_view **views)
560 {
561 struct r600_context *rctx = (struct r600_context *) pipe;
562 struct r600_textures_info *dst = &rctx->samplers[shader];
563 struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
564 uint32_t dirty_sampler_states_mask = 0;
565 unsigned i;
566 /* This sets 1-bit for textures with index >= count. */
567 uint32_t disable_mask = ~((1ull << count) - 1);
568 /* These are the new textures set by this function. */
569 uint32_t new_mask = 0;
570
571 /* Set textures with index >= count to NULL. */
572 uint32_t remaining_mask;
573
574 assert(start == 0); /* XXX fix below */
575
576 remaining_mask = dst->views.enabled_mask & disable_mask;
577
578 while (remaining_mask) {
579 i = u_bit_scan(&remaining_mask);
580 assert(dst->views.views[i]);
581
582 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
583 }
584
585 for (i = 0; i < count; i++) {
586 if (rviews[i] == dst->views.views[i]) {
587 continue;
588 }
589
590 if (rviews[i]) {
591 struct r600_texture *rtex =
592 (struct r600_texture*)rviews[i]->base.texture;
593
594 if (rtex->is_depth && !rtex->is_flushing_texture) {
595 dst->views.compressed_depthtex_mask |= 1 << i;
596 } else {
597 dst->views.compressed_depthtex_mask &= ~(1 << i);
598 }
599
600 /* Track compressed colorbuffers for Evergreen (Cayman doesn't need this). */
601 if (rctx->chip_class != CAYMAN && rtex->cmask_size && rtex->fmask_size) {
602 dst->views.compressed_colortex_mask |= 1 << i;
603 } else {
604 dst->views.compressed_colortex_mask &= ~(1 << i);
605 }
606
607 /* Changing from array to non-arrays textures and vice versa requires
608 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
609 if (rctx->chip_class <= R700 &&
610 (dst->states.enabled_mask & (1 << i)) &&
611 (rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
612 rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) {
613 dirty_sampler_states_mask |= 1 << i;
614 }
615
616 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]);
617 new_mask |= 1 << i;
618 } else {
619 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
620 disable_mask |= 1 << i;
621 }
622 }
623
624 dst->views.enabled_mask &= ~disable_mask;
625 dst->views.dirty_mask &= dst->views.enabled_mask;
626 dst->views.enabled_mask |= new_mask;
627 dst->views.dirty_mask |= new_mask;
628 dst->views.compressed_depthtex_mask &= dst->views.enabled_mask;
629 dst->views.compressed_colortex_mask &= dst->views.enabled_mask;
630
631 r600_sampler_views_dirty(rctx, &dst->views);
632
633 if (dirty_sampler_states_mask) {
634 dst->states.dirty_mask |= dirty_sampler_states_mask;
635 r600_sampler_states_dirty(rctx, &dst->states);
636 }
637 }
638
639 static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
640 struct pipe_sampler_view **views)
641 {
642 r600_set_sampler_views(ctx, PIPE_SHADER_VERTEX, 0, count, views);
643 }
644
645 static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
646 struct pipe_sampler_view **views)
647 {
648 r600_set_sampler_views(ctx, PIPE_SHADER_FRAGMENT, 0, count, views);
649 }
650
651 static void r600_set_viewport_state(struct pipe_context *ctx,
652 const struct pipe_viewport_state *state)
653 {
654 struct r600_context *rctx = (struct r600_context *)ctx;
655 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
656
657 if (rstate == NULL)
658 return;
659
660 rctx->viewport = *state;
661 rstate->id = R600_PIPE_STATE_VIEWPORT;
662 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
663 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
664 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
665 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
666 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
667 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
668
669 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
670 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
671 r600_context_pipe_state_set(rctx, rstate);
672 }
673
674 static void *r600_create_vertex_elements(struct pipe_context *ctx, unsigned count,
675 const struct pipe_vertex_element *elements)
676 {
677 struct r600_context *rctx = (struct r600_context *)ctx;
678 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
679
680 assert(count < 32);
681 if (!v)
682 return NULL;
683
684 v->count = count;
685 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
686
687 if (r600_vertex_elements_build_fetch_shader(rctx, v)) {
688 FREE(v);
689 return NULL;
690 }
691
692 return v;
693 }
694
695 /* Compute the key for the hw shader variant */
696 static INLINE unsigned r600_shader_selector_key(struct pipe_context * ctx,
697 struct r600_pipe_shader_selector * sel)
698 {
699 struct r600_context *rctx = (struct r600_context *)ctx;
700 unsigned key;
701
702 if (sel->type == PIPE_SHADER_FRAGMENT) {
703 key = rctx->two_side |
704 ((rctx->alpha_to_one && rctx->multisample_enable && !rctx->cb0_is_integer) << 1) |
705 (MIN2(sel->nr_ps_max_color_exports, rctx->nr_cbufs + rctx->dual_src_blend) << 2);
706 } else
707 key = 0;
708
709 return key;
710 }
711
712 /* Select the hw shader variant depending on the current state.
713 * (*dirty) is set to 1 if current variant was changed */
714 static int r600_shader_select(struct pipe_context *ctx,
715 struct r600_pipe_shader_selector* sel,
716 unsigned *dirty)
717 {
718 unsigned key;
719 struct r600_context *rctx = (struct r600_context *)ctx;
720 struct r600_pipe_shader * shader = NULL;
721 int r;
722
723 key = r600_shader_selector_key(ctx, sel);
724
725 /* Check if we don't need to change anything.
726 * This path is also used for most shaders that don't need multiple
727 * variants, it will cost just a computation of the key and this
728 * test. */
729 if (likely(sel->current && sel->current->key == key)) {
730 return 0;
731 }
732
733 /* lookup if we have other variants in the list */
734 if (sel->num_shaders > 1) {
735 struct r600_pipe_shader *p = sel->current, *c = p->next_variant;
736
737 while (c && c->key != key) {
738 p = c;
739 c = c->next_variant;
740 }
741
742 if (c) {
743 p->next_variant = c->next_variant;
744 shader = c;
745 }
746 }
747
748 if (unlikely(!shader)) {
749 shader = CALLOC(1, sizeof(struct r600_pipe_shader));
750 shader->selector = sel;
751
752 r = r600_pipe_shader_create(ctx, shader);
753 if (unlikely(r)) {
754 R600_ERR("Failed to build shader variant (type=%u, key=%u) %d\n",
755 sel->type, key, r);
756 sel->current = NULL;
757 return r;
758 }
759
760 /* We don't know the value of nr_ps_max_color_exports until we built
761 * at least one variant, so we may need to recompute the key after
762 * building first variant. */
763 if (sel->type == PIPE_SHADER_FRAGMENT &&
764 sel->num_shaders == 0) {
765 sel->nr_ps_max_color_exports = shader->shader.nr_ps_max_color_exports;
766 key = r600_shader_selector_key(ctx, sel);
767 }
768
769 shader->key = key;
770 sel->num_shaders++;
771 }
772
773 if (dirty)
774 *dirty = 1;
775
776 shader->next_variant = sel->current;
777 sel->current = shader;
778
779 if (rctx->chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
780 r600_adjust_gprs(rctx);
781 }
782
783 if (rctx->ps_shader &&
784 rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
785 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
786 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
787 }
788 return 0;
789 }
790
791 static void *r600_create_shader_state(struct pipe_context *ctx,
792 const struct pipe_shader_state *state,
793 unsigned pipe_shader_type)
794 {
795 struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector);
796 int r;
797
798 sel->type = pipe_shader_type;
799 sel->tokens = tgsi_dup_tokens(state->tokens);
800 sel->so = state->stream_output;
801
802 r = r600_shader_select(ctx, sel, NULL);
803 if (r)
804 return NULL;
805
806 return sel;
807 }
808
809 static void *r600_create_ps_state(struct pipe_context *ctx,
810 const struct pipe_shader_state *state)
811 {
812 return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
813 }
814
815 static void *r600_create_vs_state(struct pipe_context *ctx,
816 const struct pipe_shader_state *state)
817 {
818 return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
819 }
820
821 static void r600_bind_ps_state(struct pipe_context *ctx, void *state)
822 {
823 struct r600_context *rctx = (struct r600_context *)ctx;
824
825 if (!state)
826 state = rctx->dummy_pixel_shader;
827
828 rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
829 r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
830
831 if (rctx->chip_class <= R700) {
832 bool multiwrite = rctx->ps_shader->current->shader.fs_write_all;
833
834 if (rctx->cb_misc_state.multiwrite != multiwrite) {
835 rctx->cb_misc_state.multiwrite = multiwrite;
836 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
837 }
838
839 if (rctx->vs_shader)
840 r600_adjust_gprs(rctx);
841 }
842
843 if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
844 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
845 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
846 }
847 }
848
849 static void r600_bind_vs_state(struct pipe_context *ctx, void *state)
850 {
851 struct r600_context *rctx = (struct r600_context *)ctx;
852
853 rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
854 if (state) {
855 r600_context_pipe_state_set(rctx, &rctx->vs_shader->current->rstate);
856
857 if (rctx->chip_class < EVERGREEN && rctx->ps_shader)
858 r600_adjust_gprs(rctx);
859 }
860 }
861
862 static void r600_delete_shader_selector(struct pipe_context *ctx,
863 struct r600_pipe_shader_selector *sel)
864 {
865 struct r600_pipe_shader *p = sel->current, *c;
866 while (p) {
867 c = p->next_variant;
868 r600_pipe_shader_destroy(ctx, p);
869 free(p);
870 p = c;
871 }
872
873 free(sel->tokens);
874 free(sel);
875 }
876
877
878 static void r600_delete_ps_state(struct pipe_context *ctx, void *state)
879 {
880 struct r600_context *rctx = (struct r600_context *)ctx;
881 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
882
883 if (rctx->ps_shader == sel) {
884 rctx->ps_shader = NULL;
885 }
886
887 r600_delete_shader_selector(ctx, sel);
888 }
889
890 static void r600_delete_vs_state(struct pipe_context *ctx, void *state)
891 {
892 struct r600_context *rctx = (struct r600_context *)ctx;
893 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
894
895 if (rctx->vs_shader == sel) {
896 rctx->vs_shader = NULL;
897 }
898
899 r600_delete_shader_selector(ctx, sel);
900 }
901
902 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
903 {
904 if (state->dirty_mask) {
905 rctx->flags |= R600_CONTEXT_SHADERCONST_FLUSH;
906 state->atom.num_dw = rctx->chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
907 : util_bitcount(state->dirty_mask)*19;
908 r600_atom_dirty(rctx, &state->atom);
909 }
910 }
911
912 static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
913 struct pipe_constant_buffer *input)
914 {
915 struct r600_context *rctx = (struct r600_context *)ctx;
916 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
917 struct pipe_constant_buffer *cb;
918 const uint8_t *ptr;
919
920 /* Note that the state tracker can unbind constant buffers by
921 * passing NULL here.
922 */
923 if (unlikely(!input)) {
924 state->enabled_mask &= ~(1 << index);
925 state->dirty_mask &= ~(1 << index);
926 pipe_resource_reference(&state->cb[index].buffer, NULL);
927 return;
928 }
929
930 cb = &state->cb[index];
931 cb->buffer_size = input->buffer_size;
932
933 ptr = input->user_buffer;
934
935 if (ptr) {
936 /* Upload the user buffer. */
937 if (R600_BIG_ENDIAN) {
938 uint32_t *tmpPtr;
939 unsigned i, size = input->buffer_size;
940
941 if (!(tmpPtr = malloc(size))) {
942 R600_ERR("Failed to allocate BE swap buffer.\n");
943 return;
944 }
945
946 for (i = 0; i < size / 4; ++i) {
947 tmpPtr[i] = bswap_32(((uint32_t *)ptr)[i]);
948 }
949
950 u_upload_data(rctx->uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer);
951 free(tmpPtr);
952 } else {
953 u_upload_data(rctx->uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer);
954 }
955 } else {
956 /* Setup the hw buffer. */
957 cb->buffer_offset = input->buffer_offset;
958 pipe_resource_reference(&cb->buffer, input->buffer);
959 }
960
961 state->enabled_mask |= 1 << index;
962 state->dirty_mask |= 1 << index;
963 r600_constant_buffers_dirty(rctx, state);
964 }
965
966 static struct pipe_stream_output_target *
967 r600_create_so_target(struct pipe_context *ctx,
968 struct pipe_resource *buffer,
969 unsigned buffer_offset,
970 unsigned buffer_size)
971 {
972 struct r600_context *rctx = (struct r600_context *)ctx;
973 struct r600_so_target *t;
974 void *ptr;
975
976 t = CALLOC_STRUCT(r600_so_target);
977 if (!t) {
978 return NULL;
979 }
980
981 t->b.reference.count = 1;
982 t->b.context = ctx;
983 pipe_resource_reference(&t->b.buffer, buffer);
984 t->b.buffer_offset = buffer_offset;
985 t->b.buffer_size = buffer_size;
986
987 t->filled_size = (struct r600_resource*)
988 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4);
989 ptr = rctx->ws->buffer_map(t->filled_size->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
990 memset(ptr, 0, t->filled_size->buf->size);
991 rctx->ws->buffer_unmap(t->filled_size->cs_buf);
992
993 return &t->b;
994 }
995
996 static void r600_so_target_destroy(struct pipe_context *ctx,
997 struct pipe_stream_output_target *target)
998 {
999 struct r600_so_target *t = (struct r600_so_target*)target;
1000 pipe_resource_reference(&t->b.buffer, NULL);
1001 pipe_resource_reference((struct pipe_resource**)&t->filled_size, NULL);
1002 FREE(t);
1003 }
1004
1005 static void r600_set_so_targets(struct pipe_context *ctx,
1006 unsigned num_targets,
1007 struct pipe_stream_output_target **targets,
1008 unsigned append_bitmask)
1009 {
1010 struct r600_context *rctx = (struct r600_context *)ctx;
1011 unsigned i;
1012
1013 /* Stop streamout. */
1014 if (rctx->num_so_targets && !rctx->streamout_start) {
1015 r600_context_streamout_end(rctx);
1016 }
1017
1018 /* Set the new targets. */
1019 for (i = 0; i < num_targets; i++) {
1020 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]);
1021 }
1022 for (; i < rctx->num_so_targets; i++) {
1023 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL);
1024 }
1025
1026 rctx->num_so_targets = num_targets;
1027 rctx->streamout_start = num_targets != 0;
1028 rctx->streamout_append_bitmask = append_bitmask;
1029 }
1030
1031 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1032 {
1033 struct r600_context *rctx = (struct r600_context*)pipe;
1034
1035 if (rctx->sample_mask.sample_mask == (uint16_t)sample_mask)
1036 return;
1037
1038 rctx->sample_mask.sample_mask = sample_mask;
1039 r600_atom_dirty(rctx, &rctx->sample_mask.atom);
1040 }
1041
1042 static void r600_update_derived_state(struct r600_context *rctx)
1043 {
1044 struct pipe_context * ctx = (struct pipe_context*)rctx;
1045 unsigned ps_dirty = 0, blend_override;
1046
1047 if (!rctx->blitter->running) {
1048 unsigned i;
1049
1050 /* Decompress textures if needed. */
1051 for (i = 0; i < PIPE_SHADER_TYPES; i++) {
1052 struct r600_samplerview_state *views = &rctx->samplers[i].views;
1053 if (views->compressed_depthtex_mask) {
1054 r600_decompress_depth_textures(rctx, views);
1055 }
1056 if (views->compressed_colortex_mask) {
1057 r600_decompress_color_textures(rctx, views);
1058 }
1059 }
1060 }
1061
1062 r600_shader_select(ctx, rctx->ps_shader, &ps_dirty);
1063
1064 if (rctx->ps_shader && ((rctx->sprite_coord_enable &&
1065 (rctx->ps_shader->current->sprite_coord_enable != rctx->sprite_coord_enable)) ||
1066 (rctx->rasterizer && rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade))) {
1067
1068 if (rctx->chip_class >= EVERGREEN)
1069 evergreen_pipe_shader_ps(ctx, rctx->ps_shader->current);
1070 else
1071 r600_pipe_shader_ps(ctx, rctx->ps_shader->current);
1072
1073 ps_dirty = 1;
1074 }
1075
1076 if (ps_dirty)
1077 r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
1078
1079 blend_override = (rctx->dual_src_blend &&
1080 rctx->ps_shader->current->nr_ps_color_outputs < 2);
1081
1082 if (blend_override != rctx->blend_override) {
1083 rctx->blend_override = blend_override;
1084 r600_bind_blend_state_internal(rctx,
1085 blend_override ? rctx->no_blend : rctx->blend);
1086 }
1087
1088 if (rctx->chip_class >= EVERGREEN) {
1089 evergreen_update_dual_export_state(rctx);
1090 } else {
1091 r600_update_dual_export_state(rctx);
1092 }
1093 }
1094
1095 static unsigned r600_conv_prim_to_gs_out(unsigned mode)
1096 {
1097 static const int prim_conv[] = {
1098 V_028A6C_OUTPRIM_TYPE_POINTLIST,
1099 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1100 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1101 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1102 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1103 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1104 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1105 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1106 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1107 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1108 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1109 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1110 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1111 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1112 V_028A6C_OUTPRIM_TYPE_TRISTRIP
1113 };
1114 assert(mode < Elements(prim_conv));
1115
1116 return prim_conv[mode];
1117 }
1118
1119 static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
1120 {
1121 struct r600_context *rctx = (struct r600_context *)ctx;
1122 struct pipe_draw_info info = *dinfo;
1123 struct pipe_index_buffer ib = {};
1124 unsigned prim, ls_mask = 0, i;
1125 struct r600_block *dirty_block = NULL, *next_block = NULL;
1126 struct radeon_winsys_cs *cs = rctx->cs;
1127 uint64_t va;
1128 uint8_t *ptr;
1129
1130 if ((!info.count && (info.indexed || !info.count_from_stream_output)) ||
1131 !r600_conv_pipe_prim(info.mode, &prim)) {
1132 assert(0);
1133 return;
1134 }
1135
1136 if (!rctx->vs_shader) {
1137 assert(0);
1138 return;
1139 }
1140
1141 r600_update_derived_state(rctx);
1142
1143 if (info.indexed) {
1144 /* Initialize the index buffer struct. */
1145 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
1146 ib.user_buffer = rctx->index_buffer.user_buffer;
1147 ib.index_size = rctx->index_buffer.index_size;
1148 ib.offset = rctx->index_buffer.offset + info.start * ib.index_size;
1149
1150 /* Translate or upload, if needed. */
1151 r600_translate_index_buffer(rctx, &ib, info.count);
1152
1153 ptr = (uint8_t*)ib.user_buffer;
1154 if (!ib.buffer && ptr) {
1155 u_upload_data(rctx->uploader, 0, info.count * ib.index_size,
1156 ptr, &ib.offset, &ib.buffer);
1157 }
1158 } else {
1159 info.index_bias = info.start;
1160 }
1161
1162 if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
1163 rctx->vgt.id = R600_PIPE_STATE_VGT;
1164 rctx->vgt.nregs = 0;
1165 r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim);
1166 r600_pipe_state_add_reg(&rctx->vgt, R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0);
1167 r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias);
1168 r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index);
1169 r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart);
1170 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
1171 r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0);
1172 r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0);
1173 r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0);
1174 }
1175
1176 rctx->vgt.nregs = 0;
1177 r600_pipe_state_mod_reg(&rctx->vgt, prim);
1178 r600_pipe_state_mod_reg(&rctx->vgt, r600_conv_prim_to_gs_out(info.mode));
1179 r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
1180 r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
1181 r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart);
1182 r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance);
1183
1184 if (prim == V_008958_DI_PT_LINELIST)
1185 ls_mask = 1;
1186 else if (prim == V_008958_DI_PT_LINESTRIP ||
1187 prim == V_008958_DI_PT_LINELOOP)
1188 ls_mask = 2;
1189 r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask) | rctx->pa_sc_line_stipple);
1190 r600_pipe_state_mod_reg(&rctx->vgt,
1191 rctx->vs_shader->current->pa_cl_vs_out_cntl |
1192 (rctx->rasterizer->clip_plane_enable & rctx->vs_shader->current->shader.clip_dist_write));
1193 r600_pipe_state_mod_reg(&rctx->vgt,
1194 rctx->pa_cl_clip_cntl |
1195 (rctx->vs_shader->current->shader.clip_dist_write ||
1196 rctx->vs_shader->current->shader.vs_prohibit_ucps ?
1197 0 : rctx->rasterizer->clip_plane_enable & 0x3F));
1198
1199 r600_context_pipe_state_set(rctx, &rctx->vgt);
1200
1201 /* Enable stream out if needed. */
1202 if (rctx->streamout_start) {
1203 r600_context_streamout_begin(rctx);
1204 rctx->streamout_start = FALSE;
1205 }
1206
1207 /* Emit states (the function expects that we emit at most 17 dwords here). */
1208 r600_need_cs_space(rctx, 0, TRUE);
1209 r600_flush_emit(rctx);
1210
1211 for (i = 0; i < R600_MAX_ATOM; i++) {
1212 if (rctx->atoms[i] == NULL || !rctx->atoms[i]->dirty) {
1213 continue;
1214 }
1215 r600_emit_atom(rctx, rctx->atoms[i]);
1216 }
1217 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) {
1218 r600_context_block_emit_dirty(rctx, dirty_block, 0 /* pkt_flags */);
1219 }
1220 rctx->pm4_dirty_cdwords = 0;
1221
1222 /* draw packet */
1223 cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->predicate_drawing);
1224 cs->buf[cs->cdw++] = info.instance_count;
1225 if (info.indexed) {
1226 cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->predicate_drawing);
1227 cs->buf[cs->cdw++] = ib.index_size == 4 ?
1228 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
1229 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
1230
1231 va = r600_resource_va(ctx->screen, ib.buffer);
1232 va += ib.offset;
1233 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->predicate_drawing);
1234 cs->buf[cs->cdw++] = va;
1235 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
1236 cs->buf[cs->cdw++] = info.count;
1237 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
1238 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->predicate_drawing);
1239 cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
1240 } else {
1241 if (info.count_from_stream_output) {
1242 struct r600_so_target *t = (struct r600_so_target*)info.count_from_stream_output;
1243 uint64_t va = r600_resource_va(&rctx->screen->screen, (void*)t->filled_size);
1244
1245 r600_write_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
1246
1247 cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0);
1248 cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG;
1249 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */
1250 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
1251 cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */
1252 cs->buf[cs->cdw++] = 0; /* unused */
1253
1254 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1255 cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, t->filled_size, RADEON_USAGE_READ);
1256 }
1257
1258 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->predicate_drawing);
1259 cs->buf[cs->cdw++] = info.count;
1260 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
1261 (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
1262 }
1263
1264 /* Set the depth buffer as dirty. */
1265 if (rctx->framebuffer.zsbuf) {
1266 struct pipe_surface *surf = rctx->framebuffer.zsbuf;
1267 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
1268
1269 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1270 }
1271 if (rctx->compressed_cb_mask) {
1272 struct pipe_surface *surf;
1273 struct r600_texture *rtex;
1274 unsigned mask = rctx->compressed_cb_mask;
1275
1276 do {
1277 unsigned i = u_bit_scan(&mask);
1278 surf = rctx->framebuffer.cbufs[i];
1279 rtex = (struct r600_texture*)surf->texture;
1280
1281 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1282
1283 } while (mask);
1284 }
1285
1286 pipe_resource_reference(&ib.buffer, NULL);
1287 }
1288
1289 void r600_draw_rectangle(struct blitter_context *blitter,
1290 unsigned x1, unsigned y1, unsigned x2, unsigned y2, float depth,
1291 enum blitter_attrib_type type, const union pipe_color_union *attrib)
1292 {
1293 struct r600_context *rctx = (struct r600_context*)util_blitter_get_pipe(blitter);
1294 struct pipe_viewport_state viewport;
1295 struct pipe_resource *buf = NULL;
1296 unsigned offset = 0;
1297 float *vb;
1298
1299 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
1300 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
1301 return;
1302 }
1303
1304 /* Some operations (like color resolve on r6xx) don't work
1305 * with the conventional primitive types.
1306 * One that works is PT_RECTLIST, which we use here. */
1307
1308 /* setup viewport */
1309 viewport.scale[0] = 1.0f;
1310 viewport.scale[1] = 1.0f;
1311 viewport.scale[2] = 1.0f;
1312 viewport.scale[3] = 1.0f;
1313 viewport.translate[0] = 0.0f;
1314 viewport.translate[1] = 0.0f;
1315 viewport.translate[2] = 0.0f;
1316 viewport.translate[3] = 0.0f;
1317 rctx->context.set_viewport_state(&rctx->context, &viewport);
1318
1319 /* Upload vertices. The hw rectangle has only 3 vertices,
1320 * I guess the 4th one is derived from the first 3.
1321 * The vertex specification should match u_blitter's vertex element state. */
1322 u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, &offset, &buf, (void**)&vb);
1323 vb[0] = x1;
1324 vb[1] = y1;
1325 vb[2] = depth;
1326 vb[3] = 1;
1327
1328 vb[8] = x1;
1329 vb[9] = y2;
1330 vb[10] = depth;
1331 vb[11] = 1;
1332
1333 vb[16] = x2;
1334 vb[17] = y1;
1335 vb[18] = depth;
1336 vb[19] = 1;
1337
1338 if (attrib) {
1339 memcpy(vb+4, attrib->f, sizeof(float)*4);
1340 memcpy(vb+12, attrib->f, sizeof(float)*4);
1341 memcpy(vb+20, attrib->f, sizeof(float)*4);
1342 }
1343
1344 /* draw */
1345 util_draw_vertex_buffer(&rctx->context, NULL, buf, offset,
1346 R600_PRIM_RECTANGLE_LIST, 3, 2);
1347 pipe_resource_reference(&buf, NULL);
1348 }
1349
1350 void _r600_pipe_state_add_reg_bo(struct r600_context *ctx,
1351 struct r600_pipe_state *state,
1352 uint32_t offset, uint32_t value,
1353 uint32_t range_id, uint32_t block_id,
1354 struct r600_resource *bo,
1355 enum radeon_bo_usage usage)
1356
1357 {
1358 struct r600_range *range;
1359 struct r600_block *block;
1360
1361 if (bo) assert(usage);
1362
1363 range = &ctx->range[range_id];
1364 block = range->blocks[block_id];
1365 state->regs[state->nregs].block = block;
1366 state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
1367
1368 state->regs[state->nregs].value = value;
1369 state->regs[state->nregs].bo = bo;
1370 state->regs[state->nregs].bo_usage = usage;
1371
1372 state->nregs++;
1373 assert(state->nregs < R600_BLOCK_MAX_REG);
1374 }
1375
1376 void _r600_pipe_state_add_reg(struct r600_context *ctx,
1377 struct r600_pipe_state *state,
1378 uint32_t offset, uint32_t value,
1379 uint32_t range_id, uint32_t block_id)
1380 {
1381 _r600_pipe_state_add_reg_bo(ctx, state, offset, value,
1382 range_id, block_id, NULL, 0);
1383 }
1384
1385 uint32_t r600_translate_stencil_op(int s_op)
1386 {
1387 switch (s_op) {
1388 case PIPE_STENCIL_OP_KEEP:
1389 return V_028800_STENCIL_KEEP;
1390 case PIPE_STENCIL_OP_ZERO:
1391 return V_028800_STENCIL_ZERO;
1392 case PIPE_STENCIL_OP_REPLACE:
1393 return V_028800_STENCIL_REPLACE;
1394 case PIPE_STENCIL_OP_INCR:
1395 return V_028800_STENCIL_INCR;
1396 case PIPE_STENCIL_OP_DECR:
1397 return V_028800_STENCIL_DECR;
1398 case PIPE_STENCIL_OP_INCR_WRAP:
1399 return V_028800_STENCIL_INCR_WRAP;
1400 case PIPE_STENCIL_OP_DECR_WRAP:
1401 return V_028800_STENCIL_DECR_WRAP;
1402 case PIPE_STENCIL_OP_INVERT:
1403 return V_028800_STENCIL_INVERT;
1404 default:
1405 R600_ERR("Unknown stencil op %d", s_op);
1406 assert(0);
1407 break;
1408 }
1409 return 0;
1410 }
1411
1412 uint32_t r600_translate_fill(uint32_t func)
1413 {
1414 switch(func) {
1415 case PIPE_POLYGON_MODE_FILL:
1416 return 2;
1417 case PIPE_POLYGON_MODE_LINE:
1418 return 1;
1419 case PIPE_POLYGON_MODE_POINT:
1420 return 0;
1421 default:
1422 assert(0);
1423 return 0;
1424 }
1425 }
1426
1427 unsigned r600_tex_wrap(unsigned wrap)
1428 {
1429 switch (wrap) {
1430 default:
1431 case PIPE_TEX_WRAP_REPEAT:
1432 return V_03C000_SQ_TEX_WRAP;
1433 case PIPE_TEX_WRAP_CLAMP:
1434 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1435 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1436 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1437 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1438 return V_03C000_SQ_TEX_CLAMP_BORDER;
1439 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1440 return V_03C000_SQ_TEX_MIRROR;
1441 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1442 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1443 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1444 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1445 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1446 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1447 }
1448 }
1449
1450 unsigned r600_tex_filter(unsigned filter)
1451 {
1452 switch (filter) {
1453 default:
1454 case PIPE_TEX_FILTER_NEAREST:
1455 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1456 case PIPE_TEX_FILTER_LINEAR:
1457 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1458 }
1459 }
1460
1461 unsigned r600_tex_mipfilter(unsigned filter)
1462 {
1463 switch (filter) {
1464 case PIPE_TEX_MIPFILTER_NEAREST:
1465 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1466 case PIPE_TEX_MIPFILTER_LINEAR:
1467 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1468 default:
1469 case PIPE_TEX_MIPFILTER_NONE:
1470 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1471 }
1472 }
1473
1474 unsigned r600_tex_compare(unsigned compare)
1475 {
1476 switch (compare) {
1477 default:
1478 case PIPE_FUNC_NEVER:
1479 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1480 case PIPE_FUNC_LESS:
1481 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1482 case PIPE_FUNC_EQUAL:
1483 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1484 case PIPE_FUNC_LEQUAL:
1485 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1486 case PIPE_FUNC_GREATER:
1487 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1488 case PIPE_FUNC_NOTEQUAL:
1489 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1490 case PIPE_FUNC_GEQUAL:
1491 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1492 case PIPE_FUNC_ALWAYS:
1493 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1494 }
1495 }
1496
1497 /* keep this at the end of this file, please */
1498 void r600_init_common_state_functions(struct r600_context *rctx)
1499 {
1500 rctx->context.create_fs_state = r600_create_ps_state;
1501 rctx->context.create_vs_state = r600_create_vs_state;
1502 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1503 rctx->context.bind_blend_state = r600_bind_blend_state;
1504 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1505 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler_states;
1506 rctx->context.bind_fs_state = r600_bind_ps_state;
1507 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1508 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1509 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler_states;
1510 rctx->context.bind_vs_state = r600_bind_vs_state;
1511 rctx->context.delete_blend_state = r600_delete_state;
1512 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1513 rctx->context.delete_fs_state = r600_delete_ps_state;
1514 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1515 rctx->context.delete_sampler_state = r600_delete_sampler_state;
1516 rctx->context.delete_vertex_elements_state = r600_delete_vertex_elements;
1517 rctx->context.delete_vs_state = r600_delete_vs_state;
1518 rctx->context.set_blend_color = r600_set_blend_color;
1519 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1520 rctx->context.set_sample_mask = r600_set_sample_mask;
1521 rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1522 rctx->context.set_viewport_state = r600_set_viewport_state;
1523 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1524 rctx->context.set_index_buffer = r600_set_index_buffer;
1525 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views;
1526 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views;
1527 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1528 rctx->context.texture_barrier = r600_texture_barrier;
1529 rctx->context.create_stream_output_target = r600_create_so_target;
1530 rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1531 rctx->context.set_stream_output_targets = r600_set_so_targets;
1532 rctx->context.draw_vbo = r600_draw_vbo;
1533 }