2 * Copyright 2010 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
27 #include "r600_formats.h"
28 #include "r600_shader.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_format_s3tc.h"
33 #include "util/u_index_modify.h"
34 #include "util/u_memory.h"
35 #include "util/u_upload_mgr.h"
36 #include "util/u_math.h"
37 #include "tgsi/tgsi_parse.h"
39 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
41 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
)
44 cb
->buf
= CALLOC(1, 4 * num_dw
);
45 cb
->max_num_dw
= num_dw
;
48 void r600_release_command_buffer(struct r600_command_buffer
*cb
)
53 void r600_init_atom(struct r600_context
*rctx
,
54 struct r600_atom
*atom
,
56 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
59 assert(id
< R600_NUM_ATOMS
);
60 assert(rctx
->atoms
[id
] == NULL
);
61 rctx
->atoms
[id
] = atom
;
62 atom
->emit
= (void*)emit
;
63 atom
->num_dw
= num_dw
;
67 void r600_emit_cso_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
69 r600_emit_command_buffer(rctx
->b
.rings
.gfx
.cs
, ((struct r600_cso_state
*)atom
)->cb
);
72 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
74 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
75 struct r600_alphatest_state
*a
= (struct r600_alphatest_state
*)atom
;
76 unsigned alpha_ref
= a
->sx_alpha_ref
;
78 if (rctx
->b
.chip_class
>= EVERGREEN
&& a
->cb0_export_16bpc
) {
82 r600_write_context_reg(cs
, R_028410_SX_ALPHA_TEST_CONTROL
,
83 a
->sx_alpha_test_control
|
84 S_028410_ALPHA_TEST_BYPASS(a
->bypass
));
85 r600_write_context_reg(cs
, R_028438_SX_ALPHA_REF
, alpha_ref
);
88 static void r600_texture_barrier(struct pipe_context
*ctx
)
90 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
92 rctx
->b
.flags
|= R600_CONTEXT_INV_TEX_CACHE
|
93 R600_CONTEXT_FLUSH_AND_INV_CB
|
94 R600_CONTEXT_FLUSH_AND_INV
|
95 R600_CONTEXT_WAIT_3D_IDLE
;
98 static unsigned r600_conv_pipe_prim(unsigned prim
)
100 static const unsigned prim_conv
[] = {
101 V_008958_DI_PT_POINTLIST
,
102 V_008958_DI_PT_LINELIST
,
103 V_008958_DI_PT_LINELOOP
,
104 V_008958_DI_PT_LINESTRIP
,
105 V_008958_DI_PT_TRILIST
,
106 V_008958_DI_PT_TRISTRIP
,
107 V_008958_DI_PT_TRIFAN
,
108 V_008958_DI_PT_QUADLIST
,
109 V_008958_DI_PT_QUADSTRIP
,
110 V_008958_DI_PT_POLYGON
,
111 V_008958_DI_PT_LINELIST_ADJ
,
112 V_008958_DI_PT_LINESTRIP_ADJ
,
113 V_008958_DI_PT_TRILIST_ADJ
,
114 V_008958_DI_PT_TRISTRIP_ADJ
,
115 V_008958_DI_PT_RECTLIST
117 return prim_conv
[prim
];
120 /* common state between evergreen and r600 */
122 static void r600_bind_blend_state_internal(struct r600_context
*rctx
,
123 struct r600_blend_state
*blend
, bool blend_disable
)
125 unsigned color_control
;
126 bool update_cb
= false;
128 rctx
->alpha_to_one
= blend
->alpha_to_one
;
129 rctx
->dual_src_blend
= blend
->dual_src_blend
;
131 if (!blend_disable
) {
132 r600_set_cso_state_with_cb(&rctx
->blend_state
, blend
, &blend
->buffer
);
133 color_control
= blend
->cb_color_control
;
135 /* Blending is disabled. */
136 r600_set_cso_state_with_cb(&rctx
->blend_state
, blend
, &blend
->buffer_no_blend
);
137 color_control
= blend
->cb_color_control_no_blend
;
140 /* Update derived states. */
141 if (rctx
->cb_misc_state
.blend_colormask
!= blend
->cb_target_mask
) {
142 rctx
->cb_misc_state
.blend_colormask
= blend
->cb_target_mask
;
145 if (rctx
->b
.chip_class
<= R700
&&
146 rctx
->cb_misc_state
.cb_color_control
!= color_control
) {
147 rctx
->cb_misc_state
.cb_color_control
= color_control
;
150 if (rctx
->cb_misc_state
.dual_src_blend
!= blend
->dual_src_blend
) {
151 rctx
->cb_misc_state
.dual_src_blend
= blend
->dual_src_blend
;
155 rctx
->cb_misc_state
.atom
.dirty
= true;
159 static void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
)
161 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
162 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
167 r600_bind_blend_state_internal(rctx
, blend
, rctx
->force_blend_disable
);
170 static void r600_set_blend_color(struct pipe_context
*ctx
,
171 const struct pipe_blend_color
*state
)
173 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
175 rctx
->blend_color
.state
= *state
;
176 rctx
->blend_color
.atom
.dirty
= true;
179 void r600_emit_blend_color(struct r600_context
*rctx
, struct r600_atom
*atom
)
181 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
182 struct pipe_blend_color
*state
= &rctx
->blend_color
.state
;
184 r600_write_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
185 radeon_emit(cs
, fui(state
->color
[0])); /* R_028414_CB_BLEND_RED */
186 radeon_emit(cs
, fui(state
->color
[1])); /* R_028418_CB_BLEND_GREEN */
187 radeon_emit(cs
, fui(state
->color
[2])); /* R_02841C_CB_BLEND_BLUE */
188 radeon_emit(cs
, fui(state
->color
[3])); /* R_028420_CB_BLEND_ALPHA */
191 void r600_emit_vgt_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
193 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
194 struct r600_vgt_state
*a
= (struct r600_vgt_state
*)atom
;
196 r600_write_context_reg(cs
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, a
->vgt_multi_prim_ib_reset_en
);
197 r600_write_context_reg_seq(cs
, R_028408_VGT_INDX_OFFSET
, 2);
198 radeon_emit(cs
, a
->vgt_indx_offset
); /* R_028408_VGT_INDX_OFFSET */
199 radeon_emit(cs
, a
->vgt_multi_prim_ib_reset_indx
); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
202 static void r600_set_clip_state(struct pipe_context
*ctx
,
203 const struct pipe_clip_state
*state
)
205 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
206 struct pipe_constant_buffer cb
;
208 rctx
->clip_state
.state
= *state
;
209 rctx
->clip_state
.atom
.dirty
= true;
212 cb
.user_buffer
= state
->ucp
;
213 cb
.buffer_offset
= 0;
214 cb
.buffer_size
= 4*4*8;
215 ctx
->set_constant_buffer(ctx
, PIPE_SHADER_VERTEX
, R600_UCP_CONST_BUFFER
, &cb
);
216 pipe_resource_reference(&cb
.buffer
, NULL
);
219 static void r600_set_stencil_ref(struct pipe_context
*ctx
,
220 const struct r600_stencil_ref
*state
)
222 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
224 rctx
->stencil_ref
.state
= *state
;
225 rctx
->stencil_ref
.atom
.dirty
= true;
228 void r600_emit_stencil_ref(struct r600_context
*rctx
, struct r600_atom
*atom
)
230 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
231 struct r600_stencil_ref_state
*a
= (struct r600_stencil_ref_state
*)atom
;
233 r600_write_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
234 radeon_emit(cs
, /* R_028430_DB_STENCILREFMASK */
235 S_028430_STENCILREF(a
->state
.ref_value
[0]) |
236 S_028430_STENCILMASK(a
->state
.valuemask
[0]) |
237 S_028430_STENCILWRITEMASK(a
->state
.writemask
[0]));
238 radeon_emit(cs
, /* R_028434_DB_STENCILREFMASK_BF */
239 S_028434_STENCILREF_BF(a
->state
.ref_value
[1]) |
240 S_028434_STENCILMASK_BF(a
->state
.valuemask
[1]) |
241 S_028434_STENCILWRITEMASK_BF(a
->state
.writemask
[1]));
244 static void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
245 const struct pipe_stencil_ref
*state
)
247 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
248 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)rctx
->dsa_state
.cso
;
249 struct r600_stencil_ref ref
;
251 rctx
->stencil_ref
.pipe_state
= *state
;
256 ref
.ref_value
[0] = state
->ref_value
[0];
257 ref
.ref_value
[1] = state
->ref_value
[1];
258 ref
.valuemask
[0] = dsa
->valuemask
[0];
259 ref
.valuemask
[1] = dsa
->valuemask
[1];
260 ref
.writemask
[0] = dsa
->writemask
[0];
261 ref
.writemask
[1] = dsa
->writemask
[1];
263 r600_set_stencil_ref(ctx
, &ref
);
266 static void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
268 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
269 struct r600_dsa_state
*dsa
= state
;
270 struct r600_stencil_ref ref
;
273 r600_set_cso_state_with_cb(&rctx
->dsa_state
, NULL
, NULL
);
277 r600_set_cso_state_with_cb(&rctx
->dsa_state
, dsa
, &dsa
->buffer
);
279 ref
.ref_value
[0] = rctx
->stencil_ref
.pipe_state
.ref_value
[0];
280 ref
.ref_value
[1] = rctx
->stencil_ref
.pipe_state
.ref_value
[1];
281 ref
.valuemask
[0] = dsa
->valuemask
[0];
282 ref
.valuemask
[1] = dsa
->valuemask
[1];
283 ref
.writemask
[0] = dsa
->writemask
[0];
284 ref
.writemask
[1] = dsa
->writemask
[1];
285 if (rctx
->zwritemask
!= dsa
->zwritemask
) {
286 rctx
->zwritemask
= dsa
->zwritemask
;
287 if (rctx
->b
.chip_class
>= EVERGREEN
) {
288 /* work around some issue when not writting to zbuffer
289 * we are having lockup on evergreen so do not enable
290 * hyperz when not writting zbuffer
292 rctx
->db_misc_state
.atom
.dirty
= true;
296 r600_set_stencil_ref(ctx
, &ref
);
298 /* Update alphatest state. */
299 if (rctx
->alphatest_state
.sx_alpha_test_control
!= dsa
->sx_alpha_test_control
||
300 rctx
->alphatest_state
.sx_alpha_ref
!= dsa
->alpha_ref
) {
301 rctx
->alphatest_state
.sx_alpha_test_control
= dsa
->sx_alpha_test_control
;
302 rctx
->alphatest_state
.sx_alpha_ref
= dsa
->alpha_ref
;
303 rctx
->alphatest_state
.atom
.dirty
= true;
307 static void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
)
309 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
310 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
315 rctx
->rasterizer
= rs
;
317 r600_set_cso_state_with_cb(&rctx
->rasterizer_state
, rs
, &rs
->buffer
);
319 if (rs
->offset_enable
&&
320 (rs
->offset_units
!= rctx
->poly_offset_state
.offset_units
||
321 rs
->offset_scale
!= rctx
->poly_offset_state
.offset_scale
)) {
322 rctx
->poly_offset_state
.offset_units
= rs
->offset_units
;
323 rctx
->poly_offset_state
.offset_scale
= rs
->offset_scale
;
324 rctx
->poly_offset_state
.atom
.dirty
= true;
327 /* Update clip_misc_state. */
328 if (rctx
->clip_misc_state
.pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
||
329 rctx
->clip_misc_state
.clip_plane_enable
!= rs
->clip_plane_enable
) {
330 rctx
->clip_misc_state
.pa_cl_clip_cntl
= rs
->pa_cl_clip_cntl
;
331 rctx
->clip_misc_state
.clip_plane_enable
= rs
->clip_plane_enable
;
332 rctx
->clip_misc_state
.atom
.dirty
= true;
335 /* Workaround for a missing scissor enable on r600. */
336 if (rctx
->b
.chip_class
== R600
&&
337 rs
->scissor_enable
!= rctx
->scissor
[0].enable
) {
338 rctx
->scissor
[0].enable
= rs
->scissor_enable
;
339 rctx
->scissor
[0].atom
.dirty
= true;
342 /* Re-emit PA_SC_LINE_STIPPLE. */
343 rctx
->last_primitive_type
= -1;
346 static void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
)
348 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
350 r600_release_command_buffer(&rs
->buffer
);
354 static void r600_sampler_view_destroy(struct pipe_context
*ctx
,
355 struct pipe_sampler_view
*state
)
357 struct r600_pipe_sampler_view
*resource
= (struct r600_pipe_sampler_view
*)state
;
359 pipe_resource_reference(&state
->texture
, NULL
);
363 void r600_sampler_states_dirty(struct r600_context
*rctx
,
364 struct r600_sampler_states
*state
)
366 if (state
->dirty_mask
) {
367 if (state
->dirty_mask
& state
->has_bordercolor_mask
) {
368 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
371 util_bitcount(state
->dirty_mask
& state
->has_bordercolor_mask
) * 11 +
372 util_bitcount(state
->dirty_mask
& ~state
->has_bordercolor_mask
) * 5;
373 state
->atom
.dirty
= true;
377 static void r600_bind_sampler_states(struct pipe_context
*pipe
,
380 unsigned count
, void **states
)
382 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
383 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
384 struct r600_pipe_sampler_state
**rstates
= (struct r600_pipe_sampler_state
**)states
;
385 int seamless_cube_map
= -1;
387 /* This sets 1-bit for states with index >= count. */
388 uint32_t disable_mask
= ~((1ull << count
) - 1);
389 /* These are the new states set by this function. */
390 uint32_t new_mask
= 0;
392 assert(start
== 0); /* XXX fix below */
394 if (shader
!= PIPE_SHADER_VERTEX
&&
395 shader
!= PIPE_SHADER_FRAGMENT
) {
399 for (i
= 0; i
< count
; i
++) {
400 struct r600_pipe_sampler_state
*rstate
= rstates
[i
];
402 if (rstate
== dst
->states
.states
[i
]) {
407 if (rstate
->border_color_use
) {
408 dst
->states
.has_bordercolor_mask
|= 1 << i
;
410 dst
->states
.has_bordercolor_mask
&= ~(1 << i
);
412 seamless_cube_map
= rstate
->seamless_cube_map
;
416 disable_mask
|= 1 << i
;
420 memcpy(dst
->states
.states
, rstates
, sizeof(void*) * count
);
421 memset(dst
->states
.states
+ count
, 0, sizeof(void*) * (NUM_TEX_UNITS
- count
));
423 dst
->states
.enabled_mask
&= ~disable_mask
;
424 dst
->states
.dirty_mask
&= dst
->states
.enabled_mask
;
425 dst
->states
.enabled_mask
|= new_mask
;
426 dst
->states
.dirty_mask
|= new_mask
;
427 dst
->states
.has_bordercolor_mask
&= dst
->states
.enabled_mask
;
429 r600_sampler_states_dirty(rctx
, &dst
->states
);
431 /* Seamless cubemap state. */
432 if (rctx
->b
.chip_class
<= R700
&&
433 seamless_cube_map
!= -1 &&
434 seamless_cube_map
!= rctx
->seamless_cube_map
.enabled
) {
435 /* change in TA_CNTL_AUX need a pipeline flush */
436 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
437 rctx
->seamless_cube_map
.enabled
= seamless_cube_map
;
438 rctx
->seamless_cube_map
.atom
.dirty
= true;
442 static void r600_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
447 static void r600_delete_blend_state(struct pipe_context
*ctx
, void *state
)
449 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
451 r600_release_command_buffer(&blend
->buffer
);
452 r600_release_command_buffer(&blend
->buffer_no_blend
);
456 static void r600_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
458 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
459 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)state
;
461 if (rctx
->dsa_state
.cso
== state
) {
462 ctx
->bind_depth_stencil_alpha_state(ctx
, NULL
);
465 r600_release_command_buffer(&dsa
->buffer
);
469 static void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
471 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
473 r600_set_cso_state(&rctx
->vertex_fetch_shader
, state
);
476 static void r600_delete_vertex_elements(struct pipe_context
*ctx
, void *state
)
478 struct r600_fetch_shader
*shader
= (struct r600_fetch_shader
*)state
;
479 pipe_resource_reference((struct pipe_resource
**)&shader
->buffer
, NULL
);
483 static void r600_set_index_buffer(struct pipe_context
*ctx
,
484 const struct pipe_index_buffer
*ib
)
486 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
489 pipe_resource_reference(&rctx
->index_buffer
.buffer
, ib
->buffer
);
490 memcpy(&rctx
->index_buffer
, ib
, sizeof(*ib
));
491 r600_context_add_resource_size(ctx
, ib
->buffer
);
493 pipe_resource_reference(&rctx
->index_buffer
.buffer
, NULL
);
497 void r600_vertex_buffers_dirty(struct r600_context
*rctx
)
499 if (rctx
->vertex_buffer_state
.dirty_mask
) {
500 rctx
->b
.flags
|= R600_CONTEXT_INV_VERTEX_CACHE
;
501 rctx
->vertex_buffer_state
.atom
.num_dw
= (rctx
->b
.chip_class
>= EVERGREEN
? 12 : 11) *
502 util_bitcount(rctx
->vertex_buffer_state
.dirty_mask
);
503 rctx
->vertex_buffer_state
.atom
.dirty
= true;
507 static void r600_set_vertex_buffers(struct pipe_context
*ctx
,
508 unsigned start_slot
, unsigned count
,
509 const struct pipe_vertex_buffer
*input
)
511 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
512 struct r600_vertexbuf_state
*state
= &rctx
->vertex_buffer_state
;
513 struct pipe_vertex_buffer
*vb
= state
->vb
+ start_slot
;
515 uint32_t disable_mask
= 0;
516 /* These are the new buffers set by this function. */
517 uint32_t new_buffer_mask
= 0;
519 /* Set vertex buffers. */
521 for (i
= 0; i
< count
; i
++) {
522 if (memcmp(&input
[i
], &vb
[i
], sizeof(struct pipe_vertex_buffer
))) {
523 if (input
[i
].buffer
) {
524 vb
[i
].stride
= input
[i
].stride
;
525 vb
[i
].buffer_offset
= input
[i
].buffer_offset
;
526 pipe_resource_reference(&vb
[i
].buffer
, input
[i
].buffer
);
527 new_buffer_mask
|= 1 << i
;
528 r600_context_add_resource_size(ctx
, input
[i
].buffer
);
530 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
531 disable_mask
|= 1 << i
;
536 for (i
= 0; i
< count
; i
++) {
537 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
539 disable_mask
= ((1ull << count
) - 1);
542 disable_mask
<<= start_slot
;
543 new_buffer_mask
<<= start_slot
;
545 rctx
->vertex_buffer_state
.enabled_mask
&= ~disable_mask
;
546 rctx
->vertex_buffer_state
.dirty_mask
&= rctx
->vertex_buffer_state
.enabled_mask
;
547 rctx
->vertex_buffer_state
.enabled_mask
|= new_buffer_mask
;
548 rctx
->vertex_buffer_state
.dirty_mask
|= new_buffer_mask
;
550 r600_vertex_buffers_dirty(rctx
);
553 void r600_sampler_views_dirty(struct r600_context
*rctx
,
554 struct r600_samplerview_state
*state
)
556 if (state
->dirty_mask
) {
557 rctx
->b
.flags
|= R600_CONTEXT_INV_TEX_CACHE
;
558 state
->atom
.num_dw
= (rctx
->b
.chip_class
>= EVERGREEN
? 14 : 13) *
559 util_bitcount(state
->dirty_mask
);
560 state
->atom
.dirty
= true;
564 static void r600_set_sampler_views(struct pipe_context
*pipe
, unsigned shader
,
565 unsigned start
, unsigned count
,
566 struct pipe_sampler_view
**views
)
568 struct r600_context
*rctx
= (struct r600_context
*) pipe
;
569 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
570 struct r600_pipe_sampler_view
**rviews
= (struct r600_pipe_sampler_view
**)views
;
571 uint32_t dirty_sampler_states_mask
= 0;
573 /* This sets 1-bit for textures with index >= count. */
574 uint32_t disable_mask
= ~((1ull << count
) - 1);
575 /* These are the new textures set by this function. */
576 uint32_t new_mask
= 0;
578 /* Set textures with index >= count to NULL. */
579 uint32_t remaining_mask
;
581 assert(start
== 0); /* XXX fix below */
583 if (shader
== PIPE_SHADER_COMPUTE
) {
584 evergreen_set_cs_sampler_view(pipe
, start
, count
, views
);
588 remaining_mask
= dst
->views
.enabled_mask
& disable_mask
;
590 while (remaining_mask
) {
591 i
= u_bit_scan(&remaining_mask
);
592 assert(dst
->views
.views
[i
]);
594 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
597 for (i
= 0; i
< count
; i
++) {
598 if (rviews
[i
] == dst
->views
.views
[i
]) {
603 struct r600_texture
*rtex
=
604 (struct r600_texture
*)rviews
[i
]->base
.texture
;
606 if (rviews
[i
]->base
.texture
->target
!= PIPE_BUFFER
) {
607 if (rtex
->is_depth
&& !rtex
->is_flushing_texture
) {
608 dst
->views
.compressed_depthtex_mask
|= 1 << i
;
610 dst
->views
.compressed_depthtex_mask
&= ~(1 << i
);
613 /* Track compressed colorbuffers. */
614 if (rtex
->cmask
.size
) {
615 dst
->views
.compressed_colortex_mask
|= 1 << i
;
617 dst
->views
.compressed_colortex_mask
&= ~(1 << i
);
620 /* Changing from array to non-arrays textures and vice versa requires
621 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
622 if (rctx
->b
.chip_class
<= R700
&&
623 (dst
->states
.enabled_mask
& (1 << i
)) &&
624 (rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_1D_ARRAY
||
625 rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_2D_ARRAY
) != dst
->is_array_sampler
[i
]) {
626 dirty_sampler_states_mask
|= 1 << i
;
629 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], views
[i
]);
631 r600_context_add_resource_size(pipe
, views
[i
]->texture
);
633 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
634 disable_mask
|= 1 << i
;
638 dst
->views
.enabled_mask
&= ~disable_mask
;
639 dst
->views
.dirty_mask
&= dst
->views
.enabled_mask
;
640 dst
->views
.enabled_mask
|= new_mask
;
641 dst
->views
.dirty_mask
|= new_mask
;
642 dst
->views
.compressed_depthtex_mask
&= dst
->views
.enabled_mask
;
643 dst
->views
.compressed_colortex_mask
&= dst
->views
.enabled_mask
;
644 dst
->views
.dirty_txq_constants
= TRUE
;
645 dst
->views
.dirty_buffer_constants
= TRUE
;
646 r600_sampler_views_dirty(rctx
, &dst
->views
);
648 if (dirty_sampler_states_mask
) {
649 dst
->states
.dirty_mask
|= dirty_sampler_states_mask
;
650 r600_sampler_states_dirty(rctx
, &dst
->states
);
654 static void r600_set_viewport_states(struct pipe_context
*ctx
,
656 unsigned num_viewports
,
657 const struct pipe_viewport_state
*state
)
659 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
662 for (i
= start_slot
; i
< start_slot
+ num_viewports
; i
++) {
663 rctx
->viewport
[i
].state
= state
[i
- start_slot
];
664 rctx
->viewport
[i
].atom
.dirty
= true;
668 void r600_emit_viewport_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
670 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
671 struct r600_viewport_state
*rstate
= (struct r600_viewport_state
*)atom
;
672 struct pipe_viewport_state
*state
= &rstate
->state
;
673 int offset
= rstate
->idx
* 6 * 4;
675 r600_write_context_reg_seq(cs
, R_02843C_PA_CL_VPORT_XSCALE_0
+ offset
, 6);
676 radeon_emit(cs
, fui(state
->scale
[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
677 radeon_emit(cs
, fui(state
->translate
[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
678 radeon_emit(cs
, fui(state
->scale
[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
679 radeon_emit(cs
, fui(state
->translate
[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
680 radeon_emit(cs
, fui(state
->scale
[2])); /* R_02844C_PA_CL_VPORT_ZSCALE_0 */
681 radeon_emit(cs
, fui(state
->translate
[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
684 /* Compute the key for the hw shader variant */
685 static INLINE
struct r600_shader_key
r600_shader_selector_key(struct pipe_context
* ctx
,
686 struct r600_pipe_shader_selector
* sel
)
688 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
689 struct r600_shader_key key
;
690 memset(&key
, 0, sizeof(key
));
692 if (sel
->type
== PIPE_SHADER_FRAGMENT
) {
693 key
.color_two_side
= rctx
->rasterizer
&& rctx
->rasterizer
->two_side
;
694 key
.alpha_to_one
= rctx
->alpha_to_one
&&
695 rctx
->rasterizer
&& rctx
->rasterizer
->multisample_enable
&&
696 !rctx
->framebuffer
.cb0_is_integer
;
697 key
.nr_cbufs
= rctx
->framebuffer
.state
.nr_cbufs
;
698 /* Dual-source blending only makes sense with nr_cbufs == 1. */
699 if (key
.nr_cbufs
== 1 && rctx
->dual_src_blend
)
701 } else if (sel
->type
== PIPE_SHADER_VERTEX
) {
702 key
.vs_as_es
= (rctx
->gs_shader
!= NULL
);
707 /* Select the hw shader variant depending on the current state.
708 * (*dirty) is set to 1 if current variant was changed */
709 static int r600_shader_select(struct pipe_context
*ctx
,
710 struct r600_pipe_shader_selector
* sel
,
713 struct r600_shader_key key
;
714 struct r600_pipe_shader
* shader
= NULL
;
717 memset(&key
, 0, sizeof(key
));
718 key
= r600_shader_selector_key(ctx
, sel
);
720 /* Check if we don't need to change anything.
721 * This path is also used for most shaders that don't need multiple
722 * variants, it will cost just a computation of the key and this
724 if (likely(sel
->current
&& memcmp(&sel
->current
->key
, &key
, sizeof(key
)) == 0)) {
728 /* lookup if we have other variants in the list */
729 if (sel
->num_shaders
> 1) {
730 struct r600_pipe_shader
*p
= sel
->current
, *c
= p
->next_variant
;
732 while (c
&& memcmp(&c
->key
, &key
, sizeof(key
)) != 0) {
738 p
->next_variant
= c
->next_variant
;
743 if (unlikely(!shader
)) {
744 shader
= CALLOC(1, sizeof(struct r600_pipe_shader
));
745 shader
->selector
= sel
;
747 r
= r600_pipe_shader_create(ctx
, shader
, key
);
749 R600_ERR("Failed to build shader variant (type=%u) %d\n",
756 /* We don't know the value of nr_ps_max_color_exports until we built
757 * at least one variant, so we may need to recompute the key after
758 * building first variant. */
759 if (sel
->type
== PIPE_SHADER_FRAGMENT
&&
760 sel
->num_shaders
== 0) {
761 sel
->nr_ps_max_color_exports
= shader
->shader
.nr_ps_max_color_exports
;
762 key
= r600_shader_selector_key(ctx
, sel
);
765 memcpy(&shader
->key
, &key
, sizeof(key
));
772 shader
->next_variant
= sel
->current
;
773 sel
->current
= shader
;
778 static void *r600_create_shader_state(struct pipe_context
*ctx
,
779 const struct pipe_shader_state
*state
,
780 unsigned pipe_shader_type
)
782 struct r600_pipe_shader_selector
*sel
= CALLOC_STRUCT(r600_pipe_shader_selector
);
784 sel
->type
= pipe_shader_type
;
785 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
786 sel
->so
= state
->stream_output
;
790 static void *r600_create_ps_state(struct pipe_context
*ctx
,
791 const struct pipe_shader_state
*state
)
793 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_FRAGMENT
);
796 static void *r600_create_vs_state(struct pipe_context
*ctx
,
797 const struct pipe_shader_state
*state
)
799 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_VERTEX
);
802 static void *r600_create_gs_state(struct pipe_context
*ctx
,
803 const struct pipe_shader_state
*state
)
805 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_GEOMETRY
);
808 static void r600_bind_ps_state(struct pipe_context
*ctx
, void *state
)
810 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
813 state
= rctx
->dummy_pixel_shader
;
815 rctx
->ps_shader
= (struct r600_pipe_shader_selector
*)state
;
818 static void r600_bind_vs_state(struct pipe_context
*ctx
, void *state
)
820 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
825 rctx
->vs_shader
= (struct r600_pipe_shader_selector
*)state
;
826 rctx
->b
.streamout
.stride_in_dw
= rctx
->vs_shader
->so
.stride
;
829 static void r600_bind_gs_state(struct pipe_context
*ctx
, void *state
)
831 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
833 rctx
->gs_shader
= (struct r600_pipe_shader_selector
*)state
;
837 rctx
->b
.streamout
.stride_in_dw
= rctx
->gs_shader
->so
.stride
;
840 static void r600_delete_shader_selector(struct pipe_context
*ctx
,
841 struct r600_pipe_shader_selector
*sel
)
843 struct r600_pipe_shader
*p
= sel
->current
, *c
;
846 r600_pipe_shader_destroy(ctx
, p
);
856 static void r600_delete_ps_state(struct pipe_context
*ctx
, void *state
)
858 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
859 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
861 if (rctx
->ps_shader
== sel
) {
862 rctx
->ps_shader
= NULL
;
865 r600_delete_shader_selector(ctx
, sel
);
868 static void r600_delete_vs_state(struct pipe_context
*ctx
, void *state
)
870 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
871 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
873 if (rctx
->vs_shader
== sel
) {
874 rctx
->vs_shader
= NULL
;
877 r600_delete_shader_selector(ctx
, sel
);
881 static void r600_delete_gs_state(struct pipe_context
*ctx
, void *state
)
883 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
884 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
886 if (rctx
->gs_shader
== sel
) {
887 rctx
->gs_shader
= NULL
;
890 r600_delete_shader_selector(ctx
, sel
);
894 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
)
896 if (state
->dirty_mask
) {
897 rctx
->b
.flags
|= R600_CONTEXT_INV_CONST_CACHE
;
898 state
->atom
.num_dw
= rctx
->b
.chip_class
>= EVERGREEN
? util_bitcount(state
->dirty_mask
)*20
899 : util_bitcount(state
->dirty_mask
)*19;
900 state
->atom
.dirty
= true;
904 static void r600_set_constant_buffer(struct pipe_context
*ctx
, uint shader
, uint index
,
905 struct pipe_constant_buffer
*input
)
907 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
908 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
909 struct pipe_constant_buffer
*cb
;
912 /* Note that the state tracker can unbind constant buffers by
915 if (unlikely(!input
|| (!input
->buffer
&& !input
->user_buffer
))) {
916 state
->enabled_mask
&= ~(1 << index
);
917 state
->dirty_mask
&= ~(1 << index
);
918 pipe_resource_reference(&state
->cb
[index
].buffer
, NULL
);
922 cb
= &state
->cb
[index
];
923 cb
->buffer_size
= input
->buffer_size
;
925 ptr
= input
->user_buffer
;
928 /* Upload the user buffer. */
929 if (R600_BIG_ENDIAN
) {
931 unsigned i
, size
= input
->buffer_size
;
933 if (!(tmpPtr
= malloc(size
))) {
934 R600_ERR("Failed to allocate BE swap buffer.\n");
938 for (i
= 0; i
< size
/ 4; ++i
) {
939 tmpPtr
[i
] = util_cpu_to_le32(((uint32_t *)ptr
)[i
]);
942 u_upload_data(rctx
->b
.uploader
, 0, size
, tmpPtr
, &cb
->buffer_offset
, &cb
->buffer
);
945 u_upload_data(rctx
->b
.uploader
, 0, input
->buffer_size
, ptr
, &cb
->buffer_offset
, &cb
->buffer
);
947 /* account it in gtt */
948 rctx
->b
.gtt
+= input
->buffer_size
;
950 /* Setup the hw buffer. */
951 cb
->buffer_offset
= input
->buffer_offset
;
952 pipe_resource_reference(&cb
->buffer
, input
->buffer
);
953 r600_context_add_resource_size(ctx
, input
->buffer
);
956 state
->enabled_mask
|= 1 << index
;
957 state
->dirty_mask
|= 1 << index
;
958 r600_constant_buffers_dirty(rctx
, state
);
961 static void r600_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
963 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
965 if (rctx
->sample_mask
.sample_mask
== (uint16_t)sample_mask
)
968 rctx
->sample_mask
.sample_mask
= sample_mask
;
969 rctx
->sample_mask
.atom
.dirty
= true;
973 * On r600/700 hw we don't have vertex fetch swizzle, though TBO
974 * doesn't require full swizzles it does need masking and setting alpha
975 * to one, so we setup a set of 5 constants with the masks + alpha value
976 * then in the shader, we AND the 4 components with 0xffffffff or 0,
977 * then OR the alpha with the value given here.
978 * We use a 6th constant to store the txq buffer size in
980 static void r600_setup_buffer_constants(struct r600_context
*rctx
, int shader_type
)
982 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
985 struct pipe_constant_buffer cb
;
988 if (!samplers
->views
.dirty_buffer_constants
)
991 samplers
->views
.dirty_buffer_constants
= FALSE
;
993 bits
= util_last_bit(samplers
->views
.enabled_mask
);
994 array_size
= bits
* 8 * sizeof(uint32_t) * 4;
995 samplers
->buffer_constants
= realloc(samplers
->buffer_constants
, array_size
);
996 memset(samplers
->buffer_constants
, 0, array_size
);
997 for (i
= 0; i
< bits
; i
++) {
998 if (samplers
->views
.enabled_mask
& (1 << i
)) {
1000 const struct util_format_description
*desc
;
1001 desc
= util_format_description(samplers
->views
.views
[i
]->base
.format
);
1003 for (j
= 0; j
< 4; j
++)
1004 if (j
< desc
->nr_channels
)
1005 samplers
->buffer_constants
[offset
+j
] = 0xffffffff;
1007 samplers
->buffer_constants
[offset
+j
] = 0x0;
1008 if (desc
->nr_channels
< 4) {
1009 if (desc
->channel
[0].pure_integer
)
1010 samplers
->buffer_constants
[offset
+4] = 1;
1012 samplers
->buffer_constants
[offset
+4] = 0x3f800000;
1014 samplers
->buffer_constants
[offset
+ 4] = 0;
1016 samplers
->buffer_constants
[offset
+ 5] = samplers
->views
.views
[i
]->base
.texture
->width0
/ util_format_get_blocksize(samplers
->views
.views
[i
]->base
.format
);
1021 cb
.user_buffer
= samplers
->buffer_constants
;
1022 cb
.buffer_offset
= 0;
1023 cb
.buffer_size
= array_size
;
1024 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, shader_type
, R600_BUFFER_INFO_CONST_BUFFER
, &cb
);
1025 pipe_resource_reference(&cb
.buffer
, NULL
);
1028 /* On evergreen we only need to store the buffer size for TXQ */
1029 static void eg_setup_buffer_constants(struct r600_context
*rctx
, int shader_type
)
1031 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1033 uint32_t array_size
;
1034 struct pipe_constant_buffer cb
;
1037 if (!samplers
->views
.dirty_buffer_constants
)
1040 samplers
->views
.dirty_buffer_constants
= FALSE
;
1042 bits
= util_last_bit(samplers
->views
.enabled_mask
);
1043 array_size
= bits
* sizeof(uint32_t) * 4;
1044 samplers
->buffer_constants
= realloc(samplers
->buffer_constants
, array_size
);
1045 memset(samplers
->buffer_constants
, 0, array_size
);
1046 for (i
= 0; i
< bits
; i
++)
1047 if (samplers
->views
.enabled_mask
& (1 << i
))
1048 samplers
->buffer_constants
[i
] = samplers
->views
.views
[i
]->base
.texture
->width0
/ util_format_get_blocksize(samplers
->views
.views
[i
]->base
.format
);
1051 cb
.user_buffer
= samplers
->buffer_constants
;
1052 cb
.buffer_offset
= 0;
1053 cb
.buffer_size
= array_size
;
1054 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, shader_type
, R600_BUFFER_INFO_CONST_BUFFER
, &cb
);
1055 pipe_resource_reference(&cb
.buffer
, NULL
);
1058 static void r600_setup_txq_cube_array_constants(struct r600_context
*rctx
, int shader_type
)
1060 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1062 uint32_t array_size
;
1063 struct pipe_constant_buffer cb
;
1066 if (!samplers
->views
.dirty_txq_constants
)
1069 samplers
->views
.dirty_txq_constants
= FALSE
;
1071 bits
= util_last_bit(samplers
->views
.enabled_mask
);
1072 array_size
= bits
* sizeof(uint32_t) * 4;
1073 samplers
->txq_constants
= realloc(samplers
->txq_constants
, array_size
);
1074 memset(samplers
->txq_constants
, 0, array_size
);
1075 for (i
= 0; i
< bits
; i
++)
1076 if (samplers
->views
.enabled_mask
& (1 << i
))
1077 samplers
->txq_constants
[i
] = samplers
->views
.views
[i
]->base
.texture
->array_size
/ 6;
1080 cb
.user_buffer
= samplers
->txq_constants
;
1081 cb
.buffer_offset
= 0;
1082 cb
.buffer_size
= array_size
;
1083 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, shader_type
, R600_TXQ_CONST_BUFFER
, &cb
);
1084 pipe_resource_reference(&cb
.buffer
, NULL
);
1087 static void update_shader_atom(struct pipe_context
*ctx
,
1088 struct r600_shader_state
*state
,
1089 struct r600_pipe_shader
*shader
)
1091 state
->shader
= shader
;
1093 state
->atom
.num_dw
= shader
->command_buffer
.num_dw
;
1094 state
->atom
.dirty
= true;
1095 r600_context_add_resource_size(ctx
, (struct pipe_resource
*)shader
->bo
);
1097 state
->atom
.num_dw
= 0;
1098 state
->atom
.dirty
= false;
1102 static void update_gs_block_state(struct r600_context
*rctx
, unsigned enable
)
1104 if (rctx
->shader_stages
.geom_enable
!= enable
) {
1105 rctx
->shader_stages
.geom_enable
= enable
;
1106 rctx
->shader_stages
.atom
.dirty
= true;
1109 if (rctx
->gs_rings
.enable
!= enable
) {
1110 rctx
->gs_rings
.enable
= enable
;
1111 rctx
->gs_rings
.atom
.dirty
= true;
1113 if (enable
&& !rctx
->gs_rings
.esgs_ring
.buffer
) {
1114 unsigned size
= 0x1C000;
1115 rctx
->gs_rings
.esgs_ring
.buffer
=
1116 pipe_buffer_create(rctx
->b
.b
.screen
, PIPE_BIND_CUSTOM
,
1117 PIPE_USAGE_DEFAULT
, size
);
1118 rctx
->gs_rings
.esgs_ring
.buffer_size
= size
;
1122 rctx
->gs_rings
.gsvs_ring
.buffer
=
1123 pipe_buffer_create(rctx
->b
.b
.screen
, PIPE_BIND_CUSTOM
,
1124 PIPE_USAGE_DEFAULT
, size
);
1125 rctx
->gs_rings
.gsvs_ring
.buffer_size
= size
;
1129 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_GEOMETRY
,
1130 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.esgs_ring
);
1131 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_VERTEX
,
1132 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.gsvs_ring
);
1134 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_GEOMETRY
,
1135 R600_GS_RING_CONST_BUFFER
, NULL
);
1136 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_VERTEX
,
1137 R600_GS_RING_CONST_BUFFER
, NULL
);
1142 static bool r600_update_derived_state(struct r600_context
*rctx
)
1144 struct pipe_context
* ctx
= (struct pipe_context
*)rctx
;
1145 bool ps_dirty
= false, vs_dirty
= false, gs_dirty
= false;
1148 if (!rctx
->blitter
->running
) {
1151 /* Decompress textures if needed. */
1152 for (i
= 0; i
< PIPE_SHADER_TYPES
; i
++) {
1153 struct r600_samplerview_state
*views
= &rctx
->samplers
[i
].views
;
1154 if (views
->compressed_depthtex_mask
) {
1155 r600_decompress_depth_textures(rctx
, views
);
1157 if (views
->compressed_colortex_mask
) {
1158 r600_decompress_color_textures(rctx
, views
);
1163 update_gs_block_state(rctx
, rctx
->gs_shader
!= NULL
);
1165 if (rctx
->gs_shader
) {
1166 r600_shader_select(ctx
, rctx
->gs_shader
, &gs_dirty
);
1167 if (unlikely(!rctx
->gs_shader
->current
))
1170 if (!rctx
->shader_stages
.geom_enable
) {
1171 rctx
->shader_stages
.geom_enable
= true;
1172 rctx
->shader_stages
.atom
.dirty
= true;
1175 /* gs_shader provides GS and VS (copy shader) */
1176 if (unlikely(rctx
->geometry_shader
.shader
!= rctx
->gs_shader
->current
)) {
1177 update_shader_atom(ctx
, &rctx
->geometry_shader
, rctx
->gs_shader
->current
);
1178 update_shader_atom(ctx
, &rctx
->vertex_shader
, rctx
->gs_shader
->current
->gs_copy_shader
);
1179 /* Update clip misc state. */
1180 if (rctx
->gs_shader
->current
->gs_copy_shader
->pa_cl_vs_out_cntl
!= rctx
->clip_misc_state
.pa_cl_vs_out_cntl
||
1181 rctx
->gs_shader
->current
->gs_copy_shader
->shader
.clip_dist_write
!= rctx
->clip_misc_state
.clip_dist_write
||
1182 rctx
->clip_misc_state
.clip_disable
!= rctx
->gs_shader
->current
->shader
.vs_position_window_space
) {
1183 rctx
->clip_misc_state
.pa_cl_vs_out_cntl
= rctx
->gs_shader
->current
->gs_copy_shader
->pa_cl_vs_out_cntl
;
1184 rctx
->clip_misc_state
.clip_dist_write
= rctx
->gs_shader
->current
->gs_copy_shader
->shader
.clip_dist_write
;
1185 rctx
->clip_misc_state
.clip_disable
= rctx
->gs_shader
->current
->shader
.vs_position_window_space
;
1186 rctx
->clip_misc_state
.atom
.dirty
= true;
1190 r600_shader_select(ctx
, rctx
->vs_shader
, &vs_dirty
);
1191 if (unlikely(!rctx
->vs_shader
->current
))
1194 /* vs_shader is used as ES */
1195 if (unlikely(vs_dirty
|| rctx
->export_shader
.shader
!= rctx
->vs_shader
->current
)) {
1196 update_shader_atom(ctx
, &rctx
->export_shader
, rctx
->vs_shader
->current
);
1199 if (unlikely(rctx
->geometry_shader
.shader
)) {
1200 update_shader_atom(ctx
, &rctx
->geometry_shader
, NULL
);
1201 update_shader_atom(ctx
, &rctx
->export_shader
, NULL
);
1202 rctx
->shader_stages
.geom_enable
= false;
1203 rctx
->shader_stages
.atom
.dirty
= true;
1206 r600_shader_select(ctx
, rctx
->vs_shader
, &vs_dirty
);
1207 if (unlikely(!rctx
->vs_shader
->current
))
1210 if (unlikely(vs_dirty
|| rctx
->vertex_shader
.shader
!= rctx
->vs_shader
->current
)) {
1211 update_shader_atom(ctx
, &rctx
->vertex_shader
, rctx
->vs_shader
->current
);
1213 /* Update clip misc state. */
1214 if (rctx
->vs_shader
->current
->pa_cl_vs_out_cntl
!= rctx
->clip_misc_state
.pa_cl_vs_out_cntl
||
1215 rctx
->vs_shader
->current
->shader
.clip_dist_write
!= rctx
->clip_misc_state
.clip_dist_write
||
1216 rctx
->clip_misc_state
.clip_disable
!= rctx
->vs_shader
->current
->shader
.vs_position_window_space
) {
1217 rctx
->clip_misc_state
.pa_cl_vs_out_cntl
= rctx
->vs_shader
->current
->pa_cl_vs_out_cntl
;
1218 rctx
->clip_misc_state
.clip_dist_write
= rctx
->vs_shader
->current
->shader
.clip_dist_write
;
1219 rctx
->clip_misc_state
.clip_disable
= rctx
->vs_shader
->current
->shader
.vs_position_window_space
;
1220 rctx
->clip_misc_state
.atom
.dirty
= true;
1225 r600_shader_select(ctx
, rctx
->ps_shader
, &ps_dirty
);
1226 if (unlikely(!rctx
->ps_shader
->current
))
1229 if (unlikely(ps_dirty
|| rctx
->pixel_shader
.shader
!= rctx
->ps_shader
->current
)) {
1231 if (rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
1232 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
1233 rctx
->cb_misc_state
.atom
.dirty
= true;
1236 if (rctx
->b
.chip_class
<= R700
) {
1237 bool multiwrite
= rctx
->ps_shader
->current
->shader
.fs_write_all
;
1239 if (rctx
->cb_misc_state
.multiwrite
!= multiwrite
) {
1240 rctx
->cb_misc_state
.multiwrite
= multiwrite
;
1241 rctx
->cb_misc_state
.atom
.dirty
= true;
1245 if (rctx
->b
.chip_class
>= EVERGREEN
) {
1246 evergreen_update_db_shader_control(rctx
);
1248 r600_update_db_shader_control(rctx
);
1251 if (unlikely(!ps_dirty
&& rctx
->ps_shader
&& rctx
->rasterizer
&&
1252 ((rctx
->rasterizer
->sprite_coord_enable
!= rctx
->ps_shader
->current
->sprite_coord_enable
) ||
1253 (rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
)))) {
1255 if (rctx
->b
.chip_class
>= EVERGREEN
)
1256 evergreen_update_ps_state(ctx
, rctx
->ps_shader
->current
);
1258 r600_update_ps_state(ctx
, rctx
->ps_shader
->current
);
1261 update_shader_atom(ctx
, &rctx
->pixel_shader
, rctx
->ps_shader
->current
);
1264 /* on R600 we stuff masks + txq info into one constant buffer */
1265 /* on evergreen we only need a txq info one */
1266 if (rctx
->b
.chip_class
< EVERGREEN
) {
1267 if (rctx
->ps_shader
&& rctx
->ps_shader
->current
->shader
.uses_tex_buffers
)
1268 r600_setup_buffer_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1269 if (rctx
->vs_shader
&& rctx
->vs_shader
->current
->shader
.uses_tex_buffers
)
1270 r600_setup_buffer_constants(rctx
, PIPE_SHADER_VERTEX
);
1271 if (rctx
->gs_shader
&& rctx
->gs_shader
->current
->shader
.uses_tex_buffers
)
1272 r600_setup_buffer_constants(rctx
, PIPE_SHADER_GEOMETRY
);
1274 if (rctx
->ps_shader
&& rctx
->ps_shader
->current
->shader
.uses_tex_buffers
)
1275 eg_setup_buffer_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1276 if (rctx
->vs_shader
&& rctx
->vs_shader
->current
->shader
.uses_tex_buffers
)
1277 eg_setup_buffer_constants(rctx
, PIPE_SHADER_VERTEX
);
1278 if (rctx
->gs_shader
&& rctx
->gs_shader
->current
->shader
.uses_tex_buffers
)
1279 eg_setup_buffer_constants(rctx
, PIPE_SHADER_GEOMETRY
);
1283 if (rctx
->ps_shader
&& rctx
->ps_shader
->current
->shader
.has_txq_cube_array_z_comp
)
1284 r600_setup_txq_cube_array_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1285 if (rctx
->vs_shader
&& rctx
->vs_shader
->current
->shader
.has_txq_cube_array_z_comp
)
1286 r600_setup_txq_cube_array_constants(rctx
, PIPE_SHADER_VERTEX
);
1287 if (rctx
->gs_shader
&& rctx
->gs_shader
->current
->shader
.has_txq_cube_array_z_comp
)
1288 r600_setup_txq_cube_array_constants(rctx
, PIPE_SHADER_GEOMETRY
);
1290 if (rctx
->b
.chip_class
< EVERGREEN
&& rctx
->ps_shader
&& rctx
->vs_shader
) {
1291 if (!r600_adjust_gprs(rctx
)) {
1292 /* discard rendering */
1297 blend_disable
= (rctx
->dual_src_blend
&&
1298 rctx
->ps_shader
->current
->nr_ps_color_outputs
< 2);
1300 if (blend_disable
!= rctx
->force_blend_disable
) {
1301 rctx
->force_blend_disable
= blend_disable
;
1302 r600_bind_blend_state_internal(rctx
,
1303 rctx
->blend_state
.cso
,
1310 void r600_emit_clip_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1312 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1313 struct r600_clip_misc_state
*state
= &rctx
->clip_misc_state
;
1315 r600_write_context_reg(cs
, R_028810_PA_CL_CLIP_CNTL
,
1316 state
->pa_cl_clip_cntl
|
1317 (state
->clip_dist_write
? 0 : state
->clip_plane_enable
& 0x3F) |
1318 S_028810_CLIP_DISABLE(state
->clip_disable
));
1319 r600_write_context_reg(cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
1320 state
->pa_cl_vs_out_cntl
|
1321 (state
->clip_plane_enable
& state
->clip_dist_write
));
1324 static void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*dinfo
)
1326 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1327 struct pipe_draw_info info
= *dinfo
;
1328 struct pipe_index_buffer ib
= {};
1330 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1332 if (!info
.count
&& (info
.indexed
|| !info
.count_from_stream_output
)) {
1336 if (!rctx
->vs_shader
|| !rctx
->ps_shader
) {
1341 /* make sure that the gfx ring is only one active */
1342 if (rctx
->b
.rings
.dma
.cs
&& rctx
->b
.rings
.dma
.cs
->cdw
) {
1343 rctx
->b
.rings
.dma
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
1346 if (!r600_update_derived_state(rctx
)) {
1347 /* useless to render because current rendering command
1354 /* Initialize the index buffer struct. */
1355 pipe_resource_reference(&ib
.buffer
, rctx
->index_buffer
.buffer
);
1356 ib
.user_buffer
= rctx
->index_buffer
.user_buffer
;
1357 ib
.index_size
= rctx
->index_buffer
.index_size
;
1358 ib
.offset
= rctx
->index_buffer
.offset
+ info
.start
* ib
.index_size
;
1360 /* Translate 8-bit indices to 16-bit. */
1361 if (ib
.index_size
== 1) {
1362 struct pipe_resource
*out_buffer
= NULL
;
1363 unsigned out_offset
;
1366 u_upload_alloc(rctx
->b
.uploader
, 0, info
.count
* 2,
1367 &out_offset
, &out_buffer
, &ptr
);
1369 util_shorten_ubyte_elts_to_userptr(
1370 &rctx
->b
.b
, &ib
, 0, ib
.offset
, info
.count
, ptr
);
1372 pipe_resource_reference(&ib
.buffer
, NULL
);
1373 ib
.user_buffer
= NULL
;
1374 ib
.buffer
= out_buffer
;
1375 ib
.offset
= out_offset
;
1379 /* Upload the index buffer.
1380 * The upload is skipped for small index counts on little-endian machines
1381 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
1382 * Note: Instanced rendering in combination with immediate indices hangs. */
1383 if (ib
.user_buffer
&& (R600_BIG_ENDIAN
|| info
.instance_count
> 1 ||
1384 info
.count
*ib
.index_size
> 20)) {
1385 u_upload_data(rctx
->b
.uploader
, 0, info
.count
* ib
.index_size
,
1386 ib
.user_buffer
, &ib
.offset
, &ib
.buffer
);
1387 ib
.user_buffer
= NULL
;
1390 info
.index_bias
= info
.start
;
1393 /* Set the index offset and primitive restart. */
1394 if (rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
!= info
.primitive_restart
||
1395 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
!= info
.restart_index
||
1396 rctx
->vgt_state
.vgt_indx_offset
!= info
.index_bias
) {
1397 rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
= info
.primitive_restart
;
1398 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
= info
.restart_index
;
1399 rctx
->vgt_state
.vgt_indx_offset
= info
.index_bias
;
1400 rctx
->vgt_state
.atom
.dirty
= true;
1403 /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
1404 if (rctx
->b
.chip_class
== R600
) {
1405 rctx
->b
.flags
|= R600_CONTEXT_PS_PARTIAL_FLUSH
;
1406 rctx
->cb_misc_state
.atom
.dirty
= true;
1410 r600_need_cs_space(rctx
, ib
.user_buffer
? 5 : 0, TRUE
);
1411 r600_flush_emit(rctx
);
1413 for (i
= 0; i
< R600_NUM_ATOMS
; i
++) {
1414 if (rctx
->atoms
[i
] == NULL
|| !rctx
->atoms
[i
]->dirty
) {
1417 r600_emit_atom(rctx
, rctx
->atoms
[i
]);
1420 /* On R6xx, CULL_FRONT=1 culls all points, lines, and rectangles,
1421 * even though it should have no effect on those. */
1422 if (rctx
->b
.chip_class
== R600
&& rctx
->rasterizer
) {
1423 unsigned su_sc_mode_cntl
= rctx
->rasterizer
->pa_su_sc_mode_cntl
;
1424 unsigned prim
= info
.mode
;
1426 if (rctx
->gs_shader
) {
1427 prim
= rctx
->gs_shader
->current
->shader
.gs_output_prim
;
1429 prim
= r600_conv_prim_to_gs_out(prim
); /* decrease the number of types to 3 */
1431 if (prim
== V_028A6C_OUTPRIM_TYPE_POINTLIST
||
1432 prim
== V_028A6C_OUTPRIM_TYPE_LINESTRIP
||
1433 info
.mode
== R600_PRIM_RECTANGLE_LIST
) {
1434 su_sc_mode_cntl
&= C_028814_CULL_FRONT
;
1436 r600_write_context_reg(cs
, R_028814_PA_SU_SC_MODE_CNTL
, su_sc_mode_cntl
);
1439 /* Update start instance. */
1440 if (rctx
->last_start_instance
!= info
.start_instance
) {
1441 r600_write_ctl_const(cs
, R_03CFF4_SQ_VTX_START_INST_LOC
, info
.start_instance
);
1442 rctx
->last_start_instance
= info
.start_instance
;
1445 /* Update the primitive type. */
1446 if (rctx
->last_primitive_type
!= info
.mode
) {
1447 unsigned ls_mask
= 0;
1449 if (info
.mode
== PIPE_PRIM_LINES
)
1451 else if (info
.mode
== PIPE_PRIM_LINE_STRIP
||
1452 info
.mode
== PIPE_PRIM_LINE_LOOP
)
1455 r600_write_context_reg(cs
, R_028A0C_PA_SC_LINE_STIPPLE
,
1456 S_028A0C_AUTO_RESET_CNTL(ls_mask
) |
1457 (rctx
->rasterizer
? rctx
->rasterizer
->pa_sc_line_stipple
: 0));
1458 r600_write_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
,
1459 r600_conv_pipe_prim(info
.mode
));
1461 rctx
->last_primitive_type
= info
.mode
;
1465 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NUM_INSTANCES
, 0, rctx
->b
.predicate_drawing
);
1466 cs
->buf
[cs
->cdw
++] = info
.instance_count
;
1468 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_INDEX_TYPE
, 0, rctx
->b
.predicate_drawing
);
1469 cs
->buf
[cs
->cdw
++] = ib
.index_size
== 4 ?
1470 (VGT_INDEX_32
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_32_BIT
: 0)) :
1471 (VGT_INDEX_16
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_16_BIT
: 0));
1473 if (ib
.user_buffer
) {
1474 unsigned size_bytes
= info
.count
*ib
.index_size
;
1475 unsigned size_dw
= align(size_bytes
, 4) / 4;
1476 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX_IMMD
, 1 + size_dw
, rctx
->b
.predicate_drawing
);
1477 cs
->buf
[cs
->cdw
++] = info
.count
;
1478 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_IMMEDIATE
;
1479 memcpy(cs
->buf
+cs
->cdw
, ib
.user_buffer
, size_bytes
);
1482 uint64_t va
= r600_resource(ib
.buffer
)->gpu_address
+ ib
.offset
;
1483 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX
, 3, rctx
->b
.predicate_drawing
);
1484 cs
->buf
[cs
->cdw
++] = va
;
1485 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFF;
1486 cs
->buf
[cs
->cdw
++] = info
.count
;
1487 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_DMA
;
1488 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, rctx
->b
.predicate_drawing
);
1489 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
,
1490 (struct r600_resource
*)ib
.buffer
,
1491 RADEON_USAGE_READ
, RADEON_PRIO_MIN
);
1494 if (info
.count_from_stream_output
) {
1495 struct r600_so_target
*t
= (struct r600_so_target
*)info
.count_from_stream_output
;
1496 uint64_t va
= t
->buf_filled_size
->gpu_address
+ t
->buf_filled_size_offset
;
1498 r600_write_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
, t
->stride_in_dw
);
1500 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_COPY_DW
, 4, 0);
1501 cs
->buf
[cs
->cdw
++] = COPY_DW_SRC_IS_MEM
| COPY_DW_DST_IS_REG
;
1502 cs
->buf
[cs
->cdw
++] = va
& 0xFFFFFFFFUL
; /* src address lo */
1503 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFFUL
; /* src address hi */
1504 cs
->buf
[cs
->cdw
++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2; /* dst register */
1505 cs
->buf
[cs
->cdw
++] = 0; /* unused */
1507 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
1508 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
,
1509 t
->buf_filled_size
, RADEON_USAGE_READ
,
1513 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX_AUTO
, 1, rctx
->b
.predicate_drawing
);
1514 cs
->buf
[cs
->cdw
++] = info
.count
;
1515 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
1516 (info
.count_from_stream_output
? S_0287F0_USE_OPAQUE(1) : 0);
1519 if (rctx
->screen
->b
.trace_bo
) {
1520 r600_trace_emit(rctx
);
1523 /* Set the depth buffer as dirty. */
1524 if (rctx
->framebuffer
.state
.zsbuf
) {
1525 struct pipe_surface
*surf
= rctx
->framebuffer
.state
.zsbuf
;
1526 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
1528 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1530 if (rctx
->framebuffer
.compressed_cb_mask
) {
1531 struct pipe_surface
*surf
;
1532 struct r600_texture
*rtex
;
1533 unsigned mask
= rctx
->framebuffer
.compressed_cb_mask
;
1536 unsigned i
= u_bit_scan(&mask
);
1537 surf
= rctx
->framebuffer
.state
.cbufs
[i
];
1538 rtex
= (struct r600_texture
*)surf
->texture
;
1540 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1545 pipe_resource_reference(&ib
.buffer
, NULL
);
1546 rctx
->b
.num_draw_calls
++;
1549 void r600_draw_rectangle(struct blitter_context
*blitter
,
1550 int x1
, int y1
, int x2
, int y2
, float depth
,
1551 enum blitter_attrib_type type
, const union pipe_color_union
*attrib
)
1553 struct r600_context
*rctx
= (struct r600_context
*)util_blitter_get_pipe(blitter
);
1554 struct pipe_viewport_state viewport
;
1555 struct pipe_resource
*buf
= NULL
;
1556 unsigned offset
= 0;
1559 if (type
== UTIL_BLITTER_ATTRIB_TEXCOORD
) {
1560 util_blitter_draw_rectangle(blitter
, x1
, y1
, x2
, y2
, depth
, type
, attrib
);
1564 /* Some operations (like color resolve on r6xx) don't work
1565 * with the conventional primitive types.
1566 * One that works is PT_RECTLIST, which we use here. */
1568 /* setup viewport */
1569 viewport
.scale
[0] = 1.0f
;
1570 viewport
.scale
[1] = 1.0f
;
1571 viewport
.scale
[2] = 1.0f
;
1572 viewport
.scale
[3] = 1.0f
;
1573 viewport
.translate
[0] = 0.0f
;
1574 viewport
.translate
[1] = 0.0f
;
1575 viewport
.translate
[2] = 0.0f
;
1576 viewport
.translate
[3] = 0.0f
;
1577 rctx
->b
.b
.set_viewport_states(&rctx
->b
.b
, 0, 1, &viewport
);
1579 /* Upload vertices. The hw rectangle has only 3 vertices,
1580 * I guess the 4th one is derived from the first 3.
1581 * The vertex specification should match u_blitter's vertex element state. */
1582 u_upload_alloc(rctx
->b
.uploader
, 0, sizeof(float) * 24, &offset
, &buf
, (void**)&vb
);
1599 memcpy(vb
+4, attrib
->f
, sizeof(float)*4);
1600 memcpy(vb
+12, attrib
->f
, sizeof(float)*4);
1601 memcpy(vb
+20, attrib
->f
, sizeof(float)*4);
1605 util_draw_vertex_buffer(&rctx
->b
.b
, NULL
, buf
, rctx
->blitter
->vb_slot
, offset
,
1606 R600_PRIM_RECTANGLE_LIST
, 3, 2);
1607 pipe_resource_reference(&buf
, NULL
);
1610 uint32_t r600_translate_stencil_op(int s_op
)
1613 case PIPE_STENCIL_OP_KEEP
:
1614 return V_028800_STENCIL_KEEP
;
1615 case PIPE_STENCIL_OP_ZERO
:
1616 return V_028800_STENCIL_ZERO
;
1617 case PIPE_STENCIL_OP_REPLACE
:
1618 return V_028800_STENCIL_REPLACE
;
1619 case PIPE_STENCIL_OP_INCR
:
1620 return V_028800_STENCIL_INCR
;
1621 case PIPE_STENCIL_OP_DECR
:
1622 return V_028800_STENCIL_DECR
;
1623 case PIPE_STENCIL_OP_INCR_WRAP
:
1624 return V_028800_STENCIL_INCR_WRAP
;
1625 case PIPE_STENCIL_OP_DECR_WRAP
:
1626 return V_028800_STENCIL_DECR_WRAP
;
1627 case PIPE_STENCIL_OP_INVERT
:
1628 return V_028800_STENCIL_INVERT
;
1630 R600_ERR("Unknown stencil op %d", s_op
);
1637 uint32_t r600_translate_fill(uint32_t func
)
1640 case PIPE_POLYGON_MODE_FILL
:
1642 case PIPE_POLYGON_MODE_LINE
:
1644 case PIPE_POLYGON_MODE_POINT
:
1652 unsigned r600_tex_wrap(unsigned wrap
)
1656 case PIPE_TEX_WRAP_REPEAT
:
1657 return V_03C000_SQ_TEX_WRAP
;
1658 case PIPE_TEX_WRAP_CLAMP
:
1659 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER
;
1660 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1661 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL
;
1662 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1663 return V_03C000_SQ_TEX_CLAMP_BORDER
;
1664 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1665 return V_03C000_SQ_TEX_MIRROR
;
1666 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1667 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1668 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1669 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1670 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1671 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER
;
1675 unsigned r600_tex_filter(unsigned filter
)
1679 case PIPE_TEX_FILTER_NEAREST
:
1680 return V_03C000_SQ_TEX_XY_FILTER_POINT
;
1681 case PIPE_TEX_FILTER_LINEAR
:
1682 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR
;
1686 unsigned r600_tex_mipfilter(unsigned filter
)
1689 case PIPE_TEX_MIPFILTER_NEAREST
:
1690 return V_03C000_SQ_TEX_Z_FILTER_POINT
;
1691 case PIPE_TEX_MIPFILTER_LINEAR
:
1692 return V_03C000_SQ_TEX_Z_FILTER_LINEAR
;
1694 case PIPE_TEX_MIPFILTER_NONE
:
1695 return V_03C000_SQ_TEX_Z_FILTER_NONE
;
1699 unsigned r600_tex_compare(unsigned compare
)
1703 case PIPE_FUNC_NEVER
:
1704 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER
;
1705 case PIPE_FUNC_LESS
:
1706 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS
;
1707 case PIPE_FUNC_EQUAL
:
1708 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1709 case PIPE_FUNC_LEQUAL
:
1710 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1711 case PIPE_FUNC_GREATER
:
1712 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER
;
1713 case PIPE_FUNC_NOTEQUAL
:
1714 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1715 case PIPE_FUNC_GEQUAL
:
1716 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1717 case PIPE_FUNC_ALWAYS
:
1718 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1722 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
1724 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
1725 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
1727 (wrap
== PIPE_TEX_WRAP_CLAMP
||
1728 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
1731 bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
)
1733 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
1734 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
1736 return (state
->border_color
.ui
[0] || state
->border_color
.ui
[1] ||
1737 state
->border_color
.ui
[2] || state
->border_color
.ui
[3]) &&
1738 (wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) ||
1739 wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) ||
1740 wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
));
1743 void r600_emit_shader(struct r600_context
*rctx
, struct r600_atom
*a
)
1746 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1747 struct r600_pipe_shader
*shader
= ((struct r600_shader_state
*)a
)->shader
;
1752 r600_emit_command_buffer(cs
, &shader
->command_buffer
);
1753 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1754 radeon_emit(cs
, r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, shader
->bo
,
1755 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_DATA
));
1758 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
1759 const unsigned char *swizzle_view
,
1763 unsigned char swizzle
[4];
1764 unsigned result
= 0;
1765 const uint32_t tex_swizzle_shift
[4] = {
1768 const uint32_t vtx_swizzle_shift
[4] = {
1771 const uint32_t swizzle_bit
[4] = {
1774 const uint32_t *swizzle_shift
= tex_swizzle_shift
;
1777 swizzle_shift
= vtx_swizzle_shift
;
1780 util_format_compose_swizzles(swizzle_format
, swizzle_view
, swizzle
);
1782 memcpy(swizzle
, swizzle_format
, 4);
1786 for (i
= 0; i
< 4; i
++) {
1787 switch (swizzle
[i
]) {
1788 case UTIL_FORMAT_SWIZZLE_Y
:
1789 result
|= swizzle_bit
[1] << swizzle_shift
[i
];
1791 case UTIL_FORMAT_SWIZZLE_Z
:
1792 result
|= swizzle_bit
[2] << swizzle_shift
[i
];
1794 case UTIL_FORMAT_SWIZZLE_W
:
1795 result
|= swizzle_bit
[3] << swizzle_shift
[i
];
1797 case UTIL_FORMAT_SWIZZLE_0
:
1798 result
|= V_038010_SQ_SEL_0
<< swizzle_shift
[i
];
1800 case UTIL_FORMAT_SWIZZLE_1
:
1801 result
|= V_038010_SQ_SEL_1
<< swizzle_shift
[i
];
1803 default: /* UTIL_FORMAT_SWIZZLE_X */
1804 result
|= swizzle_bit
[0] << swizzle_shift
[i
];
1810 /* texture format translate */
1811 uint32_t r600_translate_texformat(struct pipe_screen
*screen
,
1812 enum pipe_format format
,
1813 const unsigned char *swizzle_view
,
1814 uint32_t *word4_p
, uint32_t *yuv_format_p
)
1816 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
1817 uint32_t result
= 0, word4
= 0, yuv_format
= 0;
1818 const struct util_format_description
*desc
;
1819 boolean uniform
= TRUE
;
1820 bool enable_s3tc
= rscreen
->b
.info
.drm_minor
>= 9;
1821 bool is_srgb_valid
= FALSE
;
1822 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
1823 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
1826 const uint32_t sign_bit
[4] = {
1827 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED
),
1828 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED
),
1829 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED
),
1830 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED
)
1832 desc
= util_format_description(format
);
1834 /* Depth and stencil swizzling is handled separately. */
1835 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
) {
1836 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
, FALSE
);
1839 /* Colorspace (return non-RGB formats directly). */
1840 switch (desc
->colorspace
) {
1841 /* Depth stencil formats */
1842 case UTIL_FORMAT_COLORSPACE_ZS
:
1844 /* Depth sampler formats. */
1845 case PIPE_FORMAT_Z16_UNORM
:
1846 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1849 case PIPE_FORMAT_Z24X8_UNORM
:
1850 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1851 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1854 case PIPE_FORMAT_X8Z24_UNORM
:
1855 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1856 if (rscreen
->b
.chip_class
< EVERGREEN
)
1858 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
1861 case PIPE_FORMAT_Z32_FLOAT
:
1862 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1863 result
= FMT_32_FLOAT
;
1865 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1866 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1867 result
= FMT_X24_8_32_FLOAT
;
1869 /* Stencil sampler formats. */
1870 case PIPE_FORMAT_S8_UINT
:
1871 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1872 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1875 case PIPE_FORMAT_X24S8_UINT
:
1876 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1877 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
1880 case PIPE_FORMAT_S8X24_UINT
:
1881 if (rscreen
->b
.chip_class
< EVERGREEN
)
1883 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1884 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1887 case PIPE_FORMAT_X32_S8X24_UINT
:
1888 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1889 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
1890 result
= FMT_X24_8_32_FLOAT
;
1896 case UTIL_FORMAT_COLORSPACE_YUV
:
1897 yuv_format
|= (1 << 30);
1899 case PIPE_FORMAT_UYVY
:
1900 case PIPE_FORMAT_YUYV
:
1904 goto out_unknown
; /* XXX */
1906 case UTIL_FORMAT_COLORSPACE_SRGB
:
1907 word4
|= S_038010_FORCE_DEGAMMA(1);
1914 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1919 case PIPE_FORMAT_RGTC1_SNORM
:
1920 case PIPE_FORMAT_LATC1_SNORM
:
1921 word4
|= sign_bit
[0];
1922 case PIPE_FORMAT_RGTC1_UNORM
:
1923 case PIPE_FORMAT_LATC1_UNORM
:
1926 case PIPE_FORMAT_RGTC2_SNORM
:
1927 case PIPE_FORMAT_LATC2_SNORM
:
1928 word4
|= sign_bit
[0] | sign_bit
[1];
1929 case PIPE_FORMAT_RGTC2_UNORM
:
1930 case PIPE_FORMAT_LATC2_UNORM
:
1938 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1943 if (!util_format_s3tc_enabled
) {
1948 case PIPE_FORMAT_DXT1_RGB
:
1949 case PIPE_FORMAT_DXT1_RGBA
:
1950 case PIPE_FORMAT_DXT1_SRGB
:
1951 case PIPE_FORMAT_DXT1_SRGBA
:
1953 is_srgb_valid
= TRUE
;
1955 case PIPE_FORMAT_DXT3_RGBA
:
1956 case PIPE_FORMAT_DXT3_SRGBA
:
1958 is_srgb_valid
= TRUE
;
1960 case PIPE_FORMAT_DXT5_RGBA
:
1961 case PIPE_FORMAT_DXT5_SRGBA
:
1963 is_srgb_valid
= TRUE
;
1970 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
1972 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
1973 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
1976 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
1977 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
1985 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1986 result
= FMT_5_9_9_9_SHAREDEXP
;
1988 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1989 result
= FMT_10_11_11_FLOAT
;
1994 for (i
= 0; i
< desc
->nr_channels
; i
++) {
1995 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1996 word4
|= sign_bit
[i
];
2000 /* R8G8Bx_SNORM - XXX CxV8U8 */
2002 /* See whether the components are of the same size. */
2003 for (i
= 1; i
< desc
->nr_channels
; i
++) {
2004 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
2007 /* Non-uniform formats. */
2009 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
2010 desc
->channel
[0].pure_integer
)
2011 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2012 switch(desc
->nr_channels
) {
2014 if (desc
->channel
[0].size
== 5 &&
2015 desc
->channel
[1].size
== 6 &&
2016 desc
->channel
[2].size
== 5) {
2022 if (desc
->channel
[0].size
== 5 &&
2023 desc
->channel
[1].size
== 5 &&
2024 desc
->channel
[2].size
== 5 &&
2025 desc
->channel
[3].size
== 1) {
2026 result
= FMT_1_5_5_5
;
2029 if (desc
->channel
[0].size
== 10 &&
2030 desc
->channel
[1].size
== 10 &&
2031 desc
->channel
[2].size
== 10 &&
2032 desc
->channel
[3].size
== 2) {
2033 result
= FMT_2_10_10_10
;
2041 /* Find the first non-VOID channel. */
2042 for (i
= 0; i
< 4; i
++) {
2043 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2051 /* uniform formats */
2052 switch (desc
->channel
[i
].type
) {
2053 case UTIL_FORMAT_TYPE_UNSIGNED
:
2054 case UTIL_FORMAT_TYPE_SIGNED
:
2056 if (!desc
->channel
[i
].normalized
&&
2057 desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
) {
2061 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
2062 desc
->channel
[i
].pure_integer
)
2063 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2065 switch (desc
->channel
[i
].size
) {
2067 switch (desc
->nr_channels
) {
2072 result
= FMT_4_4_4_4
;
2077 switch (desc
->nr_channels
) {
2085 result
= FMT_8_8_8_8
;
2086 is_srgb_valid
= TRUE
;
2091 switch (desc
->nr_channels
) {
2099 result
= FMT_16_16_16_16
;
2104 switch (desc
->nr_channels
) {
2112 result
= FMT_32_32_32_32
;
2118 case UTIL_FORMAT_TYPE_FLOAT
:
2119 switch (desc
->channel
[i
].size
) {
2121 switch (desc
->nr_channels
) {
2123 result
= FMT_16_FLOAT
;
2126 result
= FMT_16_16_FLOAT
;
2129 result
= FMT_16_16_16_16_FLOAT
;
2134 switch (desc
->nr_channels
) {
2136 result
= FMT_32_FLOAT
;
2139 result
= FMT_32_32_FLOAT
;
2142 result
= FMT_32_32_32_32_FLOAT
;
2151 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
&& !is_srgb_valid
)
2156 *yuv_format_p
= yuv_format
;
2159 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
2163 uint32_t r600_translate_colorformat(enum chip_class chip
, enum pipe_format format
)
2165 const struct util_format_description
*desc
= util_format_description(format
);
2166 int channel
= util_format_get_first_non_void_channel(format
);
2169 #define HAS_SIZE(x,y,z,w) \
2170 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
2171 desc->channel[2].size == (z) && desc->channel[3].size == (w))
2173 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2174 return V_0280A0_COLOR_10_11_11_FLOAT
;
2176 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
||
2180 is_float
= desc
->channel
[channel
].type
== UTIL_FORMAT_TYPE_FLOAT
;
2182 switch (desc
->nr_channels
) {
2184 switch (desc
->channel
[0].size
) {
2186 return V_0280A0_COLOR_8
;
2189 return V_0280A0_COLOR_16_FLOAT
;
2191 return V_0280A0_COLOR_16
;
2194 return V_0280A0_COLOR_32_FLOAT
;
2196 return V_0280A0_COLOR_32
;
2200 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
2201 switch (desc
->channel
[0].size
) {
2204 return V_0280A0_COLOR_4_4
;
2206 return ~0U; /* removed on Evergreen */
2208 return V_0280A0_COLOR_8_8
;
2211 return V_0280A0_COLOR_16_16_FLOAT
;
2213 return V_0280A0_COLOR_16_16
;
2216 return V_0280A0_COLOR_32_32_FLOAT
;
2218 return V_0280A0_COLOR_32_32
;
2220 } else if (HAS_SIZE(8,24,0,0)) {
2221 return V_0280A0_COLOR_24_8
;
2222 } else if (HAS_SIZE(24,8,0,0)) {
2223 return V_0280A0_COLOR_8_24
;
2227 if (HAS_SIZE(5,6,5,0)) {
2228 return V_0280A0_COLOR_5_6_5
;
2229 } else if (HAS_SIZE(32,8,24,0)) {
2230 return V_0280A0_COLOR_X24_8_32_FLOAT
;
2234 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
2235 desc
->channel
[0].size
== desc
->channel
[2].size
&&
2236 desc
->channel
[0].size
== desc
->channel
[3].size
) {
2237 switch (desc
->channel
[0].size
) {
2239 return V_0280A0_COLOR_4_4_4_4
;
2241 return V_0280A0_COLOR_8_8_8_8
;
2244 return V_0280A0_COLOR_16_16_16_16_FLOAT
;
2246 return V_0280A0_COLOR_16_16_16_16
;
2249 return V_0280A0_COLOR_32_32_32_32_FLOAT
;
2251 return V_0280A0_COLOR_32_32_32_32
;
2253 } else if (HAS_SIZE(5,5,5,1)) {
2254 return V_0280A0_COLOR_1_5_5_5
;
2255 } else if (HAS_SIZE(10,10,10,2)) {
2256 return V_0280A0_COLOR_2_10_10_10
;
2263 uint32_t r600_colorformat_endian_swap(uint32_t colorformat
)
2265 if (R600_BIG_ENDIAN
) {
2266 switch(colorformat
) {
2267 /* 8-bit buffers. */
2268 case V_0280A0_COLOR_4_4
:
2269 case V_0280A0_COLOR_8
:
2272 /* 16-bit buffers. */
2273 case V_0280A0_COLOR_5_6_5
:
2274 case V_0280A0_COLOR_1_5_5_5
:
2275 case V_0280A0_COLOR_4_4_4_4
:
2276 case V_0280A0_COLOR_16
:
2277 case V_0280A0_COLOR_8_8
:
2278 return ENDIAN_8IN16
;
2280 /* 32-bit buffers. */
2281 case V_0280A0_COLOR_8_8_8_8
:
2282 case V_0280A0_COLOR_2_10_10_10
:
2283 case V_0280A0_COLOR_8_24
:
2284 case V_0280A0_COLOR_24_8
:
2285 case V_0280A0_COLOR_32_FLOAT
:
2286 case V_0280A0_COLOR_16_16_FLOAT
:
2287 case V_0280A0_COLOR_16_16
:
2288 return ENDIAN_8IN32
;
2290 /* 64-bit buffers. */
2291 case V_0280A0_COLOR_16_16_16_16
:
2292 case V_0280A0_COLOR_16_16_16_16_FLOAT
:
2293 return ENDIAN_8IN16
;
2295 case V_0280A0_COLOR_32_32_FLOAT
:
2296 case V_0280A0_COLOR_32_32
:
2297 case V_0280A0_COLOR_X24_8_32_FLOAT
:
2298 return ENDIAN_8IN32
;
2300 /* 128-bit buffers. */
2301 case V_0280A0_COLOR_32_32_32_32_FLOAT
:
2302 case V_0280A0_COLOR_32_32_32_32
:
2303 return ENDIAN_8IN32
;
2305 return ENDIAN_NONE
; /* Unsupported. */
2312 static void r600_invalidate_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
)
2314 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2315 struct r600_resource
*rbuffer
= r600_resource(buf
);
2316 unsigned i
, shader
, mask
, alignment
= rbuffer
->buf
->alignment
;
2318 /* Reallocate the buffer in the same pipe_resource. */
2319 r600_init_resource(&rctx
->screen
->b
, rbuffer
, rbuffer
->b
.b
.width0
,
2322 /* We changed the buffer, now we need to bind it where the old one was bound. */
2323 /* Vertex buffers. */
2324 mask
= rctx
->vertex_buffer_state
.enabled_mask
;
2326 i
= u_bit_scan(&mask
);
2327 if (rctx
->vertex_buffer_state
.vb
[i
].buffer
== &rbuffer
->b
.b
) {
2328 rctx
->vertex_buffer_state
.dirty_mask
|= 1 << i
;
2329 r600_vertex_buffers_dirty(rctx
);
2332 /* Streamout buffers. */
2333 for (i
= 0; i
< rctx
->b
.streamout
.num_targets
; i
++) {
2334 if (rctx
->b
.streamout
.targets
[i
]->b
.buffer
== &rbuffer
->b
.b
) {
2335 if (rctx
->b
.streamout
.begin_emitted
) {
2336 r600_emit_streamout_end(&rctx
->b
);
2338 rctx
->b
.streamout
.append_bitmask
= rctx
->b
.streamout
.enabled_mask
;
2339 r600_streamout_buffers_dirty(&rctx
->b
);
2343 /* Constant buffers. */
2344 for (shader
= 0; shader
< PIPE_SHADER_TYPES
; shader
++) {
2345 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
2347 uint32_t mask
= state
->enabled_mask
;
2350 unsigned i
= u_bit_scan(&mask
);
2351 if (state
->cb
[i
].buffer
== &rbuffer
->b
.b
) {
2353 state
->dirty_mask
|= 1 << i
;
2357 r600_constant_buffers_dirty(rctx
, state
);
2361 /* XXX TODO: texture buffer objects */
2364 static void r600_set_occlusion_query_state(struct pipe_context
*ctx
, bool enable
)
2366 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2368 if (rctx
->db_misc_state
.occlusion_query_enabled
!= enable
) {
2369 rctx
->db_misc_state
.occlusion_query_enabled
= enable
;
2370 rctx
->db_misc_state
.atom
.dirty
= true;
2374 static void r600_need_gfx_cs_space(struct pipe_context
*ctx
, unsigned num_dw
,
2375 bool include_draw_vbo
)
2377 r600_need_cs_space((struct r600_context
*)ctx
, num_dw
, include_draw_vbo
);
2380 /* keep this at the end of this file, please */
2381 void r600_init_common_state_functions(struct r600_context
*rctx
)
2383 rctx
->b
.b
.create_fs_state
= r600_create_ps_state
;
2384 rctx
->b
.b
.create_vs_state
= r600_create_vs_state
;
2385 rctx
->b
.b
.create_gs_state
= r600_create_gs_state
;
2386 rctx
->b
.b
.create_vertex_elements_state
= r600_create_vertex_fetch_shader
;
2387 rctx
->b
.b
.bind_blend_state
= r600_bind_blend_state
;
2388 rctx
->b
.b
.bind_depth_stencil_alpha_state
= r600_bind_dsa_state
;
2389 rctx
->b
.b
.bind_sampler_states
= r600_bind_sampler_states
;
2390 rctx
->b
.b
.bind_fs_state
= r600_bind_ps_state
;
2391 rctx
->b
.b
.bind_rasterizer_state
= r600_bind_rs_state
;
2392 rctx
->b
.b
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
2393 rctx
->b
.b
.bind_vs_state
= r600_bind_vs_state
;
2394 rctx
->b
.b
.bind_gs_state
= r600_bind_gs_state
;
2395 rctx
->b
.b
.delete_blend_state
= r600_delete_blend_state
;
2396 rctx
->b
.b
.delete_depth_stencil_alpha_state
= r600_delete_dsa_state
;
2397 rctx
->b
.b
.delete_fs_state
= r600_delete_ps_state
;
2398 rctx
->b
.b
.delete_rasterizer_state
= r600_delete_rs_state
;
2399 rctx
->b
.b
.delete_sampler_state
= r600_delete_sampler_state
;
2400 rctx
->b
.b
.delete_vertex_elements_state
= r600_delete_vertex_elements
;
2401 rctx
->b
.b
.delete_vs_state
= r600_delete_vs_state
;
2402 rctx
->b
.b
.delete_gs_state
= r600_delete_gs_state
;
2403 rctx
->b
.b
.set_blend_color
= r600_set_blend_color
;
2404 rctx
->b
.b
.set_clip_state
= r600_set_clip_state
;
2405 rctx
->b
.b
.set_constant_buffer
= r600_set_constant_buffer
;
2406 rctx
->b
.b
.set_sample_mask
= r600_set_sample_mask
;
2407 rctx
->b
.b
.set_stencil_ref
= r600_set_pipe_stencil_ref
;
2408 rctx
->b
.b
.set_viewport_states
= r600_set_viewport_states
;
2409 rctx
->b
.b
.set_vertex_buffers
= r600_set_vertex_buffers
;
2410 rctx
->b
.b
.set_index_buffer
= r600_set_index_buffer
;
2411 rctx
->b
.b
.set_sampler_views
= r600_set_sampler_views
;
2412 rctx
->b
.b
.sampler_view_destroy
= r600_sampler_view_destroy
;
2413 rctx
->b
.b
.texture_barrier
= r600_texture_barrier
;
2414 rctx
->b
.b
.set_stream_output_targets
= r600_set_streamout_targets
;
2415 rctx
->b
.b
.draw_vbo
= r600_draw_vbo
;
2416 rctx
->b
.invalidate_buffer
= r600_invalidate_buffer
;
2417 rctx
->b
.set_occlusion_query_state
= r600_set_occlusion_query_state
;
2418 rctx
->b
.need_gfx_cs_space
= r600_need_gfx_cs_space
;
2421 void r600_trace_emit(struct r600_context
*rctx
)
2423 struct r600_screen
*rscreen
= rctx
->screen
;
2424 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
2428 va
= rscreen
->b
.trace_bo
->gpu_address
;
2429 reloc
= r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rscreen
->b
.trace_bo
,
2430 RADEON_USAGE_READWRITE
, RADEON_PRIO_MIN
);
2431 radeon_emit(cs
, PKT3(PKT3_MEM_WRITE
, 3, 0));
2432 radeon_emit(cs
, va
& 0xFFFFFFFFUL
);
2433 radeon_emit(cs
, (va
>> 32UL) & 0xFFUL
);
2434 radeon_emit(cs
, cs
->cdw
);
2435 radeon_emit(cs
, rscreen
->b
.cs_count
);
2436 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2437 radeon_emit(cs
, reloc
);