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r600g: if pixel shader is NULL, bind a dummy one
[mesa.git] / src / gallium / drivers / r600 / r600_state_common.c
1 /*
2 * Copyright 2010 Red Hat Inc.
3 * 2010 Jerome Glisse
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
26 */
27 #include "util/u_blitter.h"
28 #include "util/u_memory.h"
29 #include "util/u_format.h"
30 #include "pipebuffer/pb_buffer.h"
31 #include "pipe/p_shader_tokens.h"
32 #include "tgsi/tgsi_parse.h"
33 #include "r600_formats.h"
34 #include "r600_pipe.h"
35 #include "r600d.h"
36 #include "r600_hw_context_priv.h"
37
38 static void r600_emit_command_buffer(struct r600_context *rctx, struct r600_atom *atom)
39 {
40 struct radeon_winsys_cs *cs = rctx->cs;
41 struct r600_command_buffer *cb = (struct r600_command_buffer*)atom;
42
43 assert(cs->cdw + cb->atom.num_dw <= RADEON_MAX_CMDBUF_DWORDS);
44 memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->atom.num_dw);
45 cs->cdw += cb->atom.num_dw;
46 }
47
48 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags)
49 {
50 cb->atom.emit = r600_emit_command_buffer;
51 cb->atom.num_dw = 0;
52 cb->atom.flags = flags;
53 cb->buf = CALLOC(1, 4 * num_dw);
54 cb->max_num_dw = num_dw;
55 }
56
57 void r600_release_command_buffer(struct r600_command_buffer *cb)
58 {
59 FREE(cb->buf);
60 }
61
62 static void r600_emit_surface_sync(struct r600_context *rctx, struct r600_atom *atom)
63 {
64 struct radeon_winsys_cs *cs = rctx->cs;
65 struct r600_atom_surface_sync *a = (struct r600_atom_surface_sync*)atom;
66
67 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
68 cs->buf[cs->cdw++] = a->flush_flags; /* CP_COHER_CNTL */
69 cs->buf[cs->cdw++] = 0xffffffff; /* CP_COHER_SIZE */
70 cs->buf[cs->cdw++] = 0; /* CP_COHER_BASE */
71 cs->buf[cs->cdw++] = 0x0000000A; /* POLL_INTERVAL */
72
73 a->flush_flags = 0;
74 }
75
76 static void r600_emit_r6xx_flush_and_inv(struct r600_context *rctx, struct r600_atom *atom)
77 {
78 struct radeon_winsys_cs *cs = rctx->cs;
79 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
80 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
81 }
82
83 void r600_init_atom(struct r600_atom *atom,
84 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
85 unsigned num_dw, enum r600_atom_flags flags)
86 {
87 atom->emit = emit;
88 atom->num_dw = num_dw;
89 atom->flags = flags;
90 }
91
92 void r600_init_common_atoms(struct r600_context *rctx)
93 {
94 r600_init_atom(&rctx->atom_surface_sync.atom, r600_emit_surface_sync, 5, EMIT_EARLY);
95 r600_init_atom(&rctx->atom_r6xx_flush_and_inv, r600_emit_r6xx_flush_and_inv, 2, EMIT_EARLY);
96 }
97
98 unsigned r600_get_cb_flush_flags(struct r600_context *rctx)
99 {
100 unsigned flags = 0;
101
102 if (rctx->framebuffer.nr_cbufs) {
103 flags |= S_0085F0_CB_ACTION_ENA(1) |
104 (((1 << rctx->framebuffer.nr_cbufs) - 1) << S_0085F0_CB0_DEST_BASE_ENA_SHIFT);
105 }
106
107 /* Workaround for broken flushing on some R6xx chipsets. */
108 if (rctx->family == CHIP_RV670 ||
109 rctx->family == CHIP_RS780 ||
110 rctx->family == CHIP_RS880) {
111 flags |= S_0085F0_CB1_DEST_BASE_ENA(1) |
112 S_0085F0_DEST_BASE_0_ENA(1);
113 }
114 return flags;
115 }
116
117 void r600_texture_barrier(struct pipe_context *ctx)
118 {
119 struct r600_context *rctx = (struct r600_context *)ctx;
120
121 rctx->atom_surface_sync.flush_flags |= S_0085F0_TC_ACTION_ENA(1) | r600_get_cb_flush_flags(rctx);
122 r600_atom_dirty(rctx, &rctx->atom_surface_sync.atom);
123 }
124
125 static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
126 {
127 static const int prim_conv[] = {
128 V_008958_DI_PT_POINTLIST,
129 V_008958_DI_PT_LINELIST,
130 V_008958_DI_PT_LINELOOP,
131 V_008958_DI_PT_LINESTRIP,
132 V_008958_DI_PT_TRILIST,
133 V_008958_DI_PT_TRISTRIP,
134 V_008958_DI_PT_TRIFAN,
135 V_008958_DI_PT_QUADLIST,
136 V_008958_DI_PT_QUADSTRIP,
137 V_008958_DI_PT_POLYGON,
138 -1,
139 -1,
140 -1,
141 -1
142 };
143
144 *prim = prim_conv[pprim];
145 if (*prim == -1) {
146 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim);
147 return false;
148 }
149 return true;
150 }
151
152 /* common state between evergreen and r600 */
153 void r600_bind_blend_state(struct pipe_context *ctx, void *state)
154 {
155 struct r600_context *rctx = (struct r600_context *)ctx;
156 struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
157 struct r600_pipe_state *rstate;
158
159 if (state == NULL)
160 return;
161 rstate = &blend->rstate;
162 rctx->states[rstate->id] = rstate;
163 rctx->cb_target_mask = blend->cb_target_mask;
164
165 /* Replace every bit except MULTIWRITE_ENABLE. */
166 rctx->cb_color_control &= ~C_028808_MULTIWRITE_ENABLE;
167 rctx->cb_color_control |= blend->cb_color_control & C_028808_MULTIWRITE_ENABLE;
168
169 r600_context_pipe_state_set(rctx, rstate);
170 }
171
172 void r600_set_blend_color(struct pipe_context *ctx,
173 const struct pipe_blend_color *state)
174 {
175 struct r600_context *rctx = (struct r600_context *)ctx;
176 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
177
178 if (rstate == NULL)
179 return;
180
181 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
182 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), NULL, 0);
183 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), NULL, 0);
184 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), NULL, 0);
185 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), NULL, 0);
186
187 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
188 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
189 r600_context_pipe_state_set(rctx, rstate);
190 }
191
192 static void r600_set_stencil_ref(struct pipe_context *ctx,
193 const struct r600_stencil_ref *state)
194 {
195 struct r600_context *rctx = (struct r600_context *)ctx;
196 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
197
198 if (rstate == NULL)
199 return;
200
201 rstate->id = R600_PIPE_STATE_STENCIL_REF;
202 r600_pipe_state_add_reg(rstate,
203 R_028430_DB_STENCILREFMASK,
204 S_028430_STENCILREF(state->ref_value[0]) |
205 S_028430_STENCILMASK(state->valuemask[0]) |
206 S_028430_STENCILWRITEMASK(state->writemask[0]),
207 NULL, 0);
208 r600_pipe_state_add_reg(rstate,
209 R_028434_DB_STENCILREFMASK_BF,
210 S_028434_STENCILREF_BF(state->ref_value[1]) |
211 S_028434_STENCILMASK_BF(state->valuemask[1]) |
212 S_028434_STENCILWRITEMASK_BF(state->writemask[1]),
213 NULL, 0);
214
215 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
216 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
217 r600_context_pipe_state_set(rctx, rstate);
218 }
219
220 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
221 const struct pipe_stencil_ref *state)
222 {
223 struct r600_context *rctx = (struct r600_context *)ctx;
224 struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA];
225 struct r600_stencil_ref ref;
226
227 rctx->stencil_ref = *state;
228
229 if (!dsa)
230 return;
231
232 ref.ref_value[0] = state->ref_value[0];
233 ref.ref_value[1] = state->ref_value[1];
234 ref.valuemask[0] = dsa->valuemask[0];
235 ref.valuemask[1] = dsa->valuemask[1];
236 ref.writemask[0] = dsa->writemask[0];
237 ref.writemask[1] = dsa->writemask[1];
238
239 r600_set_stencil_ref(ctx, &ref);
240 }
241
242 void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
243 {
244 struct r600_context *rctx = (struct r600_context *)ctx;
245 struct r600_pipe_dsa *dsa = state;
246 struct r600_pipe_state *rstate;
247 struct r600_stencil_ref ref;
248
249 if (state == NULL)
250 return;
251 rstate = &dsa->rstate;
252 rctx->states[rstate->id] = rstate;
253 rctx->alpha_ref = dsa->alpha_ref;
254 rctx->alpha_ref_dirty = true;
255 r600_context_pipe_state_set(rctx, rstate);
256
257 ref.ref_value[0] = rctx->stencil_ref.ref_value[0];
258 ref.ref_value[1] = rctx->stencil_ref.ref_value[1];
259 ref.valuemask[0] = dsa->valuemask[0];
260 ref.valuemask[1] = dsa->valuemask[1];
261 ref.writemask[0] = dsa->writemask[0];
262 ref.writemask[1] = dsa->writemask[1];
263
264 r600_set_stencil_ref(ctx, &ref);
265
266 if (rctx->atom_db_misc_state.flush_depthstencil_enabled != dsa->is_flush) {
267 rctx->atom_db_misc_state.flush_depthstencil_enabled = dsa->is_flush;
268 r600_atom_dirty(rctx, &rctx->atom_db_misc_state.atom);
269 }
270 }
271
272 void r600_set_max_scissor(struct r600_context *rctx)
273 {
274 /* Set a scissor state such that it doesn't do anything. */
275 struct pipe_scissor_state scissor;
276 scissor.minx = 0;
277 scissor.miny = 0;
278 scissor.maxx = 8192;
279 scissor.maxy = 8192;
280
281 r600_set_scissor_state(rctx, &scissor);
282 }
283
284 void r600_bind_rs_state(struct pipe_context *ctx, void *state)
285 {
286 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
287 struct r600_context *rctx = (struct r600_context *)ctx;
288
289 if (state == NULL)
290 return;
291
292 rctx->sprite_coord_enable = rs->sprite_coord_enable;
293 rctx->two_side = rs->two_side;
294 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
295 rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
296
297 rctx->rasterizer = rs;
298
299 rctx->states[rs->rstate.id] = &rs->rstate;
300 r600_context_pipe_state_set(rctx, &rs->rstate);
301
302 if (rctx->chip_class >= EVERGREEN) {
303 evergreen_polygon_offset_update(rctx);
304 evergreen_set_rasterizer_discard(ctx, rs->rasterizer_discard);
305 } else {
306 r600_polygon_offset_update(rctx);
307 }
308
309 /* Workaround for a missing scissor enable on r600. */
310 if (rctx->chip_class == R600) {
311 if (rs->scissor_enable != rctx->scissor_enable) {
312 rctx->scissor_enable = rs->scissor_enable;
313
314 if (rs->scissor_enable) {
315 r600_set_scissor_state(rctx, &rctx->scissor_state);
316 } else {
317 r600_set_max_scissor(rctx);
318 }
319 }
320 }
321 }
322
323 void r600_delete_rs_state(struct pipe_context *ctx, void *state)
324 {
325 struct r600_context *rctx = (struct r600_context *)ctx;
326 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
327
328 if (rctx->rasterizer == rs) {
329 rctx->rasterizer = NULL;
330 }
331 if (rctx->states[rs->rstate.id] == &rs->rstate) {
332 rctx->states[rs->rstate.id] = NULL;
333 }
334 free(rs);
335 }
336
337 void r600_sampler_view_destroy(struct pipe_context *ctx,
338 struct pipe_sampler_view *state)
339 {
340 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
341
342 pipe_resource_reference(&state->texture, NULL);
343 FREE(resource);
344 }
345
346 void r600_delete_state(struct pipe_context *ctx, void *state)
347 {
348 struct r600_context *rctx = (struct r600_context *)ctx;
349 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
350
351 if (rctx->states[rstate->id] == rstate) {
352 rctx->states[rstate->id] = NULL;
353 }
354 for (int i = 0; i < rstate->nregs; i++) {
355 pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL);
356 }
357 free(rstate);
358 }
359
360 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
361 {
362 struct r600_context *rctx = (struct r600_context *)ctx;
363 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
364
365 rctx->vertex_elements = v;
366 if (v) {
367 r600_inval_shader_cache(rctx);
368 u_vbuf_bind_vertex_elements(rctx->vbuf_mgr, state,
369 v->vmgr_elements);
370
371 rctx->states[v->rstate.id] = &v->rstate;
372 r600_context_pipe_state_set(rctx, &v->rstate);
373 }
374 }
375
376 void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
377 {
378 struct r600_context *rctx = (struct r600_context *)ctx;
379 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
380
381 if (rctx->states[v->rstate.id] == &v->rstate) {
382 rctx->states[v->rstate.id] = NULL;
383 }
384 if (rctx->vertex_elements == state)
385 rctx->vertex_elements = NULL;
386
387 pipe_resource_reference((struct pipe_resource**)&v->fetch_shader, NULL);
388 u_vbuf_destroy_vertex_elements(rctx->vbuf_mgr, v->vmgr_elements);
389 FREE(state);
390 }
391
392
393 void r600_set_index_buffer(struct pipe_context *ctx,
394 const struct pipe_index_buffer *ib)
395 {
396 struct r600_context *rctx = (struct r600_context *)ctx;
397
398 u_vbuf_set_index_buffer(rctx->vbuf_mgr, ib);
399 }
400
401 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
402 const struct pipe_vertex_buffer *buffers)
403 {
404 struct r600_context *rctx = (struct r600_context *)ctx;
405 int i;
406
407 /* Zero states. */
408 for (i = 0; i < count; i++) {
409 if (!buffers[i].buffer) {
410 r600_context_pipe_state_set_fs_resource(rctx, NULL, i);
411 }
412 }
413 for (; i < rctx->vbuf_mgr->nr_real_vertex_buffers; i++) {
414 r600_context_pipe_state_set_fs_resource(rctx, NULL, i);
415 }
416
417 u_vbuf_set_vertex_buffers(rctx->vbuf_mgr, count, buffers);
418 }
419
420 void *r600_create_vertex_elements(struct pipe_context *ctx,
421 unsigned count,
422 const struct pipe_vertex_element *elements)
423 {
424 struct r600_context *rctx = (struct r600_context *)ctx;
425 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
426
427 assert(count < 32);
428 if (!v)
429 return NULL;
430
431 v->count = count;
432 v->vmgr_elements =
433 u_vbuf_create_vertex_elements(rctx->vbuf_mgr, count,
434 elements, v->elements);
435
436 if (r600_vertex_elements_build_fetch_shader(rctx, v)) {
437 FREE(v);
438 return NULL;
439 }
440
441 return v;
442 }
443
444 void *r600_create_shader_state(struct pipe_context *ctx,
445 const struct pipe_shader_state *state)
446 {
447 struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader);
448 int r;
449
450 shader->tokens = tgsi_dup_tokens(state->tokens);
451 shader->so = state->stream_output;
452
453 r = r600_pipe_shader_create(ctx, shader);
454 if (r) {
455 return NULL;
456 }
457 return shader;
458 }
459
460 void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
461 {
462 struct r600_context *rctx = (struct r600_context *)ctx;
463
464 if (!state) {
465 state = rctx->dummy_pixel_shader;
466 }
467
468 rctx->ps_shader = (struct r600_pipe_shader *)state;
469
470 r600_inval_shader_cache(rctx);
471 r600_context_pipe_state_set(rctx, &rctx->ps_shader->rstate);
472
473 rctx->cb_color_control &= C_028808_MULTIWRITE_ENABLE;
474 rctx->cb_color_control |= S_028808_MULTIWRITE_ENABLE(!!rctx->ps_shader->shader.fs_write_all);
475
476 if (rctx->ps_shader && rctx->vs_shader) {
477 r600_adjust_gprs(rctx);
478 }
479 }
480
481 void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
482 {
483 struct r600_context *rctx = (struct r600_context *)ctx;
484
485 rctx->vs_shader = (struct r600_pipe_shader *)state;
486 if (state) {
487 r600_inval_shader_cache(rctx);
488 r600_context_pipe_state_set(rctx, &rctx->vs_shader->rstate);
489 }
490 if (rctx->ps_shader && rctx->vs_shader) {
491 r600_adjust_gprs(rctx);
492 }
493 }
494
495 void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
496 {
497 struct r600_context *rctx = (struct r600_context *)ctx;
498 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
499
500 if (rctx->ps_shader == shader) {
501 rctx->ps_shader = NULL;
502 }
503
504 free(shader->tokens);
505 r600_pipe_shader_destroy(ctx, shader);
506 free(shader);
507 }
508
509 void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
510 {
511 struct r600_context *rctx = (struct r600_context *)ctx;
512 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
513
514 if (rctx->vs_shader == shader) {
515 rctx->vs_shader = NULL;
516 }
517
518 free(shader->tokens);
519 r600_pipe_shader_destroy(ctx, shader);
520 free(shader);
521 }
522
523 static void r600_update_alpha_ref(struct r600_context *rctx)
524 {
525 unsigned alpha_ref;
526 struct r600_pipe_state rstate;
527
528 alpha_ref = rctx->alpha_ref;
529 rstate.nregs = 0;
530 if (rctx->export_16bpc)
531 alpha_ref &= ~0x1FFF;
532 r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref, NULL, 0);
533
534 r600_context_pipe_state_set(rctx, &rstate);
535 rctx->alpha_ref_dirty = false;
536 }
537
538 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
539 struct pipe_resource *buffer)
540 {
541 struct r600_context *rctx = (struct r600_context *)ctx;
542 struct r600_resource *rbuffer = r600_resource(buffer);
543 struct r600_pipe_resource_state *rstate;
544 uint64_t va_offset;
545 uint32_t offset;
546
547 /* Note that the state tracker can unbind constant buffers by
548 * passing NULL here.
549 */
550 if (buffer == NULL) {
551 return;
552 }
553
554 r600_inval_shader_cache(rctx);
555
556 r600_upload_const_buffer(rctx, &rbuffer, &offset);
557 va_offset = r600_resource_va(ctx->screen, (void*)rbuffer);
558 va_offset += offset;
559 va_offset >>= 8;
560
561 switch (shader) {
562 case PIPE_SHADER_VERTEX:
563 rctx->vs_const_buffer.nregs = 0;
564 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
565 R_028180_ALU_CONST_BUFFER_SIZE_VS_0 + index * 4,
566 ALIGN_DIVUP(buffer->width0 >> 4, 16),
567 NULL, 0);
568 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
569 R_028980_ALU_CONST_CACHE_VS_0 + index * 4,
570 va_offset, rbuffer, RADEON_USAGE_READ);
571 r600_context_pipe_state_set(rctx, &rctx->vs_const_buffer);
572
573 rstate = &rctx->vs_const_buffer_resource[index];
574 if (!rstate->id) {
575 if (rctx->chip_class >= EVERGREEN) {
576 evergreen_pipe_init_buffer_resource(rctx, rstate);
577 } else {
578 r600_pipe_init_buffer_resource(rctx, rstate);
579 }
580 }
581
582 if (rctx->chip_class >= EVERGREEN) {
583 evergreen_pipe_mod_buffer_resource(ctx, rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
584 } else {
585 r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
586 }
587 r600_context_pipe_state_set_vs_resource(rctx, rstate, index);
588 break;
589 case PIPE_SHADER_FRAGMENT:
590 rctx->ps_const_buffer.nregs = 0;
591 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
592 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
593 ALIGN_DIVUP(buffer->width0 >> 4, 16),
594 NULL, 0);
595 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
596 R_028940_ALU_CONST_CACHE_PS_0,
597 va_offset, rbuffer, RADEON_USAGE_READ);
598 r600_context_pipe_state_set(rctx, &rctx->ps_const_buffer);
599
600 rstate = &rctx->ps_const_buffer_resource[index];
601 if (!rstate->id) {
602 if (rctx->chip_class >= EVERGREEN) {
603 evergreen_pipe_init_buffer_resource(rctx, rstate);
604 } else {
605 r600_pipe_init_buffer_resource(rctx, rstate);
606 }
607 }
608 if (rctx->chip_class >= EVERGREEN) {
609 evergreen_pipe_mod_buffer_resource(ctx, rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
610 } else {
611 r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
612 }
613 r600_context_pipe_state_set_ps_resource(rctx, rstate, index);
614 break;
615 default:
616 R600_ERR("unsupported %d\n", shader);
617 return;
618 }
619
620 if (buffer != &rbuffer->b.b.b)
621 pipe_resource_reference((struct pipe_resource**)&rbuffer, NULL);
622 }
623
624 struct pipe_stream_output_target *
625 r600_create_so_target(struct pipe_context *ctx,
626 struct pipe_resource *buffer,
627 unsigned buffer_offset,
628 unsigned buffer_size)
629 {
630 struct r600_context *rctx = (struct r600_context *)ctx;
631 struct r600_so_target *t;
632 void *ptr;
633
634 t = CALLOC_STRUCT(r600_so_target);
635 if (!t) {
636 return NULL;
637 }
638
639 t->b.reference.count = 1;
640 t->b.context = ctx;
641 pipe_resource_reference(&t->b.buffer, buffer);
642 t->b.buffer_offset = buffer_offset;
643 t->b.buffer_size = buffer_size;
644
645 t->filled_size = (struct r600_resource*)
646 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4);
647 ptr = rctx->ws->buffer_map(t->filled_size->buf, rctx->cs, PIPE_TRANSFER_WRITE);
648 memset(ptr, 0, t->filled_size->buf->size);
649 rctx->ws->buffer_unmap(t->filled_size->buf);
650
651 return &t->b;
652 }
653
654 void r600_so_target_destroy(struct pipe_context *ctx,
655 struct pipe_stream_output_target *target)
656 {
657 struct r600_so_target *t = (struct r600_so_target*)target;
658 pipe_resource_reference(&t->b.buffer, NULL);
659 pipe_resource_reference((struct pipe_resource**)&t->filled_size, NULL);
660 FREE(t);
661 }
662
663 void r600_set_so_targets(struct pipe_context *ctx,
664 unsigned num_targets,
665 struct pipe_stream_output_target **targets,
666 unsigned append_bitmask)
667 {
668 struct r600_context *rctx = (struct r600_context *)ctx;
669 unsigned i;
670
671 /* Stop streamout. */
672 if (rctx->num_so_targets) {
673 r600_context_streamout_end(rctx);
674 }
675
676 /* Set the new targets. */
677 for (i = 0; i < num_targets; i++) {
678 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]);
679 }
680 for (; i < rctx->num_so_targets; i++) {
681 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL);
682 }
683
684 rctx->num_so_targets = num_targets;
685 rctx->streamout_start = num_targets != 0;
686 rctx->streamout_append_bitmask = append_bitmask;
687 }
688
689 static void r600_vertex_buffer_update(struct r600_context *rctx)
690 {
691 struct r600_pipe_resource_state *rstate;
692 struct r600_resource *rbuffer;
693 struct pipe_vertex_buffer *vertex_buffer;
694 unsigned i, count, offset;
695
696 r600_inval_vertex_cache(rctx);
697
698 if (rctx->vertex_elements->vbuffer_need_offset) {
699 /* one resource per vertex elements */
700 count = rctx->vertex_elements->count;
701 } else {
702 /* bind vertex buffer once */
703 count = rctx->vbuf_mgr->nr_real_vertex_buffers;
704 }
705
706 for (i = 0 ; i < count; i++) {
707 rstate = &rctx->fs_resource[i];
708
709 if (rctx->vertex_elements->vbuffer_need_offset) {
710 /* one resource per vertex elements */
711 unsigned vbuffer_index;
712 vbuffer_index = rctx->vertex_elements->elements[i].vertex_buffer_index;
713 vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[vbuffer_index];
714 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
715 offset = rctx->vertex_elements->vbuffer_offset[i];
716 } else {
717 /* bind vertex buffer once */
718 vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[i];
719 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
720 offset = 0;
721 }
722 if (vertex_buffer == NULL || rbuffer == NULL)
723 continue;
724 offset += vertex_buffer->buffer_offset;
725
726 if (!rstate->id) {
727 if (rctx->chip_class >= EVERGREEN) {
728 evergreen_pipe_init_buffer_resource(rctx, rstate);
729 } else {
730 r600_pipe_init_buffer_resource(rctx, rstate);
731 }
732 }
733
734 if (rctx->chip_class >= EVERGREEN) {
735 evergreen_pipe_mod_buffer_resource(&rctx->context, rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ);
736 } else {
737 r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ);
738 }
739 r600_context_pipe_state_set_fs_resource(rctx, rstate, i);
740 }
741 }
742
743 static int r600_shader_rebuild(struct pipe_context * ctx, struct r600_pipe_shader * shader)
744 {
745 struct r600_context *rctx = (struct r600_context *)ctx;
746 int r;
747
748 r600_pipe_shader_destroy(ctx, shader);
749 r = r600_pipe_shader_create(ctx, shader);
750 if (r) {
751 return r;
752 }
753 r600_context_pipe_state_set(rctx, &shader->rstate);
754
755 return 0;
756 }
757
758 static void r600_update_derived_state(struct r600_context *rctx)
759 {
760 struct pipe_context * ctx = (struct pipe_context*)rctx;
761 struct r600_pipe_state rstate;
762
763 rstate.nregs = 0;
764
765 if (rstate.nregs)
766 r600_context_pipe_state_set(rctx, &rstate);
767
768 if (!rctx->blitter->running) {
769 if (rctx->have_depth_fb || rctx->have_depth_texture)
770 r600_flush_depth_textures(rctx);
771 }
772
773 if (rctx->chip_class < EVERGREEN) {
774 r600_update_sampler_states(rctx);
775 }
776
777 if ((rctx->ps_shader->shader.two_side != rctx->two_side) ||
778 ((rctx->chip_class >= EVERGREEN) && rctx->ps_shader->shader.fs_write_all &&
779 (rctx->ps_shader->shader.nr_cbufs != rctx->nr_cbufs))) {
780 r600_shader_rebuild(&rctx->context, rctx->ps_shader);
781 }
782
783 if (rctx->alpha_ref_dirty) {
784 r600_update_alpha_ref(rctx);
785 }
786
787 if (rctx->ps_shader && ((rctx->sprite_coord_enable &&
788 (rctx->ps_shader->sprite_coord_enable != rctx->sprite_coord_enable)) ||
789 (rctx->rasterizer && rctx->rasterizer->flatshade != rctx->ps_shader->flatshade))) {
790
791 if (rctx->chip_class >= EVERGREEN)
792 evergreen_pipe_shader_ps(ctx, rctx->ps_shader);
793 else
794 r600_pipe_shader_ps(ctx, rctx->ps_shader);
795
796 r600_context_pipe_state_set(rctx, &rctx->ps_shader->rstate);
797 }
798
799 }
800
801 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
802 {
803 struct r600_context *rctx = (struct r600_context *)ctx;
804 struct pipe_draw_info info = *dinfo;
805 struct pipe_index_buffer ib = {};
806 unsigned prim, mask, ls_mask = 0;
807 struct r600_block *dirty_block = NULL, *next_block = NULL;
808 struct r600_atom *state = NULL, *next_state = NULL;
809 struct radeon_winsys_cs *cs = rctx->cs;
810 uint64_t va;
811
812 if ((!info.count && (info.indexed || !info.count_from_stream_output)) ||
813 (info.indexed && !rctx->vbuf_mgr->index_buffer.buffer) ||
814 !r600_conv_pipe_prim(info.mode, &prim)) {
815 assert(0);
816 return;
817 }
818
819 if (!rctx->vs_shader) {
820 assert(0);
821 return;
822 }
823
824 r600_update_derived_state(rctx);
825
826 u_vbuf_draw_begin(rctx->vbuf_mgr, &info);
827 r600_vertex_buffer_update(rctx);
828
829 if (info.indexed) {
830 /* Initialize the index buffer struct. */
831 pipe_resource_reference(&ib.buffer, rctx->vbuf_mgr->index_buffer.buffer);
832 ib.index_size = rctx->vbuf_mgr->index_buffer.index_size;
833 ib.offset = rctx->vbuf_mgr->index_buffer.offset + info.start * ib.index_size;
834
835 /* Translate or upload, if needed. */
836 r600_translate_index_buffer(rctx, &ib, info.count);
837
838 if (u_vbuf_resource(ib.buffer)->user_ptr) {
839 r600_upload_index_buffer(rctx, &ib, info.count);
840 }
841 } else {
842 info.index_bias = info.start;
843 if (info.count_from_stream_output) {
844 r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info.count_from_stream_output);
845 }
846 }
847
848 mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
849
850 if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
851 rctx->vgt.id = R600_PIPE_STATE_VGT;
852 rctx->vgt.nregs = 0;
853 r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, NULL, 0);
854 r600_pipe_state_add_reg(&rctx->vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, NULL, 0);
855 r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias, NULL, 0);
856 r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index, NULL, 0);
857 r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart, NULL, 0);
858 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance, NULL, 0);
859 r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0, NULL, 0);
860 if (rctx->chip_class <= R700)
861 r600_pipe_state_add_reg(&rctx->vgt, R_028808_CB_COLOR_CONTROL, rctx->cb_color_control, NULL, 0);
862 r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0, NULL, 0);
863 r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0, NULL, 0);
864 }
865
866 rctx->vgt.nregs = 0;
867 r600_pipe_state_mod_reg(&rctx->vgt, prim);
868 r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_target_mask & mask);
869 r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
870 r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
871 r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart);
872 r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance);
873
874 if (prim == V_008958_DI_PT_LINELIST)
875 ls_mask = 1;
876 else if (prim == V_008958_DI_PT_LINESTRIP)
877 ls_mask = 2;
878 r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask) | rctx->pa_sc_line_stipple);
879 if (rctx->chip_class <= R700)
880 r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_color_control);
881 r600_pipe_state_mod_reg(&rctx->vgt,
882 rctx->vs_shader->pa_cl_vs_out_cntl |
883 (rctx->rasterizer->clip_plane_enable & rctx->vs_shader->shader.clip_dist_write));
884 r600_pipe_state_mod_reg(&rctx->vgt,
885 rctx->pa_cl_clip_cntl |
886 (rctx->vs_shader->shader.clip_dist_write ||
887 rctx->vs_shader->shader.vs_prohibit_ucps ?
888 0 : rctx->rasterizer->clip_plane_enable & 0x3F));
889
890 r600_context_pipe_state_set(rctx, &rctx->vgt);
891
892 /* Emit states (the function expects that we emit at most 17 dwords here). */
893 r600_need_cs_space(rctx, 0, TRUE);
894
895 LIST_FOR_EACH_ENTRY_SAFE(state, next_state, &rctx->dirty_states, head) {
896 r600_emit_atom(rctx, state);
897 }
898 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) {
899 r600_context_block_emit_dirty(rctx, dirty_block);
900 }
901 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->resource_dirty,list) {
902 r600_context_block_resource_emit_dirty(rctx, dirty_block);
903 }
904 rctx->pm4_dirty_cdwords = 0;
905
906 /* Enable stream out if needed. */
907 if (rctx->streamout_start) {
908 r600_context_streamout_begin(rctx);
909 rctx->streamout_start = FALSE;
910 }
911
912 /* draw packet */
913 cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->predicate_drawing);
914 cs->buf[cs->cdw++] = ib.index_size == 4 ?
915 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
916 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
917 cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->predicate_drawing);
918 cs->buf[cs->cdw++] = info.instance_count;
919 if (info.indexed) {
920 va = r600_resource_va(ctx->screen, ib.buffer);
921 va += ib.offset;
922 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->predicate_drawing);
923 cs->buf[cs->cdw++] = va;
924 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
925 cs->buf[cs->cdw++] = info.count;
926 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
927 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->predicate_drawing);
928 cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
929 } else {
930 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->predicate_drawing);
931 cs->buf[cs->cdw++] = info.count;
932 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
933 (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
934 }
935
936 rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING;
937
938 if (rctx->framebuffer.zsbuf)
939 {
940 struct pipe_resource *tex = rctx->framebuffer.zsbuf->texture;
941 ((struct r600_resource_texture *)tex)->dirty_db = TRUE;
942 }
943
944 pipe_resource_reference(&ib.buffer, NULL);
945 u_vbuf_draw_end(rctx->vbuf_mgr);
946 }
947
948 void _r600_pipe_state_add_reg(struct r600_context *ctx,
949 struct r600_pipe_state *state,
950 uint32_t offset, uint32_t value,
951 uint32_t range_id, uint32_t block_id,
952 struct r600_resource *bo,
953 enum radeon_bo_usage usage)
954 {
955 struct r600_range *range;
956 struct r600_block *block;
957
958 if (bo) assert(usage);
959
960 range = &ctx->range[range_id];
961 block = range->blocks[block_id];
962 state->regs[state->nregs].block = block;
963 state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
964
965 state->regs[state->nregs].value = value;
966 state->regs[state->nregs].bo = bo;
967 state->regs[state->nregs].bo_usage = usage;
968
969 state->nregs++;
970 assert(state->nregs < R600_BLOCK_MAX_REG);
971 }
972
973 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
974 uint32_t offset, uint32_t value,
975 struct r600_resource *bo,
976 enum radeon_bo_usage usage)
977 {
978 if (bo) assert(usage);
979
980 state->regs[state->nregs].id = offset;
981 state->regs[state->nregs].block = NULL;
982 state->regs[state->nregs].value = value;
983 state->regs[state->nregs].bo = bo;
984 state->regs[state->nregs].bo_usage = usage;
985
986 state->nregs++;
987 assert(state->nregs < R600_BLOCK_MAX_REG);
988 }
989
990 uint32_t r600_translate_stencil_op(int s_op)
991 {
992 switch (s_op) {
993 case PIPE_STENCIL_OP_KEEP:
994 return V_028800_STENCIL_KEEP;
995 case PIPE_STENCIL_OP_ZERO:
996 return V_028800_STENCIL_ZERO;
997 case PIPE_STENCIL_OP_REPLACE:
998 return V_028800_STENCIL_REPLACE;
999 case PIPE_STENCIL_OP_INCR:
1000 return V_028800_STENCIL_INCR;
1001 case PIPE_STENCIL_OP_DECR:
1002 return V_028800_STENCIL_DECR;
1003 case PIPE_STENCIL_OP_INCR_WRAP:
1004 return V_028800_STENCIL_INCR_WRAP;
1005 case PIPE_STENCIL_OP_DECR_WRAP:
1006 return V_028800_STENCIL_DECR_WRAP;
1007 case PIPE_STENCIL_OP_INVERT:
1008 return V_028800_STENCIL_INVERT;
1009 default:
1010 R600_ERR("Unknown stencil op %d", s_op);
1011 assert(0);
1012 break;
1013 }
1014 return 0;
1015 }
1016
1017 uint32_t r600_translate_fill(uint32_t func)
1018 {
1019 switch(func) {
1020 case PIPE_POLYGON_MODE_FILL:
1021 return 2;
1022 case PIPE_POLYGON_MODE_LINE:
1023 return 1;
1024 case PIPE_POLYGON_MODE_POINT:
1025 return 0;
1026 default:
1027 assert(0);
1028 return 0;
1029 }
1030 }
1031
1032 unsigned r600_tex_wrap(unsigned wrap)
1033 {
1034 switch (wrap) {
1035 default:
1036 case PIPE_TEX_WRAP_REPEAT:
1037 return V_03C000_SQ_TEX_WRAP;
1038 case PIPE_TEX_WRAP_CLAMP:
1039 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1040 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1041 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1042 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1043 return V_03C000_SQ_TEX_CLAMP_BORDER;
1044 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1045 return V_03C000_SQ_TEX_MIRROR;
1046 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1047 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1048 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1049 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1050 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1051 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1052 }
1053 }
1054
1055 unsigned r600_tex_filter(unsigned filter)
1056 {
1057 switch (filter) {
1058 default:
1059 case PIPE_TEX_FILTER_NEAREST:
1060 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1061 case PIPE_TEX_FILTER_LINEAR:
1062 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1063 }
1064 }
1065
1066 unsigned r600_tex_mipfilter(unsigned filter)
1067 {
1068 switch (filter) {
1069 case PIPE_TEX_MIPFILTER_NEAREST:
1070 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1071 case PIPE_TEX_MIPFILTER_LINEAR:
1072 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1073 default:
1074 case PIPE_TEX_MIPFILTER_NONE:
1075 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1076 }
1077 }
1078
1079 unsigned r600_tex_compare(unsigned compare)
1080 {
1081 switch (compare) {
1082 default:
1083 case PIPE_FUNC_NEVER:
1084 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1085 case PIPE_FUNC_LESS:
1086 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1087 case PIPE_FUNC_EQUAL:
1088 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1089 case PIPE_FUNC_LEQUAL:
1090 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1091 case PIPE_FUNC_GREATER:
1092 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1093 case PIPE_FUNC_NOTEQUAL:
1094 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1095 case PIPE_FUNC_GEQUAL:
1096 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1097 case PIPE_FUNC_ALWAYS:
1098 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1099 }
1100 }