2 * Copyright 2010 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
27 #include "r600_formats.h"
30 #include "util/u_draw_quad.h"
31 #include "util/u_upload_mgr.h"
32 #include "tgsi/tgsi_parse.h"
35 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
37 static void r600_emit_command_buffer(struct r600_context
*rctx
, struct r600_atom
*atom
)
39 struct radeon_winsys_cs
*cs
= rctx
->cs
;
40 struct r600_command_buffer
*cb
= (struct r600_command_buffer
*)atom
;
42 assert(cs
->cdw
+ cb
->atom
.num_dw
<= RADEON_MAX_CMDBUF_DWORDS
);
43 memcpy(cs
->buf
+ cs
->cdw
, cb
->buf
, 4 * cb
->atom
.num_dw
);
44 cs
->cdw
+= cb
->atom
.num_dw
;
47 void r600_init_command_buffer(struct r600_context
*rctx
, struct r600_command_buffer
*cb
, unsigned id
, unsigned num_dw
)
49 r600_init_atom(rctx
, &cb
->atom
, id
, r600_emit_command_buffer
, 0);
50 cb
->buf
= CALLOC(1, 4 * num_dw
);
51 cb
->max_num_dw
= num_dw
;
54 void r600_release_command_buffer(struct r600_command_buffer
*cb
)
59 void r600_init_atom(struct r600_context
*rctx
,
60 struct r600_atom
*atom
,
62 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
65 assert(id
< R600_MAX_ATOM
);
66 assert(rctx
->atoms
[id
] == NULL
);
67 rctx
->atoms
[id
] = atom
;
70 atom
->num_dw
= num_dw
;
74 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
76 struct radeon_winsys_cs
*cs
= rctx
->cs
;
77 struct r600_alphatest_state
*a
= (struct r600_alphatest_state
*)atom
;
78 unsigned alpha_ref
= a
->sx_alpha_ref
;
80 if (rctx
->chip_class
>= EVERGREEN
&& a
->cb0_export_16bpc
) {
84 r600_write_context_reg(cs
, R_028410_SX_ALPHA_TEST_CONTROL
,
85 a
->sx_alpha_test_control
|
86 S_028410_ALPHA_TEST_BYPASS(a
->bypass
));
87 r600_write_context_reg(cs
, R_028438_SX_ALPHA_REF
, alpha_ref
);
90 void r600_texture_barrier(struct pipe_context
*ctx
)
92 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
94 rctx
->flags
|= R600_CONTEXT_CB_FLUSH
| R600_CONTEXT_TEX_FLUSH
;
97 if (rctx
->chip_class
== R600
) {
98 rctx
->flags
|= R600_CONTEXT_FLUSH_AND_INV
;
102 static bool r600_conv_pipe_prim(unsigned pprim
, unsigned *prim
)
104 static const int prim_conv
[] = {
105 V_008958_DI_PT_POINTLIST
,
106 V_008958_DI_PT_LINELIST
,
107 V_008958_DI_PT_LINELOOP
,
108 V_008958_DI_PT_LINESTRIP
,
109 V_008958_DI_PT_TRILIST
,
110 V_008958_DI_PT_TRISTRIP
,
111 V_008958_DI_PT_TRIFAN
,
112 V_008958_DI_PT_QUADLIST
,
113 V_008958_DI_PT_QUADSTRIP
,
114 V_008958_DI_PT_POLYGON
,
119 V_008958_DI_PT_RECTLIST
122 *prim
= prim_conv
[pprim
];
124 fprintf(stderr
, "%s:%d unsupported %d\n", __func__
, __LINE__
, pprim
);
130 /* common state between evergreen and r600 */
132 static void r600_bind_blend_state_internal(struct r600_context
*rctx
,
133 struct r600_pipe_blend
*blend
)
135 struct r600_pipe_state
*rstate
;
136 bool update_cb
= false;
138 rstate
= &blend
->rstate
;
139 rctx
->states
[rstate
->id
] = rstate
;
140 r600_context_pipe_state_set(rctx
, rstate
);
142 if (rctx
->cb_misc_state
.blend_colormask
!= blend
->cb_target_mask
) {
143 rctx
->cb_misc_state
.blend_colormask
= blend
->cb_target_mask
;
146 if (rctx
->chip_class
<= R700
&&
147 rctx
->cb_misc_state
.cb_color_control
!= blend
->cb_color_control
) {
148 rctx
->cb_misc_state
.cb_color_control
= blend
->cb_color_control
;
151 if (rctx
->cb_misc_state
.dual_src_blend
!= blend
->dual_src_blend
) {
152 rctx
->cb_misc_state
.dual_src_blend
= blend
->dual_src_blend
;
156 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
160 void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
)
162 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
163 struct r600_pipe_blend
*blend
= (struct r600_pipe_blend
*)state
;
169 rctx
->alpha_to_one
= blend
->alpha_to_one
;
170 rctx
->dual_src_blend
= blend
->dual_src_blend
;
172 if (!rctx
->blend_override
)
173 r600_bind_blend_state_internal(rctx
, blend
);
176 void r600_set_blend_color(struct pipe_context
*ctx
,
177 const struct pipe_blend_color
*state
)
179 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
180 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
185 rstate
->id
= R600_PIPE_STATE_BLEND_COLOR
;
186 r600_pipe_state_add_reg(rstate
, R_028414_CB_BLEND_RED
, fui(state
->color
[0]));
187 r600_pipe_state_add_reg(rstate
, R_028418_CB_BLEND_GREEN
, fui(state
->color
[1]));
188 r600_pipe_state_add_reg(rstate
, R_02841C_CB_BLEND_BLUE
, fui(state
->color
[2]));
189 r600_pipe_state_add_reg(rstate
, R_028420_CB_BLEND_ALPHA
, fui(state
->color
[3]));
191 free(rctx
->states
[R600_PIPE_STATE_BLEND_COLOR
]);
192 rctx
->states
[R600_PIPE_STATE_BLEND_COLOR
] = rstate
;
193 r600_context_pipe_state_set(rctx
, rstate
);
196 static void r600_set_stencil_ref(struct pipe_context
*ctx
,
197 const struct r600_stencil_ref
*state
)
199 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
200 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
205 rstate
->id
= R600_PIPE_STATE_STENCIL_REF
;
206 r600_pipe_state_add_reg(rstate
,
207 R_028430_DB_STENCILREFMASK
,
208 S_028430_STENCILREF(state
->ref_value
[0]) |
209 S_028430_STENCILMASK(state
->valuemask
[0]) |
210 S_028430_STENCILWRITEMASK(state
->writemask
[0]));
211 r600_pipe_state_add_reg(rstate
,
212 R_028434_DB_STENCILREFMASK_BF
,
213 S_028434_STENCILREF_BF(state
->ref_value
[1]) |
214 S_028434_STENCILMASK_BF(state
->valuemask
[1]) |
215 S_028434_STENCILWRITEMASK_BF(state
->writemask
[1]));
217 free(rctx
->states
[R600_PIPE_STATE_STENCIL_REF
]);
218 rctx
->states
[R600_PIPE_STATE_STENCIL_REF
] = rstate
;
219 r600_context_pipe_state_set(rctx
, rstate
);
222 void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
223 const struct pipe_stencil_ref
*state
)
225 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
226 struct r600_pipe_dsa
*dsa
= (struct r600_pipe_dsa
*)rctx
->states
[R600_PIPE_STATE_DSA
];
227 struct r600_stencil_ref ref
;
229 rctx
->stencil_ref
= *state
;
234 ref
.ref_value
[0] = state
->ref_value
[0];
235 ref
.ref_value
[1] = state
->ref_value
[1];
236 ref
.valuemask
[0] = dsa
->valuemask
[0];
237 ref
.valuemask
[1] = dsa
->valuemask
[1];
238 ref
.writemask
[0] = dsa
->writemask
[0];
239 ref
.writemask
[1] = dsa
->writemask
[1];
241 r600_set_stencil_ref(ctx
, &ref
);
244 void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
246 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
247 struct r600_pipe_dsa
*dsa
= state
;
248 struct r600_pipe_state
*rstate
;
249 struct r600_stencil_ref ref
;
253 rstate
= &dsa
->rstate
;
254 rctx
->states
[rstate
->id
] = rstate
;
255 r600_context_pipe_state_set(rctx
, rstate
);
257 ref
.ref_value
[0] = rctx
->stencil_ref
.ref_value
[0];
258 ref
.ref_value
[1] = rctx
->stencil_ref
.ref_value
[1];
259 ref
.valuemask
[0] = dsa
->valuemask
[0];
260 ref
.valuemask
[1] = dsa
->valuemask
[1];
261 ref
.writemask
[0] = dsa
->writemask
[0];
262 ref
.writemask
[1] = dsa
->writemask
[1];
264 r600_set_stencil_ref(ctx
, &ref
);
266 /* Update alphatest state. */
267 if (rctx
->alphatest_state
.sx_alpha_test_control
!= dsa
->sx_alpha_test_control
||
268 rctx
->alphatest_state
.sx_alpha_ref
!= dsa
->alpha_ref
) {
269 rctx
->alphatest_state
.sx_alpha_test_control
= dsa
->sx_alpha_test_control
;
270 rctx
->alphatest_state
.sx_alpha_ref
= dsa
->alpha_ref
;
271 r600_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
275 void r600_set_max_scissor(struct r600_context
*rctx
)
277 /* Set a scissor state such that it doesn't do anything. */
278 struct pipe_scissor_state scissor
;
284 r600_set_scissor_state(rctx
, &scissor
);
287 void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
)
289 struct r600_pipe_rasterizer
*rs
= (struct r600_pipe_rasterizer
*)state
;
290 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
295 rctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
296 rctx
->two_side
= rs
->two_side
;
297 rctx
->pa_sc_line_stipple
= rs
->pa_sc_line_stipple
;
298 rctx
->pa_cl_clip_cntl
= rs
->pa_cl_clip_cntl
;
299 rctx
->multisample_enable
= rs
->multisample_enable
;
301 rctx
->rasterizer
= rs
;
303 rctx
->states
[rs
->rstate
.id
] = &rs
->rstate
;
304 r600_context_pipe_state_set(rctx
, &rs
->rstate
);
306 if (rctx
->chip_class
>= EVERGREEN
) {
307 evergreen_polygon_offset_update(rctx
);
309 r600_polygon_offset_update(rctx
);
312 /* Workaround for a missing scissor enable on r600. */
313 if (rctx
->chip_class
== R600
) {
314 if (rs
->scissor_enable
!= rctx
->scissor_enable
) {
315 rctx
->scissor_enable
= rs
->scissor_enable
;
317 if (rs
->scissor_enable
) {
318 r600_set_scissor_state(rctx
, &rctx
->scissor_state
);
320 r600_set_max_scissor(rctx
);
326 void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
)
328 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
329 struct r600_pipe_rasterizer
*rs
= (struct r600_pipe_rasterizer
*)state
;
331 if (rctx
->rasterizer
== rs
) {
332 rctx
->rasterizer
= NULL
;
334 if (rctx
->states
[rs
->rstate
.id
] == &rs
->rstate
) {
335 rctx
->states
[rs
->rstate
.id
] = NULL
;
340 void r600_sampler_view_destroy(struct pipe_context
*ctx
,
341 struct pipe_sampler_view
*state
)
343 struct r600_pipe_sampler_view
*resource
= (struct r600_pipe_sampler_view
*)state
;
345 pipe_resource_reference(&state
->texture
, NULL
);
349 static void r600_bind_samplers(struct pipe_context
*pipe
,
352 unsigned count
, void **states
)
354 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
355 struct r600_textures_info
*dst
;
356 int seamless_cube_map
= -1;
359 assert(start
== 0); /* XXX fix below */
362 case PIPE_SHADER_VERTEX
:
363 dst
= &rctx
->vs_samplers
;
365 case PIPE_SHADER_FRAGMENT
:
366 dst
= &rctx
->ps_samplers
;
369 debug_error("bad shader in r600_bind_samplers()");
373 memcpy(dst
->samplers
, states
, sizeof(void*) * count
);
374 dst
->n_samplers
= count
;
375 dst
->atom_sampler
.num_dw
= 0;
377 for (i
= 0; i
< count
; i
++) {
378 struct r600_pipe_sampler_state
*sampler
= states
[i
];
380 if (sampler
== NULL
) {
383 if (sampler
->border_color_use
) {
384 dst
->atom_sampler
.num_dw
+= 11;
385 rctx
->flags
|= R600_CONTEXT_PS_PARTIAL_FLUSH
;
387 dst
->atom_sampler
.num_dw
+= 5;
389 seamless_cube_map
= sampler
->seamless_cube_map
;
391 if (rctx
->chip_class
<= R700
&& seamless_cube_map
!= -1 && seamless_cube_map
!= rctx
->seamless_cube_map
.enabled
) {
392 /* change in TA_CNTL_AUX need a pipeline flush */
393 rctx
->flags
|= R600_CONTEXT_PS_PARTIAL_FLUSH
;
394 rctx
->seamless_cube_map
.enabled
= seamless_cube_map
;
395 r600_atom_dirty(rctx
, &rctx
->seamless_cube_map
.atom
);
397 if (dst
->atom_sampler
.num_dw
) {
398 r600_atom_dirty(rctx
, &dst
->atom_sampler
);
402 void r600_bind_vs_samplers(struct pipe_context
*ctx
, unsigned count
, void **states
)
404 r600_bind_samplers(ctx
, PIPE_SHADER_VERTEX
, 0, count
, states
);
407 void r600_bind_ps_samplers(struct pipe_context
*ctx
, unsigned count
, void **states
)
409 r600_bind_samplers(ctx
, PIPE_SHADER_FRAGMENT
, 0, count
, states
);
412 void r600_delete_sampler(struct pipe_context
*ctx
, void *state
)
417 void r600_delete_state(struct pipe_context
*ctx
, void *state
)
419 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
420 struct r600_pipe_state
*rstate
= (struct r600_pipe_state
*)state
;
422 if (rctx
->states
[rstate
->id
] == rstate
) {
423 rctx
->states
[rstate
->id
] = NULL
;
425 for (int i
= 0; i
< rstate
->nregs
; i
++) {
426 pipe_resource_reference((struct pipe_resource
**)&rstate
->regs
[i
].bo
, NULL
);
431 void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
433 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
434 struct r600_vertex_element
*v
= (struct r600_vertex_element
*)state
;
436 rctx
->vertex_elements
= v
;
438 rctx
->states
[v
->rstate
.id
] = &v
->rstate
;
439 r600_context_pipe_state_set(rctx
, &v
->rstate
);
443 void r600_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
445 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
446 struct r600_vertex_element
*v
= (struct r600_vertex_element
*)state
;
448 if (rctx
->states
[v
->rstate
.id
] == &v
->rstate
) {
449 rctx
->states
[v
->rstate
.id
] = NULL
;
451 if (rctx
->vertex_elements
== state
)
452 rctx
->vertex_elements
= NULL
;
454 pipe_resource_reference((struct pipe_resource
**)&v
->fetch_shader
, NULL
);
458 void r600_set_index_buffer(struct pipe_context
*ctx
,
459 const struct pipe_index_buffer
*ib
)
461 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
464 pipe_resource_reference(&rctx
->index_buffer
.buffer
, ib
->buffer
);
465 memcpy(&rctx
->index_buffer
, ib
, sizeof(*ib
));
467 pipe_resource_reference(&rctx
->index_buffer
.buffer
, NULL
);
471 void r600_vertex_buffers_dirty(struct r600_context
*rctx
)
473 if (rctx
->vertex_buffer_state
.dirty_mask
) {
474 rctx
->flags
|= rctx
->has_vertex_cache
? R600_CONTEXT_VTX_FLUSH
: R600_CONTEXT_TEX_FLUSH
;
475 rctx
->vertex_buffer_state
.atom
.num_dw
= (rctx
->chip_class
>= EVERGREEN
? 12 : 11) *
476 util_bitcount(rctx
->vertex_buffer_state
.dirty_mask
);
477 r600_atom_dirty(rctx
, &rctx
->vertex_buffer_state
.atom
);
481 void r600_set_vertex_buffers(struct pipe_context
*ctx
, unsigned count
,
482 const struct pipe_vertex_buffer
*input
)
484 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
485 struct r600_vertexbuf_state
*state
= &rctx
->vertex_buffer_state
;
486 struct pipe_vertex_buffer
*vb
= state
->vb
;
488 /* This sets 1-bit for buffers with index >= count. */
489 uint32_t disable_mask
= ~((1ull << count
) - 1);
490 /* These are the new buffers set by this function. */
491 uint32_t new_buffer_mask
= 0;
493 /* Set buffers with index >= count to NULL. */
494 uint32_t remaining_buffers_mask
=
495 rctx
->vertex_buffer_state
.enabled_mask
& disable_mask
;
497 while (remaining_buffers_mask
) {
498 i
= u_bit_scan(&remaining_buffers_mask
);
499 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
502 /* Set vertex buffers. */
503 for (i
= 0; i
< count
; i
++) {
504 if (memcmp(&input
[i
], &vb
[i
], sizeof(struct pipe_vertex_buffer
))) {
505 if (input
[i
].buffer
) {
506 vb
[i
].stride
= input
[i
].stride
;
507 vb
[i
].buffer_offset
= input
[i
].buffer_offset
;
508 pipe_resource_reference(&vb
[i
].buffer
, input
[i
].buffer
);
509 new_buffer_mask
|= 1 << i
;
511 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
512 disable_mask
|= 1 << i
;
517 rctx
->vertex_buffer_state
.enabled_mask
&= ~disable_mask
;
518 rctx
->vertex_buffer_state
.dirty_mask
&= rctx
->vertex_buffer_state
.enabled_mask
;
519 rctx
->vertex_buffer_state
.enabled_mask
|= new_buffer_mask
;
520 rctx
->vertex_buffer_state
.dirty_mask
|= new_buffer_mask
;
522 r600_vertex_buffers_dirty(rctx
);
525 void r600_sampler_views_dirty(struct r600_context
*rctx
,
526 struct r600_samplerview_state
*state
)
528 if (state
->dirty_mask
) {
529 rctx
->flags
|= R600_CONTEXT_TEX_FLUSH
;
530 state
->atom
.num_dw
= (rctx
->chip_class
>= EVERGREEN
? 14 : 13) *
531 util_bitcount(state
->dirty_mask
);
532 r600_atom_dirty(rctx
, &state
->atom
);
536 void r600_set_sampler_views(struct pipe_context
*pipe
,
540 struct pipe_sampler_view
**views
)
542 struct r600_context
*rctx
= (struct r600_context
*) pipe
;
543 struct r600_textures_info
*dst
;
544 struct r600_pipe_sampler_view
**rviews
= (struct r600_pipe_sampler_view
**)views
;
546 /* This sets 1-bit for textures with index >= count. */
547 uint32_t disable_mask
= ~((1ull << count
) - 1);
548 /* These are the new textures set by this function. */
549 uint32_t new_mask
= 0;
551 /* Set textures with index >= count to NULL. */
552 uint32_t remaining_mask
;
554 assert(start
== 0); /* XXX fix below */
557 case PIPE_SHADER_VERTEX
:
558 dst
= &rctx
->vs_samplers
;
560 case PIPE_SHADER_FRAGMENT
:
561 dst
= &rctx
->ps_samplers
;
564 debug_error("bad shader in r600_set_sampler_views()");
568 remaining_mask
= dst
->views
.enabled_mask
& disable_mask
;
570 while (remaining_mask
) {
571 i
= u_bit_scan(&remaining_mask
);
572 assert(dst
->views
.views
[i
]);
574 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
577 for (i
= 0; i
< count
; i
++) {
578 if (rviews
[i
] == dst
->views
.views
[i
]) {
583 struct r600_texture
*rtex
=
584 (struct r600_texture
*)rviews
[i
]->base
.texture
;
586 if (rtex
->is_depth
&& !rtex
->is_flushing_texture
) {
587 dst
->views
.compressed_depthtex_mask
|= 1 << i
;
589 dst
->views
.compressed_depthtex_mask
&= ~(1 << i
);
592 /* Track compressed colorbuffers for Evergreen (Cayman doesn't need this). */
593 if (rctx
->chip_class
!= CAYMAN
&& rtex
->cmask_size
&& rtex
->fmask_size
) {
594 dst
->views
.compressed_colortex_mask
|= 1 << i
;
596 dst
->views
.compressed_colortex_mask
&= ~(1 << i
);
599 /* Changing from array to non-arrays textures and vice
600 * versa requires updating TEX_ARRAY_OVERRIDE on R6xx-R7xx. */
601 if (rctx
->chip_class
<= R700
&&
602 (rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_1D_ARRAY
||
603 rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_2D_ARRAY
) != dst
->is_array_sampler
[i
]) {
604 r600_atom_dirty(rctx
, &dst
->atom_sampler
);
607 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], views
[i
]);
610 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
611 disable_mask
|= 1 << i
;
615 dst
->views
.enabled_mask
&= ~disable_mask
;
616 dst
->views
.dirty_mask
&= dst
->views
.enabled_mask
;
617 dst
->views
.enabled_mask
|= new_mask
;
618 dst
->views
.dirty_mask
|= new_mask
;
619 dst
->views
.compressed_depthtex_mask
&= dst
->views
.enabled_mask
;
620 dst
->views
.compressed_colortex_mask
&= dst
->views
.enabled_mask
;
622 r600_sampler_views_dirty(rctx
, &dst
->views
);
625 void *r600_create_vertex_elements(struct pipe_context
*ctx
,
627 const struct pipe_vertex_element
*elements
)
629 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
630 struct r600_vertex_element
*v
= CALLOC_STRUCT(r600_vertex_element
);
637 memcpy(v
->elements
, elements
, sizeof(struct pipe_vertex_element
) * count
);
639 if (r600_vertex_elements_build_fetch_shader(rctx
, v
)) {
647 /* Compute the key for the hw shader variant */
648 static INLINE
unsigned r600_shader_selector_key(struct pipe_context
* ctx
,
649 struct r600_pipe_shader_selector
* sel
)
651 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
654 if (sel
->type
== PIPE_SHADER_FRAGMENT
) {
655 key
= rctx
->two_side
|
656 ((rctx
->alpha_to_one
&& rctx
->multisample_enable
&& !rctx
->cb0_is_integer
) << 1) |
657 (MIN2(sel
->nr_ps_max_color_exports
, rctx
->nr_cbufs
+ rctx
->dual_src_blend
) << 2);
664 /* Select the hw shader variant depending on the current state.
665 * (*dirty) is set to 1 if current variant was changed */
666 static int r600_shader_select(struct pipe_context
*ctx
,
667 struct r600_pipe_shader_selector
* sel
,
671 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
672 struct r600_pipe_shader
* shader
= NULL
;
675 key
= r600_shader_selector_key(ctx
, sel
);
677 /* Check if we don't need to change anything.
678 * This path is also used for most shaders that don't need multiple
679 * variants, it will cost just a computation of the key and this
681 if (likely(sel
->current
&& sel
->current
->key
== key
)) {
685 /* lookup if we have other variants in the list */
686 if (sel
->num_shaders
> 1) {
687 struct r600_pipe_shader
*p
= sel
->current
, *c
= p
->next_variant
;
689 while (c
&& c
->key
!= key
) {
695 p
->next_variant
= c
->next_variant
;
700 if (unlikely(!shader
)) {
701 shader
= CALLOC(1, sizeof(struct r600_pipe_shader
));
702 shader
->selector
= sel
;
704 r
= r600_pipe_shader_create(ctx
, shader
);
706 R600_ERR("Failed to build shader variant (type=%u, key=%u) %d\n",
712 /* We don't know the value of nr_ps_max_color_exports until we built
713 * at least one variant, so we may need to recompute the key after
714 * building first variant. */
715 if (sel
->type
== PIPE_SHADER_FRAGMENT
&&
716 sel
->num_shaders
== 0) {
717 sel
->nr_ps_max_color_exports
= shader
->shader
.nr_ps_max_color_exports
;
718 key
= r600_shader_selector_key(ctx
, sel
);
728 shader
->next_variant
= sel
->current
;
729 sel
->current
= shader
;
731 if (rctx
->chip_class
< EVERGREEN
&& rctx
->ps_shader
&& rctx
->vs_shader
) {
732 r600_adjust_gprs(rctx
);
735 if (rctx
->ps_shader
&&
736 rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
737 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
738 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
743 static void *r600_create_shader_state(struct pipe_context
*ctx
,
744 const struct pipe_shader_state
*state
,
745 unsigned pipe_shader_type
)
747 struct r600_pipe_shader_selector
*sel
= CALLOC_STRUCT(r600_pipe_shader_selector
);
750 sel
->type
= pipe_shader_type
;
751 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
752 sel
->so
= state
->stream_output
;
754 r
= r600_shader_select(ctx
, sel
, NULL
);
761 void *r600_create_shader_state_ps(struct pipe_context
*ctx
,
762 const struct pipe_shader_state
*state
)
764 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_FRAGMENT
);
767 void *r600_create_shader_state_vs(struct pipe_context
*ctx
,
768 const struct pipe_shader_state
*state
)
770 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_VERTEX
);
773 void r600_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
775 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
778 state
= rctx
->dummy_pixel_shader
;
780 rctx
->ps_shader
= (struct r600_pipe_shader_selector
*)state
;
781 r600_context_pipe_state_set(rctx
, &rctx
->ps_shader
->current
->rstate
);
783 if (rctx
->chip_class
<= R700
) {
784 bool multiwrite
= rctx
->ps_shader
->current
->shader
.fs_write_all
;
786 if (rctx
->cb_misc_state
.multiwrite
!= multiwrite
) {
787 rctx
->cb_misc_state
.multiwrite
= multiwrite
;
788 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
792 r600_adjust_gprs(rctx
);
795 if (rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
796 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
797 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
801 void r600_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
803 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
805 rctx
->vs_shader
= (struct r600_pipe_shader_selector
*)state
;
807 r600_context_pipe_state_set(rctx
, &rctx
->vs_shader
->current
->rstate
);
809 if (rctx
->chip_class
< EVERGREEN
&& rctx
->ps_shader
)
810 r600_adjust_gprs(rctx
);
814 static void r600_delete_shader_selector(struct pipe_context
*ctx
,
815 struct r600_pipe_shader_selector
*sel
)
817 struct r600_pipe_shader
*p
= sel
->current
, *c
;
820 r600_pipe_shader_destroy(ctx
, p
);
830 void r600_delete_ps_shader(struct pipe_context
*ctx
, void *state
)
832 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
833 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
835 if (rctx
->ps_shader
== sel
) {
836 rctx
->ps_shader
= NULL
;
839 r600_delete_shader_selector(ctx
, sel
);
842 void r600_delete_vs_shader(struct pipe_context
*ctx
, void *state
)
844 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
845 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
847 if (rctx
->vs_shader
== sel
) {
848 rctx
->vs_shader
= NULL
;
851 r600_delete_shader_selector(ctx
, sel
);
854 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
)
856 if (state
->dirty_mask
) {
857 rctx
->flags
|= R600_CONTEXT_SHADERCONST_FLUSH
;
858 state
->atom
.num_dw
= rctx
->chip_class
>= EVERGREEN
? util_bitcount(state
->dirty_mask
)*20
859 : util_bitcount(state
->dirty_mask
)*19;
860 r600_atom_dirty(rctx
, &state
->atom
);
864 void r600_set_constant_buffer(struct pipe_context
*ctx
, uint shader
, uint index
,
865 struct pipe_constant_buffer
*input
)
867 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
868 struct r600_constbuf_state
*state
;
869 struct pipe_constant_buffer
*cb
;
873 case PIPE_SHADER_VERTEX
:
874 state
= &rctx
->vs_constbuf_state
;
876 case PIPE_SHADER_FRAGMENT
:
877 state
= &rctx
->ps_constbuf_state
;
883 /* Note that the state tracker can unbind constant buffers by
886 if (unlikely(!input
)) {
887 state
->enabled_mask
&= ~(1 << index
);
888 state
->dirty_mask
&= ~(1 << index
);
889 pipe_resource_reference(&state
->cb
[index
].buffer
, NULL
);
893 cb
= &state
->cb
[index
];
894 cb
->buffer_size
= input
->buffer_size
;
896 ptr
= input
->user_buffer
;
899 /* Upload the user buffer. */
900 if (R600_BIG_ENDIAN
) {
902 unsigned i
, size
= input
->buffer_size
;
904 if (!(tmpPtr
= malloc(size
))) {
905 R600_ERR("Failed to allocate BE swap buffer.\n");
909 for (i
= 0; i
< size
/ 4; ++i
) {
910 tmpPtr
[i
] = bswap_32(((uint32_t *)ptr
)[i
]);
913 u_upload_data(rctx
->uploader
, 0, size
, tmpPtr
, &cb
->buffer_offset
, &cb
->buffer
);
916 u_upload_data(rctx
->uploader
, 0, input
->buffer_size
, ptr
, &cb
->buffer_offset
, &cb
->buffer
);
919 /* Setup the hw buffer. */
920 cb
->buffer_offset
= input
->buffer_offset
;
921 pipe_resource_reference(&cb
->buffer
, input
->buffer
);
924 state
->enabled_mask
|= 1 << index
;
925 state
->dirty_mask
|= 1 << index
;
926 r600_constant_buffers_dirty(rctx
, state
);
929 struct pipe_stream_output_target
*
930 r600_create_so_target(struct pipe_context
*ctx
,
931 struct pipe_resource
*buffer
,
932 unsigned buffer_offset
,
933 unsigned buffer_size
)
935 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
936 struct r600_so_target
*t
;
939 t
= CALLOC_STRUCT(r600_so_target
);
944 t
->b
.reference
.count
= 1;
946 pipe_resource_reference(&t
->b
.buffer
, buffer
);
947 t
->b
.buffer_offset
= buffer_offset
;
948 t
->b
.buffer_size
= buffer_size
;
950 t
->filled_size
= (struct r600_resource
*)
951 pipe_buffer_create(ctx
->screen
, PIPE_BIND_CUSTOM
, PIPE_USAGE_STATIC
, 4);
952 ptr
= rctx
->ws
->buffer_map(t
->filled_size
->cs_buf
, rctx
->cs
, PIPE_TRANSFER_WRITE
);
953 memset(ptr
, 0, t
->filled_size
->buf
->size
);
954 rctx
->ws
->buffer_unmap(t
->filled_size
->cs_buf
);
959 void r600_so_target_destroy(struct pipe_context
*ctx
,
960 struct pipe_stream_output_target
*target
)
962 struct r600_so_target
*t
= (struct r600_so_target
*)target
;
963 pipe_resource_reference(&t
->b
.buffer
, NULL
);
964 pipe_resource_reference((struct pipe_resource
**)&t
->filled_size
, NULL
);
968 void r600_set_so_targets(struct pipe_context
*ctx
,
969 unsigned num_targets
,
970 struct pipe_stream_output_target
**targets
,
971 unsigned append_bitmask
)
973 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
976 /* Stop streamout. */
977 if (rctx
->num_so_targets
&& !rctx
->streamout_start
) {
978 r600_context_streamout_end(rctx
);
981 /* Set the new targets. */
982 for (i
= 0; i
< num_targets
; i
++) {
983 pipe_so_target_reference((struct pipe_stream_output_target
**)&rctx
->so_targets
[i
], targets
[i
]);
985 for (; i
< rctx
->num_so_targets
; i
++) {
986 pipe_so_target_reference((struct pipe_stream_output_target
**)&rctx
->so_targets
[i
], NULL
);
989 rctx
->num_so_targets
= num_targets
;
990 rctx
->streamout_start
= num_targets
!= 0;
991 rctx
->streamout_append_bitmask
= append_bitmask
;
994 void r600_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
996 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
998 if (rctx
->sample_mask
.sample_mask
== (uint16_t)sample_mask
)
1001 rctx
->sample_mask
.sample_mask
= sample_mask
;
1002 r600_atom_dirty(rctx
, &rctx
->sample_mask
.atom
);
1005 static void r600_update_derived_state(struct r600_context
*rctx
)
1007 struct pipe_context
* ctx
= (struct pipe_context
*)rctx
;
1008 unsigned ps_dirty
= 0, blend_override
;
1010 if (!rctx
->blitter
->running
) {
1011 /* Decompress textures if needed. */
1012 if (rctx
->vs_samplers
.views
.compressed_depthtex_mask
) {
1013 r600_decompress_depth_textures(rctx
, &rctx
->vs_samplers
.views
);
1015 if (rctx
->ps_samplers
.views
.compressed_depthtex_mask
) {
1016 r600_decompress_depth_textures(rctx
, &rctx
->ps_samplers
.views
);
1018 if (rctx
->vs_samplers
.views
.compressed_colortex_mask
) {
1019 r600_decompress_color_textures(rctx
, &rctx
->vs_samplers
.views
);
1021 if (rctx
->ps_samplers
.views
.compressed_colortex_mask
) {
1022 r600_decompress_color_textures(rctx
, &rctx
->ps_samplers
.views
);
1026 r600_shader_select(ctx
, rctx
->ps_shader
, &ps_dirty
);
1028 if (rctx
->ps_shader
&& ((rctx
->sprite_coord_enable
&&
1029 (rctx
->ps_shader
->current
->sprite_coord_enable
!= rctx
->sprite_coord_enable
)) ||
1030 (rctx
->rasterizer
&& rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
))) {
1032 if (rctx
->chip_class
>= EVERGREEN
)
1033 evergreen_pipe_shader_ps(ctx
, rctx
->ps_shader
->current
);
1035 r600_pipe_shader_ps(ctx
, rctx
->ps_shader
->current
);
1041 r600_context_pipe_state_set(rctx
, &rctx
->ps_shader
->current
->rstate
);
1043 blend_override
= (rctx
->dual_src_blend
&&
1044 rctx
->ps_shader
->current
->nr_ps_color_outputs
< 2);
1046 if (blend_override
!= rctx
->blend_override
) {
1047 rctx
->blend_override
= blend_override
;
1048 r600_bind_blend_state_internal(rctx
,
1049 blend_override
? rctx
->no_blend
: rctx
->blend
);
1052 if (rctx
->chip_class
>= EVERGREEN
) {
1053 evergreen_update_dual_export_state(rctx
);
1055 r600_update_dual_export_state(rctx
);
1059 static unsigned r600_conv_prim_to_gs_out(unsigned mode
)
1061 static const int prim_conv
[] = {
1062 V_028A6C_OUTPRIM_TYPE_POINTLIST
,
1063 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1064 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1065 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1066 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1067 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1068 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1069 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1070 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1071 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1072 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1073 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1074 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1075 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1076 V_028A6C_OUTPRIM_TYPE_TRISTRIP
1078 assert(mode
< Elements(prim_conv
));
1080 return prim_conv
[mode
];
1083 void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*dinfo
)
1085 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1086 struct pipe_draw_info info
= *dinfo
;
1087 struct pipe_index_buffer ib
= {};
1088 unsigned prim
, ls_mask
= 0, i
;
1089 struct r600_block
*dirty_block
= NULL
, *next_block
= NULL
;
1090 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1094 if ((!info
.count
&& (info
.indexed
|| !info
.count_from_stream_output
)) ||
1095 !r600_conv_pipe_prim(info
.mode
, &prim
)) {
1100 if (!rctx
->vs_shader
) {
1105 r600_update_derived_state(rctx
);
1108 /* Initialize the index buffer struct. */
1109 pipe_resource_reference(&ib
.buffer
, rctx
->index_buffer
.buffer
);
1110 ib
.user_buffer
= rctx
->index_buffer
.user_buffer
;
1111 ib
.index_size
= rctx
->index_buffer
.index_size
;
1112 ib
.offset
= rctx
->index_buffer
.offset
+ info
.start
* ib
.index_size
;
1114 /* Translate or upload, if needed. */
1115 r600_translate_index_buffer(rctx
, &ib
, info
.count
);
1117 ptr
= (uint8_t*)ib
.user_buffer
;
1118 if (!ib
.buffer
&& ptr
) {
1119 u_upload_data(rctx
->uploader
, 0, info
.count
* ib
.index_size
,
1120 ptr
, &ib
.offset
, &ib
.buffer
);
1123 info
.index_bias
= info
.start
;
1126 if (rctx
->vgt
.id
!= R600_PIPE_STATE_VGT
) {
1127 rctx
->vgt
.id
= R600_PIPE_STATE_VGT
;
1128 rctx
->vgt
.nregs
= 0;
1129 r600_pipe_state_add_reg(&rctx
->vgt
, R_008958_VGT_PRIMITIVE_TYPE
, prim
);
1130 r600_pipe_state_add_reg(&rctx
->vgt
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, 0);
1131 r600_pipe_state_add_reg(&rctx
->vgt
, R_028408_VGT_INDX_OFFSET
, info
.index_bias
);
1132 r600_pipe_state_add_reg(&rctx
->vgt
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
, info
.restart_index
);
1133 r600_pipe_state_add_reg(&rctx
->vgt
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, info
.primitive_restart
);
1134 r600_pipe_state_add_reg(&rctx
->vgt
, R_03CFF4_SQ_VTX_START_INST_LOC
, info
.start_instance
);
1135 r600_pipe_state_add_reg(&rctx
->vgt
, R_028A0C_PA_SC_LINE_STIPPLE
, 0);
1136 r600_pipe_state_add_reg(&rctx
->vgt
, R_02881C_PA_CL_VS_OUT_CNTL
, 0);
1137 r600_pipe_state_add_reg(&rctx
->vgt
, R_028810_PA_CL_CLIP_CNTL
, 0);
1140 rctx
->vgt
.nregs
= 0;
1141 r600_pipe_state_mod_reg(&rctx
->vgt
, prim
);
1142 r600_pipe_state_mod_reg(&rctx
->vgt
, r600_conv_prim_to_gs_out(info
.mode
));
1143 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.index_bias
);
1144 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.restart_index
);
1145 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.primitive_restart
);
1146 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.start_instance
);
1148 if (prim
== V_008958_DI_PT_LINELIST
)
1150 else if (prim
== V_008958_DI_PT_LINESTRIP
||
1151 prim
== V_008958_DI_PT_LINELOOP
)
1153 r600_pipe_state_mod_reg(&rctx
->vgt
, S_028A0C_AUTO_RESET_CNTL(ls_mask
) | rctx
->pa_sc_line_stipple
);
1154 r600_pipe_state_mod_reg(&rctx
->vgt
,
1155 rctx
->vs_shader
->current
->pa_cl_vs_out_cntl
|
1156 (rctx
->rasterizer
->clip_plane_enable
& rctx
->vs_shader
->current
->shader
.clip_dist_write
));
1157 r600_pipe_state_mod_reg(&rctx
->vgt
,
1158 rctx
->pa_cl_clip_cntl
|
1159 (rctx
->vs_shader
->current
->shader
.clip_dist_write
||
1160 rctx
->vs_shader
->current
->shader
.vs_prohibit_ucps
?
1161 0 : rctx
->rasterizer
->clip_plane_enable
& 0x3F));
1163 r600_context_pipe_state_set(rctx
, &rctx
->vgt
);
1165 /* Enable stream out if needed. */
1166 if (rctx
->streamout_start
) {
1167 r600_context_streamout_begin(rctx
);
1168 rctx
->streamout_start
= FALSE
;
1171 /* Emit states (the function expects that we emit at most 17 dwords here). */
1172 r600_need_cs_space(rctx
, 0, TRUE
);
1173 r600_flush_emit(rctx
);
1175 for (i
= 0; i
< R600_MAX_ATOM
; i
++) {
1176 if (rctx
->atoms
[i
] == NULL
|| !rctx
->atoms
[i
]->dirty
) {
1179 r600_emit_atom(rctx
, rctx
->atoms
[i
]);
1181 LIST_FOR_EACH_ENTRY_SAFE(dirty_block
, next_block
, &rctx
->dirty
,list
) {
1182 r600_context_block_emit_dirty(rctx
, dirty_block
, 0 /* pkt_flags */);
1184 rctx
->pm4_dirty_cdwords
= 0;
1187 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NUM_INSTANCES
, 0, rctx
->predicate_drawing
);
1188 cs
->buf
[cs
->cdw
++] = info
.instance_count
;
1190 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_INDEX_TYPE
, 0, rctx
->predicate_drawing
);
1191 cs
->buf
[cs
->cdw
++] = ib
.index_size
== 4 ?
1192 (VGT_INDEX_32
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_32_BIT
: 0)) :
1193 (VGT_INDEX_16
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_16_BIT
: 0));
1195 va
= r600_resource_va(ctx
->screen
, ib
.buffer
);
1197 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX
, 3, rctx
->predicate_drawing
);
1198 cs
->buf
[cs
->cdw
++] = va
;
1199 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFF;
1200 cs
->buf
[cs
->cdw
++] = info
.count
;
1201 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_DMA
;
1202 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, rctx
->predicate_drawing
);
1203 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(rctx
, (struct r600_resource
*)ib
.buffer
, RADEON_USAGE_READ
);
1205 if (info
.count_from_stream_output
) {
1206 struct r600_so_target
*t
= (struct r600_so_target
*)info
.count_from_stream_output
;
1207 uint64_t va
= r600_resource_va(&rctx
->screen
->screen
, (void*)t
->filled_size
);
1209 r600_write_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
, t
->stride_in_dw
);
1211 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_COPY_DW
, 4, 0);
1212 cs
->buf
[cs
->cdw
++] = COPY_DW_SRC_IS_MEM
| COPY_DW_DST_IS_REG
;
1213 cs
->buf
[cs
->cdw
++] = va
& 0xFFFFFFFFUL
; /* src address lo */
1214 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFFUL
; /* src address hi */
1215 cs
->buf
[cs
->cdw
++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2; /* dst register */
1216 cs
->buf
[cs
->cdw
++] = 0; /* unused */
1218 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
1219 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(rctx
, t
->filled_size
, RADEON_USAGE_READ
);
1222 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX_AUTO
, 1, rctx
->predicate_drawing
);
1223 cs
->buf
[cs
->cdw
++] = info
.count
;
1224 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
1225 (info
.count_from_stream_output
? S_0287F0_USE_OPAQUE(1) : 0);
1228 /* Set the depth buffer as dirty. */
1229 if (rctx
->framebuffer
.zsbuf
) {
1230 struct pipe_surface
*surf
= rctx
->framebuffer
.zsbuf
;
1231 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
1233 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1235 if (rctx
->compressed_cb_mask
) {
1236 struct pipe_surface
*surf
;
1237 struct r600_texture
*rtex
;
1238 unsigned mask
= rctx
->compressed_cb_mask
;
1241 unsigned i
= u_bit_scan(&mask
);
1242 surf
= rctx
->framebuffer
.cbufs
[i
];
1243 rtex
= (struct r600_texture
*)surf
->texture
;
1245 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1250 pipe_resource_reference(&ib
.buffer
, NULL
);
1253 void r600_draw_rectangle(struct blitter_context
*blitter
,
1254 unsigned x1
, unsigned y1
, unsigned x2
, unsigned y2
, float depth
,
1255 enum blitter_attrib_type type
, const union pipe_color_union
*attrib
)
1257 struct r600_context
*rctx
= (struct r600_context
*)util_blitter_get_pipe(blitter
);
1258 struct pipe_viewport_state viewport
;
1259 struct pipe_resource
*buf
= NULL
;
1260 unsigned offset
= 0;
1263 if (type
== UTIL_BLITTER_ATTRIB_TEXCOORD
) {
1264 util_blitter_draw_rectangle(blitter
, x1
, y1
, x2
, y2
, depth
, type
, attrib
);
1268 /* Some operations (like color resolve on r6xx) don't work
1269 * with the conventional primitive types.
1270 * One that works is PT_RECTLIST, which we use here. */
1272 /* setup viewport */
1273 viewport
.scale
[0] = 1.0f
;
1274 viewport
.scale
[1] = 1.0f
;
1275 viewport
.scale
[2] = 1.0f
;
1276 viewport
.scale
[3] = 1.0f
;
1277 viewport
.translate
[0] = 0.0f
;
1278 viewport
.translate
[1] = 0.0f
;
1279 viewport
.translate
[2] = 0.0f
;
1280 viewport
.translate
[3] = 0.0f
;
1281 rctx
->context
.set_viewport_state(&rctx
->context
, &viewport
);
1283 /* Upload vertices. The hw rectangle has only 3 vertices,
1284 * I guess the 4th one is derived from the first 3.
1285 * The vertex specification should match u_blitter's vertex element state. */
1286 u_upload_alloc(rctx
->uploader
, 0, sizeof(float) * 24, &offset
, &buf
, (void**)&vb
);
1303 memcpy(vb
+4, attrib
->f
, sizeof(float)*4);
1304 memcpy(vb
+12, attrib
->f
, sizeof(float)*4);
1305 memcpy(vb
+20, attrib
->f
, sizeof(float)*4);
1309 util_draw_vertex_buffer(&rctx
->context
, NULL
, buf
, offset
,
1310 R600_PRIM_RECTANGLE_LIST
, 3, 2);
1311 pipe_resource_reference(&buf
, NULL
);
1314 void _r600_pipe_state_add_reg_bo(struct r600_context
*ctx
,
1315 struct r600_pipe_state
*state
,
1316 uint32_t offset
, uint32_t value
,
1317 uint32_t range_id
, uint32_t block_id
,
1318 struct r600_resource
*bo
,
1319 enum radeon_bo_usage usage
)
1322 struct r600_range
*range
;
1323 struct r600_block
*block
;
1325 if (bo
) assert(usage
);
1327 range
= &ctx
->range
[range_id
];
1328 block
= range
->blocks
[block_id
];
1329 state
->regs
[state
->nregs
].block
= block
;
1330 state
->regs
[state
->nregs
].id
= (offset
- block
->start_offset
) >> 2;
1332 state
->regs
[state
->nregs
].value
= value
;
1333 state
->regs
[state
->nregs
].bo
= bo
;
1334 state
->regs
[state
->nregs
].bo_usage
= usage
;
1337 assert(state
->nregs
< R600_BLOCK_MAX_REG
);
1340 void _r600_pipe_state_add_reg(struct r600_context
*ctx
,
1341 struct r600_pipe_state
*state
,
1342 uint32_t offset
, uint32_t value
,
1343 uint32_t range_id
, uint32_t block_id
)
1345 _r600_pipe_state_add_reg_bo(ctx
, state
, offset
, value
,
1346 range_id
, block_id
, NULL
, 0);
1349 uint32_t r600_translate_stencil_op(int s_op
)
1352 case PIPE_STENCIL_OP_KEEP
:
1353 return V_028800_STENCIL_KEEP
;
1354 case PIPE_STENCIL_OP_ZERO
:
1355 return V_028800_STENCIL_ZERO
;
1356 case PIPE_STENCIL_OP_REPLACE
:
1357 return V_028800_STENCIL_REPLACE
;
1358 case PIPE_STENCIL_OP_INCR
:
1359 return V_028800_STENCIL_INCR
;
1360 case PIPE_STENCIL_OP_DECR
:
1361 return V_028800_STENCIL_DECR
;
1362 case PIPE_STENCIL_OP_INCR_WRAP
:
1363 return V_028800_STENCIL_INCR_WRAP
;
1364 case PIPE_STENCIL_OP_DECR_WRAP
:
1365 return V_028800_STENCIL_DECR_WRAP
;
1366 case PIPE_STENCIL_OP_INVERT
:
1367 return V_028800_STENCIL_INVERT
;
1369 R600_ERR("Unknown stencil op %d", s_op
);
1376 uint32_t r600_translate_fill(uint32_t func
)
1379 case PIPE_POLYGON_MODE_FILL
:
1381 case PIPE_POLYGON_MODE_LINE
:
1383 case PIPE_POLYGON_MODE_POINT
:
1391 unsigned r600_tex_wrap(unsigned wrap
)
1395 case PIPE_TEX_WRAP_REPEAT
:
1396 return V_03C000_SQ_TEX_WRAP
;
1397 case PIPE_TEX_WRAP_CLAMP
:
1398 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER
;
1399 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1400 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL
;
1401 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1402 return V_03C000_SQ_TEX_CLAMP_BORDER
;
1403 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1404 return V_03C000_SQ_TEX_MIRROR
;
1405 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1406 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1407 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1408 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1409 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1410 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER
;
1414 unsigned r600_tex_filter(unsigned filter
)
1418 case PIPE_TEX_FILTER_NEAREST
:
1419 return V_03C000_SQ_TEX_XY_FILTER_POINT
;
1420 case PIPE_TEX_FILTER_LINEAR
:
1421 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR
;
1425 unsigned r600_tex_mipfilter(unsigned filter
)
1428 case PIPE_TEX_MIPFILTER_NEAREST
:
1429 return V_03C000_SQ_TEX_Z_FILTER_POINT
;
1430 case PIPE_TEX_MIPFILTER_LINEAR
:
1431 return V_03C000_SQ_TEX_Z_FILTER_LINEAR
;
1433 case PIPE_TEX_MIPFILTER_NONE
:
1434 return V_03C000_SQ_TEX_Z_FILTER_NONE
;
1438 unsigned r600_tex_compare(unsigned compare
)
1442 case PIPE_FUNC_NEVER
:
1443 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER
;
1444 case PIPE_FUNC_LESS
:
1445 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS
;
1446 case PIPE_FUNC_EQUAL
:
1447 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1448 case PIPE_FUNC_LEQUAL
:
1449 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1450 case PIPE_FUNC_GREATER
:
1451 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER
;
1452 case PIPE_FUNC_NOTEQUAL
:
1453 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1454 case PIPE_FUNC_GEQUAL
:
1455 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1456 case PIPE_FUNC_ALWAYS
:
1457 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS
;