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radeonsi: Fix sampler views for depth textures.
[mesa.git] / src / gallium / drivers / r600 / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_formats.h"
28 #include "r600d.h"
29
30 #include <errno.h>
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33
34 /* Copy from a full GPU texture to a transfer's staging one. */
35 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
36 {
37 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
38 struct pipe_resource *texture = transfer->resource;
39
40 ctx->resource_copy_region(ctx, &rtransfer->staging->b.b,
41 0, 0, 0, 0, texture, transfer->level,
42 &transfer->box);
43 }
44
45
46 /* Copy from a transfer's staging texture to a full GPU one. */
47 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
48 {
49 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
50 struct pipe_resource *texture = transfer->resource;
51 struct pipe_box sbox;
52
53 u_box_origin_2d(transfer->box.width, transfer->box.height, &sbox);
54
55 ctx->resource_copy_region(ctx, texture, transfer->level,
56 transfer->box.x, transfer->box.y, transfer->box.z,
57 &rtransfer->staging->b.b,
58 0, &sbox);
59 }
60
61 unsigned r600_texture_get_offset(struct r600_texture *rtex,
62 unsigned level, unsigned layer)
63 {
64 return rtex->surface.level[level].offset +
65 layer * rtex->surface.level[level].slice_size;
66 }
67
68 static int r600_init_surface(struct r600_screen *rscreen,
69 struct radeon_surface *surface,
70 const struct pipe_resource *ptex,
71 unsigned array_mode,
72 bool is_flushed_depth)
73 {
74 const struct util_format_description *desc =
75 util_format_description(ptex->format);
76 bool is_depth, is_stencil;
77
78 is_depth = util_format_has_depth(desc);
79 is_stencil = util_format_has_stencil(desc);
80
81 surface->npix_x = ptex->width0;
82 surface->npix_y = ptex->height0;
83 surface->npix_z = ptex->depth0;
84 surface->blk_w = util_format_get_blockwidth(ptex->format);
85 surface->blk_h = util_format_get_blockheight(ptex->format);
86 surface->blk_d = 1;
87 surface->array_size = 1;
88 surface->last_level = ptex->last_level;
89
90 if (rscreen->chip_class >= EVERGREEN && !is_flushed_depth &&
91 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
92 surface->bpe = 4; /* stencil is allocated separately on evergreen */
93 } else {
94 surface->bpe = util_format_get_blocksize(ptex->format);
95 /* align byte per element on dword */
96 if (surface->bpe == 3) {
97 surface->bpe = 4;
98 }
99 }
100
101 surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1;
102 surface->flags = 0;
103
104 switch (array_mode) {
105 case V_038000_ARRAY_1D_TILED_THIN1:
106 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
107 break;
108 case V_038000_ARRAY_2D_TILED_THIN1:
109 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
110 break;
111 case V_038000_ARRAY_LINEAR_ALIGNED:
112 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
113 break;
114 case V_038000_ARRAY_LINEAR_GENERAL:
115 default:
116 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE);
117 break;
118 }
119 switch (ptex->target) {
120 case PIPE_TEXTURE_1D:
121 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
122 break;
123 case PIPE_TEXTURE_RECT:
124 case PIPE_TEXTURE_2D:
125 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
126 break;
127 case PIPE_TEXTURE_3D:
128 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
129 break;
130 case PIPE_TEXTURE_1D_ARRAY:
131 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
132 surface->array_size = ptex->array_size;
133 break;
134 case PIPE_TEXTURE_2D_ARRAY:
135 case PIPE_TEXTURE_CUBE_ARRAY: /* cube array layout like 2d layout for now */
136 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
137 surface->array_size = ptex->array_size;
138 break;
139 case PIPE_TEXTURE_CUBE:
140 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
141 break;
142 case PIPE_BUFFER:
143 default:
144 return -EINVAL;
145 }
146 if (ptex->bind & PIPE_BIND_SCANOUT) {
147 surface->flags |= RADEON_SURF_SCANOUT;
148 }
149
150 if (!is_flushed_depth && is_depth) {
151 surface->flags |= RADEON_SURF_ZBUFFER;
152
153 if (is_stencil) {
154 surface->flags |= RADEON_SURF_SBUFFER |
155 RADEON_SURF_HAS_SBUFFER_MIPTREE;
156 }
157 }
158 return 0;
159 }
160
161 static int r600_setup_surface(struct pipe_screen *screen,
162 struct r600_texture *rtex,
163 unsigned pitch_in_bytes_override)
164 {
165 struct pipe_resource *ptex = &rtex->resource.b.b;
166 struct r600_screen *rscreen = (struct r600_screen*)screen;
167 unsigned i;
168 int r;
169
170 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
171 if (r) {
172 return r;
173 }
174 rtex->size = rtex->surface.bo_size;
175 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
176 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
177 * for those
178 */
179 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
180 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
181 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
182 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
183 rtex->surface.stencil_offset =
184 rtex->surface.stencil_level[0].offset = rtex->surface.level[0].slice_size;
185 }
186 }
187 for (i = 0; i <= ptex->last_level; i++) {
188 switch (rtex->surface.level[i].mode) {
189 case RADEON_SURF_MODE_LINEAR_ALIGNED:
190 rtex->array_mode[i] = V_038000_ARRAY_LINEAR_ALIGNED;
191 break;
192 case RADEON_SURF_MODE_1D:
193 rtex->array_mode[i] = V_038000_ARRAY_1D_TILED_THIN1;
194 break;
195 case RADEON_SURF_MODE_2D:
196 rtex->array_mode[i] = V_038000_ARRAY_2D_TILED_THIN1;
197 break;
198 default:
199 case RADEON_SURF_MODE_LINEAR:
200 rtex->array_mode[i] = 0;
201 break;
202 }
203 }
204 return 0;
205 }
206
207 static boolean r600_texture_get_handle(struct pipe_screen* screen,
208 struct pipe_resource *ptex,
209 struct winsys_handle *whandle)
210 {
211 struct r600_texture *rtex = (struct r600_texture*)ptex;
212 struct r600_resource *resource = &rtex->resource;
213 struct radeon_surface *surface = &rtex->surface;
214 struct r600_screen *rscreen = (struct r600_screen*)screen;
215
216 rscreen->ws->buffer_set_tiling(resource->buf,
217 NULL,
218 surface->level[0].mode >= RADEON_SURF_MODE_1D ?
219 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
220 surface->level[0].mode >= RADEON_SURF_MODE_2D ?
221 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
222 surface->bankw, surface->bankh,
223 surface->tile_split,
224 surface->stencil_tile_split,
225 surface->mtilea,
226 rtex->surface.level[0].pitch_bytes);
227
228 return rscreen->ws->buffer_get_handle(resource->buf,
229 rtex->surface.level[0].pitch_bytes, whandle);
230 }
231
232 static void r600_texture_destroy(struct pipe_screen *screen,
233 struct pipe_resource *ptex)
234 {
235 struct r600_texture *rtex = (struct r600_texture*)ptex;
236 struct r600_resource *resource = &rtex->resource;
237
238 if (rtex->flushed_depth_texture)
239 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
240
241 pb_reference(&resource->buf, NULL);
242 FREE(rtex);
243 }
244
245 static const struct u_resource_vtbl r600_texture_vtbl;
246
247 /* The number of samples can be specified independently of the texture. */
248 void r600_texture_get_fmask_info(struct r600_screen *rscreen,
249 struct r600_texture *rtex,
250 unsigned nr_samples,
251 struct r600_fmask_info *out)
252 {
253 /* FMASK is allocated pretty much like an ordinary texture.
254 * Here we use bpe in the units of bits, not bytes. */
255 struct radeon_surface fmask = rtex->surface;
256
257 switch (nr_samples) {
258 case 2:
259 /* This should be 8,1, but we should set nsamples > 1
260 * for the allocator to treat it as a multisample surface.
261 * Let's set 4,2 then. */
262 case 4:
263 fmask.bpe = 4;
264 fmask.nsamples = 2;
265 break;
266 case 8:
267 fmask.bpe = 8;
268 fmask.nsamples = 4;
269 break;
270 case 16:
271 fmask.bpe = 16;
272 fmask.nsamples = 4;
273 break;
274 default:
275 R600_ERR("Invalid sample count for FMASK allocation.\n");
276 return;
277 }
278
279 /* R600-R700 errata? Anyway, this fixes colorbuffer corruption. */
280 if (rscreen->chip_class <= R700) {
281 fmask.bpe *= 2;
282 }
283
284 if (rscreen->chip_class >= EVERGREEN) {
285 fmask.bankh = nr_samples <= 4 ? 4 : 1;
286 }
287
288 if (rscreen->ws->surface_init(rscreen->ws, &fmask)) {
289 R600_ERR("Got error in surface_init while allocating FMASK.\n");
290 return;
291 }
292 assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
293
294 out->bank_height = fmask.bankh;
295 out->alignment = MAX2(256, fmask.bo_alignment);
296 out->size = (fmask.bo_size + 7) / 8;
297 }
298
299 static void r600_texture_allocate_fmask(struct r600_screen *rscreen,
300 struct r600_texture *rtex)
301 {
302 struct r600_fmask_info fmask;
303
304 r600_texture_get_fmask_info(rscreen, rtex,
305 rtex->resource.b.b.nr_samples, &fmask);
306
307 /* Reserve space for FMASK while converting bits back to bytes. */
308 rtex->fmask_bank_height = fmask.bank_height;
309 rtex->fmask_offset = align(rtex->size, fmask.alignment);
310 rtex->fmask_size = fmask.size;
311 rtex->size = rtex->fmask_offset + rtex->fmask_size;
312 #if 0
313 printf("FMASK width=%u, height=%i, bits=%u, size=%u\n",
314 fmask.npix_x, fmask.npix_y, fmask.bpe * fmask.nsamples, rtex->fmask_size);
315 #endif
316 }
317
318 void r600_texture_get_cmask_info(struct r600_screen *rscreen,
319 struct r600_texture *rtex,
320 struct r600_cmask_info *out)
321 {
322 unsigned cmask_tile_width = 8;
323 unsigned cmask_tile_height = 8;
324 unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
325 unsigned element_bits = 4;
326 unsigned cmask_cache_bits = 1024;
327 unsigned num_pipes = rscreen->tiling_info.num_channels;
328 unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
329
330 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
331 unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
332 unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
333 unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
334 unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
335
336 unsigned pitch_elements = align(rtex->surface.npix_x, macro_tile_width);
337 unsigned height = align(rtex->surface.npix_y, macro_tile_height);
338
339 unsigned base_align = num_pipes * pipe_interleave_bytes;
340 unsigned slice_bytes =
341 ((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
342
343 assert(macro_tile_width % 128 == 0);
344 assert(macro_tile_height % 128 == 0);
345
346 out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
347 out->alignment = MAX2(256, base_align);
348 out->size = rtex->surface.array_size * align(slice_bytes, base_align);
349 }
350
351 static void r600_texture_allocate_cmask(struct r600_screen *rscreen,
352 struct r600_texture *rtex)
353 {
354 struct r600_cmask_info cmask;
355
356 r600_texture_get_cmask_info(rscreen, rtex, &cmask);
357
358 rtex->cmask_slice_tile_max = cmask.slice_tile_max;
359 rtex->cmask_offset = align(rtex->size, cmask.alignment);
360 rtex->cmask_size = cmask.size;
361 rtex->size = rtex->cmask_offset + rtex->cmask_size;
362 #if 0
363 printf("CMASK: macro tile width = %u, macro tile height = %u, "
364 "pitch elements = %u, height = %u, slice tile max = %u\n",
365 macro_tile_width, macro_tile_height, pitch_elements, height,
366 rtex->cmask_slice_tile_max);
367 #endif
368 }
369
370 DEBUG_GET_ONCE_BOOL_OPTION(print_texdepth, "R600_PRINT_TEXDEPTH", FALSE);
371
372 static struct r600_texture *
373 r600_texture_create_object(struct pipe_screen *screen,
374 const struct pipe_resource *base,
375 unsigned pitch_in_bytes_override,
376 struct pb_buffer *buf,
377 boolean alloc_bo,
378 struct radeon_surface *surface)
379 {
380 struct r600_texture *rtex;
381 struct r600_resource *resource;
382 struct r600_screen *rscreen = (struct r600_screen*)screen;
383 int r;
384
385 rtex = CALLOC_STRUCT(r600_texture);
386 if (rtex == NULL)
387 return NULL;
388
389 resource = &rtex->resource;
390 resource->b.b = *base;
391 resource->b.vtbl = &r600_texture_vtbl;
392 pipe_reference_init(&resource->b.b.reference, 1);
393 resource->b.b.screen = screen;
394 rtex->pitch_override = pitch_in_bytes_override;
395
396 /* don't include stencil-only formats which we don't support for rendering */
397 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
398
399 rtex->surface = *surface;
400 r = r600_setup_surface(screen, rtex,
401 pitch_in_bytes_override);
402 if (r) {
403 FREE(rtex);
404 return NULL;
405 }
406
407 if (base->nr_samples > 1 && !rtex->is_depth && alloc_bo) {
408 r600_texture_allocate_cmask(rscreen, rtex);
409 r600_texture_allocate_fmask(rscreen, rtex);
410 }
411
412 if (!rtex->is_depth && base->nr_samples > 1 &&
413 (!rtex->fmask_size || !rtex->cmask_size)) {
414 FREE(rtex);
415 return NULL;
416 }
417
418 /* Tiled depth textures utilize the non-displayable tile order. */
419 rtex->non_disp_tiling = rtex->is_depth && rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D;
420
421 /* Now create the backing buffer. */
422 if (!buf && alloc_bo) {
423 unsigned base_align = rtex->surface.bo_alignment;
424 unsigned usage = R600_TEX_IS_TILED(rtex, 0) ? PIPE_USAGE_STATIC : base->usage;
425
426 if (!r600_init_resource(rscreen, resource, rtex->size, base_align, base->bind, usage)) {
427 FREE(rtex);
428 return NULL;
429 }
430 } else if (buf) {
431 /* This is usually the window framebuffer. We want it in VRAM, always. */
432 resource->buf = buf;
433 resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);
434 resource->domains = RADEON_DOMAIN_VRAM;
435 }
436
437 if (rtex->cmask_size) {
438 /* Initialize the cmask to 0xCC (= compressed state). */
439 char *ptr = rscreen->ws->buffer_map(resource->cs_buf, NULL, PIPE_TRANSFER_WRITE);
440 memset(ptr + rtex->cmask_offset, 0xCC, rtex->cmask_size);
441 rscreen->ws->buffer_unmap(resource->cs_buf);
442 }
443
444 if (debug_get_option_print_texdepth() && rtex->is_depth && rtex->non_disp_tiling) {
445 printf("Texture: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
446 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
447 "bpe=%u, nsamples=%u, flags=%u\n",
448 rtex->surface.npix_x, rtex->surface.npix_y,
449 rtex->surface.npix_z, rtex->surface.blk_w,
450 rtex->surface.blk_h, rtex->surface.blk_d,
451 rtex->surface.array_size, rtex->surface.last_level,
452 rtex->surface.bpe, rtex->surface.nsamples,
453 rtex->surface.flags);
454 if (rtex->surface.flags & RADEON_SURF_ZBUFFER) {
455 for (int i = 0; i <= rtex->surface.last_level; i++) {
456 printf(" Z %i: offset=%llu, slice_size=%llu, npix_x=%u, "
457 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
458 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
459 i, (unsigned long long)rtex->surface.level[i].offset,
460 (unsigned long long)rtex->surface.level[i].slice_size,
461 rtex->surface.level[i].npix_x,
462 rtex->surface.level[i].npix_y,
463 rtex->surface.level[i].npix_z,
464 rtex->surface.level[i].nblk_x,
465 rtex->surface.level[i].nblk_y,
466 rtex->surface.level[i].nblk_z,
467 rtex->surface.level[i].pitch_bytes,
468 rtex->surface.level[i].mode);
469 }
470 }
471 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
472 for (int i = 0; i <= rtex->surface.last_level; i++) {
473 printf(" S %i: offset=%llu, slice_size=%llu, npix_x=%u, "
474 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
475 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
476 i, (unsigned long long)rtex->surface.stencil_level[i].offset,
477 (unsigned long long)rtex->surface.stencil_level[i].slice_size,
478 rtex->surface.stencil_level[i].npix_x,
479 rtex->surface.stencil_level[i].npix_y,
480 rtex->surface.stencil_level[i].npix_z,
481 rtex->surface.stencil_level[i].nblk_x,
482 rtex->surface.stencil_level[i].nblk_y,
483 rtex->surface.stencil_level[i].nblk_z,
484 rtex->surface.stencil_level[i].pitch_bytes,
485 rtex->surface.stencil_level[i].mode);
486 }
487 }
488 }
489 return rtex;
490 }
491
492 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
493 const struct pipe_resource *templ)
494 {
495 struct r600_screen *rscreen = (struct r600_screen*)screen;
496 struct radeon_surface surface;
497 const struct util_format_description *desc = util_format_description(templ->format);
498 unsigned array_mode;
499 int r;
500
501 /* Default tiling mode for staging textures. */
502 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
503
504 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats. That's not an issue,
505 * because 422 formats are used for videos, which prefer linear buffers
506 * for fast uploads anyway. */
507 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
508 desc->layout != UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
509 if (!(templ->bind & PIPE_BIND_SCANOUT) &&
510 templ->usage != PIPE_USAGE_STAGING &&
511 templ->usage != PIPE_USAGE_STREAM &&
512 templ->target != PIPE_TEXTURE_1D &&
513 templ->target != PIPE_TEXTURE_1D_ARRAY &&
514 templ->height0 > 3) {
515 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
516 } else if (util_format_is_compressed(templ->format)) {
517 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
518 }
519 }
520
521 r = r600_init_surface(rscreen, &surface, templ, array_mode,
522 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
523 if (r) {
524 return NULL;
525 }
526 r = rscreen->ws->surface_best(rscreen->ws, &surface);
527 if (r) {
528 return NULL;
529 }
530 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
531 0, NULL, TRUE, &surface);
532 }
533
534 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
535 struct pipe_resource *texture,
536 const struct pipe_surface *templ,
537 unsigned width, unsigned height)
538 {
539 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
540
541 assert(templ->u.tex.first_layer == templ->u.tex.last_layer);
542 if (surface == NULL)
543 return NULL;
544 pipe_reference_init(&surface->base.reference, 1);
545 pipe_resource_reference(&surface->base.texture, texture);
546 surface->base.context = pipe;
547 surface->base.format = templ->format;
548 surface->base.width = width;
549 surface->base.height = height;
550 surface->base.usage = templ->usage;
551 surface->base.u = templ->u;
552 return &surface->base;
553 }
554
555 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
556 struct pipe_resource *texture,
557 const struct pipe_surface *templ)
558 {
559 struct r600_texture *rtex = (struct r600_texture*)texture;
560 unsigned level = templ->u.tex.level;
561
562 return r600_create_surface_custom(pipe, texture, templ,
563 rtex->surface.level[level].npix_x,
564 rtex->surface.level[level].npix_y);
565 }
566
567 static void r600_surface_destroy(struct pipe_context *pipe,
568 struct pipe_surface *surface)
569 {
570 struct r600_surface *surf = (struct r600_surface*)surface;
571 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, NULL);
572 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, NULL);
573 pipe_resource_reference(&surface->texture, NULL);
574 FREE(surface);
575 }
576
577 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
578 const struct pipe_resource *templ,
579 struct winsys_handle *whandle)
580 {
581 struct r600_screen *rscreen = (struct r600_screen*)screen;
582 struct pb_buffer *buf = NULL;
583 unsigned stride = 0;
584 unsigned array_mode = 0;
585 enum radeon_bo_layout micro, macro;
586 struct radeon_surface surface;
587 int r;
588
589 /* Support only 2D textures without mipmaps */
590 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
591 templ->depth0 != 1 || templ->last_level != 0)
592 return NULL;
593
594 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
595 if (!buf)
596 return NULL;
597
598 rscreen->ws->buffer_get_tiling(buf, &micro, &macro,
599 &surface.bankw, &surface.bankh,
600 &surface.tile_split,
601 &surface.stencil_tile_split,
602 &surface.mtilea);
603
604 if (macro == RADEON_LAYOUT_TILED)
605 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
606 else if (micro == RADEON_LAYOUT_TILED)
607 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
608 else
609 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
610
611 r = r600_init_surface(rscreen, &surface, templ, array_mode, false);
612 if (r) {
613 return NULL;
614 }
615 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
616 stride, buf, FALSE, &surface);
617 }
618
619 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
620 struct pipe_resource *texture,
621 struct r600_texture **staging)
622 {
623 struct r600_texture *rtex = (struct r600_texture*)texture;
624 struct pipe_resource resource;
625 struct r600_texture **flushed_depth_texture = staging ?
626 staging : &rtex->flushed_depth_texture;
627
628 if (!staging && rtex->flushed_depth_texture)
629 return true; /* it's ready */
630
631 resource.target = texture->target;
632 resource.format = texture->format;
633 resource.width0 = texture->width0;
634 resource.height0 = texture->height0;
635 resource.depth0 = texture->depth0;
636 resource.array_size = texture->array_size;
637 resource.last_level = texture->last_level;
638 resource.nr_samples = texture->nr_samples;
639 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_STATIC;
640 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
641 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
642
643 if (staging)
644 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
645
646 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
647 if (*flushed_depth_texture == NULL) {
648 R600_ERR("failed to create temporary texture to hold flushed depth\n");
649 return false;
650 }
651
652 (*flushed_depth_texture)->is_flushing_texture = TRUE;
653 (*flushed_depth_texture)->non_disp_tiling = false;
654 return true;
655 }
656
657 static void *r600_texture_transfer_map(struct pipe_context *ctx,
658 struct pipe_resource *texture,
659 unsigned level,
660 unsigned usage,
661 const struct pipe_box *box,
662 struct pipe_transfer **ptransfer)
663 {
664 struct r600_context *rctx = (struct r600_context*)ctx;
665 struct r600_texture *rtex = (struct r600_texture*)texture;
666 struct pipe_resource resource;
667 struct r600_transfer *trans;
668 boolean use_staging_texture = FALSE;
669 enum pipe_format format = texture->format;
670 struct radeon_winsys_cs_handle *buf;
671 unsigned offset = 0;
672 char *map;
673
674 if ((texture->bind & PIPE_BIND_GLOBAL) && texture->target == PIPE_BUFFER) {
675 return r600_compute_global_transfer_map(ctx, texture, level, usage, box, ptransfer);
676 }
677
678 /* We cannot map a tiled texture directly because the data is
679 * in a different order, therefore we do detiling using a blit.
680 *
681 * Also, use a temporary in GTT memory for read transfers, as
682 * the CPU is much happier reading out of cached system memory
683 * than uncached VRAM.
684 */
685 if (R600_TEX_IS_TILED(rtex, level)) {
686 use_staging_texture = TRUE;
687 }
688
689 /* Use a staging texture for uploads if the underlying BO is busy. */
690 if (!(usage & PIPE_TRANSFER_READ) &&
691 (rctx->ws->cs_is_buffer_referenced(rctx->cs, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) ||
692 rctx->ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE))) {
693 use_staging_texture = TRUE;
694 }
695
696 if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) {
697 use_staging_texture = FALSE;
698 }
699
700 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) {
701 return NULL;
702 }
703
704 trans = CALLOC_STRUCT(r600_transfer);
705 if (trans == NULL)
706 return NULL;
707 trans->transfer.resource = texture;
708 trans->transfer.level = level;
709 trans->transfer.usage = usage;
710 trans->transfer.box = *box;
711 if (rtex->is_depth) {
712 /* XXX: only readback the rectangle which is being mapped?
713 */
714 /* XXX: when discard is true, no need to read back from depth texture
715 */
716 struct r600_texture *staging_depth;
717
718 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
719 R600_ERR("failed to create temporary texture to hold untiled copy\n");
720 FREE(trans);
721 return NULL;
722 }
723
724 r600_blit_decompress_depth(ctx, rtex, staging_depth,
725 level, level,
726 box->z, box->z + box->depth - 1,
727 0, 0);
728
729 trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
730 trans->offset = r600_texture_get_offset(staging_depth, level, box->z);
731 trans->staging = (struct r600_resource*)staging_depth;
732 } else if (use_staging_texture) {
733 resource.target = PIPE_TEXTURE_2D;
734 resource.format = texture->format;
735 resource.width0 = box->width;
736 resource.height0 = box->height;
737 resource.depth0 = 1;
738 resource.array_size = 1;
739 resource.last_level = 0;
740 resource.nr_samples = 0;
741 resource.usage = PIPE_USAGE_STAGING;
742 resource.bind = 0;
743 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
744 /* For texture reading, the temporary (detiled) texture is used as
745 * a render target when blitting from a tiled texture. */
746 if (usage & PIPE_TRANSFER_READ) {
747 resource.bind |= PIPE_BIND_RENDER_TARGET;
748 }
749 /* For texture writing, the temporary texture is used as a sampler
750 * when blitting into a tiled texture. */
751 if (usage & PIPE_TRANSFER_WRITE) {
752 resource.bind |= PIPE_BIND_SAMPLER_VIEW;
753 }
754 /* Create the temporary texture. */
755 trans->staging = (struct r600_resource*)ctx->screen->resource_create(ctx->screen, &resource);
756 if (trans->staging == NULL) {
757 R600_ERR("failed to create temporary texture to hold untiled copy\n");
758 FREE(trans);
759 return NULL;
760 }
761
762 trans->transfer.stride =
763 ((struct r600_texture *)trans->staging)->surface.level[0].pitch_bytes;
764 if (usage & PIPE_TRANSFER_READ) {
765 r600_copy_to_staging_texture(ctx, trans);
766 /* Always referenced in the blit. */
767 r600_flush(ctx, NULL, 0);
768 }
769 } else {
770 trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
771 trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
772 trans->offset = r600_texture_get_offset(rtex, level, box->z);
773 }
774
775 if (trans->staging) {
776 buf = ((struct r600_resource *)trans->staging)->cs_buf;
777 } else {
778 buf = ((struct r600_resource *)texture)->cs_buf;
779 }
780
781 if (rtex->is_depth || !trans->staging)
782 offset = trans->offset +
783 box->y / util_format_get_blockheight(format) * trans->transfer.stride +
784 box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
785
786 if (!(map = rctx->ws->buffer_map(buf, rctx->cs, usage))) {
787 pipe_resource_reference((struct pipe_resource**)&trans->staging, NULL);
788 FREE(trans);
789 return NULL;
790 }
791
792 *ptransfer = &trans->transfer;
793 return map + offset;
794 }
795
796 static void r600_texture_transfer_unmap(struct pipe_context *ctx,
797 struct pipe_transfer* transfer)
798 {
799 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
800 struct r600_context *rctx = (struct r600_context*)ctx;
801 struct radeon_winsys_cs_handle *buf;
802 struct pipe_resource *texture = transfer->resource;
803 struct r600_texture *rtex = (struct r600_texture*)texture;
804
805 if ((transfer->resource->bind & PIPE_BIND_GLOBAL) && transfer->resource->target == PIPE_BUFFER) {
806 return r600_compute_global_transfer_unmap(ctx, transfer);
807 }
808
809 if (rtransfer->staging) {
810 buf = ((struct r600_resource *)rtransfer->staging)->cs_buf;
811 } else {
812 buf = ((struct r600_resource *)transfer->resource)->cs_buf;
813 }
814 rctx->ws->buffer_unmap(buf);
815
816 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
817 if (rtex->is_depth) {
818 ctx->resource_copy_region(ctx, texture, transfer->level,
819 transfer->box.x, transfer->box.y, transfer->box.z,
820 &rtransfer->staging->b.b, transfer->level,
821 &transfer->box);
822 } else {
823 r600_copy_from_staging_texture(ctx, rtransfer);
824 }
825 }
826
827 if (rtransfer->staging)
828 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
829
830 FREE(transfer);
831 }
832
833 void r600_init_surface_functions(struct r600_context *r600)
834 {
835 r600->context.create_surface = r600_create_surface;
836 r600->context.surface_destroy = r600_surface_destroy;
837 }
838
839 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
840 const unsigned char *swizzle_view)
841 {
842 unsigned i;
843 unsigned char swizzle[4];
844 unsigned result = 0;
845 const uint32_t swizzle_shift[4] = {
846 16, 19, 22, 25,
847 };
848 const uint32_t swizzle_bit[4] = {
849 0, 1, 2, 3,
850 };
851
852 if (swizzle_view) {
853 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
854 } else {
855 memcpy(swizzle, swizzle_format, 4);
856 }
857
858 /* Get swizzle. */
859 for (i = 0; i < 4; i++) {
860 switch (swizzle[i]) {
861 case UTIL_FORMAT_SWIZZLE_Y:
862 result |= swizzle_bit[1] << swizzle_shift[i];
863 break;
864 case UTIL_FORMAT_SWIZZLE_Z:
865 result |= swizzle_bit[2] << swizzle_shift[i];
866 break;
867 case UTIL_FORMAT_SWIZZLE_W:
868 result |= swizzle_bit[3] << swizzle_shift[i];
869 break;
870 case UTIL_FORMAT_SWIZZLE_0:
871 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
872 break;
873 case UTIL_FORMAT_SWIZZLE_1:
874 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
875 break;
876 default: /* UTIL_FORMAT_SWIZZLE_X */
877 result |= swizzle_bit[0] << swizzle_shift[i];
878 }
879 }
880 return result;
881 }
882
883 /* texture format translate */
884 uint32_t r600_translate_texformat(struct pipe_screen *screen,
885 enum pipe_format format,
886 const unsigned char *swizzle_view,
887 uint32_t *word4_p, uint32_t *yuv_format_p)
888 {
889 uint32_t result = 0, word4 = 0, yuv_format = 0;
890 const struct util_format_description *desc;
891 boolean uniform = TRUE;
892 static int r600_enable_s3tc = -1;
893 bool is_srgb_valid = FALSE;
894
895 int i;
896 const uint32_t sign_bit[4] = {
897 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
898 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
899 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
900 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
901 };
902 desc = util_format_description(format);
903
904 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
905
906 /* Colorspace (return non-RGB formats directly). */
907 switch (desc->colorspace) {
908 /* Depth stencil formats */
909 case UTIL_FORMAT_COLORSPACE_ZS:
910 switch (format) {
911 case PIPE_FORMAT_Z16_UNORM:
912 result = FMT_16;
913 goto out_word4;
914 case PIPE_FORMAT_X24S8_UINT:
915 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
916 case PIPE_FORMAT_Z24X8_UNORM:
917 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
918 result = FMT_8_24;
919 goto out_word4;
920 case PIPE_FORMAT_S8X24_UINT:
921 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
922 case PIPE_FORMAT_X8Z24_UNORM:
923 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
924 result = FMT_24_8;
925 goto out_word4;
926 case PIPE_FORMAT_S8_UINT:
927 result = FMT_8;
928 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
929 goto out_word4;
930 case PIPE_FORMAT_Z32_FLOAT:
931 result = FMT_32_FLOAT;
932 goto out_word4;
933 case PIPE_FORMAT_X32_S8X24_UINT:
934 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
935 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
936 result = FMT_X24_8_32_FLOAT;
937 goto out_word4;
938 default:
939 goto out_unknown;
940 }
941
942 case UTIL_FORMAT_COLORSPACE_YUV:
943 yuv_format |= (1 << 30);
944 switch (format) {
945 case PIPE_FORMAT_UYVY:
946 case PIPE_FORMAT_YUYV:
947 default:
948 break;
949 }
950 goto out_unknown; /* XXX */
951
952 case UTIL_FORMAT_COLORSPACE_SRGB:
953 word4 |= S_038010_FORCE_DEGAMMA(1);
954 break;
955
956 default:
957 break;
958 }
959
960 if (r600_enable_s3tc == -1) {
961 struct r600_screen *rscreen = (struct r600_screen *)screen;
962 if (rscreen->info.drm_minor >= 9)
963 r600_enable_s3tc = 1;
964 else
965 r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
966 }
967
968 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
969 if (!r600_enable_s3tc)
970 goto out_unknown;
971
972 switch (format) {
973 case PIPE_FORMAT_RGTC1_SNORM:
974 case PIPE_FORMAT_LATC1_SNORM:
975 word4 |= sign_bit[0];
976 case PIPE_FORMAT_RGTC1_UNORM:
977 case PIPE_FORMAT_LATC1_UNORM:
978 result = FMT_BC4;
979 goto out_word4;
980 case PIPE_FORMAT_RGTC2_SNORM:
981 case PIPE_FORMAT_LATC2_SNORM:
982 word4 |= sign_bit[0] | sign_bit[1];
983 case PIPE_FORMAT_RGTC2_UNORM:
984 case PIPE_FORMAT_LATC2_UNORM:
985 result = FMT_BC5;
986 goto out_word4;
987 default:
988 goto out_unknown;
989 }
990 }
991
992 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
993
994 if (!r600_enable_s3tc)
995 goto out_unknown;
996
997 if (!util_format_s3tc_enabled) {
998 goto out_unknown;
999 }
1000
1001 switch (format) {
1002 case PIPE_FORMAT_DXT1_RGB:
1003 case PIPE_FORMAT_DXT1_RGBA:
1004 case PIPE_FORMAT_DXT1_SRGB:
1005 case PIPE_FORMAT_DXT1_SRGBA:
1006 result = FMT_BC1;
1007 is_srgb_valid = TRUE;
1008 goto out_word4;
1009 case PIPE_FORMAT_DXT3_RGBA:
1010 case PIPE_FORMAT_DXT3_SRGBA:
1011 result = FMT_BC2;
1012 is_srgb_valid = TRUE;
1013 goto out_word4;
1014 case PIPE_FORMAT_DXT5_RGBA:
1015 case PIPE_FORMAT_DXT5_SRGBA:
1016 result = FMT_BC3;
1017 is_srgb_valid = TRUE;
1018 goto out_word4;
1019 default:
1020 goto out_unknown;
1021 }
1022 }
1023
1024 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1025 switch (format) {
1026 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1027 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1028 result = FMT_GB_GR;
1029 goto out_word4;
1030 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1031 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1032 result = FMT_BG_RG;
1033 goto out_word4;
1034 default:
1035 goto out_unknown;
1036 }
1037 }
1038
1039 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1040 result = FMT_5_9_9_9_SHAREDEXP;
1041 goto out_word4;
1042 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1043 result = FMT_10_11_11_FLOAT;
1044 goto out_word4;
1045 }
1046
1047
1048 for (i = 0; i < desc->nr_channels; i++) {
1049 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1050 word4 |= sign_bit[i];
1051 }
1052 }
1053
1054 /* R8G8Bx_SNORM - XXX CxV8U8 */
1055
1056 /* See whether the components are of the same size. */
1057 for (i = 1; i < desc->nr_channels; i++) {
1058 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1059 }
1060
1061 /* Non-uniform formats. */
1062 if (!uniform) {
1063 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1064 desc->channel[0].pure_integer)
1065 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1066 switch(desc->nr_channels) {
1067 case 3:
1068 if (desc->channel[0].size == 5 &&
1069 desc->channel[1].size == 6 &&
1070 desc->channel[2].size == 5) {
1071 result = FMT_5_6_5;
1072 goto out_word4;
1073 }
1074 goto out_unknown;
1075 case 4:
1076 if (desc->channel[0].size == 5 &&
1077 desc->channel[1].size == 5 &&
1078 desc->channel[2].size == 5 &&
1079 desc->channel[3].size == 1) {
1080 result = FMT_1_5_5_5;
1081 goto out_word4;
1082 }
1083 if (desc->channel[0].size == 10 &&
1084 desc->channel[1].size == 10 &&
1085 desc->channel[2].size == 10 &&
1086 desc->channel[3].size == 2) {
1087 result = FMT_2_10_10_10;
1088 goto out_word4;
1089 }
1090 goto out_unknown;
1091 }
1092 goto out_unknown;
1093 }
1094
1095 /* Find the first non-VOID channel. */
1096 for (i = 0; i < 4; i++) {
1097 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1098 break;
1099 }
1100 }
1101
1102 if (i == 4)
1103 goto out_unknown;
1104
1105 /* uniform formats */
1106 switch (desc->channel[i].type) {
1107 case UTIL_FORMAT_TYPE_UNSIGNED:
1108 case UTIL_FORMAT_TYPE_SIGNED:
1109 #if 0
1110 if (!desc->channel[i].normalized &&
1111 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
1112 goto out_unknown;
1113 }
1114 #endif
1115 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1116 desc->channel[i].pure_integer)
1117 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1118
1119 switch (desc->channel[i].size) {
1120 case 4:
1121 switch (desc->nr_channels) {
1122 case 2:
1123 result = FMT_4_4;
1124 goto out_word4;
1125 case 4:
1126 result = FMT_4_4_4_4;
1127 goto out_word4;
1128 }
1129 goto out_unknown;
1130 case 8:
1131 switch (desc->nr_channels) {
1132 case 1:
1133 result = FMT_8;
1134 goto out_word4;
1135 case 2:
1136 result = FMT_8_8;
1137 goto out_word4;
1138 case 4:
1139 result = FMT_8_8_8_8;
1140 is_srgb_valid = TRUE;
1141 goto out_word4;
1142 }
1143 goto out_unknown;
1144 case 16:
1145 switch (desc->nr_channels) {
1146 case 1:
1147 result = FMT_16;
1148 goto out_word4;
1149 case 2:
1150 result = FMT_16_16;
1151 goto out_word4;
1152 case 4:
1153 result = FMT_16_16_16_16;
1154 goto out_word4;
1155 }
1156 goto out_unknown;
1157 case 32:
1158 switch (desc->nr_channels) {
1159 case 1:
1160 result = FMT_32;
1161 goto out_word4;
1162 case 2:
1163 result = FMT_32_32;
1164 goto out_word4;
1165 case 4:
1166 result = FMT_32_32_32_32;
1167 goto out_word4;
1168 }
1169 }
1170 goto out_unknown;
1171
1172 case UTIL_FORMAT_TYPE_FLOAT:
1173 switch (desc->channel[i].size) {
1174 case 16:
1175 switch (desc->nr_channels) {
1176 case 1:
1177 result = FMT_16_FLOAT;
1178 goto out_word4;
1179 case 2:
1180 result = FMT_16_16_FLOAT;
1181 goto out_word4;
1182 case 4:
1183 result = FMT_16_16_16_16_FLOAT;
1184 goto out_word4;
1185 }
1186 goto out_unknown;
1187 case 32:
1188 switch (desc->nr_channels) {
1189 case 1:
1190 result = FMT_32_FLOAT;
1191 goto out_word4;
1192 case 2:
1193 result = FMT_32_32_FLOAT;
1194 goto out_word4;
1195 case 4:
1196 result = FMT_32_32_32_32_FLOAT;
1197 goto out_word4;
1198 }
1199 }
1200 goto out_unknown;
1201 }
1202
1203 out_word4:
1204
1205 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid)
1206 return ~0;
1207 if (word4_p)
1208 *word4_p = word4;
1209 if (yuv_format_p)
1210 *yuv_format_p = yuv_format;
1211 return result;
1212 out_unknown:
1213 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1214 return ~0;
1215 }
1216
1217 static const struct u_resource_vtbl r600_texture_vtbl =
1218 {
1219 r600_texture_get_handle, /* get_handle */
1220 r600_texture_destroy, /* resource_destroy */
1221 r600_texture_transfer_map, /* transfer_map */
1222 NULL, /* transfer_flush_region */
1223 r600_texture_transfer_unmap, /* transfer_unmap */
1224 NULL /* transfer_inline_write */
1225 };