2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "r600_formats.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
34 /* Copy from a full GPU texture to a transfer's staging one. */
35 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
37 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
38 struct pipe_resource
*texture
= transfer
->resource
;
40 ctx
->resource_copy_region(ctx
, &rtransfer
->staging
->b
.b
,
41 0, 0, 0, 0, texture
, transfer
->level
,
46 /* Copy from a transfer's staging texture to a full GPU one. */
47 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
49 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
50 struct pipe_resource
*texture
= transfer
->resource
;
53 u_box_origin_2d(transfer
->box
.width
, transfer
->box
.height
, &sbox
);
55 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
56 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
57 &rtransfer
->staging
->b
.b
,
61 unsigned r600_texture_get_offset(struct r600_resource_texture
*rtex
,
62 unsigned level
, unsigned layer
)
64 unsigned offset
= rtex
->offset
[level
];
66 switch (rtex
->resource
.b
.b
.target
) {
68 case PIPE_TEXTURE_CUBE
:
70 return offset
+ layer
* rtex
->layer_size
[level
];
74 static unsigned r600_get_block_alignment(struct pipe_screen
*screen
,
75 enum pipe_format format
,
78 struct r600_screen
* rscreen
= (struct r600_screen
*)screen
;
79 unsigned pixsize
= util_format_get_blocksize(format
);
83 case V_038000_ARRAY_1D_TILED_THIN1
:
85 ((rscreen
->tiling_info
.group_bytes
/ 8 / pixsize
)));
87 case V_038000_ARRAY_2D_TILED_THIN1
:
88 p_align
= MAX2(rscreen
->tiling_info
.num_banks
,
89 (((rscreen
->tiling_info
.group_bytes
/ 8 / pixsize
)) *
90 rscreen
->tiling_info
.num_banks
)) * 8;
92 case V_038000_ARRAY_LINEAR_ALIGNED
:
93 p_align
= MAX2(64, rscreen
->tiling_info
.group_bytes
/ pixsize
);
95 case V_038000_ARRAY_LINEAR_GENERAL
:
97 p_align
= rscreen
->tiling_info
.group_bytes
/ pixsize
;
103 static unsigned r600_get_height_alignment(struct pipe_screen
*screen
,
106 struct r600_screen
* rscreen
= (struct r600_screen
*)screen
;
109 switch (array_mode
) {
110 case V_038000_ARRAY_2D_TILED_THIN1
:
111 h_align
= rscreen
->tiling_info
.num_channels
* 8;
113 case V_038000_ARRAY_1D_TILED_THIN1
:
114 case V_038000_ARRAY_LINEAR_ALIGNED
:
117 case V_038000_ARRAY_LINEAR_GENERAL
:
125 static unsigned r600_get_base_alignment(struct pipe_screen
*screen
,
126 enum pipe_format format
,
129 struct r600_screen
* rscreen
= (struct r600_screen
*)screen
;
130 unsigned pixsize
= util_format_get_blocksize(format
);
131 int p_align
= r600_get_block_alignment(screen
, format
, array_mode
);
132 int h_align
= r600_get_height_alignment(screen
, array_mode
);
135 switch (array_mode
) {
136 case V_038000_ARRAY_2D_TILED_THIN1
:
137 b_align
= MAX2(rscreen
->tiling_info
.num_banks
* rscreen
->tiling_info
.num_channels
* 8 * 8 * pixsize
,
138 p_align
* pixsize
* h_align
);
140 case V_038000_ARRAY_1D_TILED_THIN1
:
141 case V_038000_ARRAY_LINEAR_ALIGNED
:
142 case V_038000_ARRAY_LINEAR_GENERAL
:
144 b_align
= rscreen
->tiling_info
.group_bytes
;
150 static unsigned mip_minify(unsigned size
, unsigned level
)
153 val
= u_minify(size
, level
);
155 val
= util_next_power_of_two(val
);
159 static unsigned r600_texture_get_nblocksx(struct pipe_screen
*screen
,
160 struct r600_resource_texture
*rtex
,
163 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
;
164 unsigned nblocksx
, block_align
, width
;
165 unsigned blocksize
= util_format_get_blocksize(rtex
->real_format
);
167 if (rtex
->pitch_override
)
168 return rtex
->pitch_override
/ blocksize
;
170 width
= mip_minify(ptex
->width0
, level
);
171 nblocksx
= util_format_get_nblocksx(rtex
->real_format
, width
);
173 block_align
= r600_get_block_alignment(screen
, rtex
->real_format
,
174 rtex
->array_mode
[level
]);
175 nblocksx
= align(nblocksx
, block_align
);
179 static unsigned r600_texture_get_nblocksy(struct pipe_screen
*screen
,
180 struct r600_resource_texture
*rtex
,
183 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
;
184 unsigned height
, tile_height
;
186 height
= mip_minify(ptex
->height0
, level
);
187 height
= util_format_get_nblocksy(rtex
->real_format
, height
);
188 tile_height
= r600_get_height_alignment(screen
,
189 rtex
->array_mode
[level
]);
191 /* XXX Hack around an alignment issue. Less tests fail with this.
193 * The thing is depth-stencil buffers should be tiled, i.e.
194 * the alignment should be >=8. If I make them tiled, stencil starts
195 * working because it no longer overlaps with the depth buffer
196 * in memory, but texturing like drawpix-stencil breaks. */
197 if (util_format_is_depth_or_stencil(rtex
->real_format
) && tile_height
< 8)
200 height
= align(height
, tile_height
);
204 static void r600_texture_set_array_mode(struct pipe_screen
*screen
,
205 struct r600_resource_texture
*rtex
,
206 unsigned level
, unsigned array_mode
)
208 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
;
210 switch (array_mode
) {
211 case V_0280A0_ARRAY_LINEAR_GENERAL
:
212 case V_0280A0_ARRAY_LINEAR_ALIGNED
:
213 case V_0280A0_ARRAY_1D_TILED_THIN1
:
215 rtex
->array_mode
[level
] = array_mode
;
217 case V_0280A0_ARRAY_2D_TILED_THIN1
:
219 unsigned w
, h
, tile_height
, tile_width
;
221 tile_height
= r600_get_height_alignment(screen
, array_mode
);
222 tile_width
= r600_get_block_alignment(screen
, rtex
->real_format
, array_mode
);
224 w
= mip_minify(ptex
->width0
, level
);
225 h
= mip_minify(ptex
->height0
, level
);
226 if (w
<= tile_width
|| h
<= tile_height
)
227 rtex
->array_mode
[level
] = V_0280A0_ARRAY_1D_TILED_THIN1
;
229 rtex
->array_mode
[level
] = array_mode
;
235 static int r600_init_surface(struct radeon_surface
*surface
,
236 const struct pipe_resource
*ptex
,
237 unsigned array_mode
, bool is_transfer
)
239 surface
->npix_x
= ptex
->width0
;
240 surface
->npix_y
= ptex
->height0
;
241 surface
->npix_z
= ptex
->depth0
;
242 surface
->blk_w
= util_format_get_blockwidth(ptex
->format
);
243 surface
->blk_h
= util_format_get_blockheight(ptex
->format
);
245 surface
->array_size
= 1;
246 surface
->last_level
= ptex
->last_level
;
247 surface
->bpe
= util_format_get_blocksize(ptex
->format
);
248 /* align byte per element on dword */
249 if (surface
->bpe
== 3) {
252 surface
->nsamples
= 1;
254 switch (array_mode
) {
255 case V_038000_ARRAY_1D_TILED_THIN1
:
256 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_1D
, MODE
);
258 case V_038000_ARRAY_2D_TILED_THIN1
:
259 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_2D
, MODE
);
261 case V_038000_ARRAY_LINEAR_ALIGNED
:
262 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED
, MODE
);
264 case V_038000_ARRAY_LINEAR_GENERAL
:
266 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR
, MODE
);
269 switch (ptex
->target
) {
270 case PIPE_TEXTURE_1D
:
271 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D
, TYPE
);
273 case PIPE_TEXTURE_RECT
:
274 case PIPE_TEXTURE_2D
:
275 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D
, TYPE
);
277 case PIPE_TEXTURE_3D
:
278 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_3D
, TYPE
);
280 case PIPE_TEXTURE_1D_ARRAY
:
281 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY
, TYPE
);
282 surface
->array_size
= ptex
->array_size
;
284 case PIPE_TEXTURE_2D_ARRAY
:
285 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY
, TYPE
);
286 surface
->array_size
= ptex
->array_size
;
288 case PIPE_TEXTURE_CUBE
:
289 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP
, TYPE
);
295 if (ptex
->bind
& PIPE_BIND_SCANOUT
) {
296 surface
->flags
|= RADEON_SURF_SCANOUT
;
298 if (util_format_is_depth_and_stencil(ptex
->format
) && !is_transfer
) {
299 surface
->flags
|= RADEON_SURF_ZBUFFER
;
300 surface
->flags
|= RADEON_SURF_SBUFFER
;
306 static int r600_setup_surface(struct pipe_screen
*screen
,
307 struct r600_resource_texture
*rtex
,
309 unsigned pitch_in_bytes_override
)
311 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
;
312 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
316 r
= rscreen
->ws
->surface_init(rscreen
->ws
, &rtex
->surface
);
320 rtex
->size
= rtex
->surface
.bo_size
;
321 if (pitch_in_bytes_override
&& pitch_in_bytes_override
!= rtex
->surface
.level
[0].pitch_bytes
) {
322 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
325 rtex
->surface
.level
[0].nblk_x
= pitch_in_bytes_override
/ rtex
->surface
.bpe
;
326 rtex
->surface
.level
[0].pitch_bytes
= pitch_in_bytes_override
;
327 rtex
->surface
.level
[0].slice_size
= pitch_in_bytes_override
* rtex
->surface
.level
[0].nblk_y
;
328 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
329 rtex
->surface
.stencil_offset
= rtex
->surface
.level
[0].slice_size
;
332 for (i
= 0; i
<= ptex
->last_level
; i
++) {
333 rtex
->offset
[i
] = rtex
->surface
.level
[i
].offset
;
334 rtex
->layer_size
[i
] = rtex
->surface
.level
[i
].slice_size
;
335 rtex
->pitch_in_bytes
[i
] = rtex
->surface
.level
[i
].pitch_bytes
;
336 switch (rtex
->surface
.level
[i
].mode
) {
337 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
338 rtex
->array_mode
[i
] = V_038000_ARRAY_LINEAR_ALIGNED
;
340 case RADEON_SURF_MODE_1D
:
341 rtex
->array_mode
[i
] = V_038000_ARRAY_1D_TILED_THIN1
;
343 case RADEON_SURF_MODE_2D
:
344 rtex
->array_mode
[i
] = V_038000_ARRAY_2D_TILED_THIN1
;
347 case RADEON_SURF_MODE_LINEAR
:
348 rtex
->array_mode
[i
] = 0;
355 static void r600_setup_miptree(struct pipe_screen
*screen
,
356 struct r600_resource_texture
*rtex
,
359 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
;
360 enum chip_class chipc
= ((struct r600_screen
*)screen
)->chip_class
;
361 unsigned size
, layer_size
, i
, offset
;
362 unsigned nblocksx
, nblocksy
;
364 for (i
= 0, offset
= 0; i
<= ptex
->last_level
; i
++) {
365 unsigned blocksize
= util_format_get_blocksize(rtex
->real_format
);
366 unsigned base_align
= r600_get_base_alignment(screen
, rtex
->real_format
, array_mode
);
368 r600_texture_set_array_mode(screen
, rtex
, i
, array_mode
);
370 nblocksx
= r600_texture_get_nblocksx(screen
, rtex
, i
);
371 nblocksy
= r600_texture_get_nblocksy(screen
, rtex
, i
);
373 if (chipc
>= EVERGREEN
&& array_mode
== V_038000_ARRAY_LINEAR_GENERAL
)
374 layer_size
= align(nblocksx
, 64) * nblocksy
* blocksize
;
376 layer_size
= nblocksx
* nblocksy
* blocksize
;
378 if (ptex
->target
== PIPE_TEXTURE_CUBE
) {
380 size
= layer_size
* 8;
382 size
= layer_size
* 6;
384 else if (ptex
->target
== PIPE_TEXTURE_3D
)
385 size
= layer_size
* u_minify(ptex
->depth0
, i
);
387 size
= layer_size
* ptex
->array_size
;
389 /* align base image and start of miptree */
390 if ((i
== 0) || (i
== 1))
391 offset
= align(offset
, base_align
);
392 rtex
->offset
[i
] = offset
;
393 rtex
->layer_size
[i
] = layer_size
;
394 rtex
->pitch_in_blocks
[i
] = nblocksx
; /* CB talks in elements */
395 rtex
->pitch_in_bytes
[i
] = nblocksx
* blocksize
;
402 /* Figure out whether u_blitter will fallback to a transfer operation.
403 * If so, don't use a staging resource.
405 static boolean
permit_hardware_blit(struct pipe_screen
*screen
,
406 const struct pipe_resource
*res
)
410 if (util_format_is_depth_or_stencil(res
->format
))
411 bind
= PIPE_BIND_DEPTH_STENCIL
;
413 bind
= PIPE_BIND_RENDER_TARGET
;
415 /* hackaround for S3TC */
416 if (util_format_is_compressed(res
->format
))
419 if (!screen
->is_format_supported(screen
,
426 if (!screen
->is_format_supported(screen
,
430 PIPE_BIND_SAMPLER_VIEW
))
436 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
437 struct pipe_resource
*ptex
,
438 struct winsys_handle
*whandle
)
440 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)ptex
;
441 struct r600_resource
*resource
= &rtex
->resource
;
442 struct radeon_surface
*surface
= &rtex
->surface
;
443 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
445 rscreen
->ws
->buffer_set_tiling(resource
->buf
,
447 surface
->level
[0].mode
>= RADEON_SURF_MODE_1D
?
448 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
,
449 surface
->level
[0].mode
>= RADEON_SURF_MODE_2D
?
450 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
,
451 surface
->bankw
, surface
->bankh
,
453 surface
->stencil_tile_split
,
455 rtex
->pitch_in_bytes
[0]);
457 return rscreen
->ws
->buffer_get_handle(resource
->buf
,
458 rtex
->pitch_in_bytes
[0], whandle
);
461 static void r600_texture_destroy(struct pipe_screen
*screen
,
462 struct pipe_resource
*ptex
)
464 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)ptex
;
465 struct r600_resource
*resource
= &rtex
->resource
;
467 if (rtex
->flushed_depth_texture
)
468 pipe_resource_reference((struct pipe_resource
**)&rtex
->flushed_depth_texture
, NULL
);
471 pipe_resource_reference((struct pipe_resource
**)&rtex
->stencil
, NULL
);
473 pb_reference(&resource
->buf
, NULL
);
477 static const struct u_resource_vtbl r600_texture_vtbl
=
479 r600_texture_get_handle
, /* get_handle */
480 r600_texture_destroy
, /* resource_destroy */
481 r600_texture_get_transfer
, /* get_transfer */
482 r600_texture_transfer_destroy
, /* transfer_destroy */
483 r600_texture_transfer_map
, /* transfer_map */
484 NULL
, /* transfer_flush_region */
485 r600_texture_transfer_unmap
, /* transfer_unmap */
486 NULL
/* transfer_inline_write */
489 static struct r600_resource_texture
*
490 r600_texture_create_object(struct pipe_screen
*screen
,
491 const struct pipe_resource
*base
,
493 unsigned pitch_in_bytes_override
,
494 unsigned max_buffer_size
,
495 struct pb_buffer
*buf
,
497 struct radeon_surface
*surface
)
499 struct r600_resource_texture
*rtex
;
500 struct r600_resource
*resource
;
501 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
504 rtex
= CALLOC_STRUCT(r600_resource_texture
);
508 resource
= &rtex
->resource
;
509 resource
->b
.b
= *base
;
510 resource
->b
.vtbl
= &r600_texture_vtbl
;
511 pipe_reference_init(&resource
->b
.b
.reference
, 1);
512 resource
->b
.b
.screen
= screen
;
513 rtex
->pitch_override
= pitch_in_bytes_override
;
514 rtex
->real_format
= base
->format
;
516 /* We must split depth and stencil into two separate buffers on Evergreen. */
517 if (!(base
->flags
& R600_RESOURCE_FLAG_TRANSFER
) &&
518 ((struct r600_screen
*)screen
)->chip_class
>= EVERGREEN
&&
519 util_format_is_depth_and_stencil(base
->format
) &&
520 !rscreen
->use_surface_alloc
) {
521 struct pipe_resource stencil
;
522 unsigned stencil_pitch_override
= 0;
524 switch (base
->format
) {
525 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
526 rtex
->real_format
= PIPE_FORMAT_Z24X8_UNORM
;
528 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
529 rtex
->real_format
= PIPE_FORMAT_X8Z24_UNORM
;
531 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
532 rtex
->real_format
= PIPE_FORMAT_Z32_FLOAT
;
540 /* Divide the pitch in bytes by 4 for stencil, because it has a smaller pixel size. */
541 if (pitch_in_bytes_override
) {
542 assert(base
->format
== PIPE_FORMAT_Z24_UNORM_S8_UINT
||
543 base
->format
== PIPE_FORMAT_S8_UINT_Z24_UNORM
);
544 stencil_pitch_override
= pitch_in_bytes_override
/ 4;
547 /* Allocate the stencil buffer. */
549 stencil
.format
= PIPE_FORMAT_S8_UINT
;
550 rtex
->stencil
= r600_texture_create_object(screen
, &stencil
, array_mode
,
551 stencil_pitch_override
,
552 max_buffer_size
, NULL
, FALSE
, surface
);
553 if (!rtex
->stencil
) {
557 /* Proceed in creating the depth buffer. */
560 /* only mark depth textures the HW can hit as depth textures */
561 if (util_format_is_depth_or_stencil(rtex
->real_format
) && permit_hardware_blit(screen
, base
))
562 rtex
->is_depth
= true;
564 r600_setup_miptree(screen
, rtex
, array_mode
);
565 if (rscreen
->use_surface_alloc
) {
566 rtex
->surface
= *surface
;
567 r
= r600_setup_surface(screen
, rtex
, array_mode
,
568 pitch_in_bytes_override
);
575 /* If we initialized separate stencil for Evergreen. place it after depth. */
577 unsigned stencil_align
, stencil_offset
;
579 stencil_align
= r600_get_base_alignment(screen
, rtex
->stencil
->real_format
, array_mode
);
580 stencil_offset
= align(rtex
->size
, stencil_align
);
582 for (unsigned i
= 0; i
<= rtex
->stencil
->resource
.b
.b
.last_level
; i
++)
583 rtex
->stencil
->offset
[i
] += stencil_offset
;
585 rtex
->size
= stencil_offset
+ rtex
->stencil
->size
;
588 /* Now create the backing buffer. */
589 if (!buf
&& alloc_bo
) {
590 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
;
591 unsigned base_align
= r600_get_base_alignment(screen
, ptex
->format
, array_mode
);
593 if (rscreen
->use_surface_alloc
) {
594 base_align
= rtex
->surface
.bo_alignment
;
595 } else if (util_format_is_depth_or_stencil(rtex
->real_format
)) {
596 /* ugly work around depth buffer need stencil room at end of bo */
597 rtex
->size
+= ptex
->width0
* ptex
->height0
;
599 if (!r600_init_resource(rscreen
, resource
, rtex
->size
, base_align
, base
->bind
, base
->usage
)) {
600 pipe_resource_reference((struct pipe_resource
**)&rtex
->stencil
, NULL
);
606 resource
->cs_buf
= rscreen
->ws
->buffer_get_cs_handle(buf
);
607 resource
->domains
= RADEON_DOMAIN_GTT
| RADEON_DOMAIN_VRAM
;
611 pb_reference(&rtex
->stencil
->resource
.buf
, rtex
->resource
.buf
);
612 rtex
->stencil
->resource
.cs_buf
= rtex
->resource
.cs_buf
;
613 rtex
->stencil
->resource
.domains
= rtex
->resource
.domains
;
618 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
619 const struct pipe_resource
*templ
)
621 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
622 struct radeon_surface surface
;
623 unsigned array_mode
= 0;
626 if (!(templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)) {
627 if (rscreen
->use_surface_alloc
&&
628 !(templ
->bind
& PIPE_BIND_SCANOUT
) &&
629 templ
->usage
!= PIPE_USAGE_STAGING
&&
630 templ
->usage
!= PIPE_USAGE_STREAM
&&
631 permit_hardware_blit(screen
, templ
)) {
632 array_mode
= V_038000_ARRAY_2D_TILED_THIN1
;
633 } else if (util_format_is_compressed(templ
->format
)) {
634 array_mode
= V_038000_ARRAY_1D_TILED_THIN1
;
638 r
= r600_init_surface(&surface
, templ
, array_mode
,
639 templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
);
643 r
= rscreen
->ws
->surface_best(rscreen
->ws
, &surface
);
647 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
, array_mode
,
648 0, 0, NULL
, TRUE
, &surface
);
651 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
652 struct pipe_resource
*texture
,
653 const struct pipe_surface
*surf_tmpl
)
655 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
656 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
657 unsigned level
= surf_tmpl
->u
.tex
.level
;
659 assert(surf_tmpl
->u
.tex
.first_layer
== surf_tmpl
->u
.tex
.last_layer
);
662 pipe_reference_init(&surface
->base
.reference
, 1);
663 pipe_resource_reference(&surface
->base
.texture
, texture
);
664 surface
->base
.context
= pipe
;
665 surface
->base
.format
= surf_tmpl
->format
;
666 surface
->base
.width
= mip_minify(texture
->width0
, level
);
667 surface
->base
.height
= mip_minify(texture
->height0
, level
);
668 surface
->base
.usage
= surf_tmpl
->usage
;
669 surface
->base
.texture
= texture
;
670 surface
->base
.u
.tex
.first_layer
= surf_tmpl
->u
.tex
.first_layer
;
671 surface
->base
.u
.tex
.last_layer
= surf_tmpl
->u
.tex
.last_layer
;
672 surface
->base
.u
.tex
.level
= level
;
674 surface
->aligned_height
= r600_texture_get_nblocksy(pipe
->screen
,
676 return &surface
->base
;
679 static void r600_surface_destroy(struct pipe_context
*pipe
,
680 struct pipe_surface
*surface
)
682 pipe_resource_reference(&surface
->texture
, NULL
);
686 struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
687 const struct pipe_resource
*templ
,
688 struct winsys_handle
*whandle
)
690 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
691 struct pb_buffer
*buf
= NULL
;
693 unsigned array_mode
= 0;
694 enum radeon_bo_layout micro
, macro
;
695 struct radeon_surface surface
;
698 /* Support only 2D textures without mipmaps */
699 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
700 templ
->depth0
!= 1 || templ
->last_level
!= 0)
703 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
);
707 rscreen
->ws
->buffer_get_tiling(buf
, µ
, ¯o
,
708 &surface
.bankw
, &surface
.bankh
,
710 &surface
.stencil_tile_split
,
713 if (macro
== RADEON_LAYOUT_TILED
)
714 array_mode
= V_0280A0_ARRAY_2D_TILED_THIN1
;
715 else if (micro
== RADEON_LAYOUT_TILED
)
716 array_mode
= V_0280A0_ARRAY_1D_TILED_THIN1
;
720 r
= r600_init_surface(&surface
, templ
, array_mode
, 0);
724 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
, array_mode
,
725 stride
, 0, buf
, FALSE
, &surface
);
728 void r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
729 struct pipe_resource
*texture
)
731 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
732 struct pipe_resource resource
;
734 if (rtex
->flushed_depth_texture
)
735 return; /* it's ready */
737 resource
.target
= texture
->target
;
738 resource
.format
= texture
->format
;
739 resource
.width0
= texture
->width0
;
740 resource
.height0
= texture
->height0
;
741 resource
.depth0
= texture
->depth0
;
742 resource
.array_size
= texture
->array_size
;
743 resource
.last_level
= texture
->last_level
;
744 resource
.nr_samples
= texture
->nr_samples
;
745 resource
.usage
= PIPE_USAGE_DYNAMIC
;
746 resource
.bind
= texture
->bind
| PIPE_BIND_DEPTH_STENCIL
;
747 resource
.flags
= R600_RESOURCE_FLAG_TRANSFER
| texture
->flags
;
749 rtex
->flushed_depth_texture
= (struct r600_resource_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
750 if (rtex
->flushed_depth_texture
== NULL
) {
751 R600_ERR("failed to create temporary texture to hold untiled copy\n");
755 ((struct r600_resource_texture
*)rtex
->flushed_depth_texture
)->is_flushing_texture
= TRUE
;
758 void r600_texture_depth_flush(struct pipe_context
*ctx
,
759 struct pipe_resource
*texture
)
761 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
763 r600_init_flushed_depth_texture(ctx
, texture
);
765 if (!rtex
->flushed_depth_texture
)
768 /* XXX: only do this if the depth texture has actually changed:
770 r600_blit_uncompress_depth(ctx
, rtex
);
773 /* Needs adjustment for pixelformat:
775 static INLINE
unsigned u_box_volume( const struct pipe_box
*box
)
777 return box
->width
* box
->depth
* box
->height
;
780 struct pipe_transfer
* r600_texture_get_transfer(struct pipe_context
*ctx
,
781 struct pipe_resource
*texture
,
784 const struct pipe_box
*box
)
786 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
787 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
788 struct pipe_resource resource
;
789 struct r600_transfer
*trans
;
790 boolean use_staging_texture
= FALSE
;
792 /* We cannot map a tiled texture directly because the data is
793 * in a different order, therefore we do detiling using a blit.
795 * Also, use a temporary in GTT memory for read transfers, as
796 * the CPU is much happier reading out of cached system memory
797 * than uncached VRAM.
799 if (R600_TEX_IS_TILED(rtex
, level
)) {
800 use_staging_texture
= TRUE
;
803 if ((usage
& PIPE_TRANSFER_READ
) && u_box_volume(box
) > 1024)
804 use_staging_texture
= TRUE
;
806 /* Use a staging texture for uploads if the underlying BO is busy. */
807 if (!(usage
& PIPE_TRANSFER_READ
) &&
808 (rctx
->ws
->cs_is_buffer_referenced(rctx
->cs
, rtex
->resource
.cs_buf
, RADEON_USAGE_READWRITE
) ||
809 rctx
->ws
->buffer_is_busy(rtex
->resource
.buf
, RADEON_USAGE_READWRITE
))) {
810 use_staging_texture
= TRUE
;
813 if (!permit_hardware_blit(ctx
->screen
, texture
) ||
814 (texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
)) {
815 use_staging_texture
= FALSE
;
818 if (use_staging_texture
&& (usage
& PIPE_TRANSFER_MAP_DIRECTLY
)) {
822 trans
= CALLOC_STRUCT(r600_transfer
);
825 pipe_resource_reference(&trans
->transfer
.resource
, texture
);
826 trans
->transfer
.level
= level
;
827 trans
->transfer
.usage
= usage
;
828 trans
->transfer
.box
= *box
;
829 if (rtex
->is_depth
) {
830 /* XXX: only readback the rectangle which is being mapped?
832 /* XXX: when discard is true, no need to read back from depth texture
834 r600_texture_depth_flush(ctx
, texture
);
835 if (!rtex
->flushed_depth_texture
) {
836 R600_ERR("failed to create temporary texture to hold untiled copy\n");
837 pipe_resource_reference(&trans
->transfer
.resource
, NULL
);
841 trans
->transfer
.stride
= rtex
->flushed_depth_texture
->pitch_in_bytes
[level
];
842 trans
->offset
= r600_texture_get_offset(rtex
->flushed_depth_texture
, level
, box
->z
);
843 return &trans
->transfer
;
844 } else if (use_staging_texture
) {
845 resource
.target
= PIPE_TEXTURE_2D
;
846 resource
.format
= texture
->format
;
847 resource
.width0
= box
->width
;
848 resource
.height0
= box
->height
;
850 resource
.array_size
= 1;
851 resource
.last_level
= 0;
852 resource
.nr_samples
= 0;
853 resource
.usage
= PIPE_USAGE_STAGING
;
855 resource
.flags
= R600_RESOURCE_FLAG_TRANSFER
;
856 /* For texture reading, the temporary (detiled) texture is used as
857 * a render target when blitting from a tiled texture. */
858 if (usage
& PIPE_TRANSFER_READ
) {
859 resource
.bind
|= PIPE_BIND_RENDER_TARGET
;
861 /* For texture writing, the temporary texture is used as a sampler
862 * when blitting into a tiled texture. */
863 if (usage
& PIPE_TRANSFER_WRITE
) {
864 resource
.bind
|= PIPE_BIND_SAMPLER_VIEW
;
866 /* Create the temporary texture. */
867 trans
->staging
= (struct r600_resource
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
868 if (trans
->staging
== NULL
) {
869 R600_ERR("failed to create temporary texture to hold untiled copy\n");
870 pipe_resource_reference(&trans
->transfer
.resource
, NULL
);
875 trans
->transfer
.stride
=
876 ((struct r600_resource_texture
*)trans
->staging
)->pitch_in_bytes
[0];
877 if (usage
& PIPE_TRANSFER_READ
) {
878 r600_copy_to_staging_texture(ctx
, trans
);
879 /* Always referenced in the blit. */
880 r600_flush(ctx
, NULL
, 0);
882 return &trans
->transfer
;
884 trans
->transfer
.stride
= rtex
->pitch_in_bytes
[level
];
885 trans
->transfer
.layer_stride
= rtex
->layer_size
[level
];
886 trans
->offset
= r600_texture_get_offset(rtex
, level
, box
->z
);
887 return &trans
->transfer
;
890 void r600_texture_transfer_destroy(struct pipe_context
*ctx
,
891 struct pipe_transfer
*transfer
)
893 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
894 struct pipe_resource
*texture
= transfer
->resource
;
895 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
897 if (rtransfer
->staging
) {
898 if (transfer
->usage
& PIPE_TRANSFER_WRITE
) {
899 r600_copy_from_staging_texture(ctx
, rtransfer
);
901 pipe_resource_reference((struct pipe_resource
**)&rtransfer
->staging
, NULL
);
904 if (rtex
->is_depth
&& !rtex
->is_flushing_texture
) {
905 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtex
->flushed_depth_texture
) {
906 struct pipe_box sbox
;
908 u_box_origin_2d(texture
->width0
, texture
->height0
, &sbox
);
910 ctx
->resource_copy_region(ctx
, texture
, 0, 0, 0, 0,
911 &rtex
->flushed_depth_texture
->resource
.b
.b
, 0,
916 pipe_resource_reference(&transfer
->resource
, NULL
);
920 void* r600_texture_transfer_map(struct pipe_context
*ctx
,
921 struct pipe_transfer
* transfer
)
923 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
924 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
925 struct radeon_winsys_cs_handle
*buf
;
926 enum pipe_format format
= transfer
->resource
->format
;
930 if ((transfer
->resource
->bind
& PIPE_BIND_GLOBAL
) && transfer
->resource
->target
== PIPE_BUFFER
) {
931 return r600_compute_global_transfer_map(ctx
, transfer
);
934 if (rtransfer
->staging
) {
935 buf
= ((struct r600_resource
*)rtransfer
->staging
)->cs_buf
;
937 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)transfer
->resource
;
939 if (rtex
->flushed_depth_texture
)
940 buf
= ((struct r600_resource
*)rtex
->flushed_depth_texture
)->cs_buf
;
942 buf
= ((struct r600_resource
*)transfer
->resource
)->cs_buf
;
944 offset
= rtransfer
->offset
+
945 transfer
->box
.y
/ util_format_get_blockheight(format
) * transfer
->stride
+
946 transfer
->box
.x
/ util_format_get_blockwidth(format
) * util_format_get_blocksize(format
);
949 if (!(map
= rctx
->ws
->buffer_map(buf
, rctx
->cs
, transfer
->usage
))) {
956 void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
957 struct pipe_transfer
* transfer
)
959 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
960 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
961 struct radeon_winsys_cs_handle
*buf
;
963 if ((transfer
->resource
->bind
& PIPE_BIND_GLOBAL
) && transfer
->resource
->target
== PIPE_BUFFER
) {
964 return r600_compute_global_transfer_unmap(ctx
, transfer
);
967 if (rtransfer
->staging
) {
968 buf
= ((struct r600_resource
*)rtransfer
->staging
)->cs_buf
;
970 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)transfer
->resource
;
972 if (rtex
->flushed_depth_texture
) {
973 buf
= ((struct r600_resource
*)rtex
->flushed_depth_texture
)->cs_buf
;
975 buf
= ((struct r600_resource
*)transfer
->resource
)->cs_buf
;
978 rctx
->ws
->buffer_unmap(buf
);
981 void r600_init_surface_functions(struct r600_context
*r600
)
983 r600
->context
.create_surface
= r600_create_surface
;
984 r600
->context
.surface_destroy
= r600_surface_destroy
;
987 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
988 const unsigned char *swizzle_view
)
991 unsigned char swizzle
[4];
993 const uint32_t swizzle_shift
[4] = {
996 const uint32_t swizzle_bit
[4] = {
1001 util_format_compose_swizzles(swizzle_format
, swizzle_view
, swizzle
);
1003 memcpy(swizzle
, swizzle_format
, 4);
1007 for (i
= 0; i
< 4; i
++) {
1008 switch (swizzle
[i
]) {
1009 case UTIL_FORMAT_SWIZZLE_Y
:
1010 result
|= swizzle_bit
[1] << swizzle_shift
[i
];
1012 case UTIL_FORMAT_SWIZZLE_Z
:
1013 result
|= swizzle_bit
[2] << swizzle_shift
[i
];
1015 case UTIL_FORMAT_SWIZZLE_W
:
1016 result
|= swizzle_bit
[3] << swizzle_shift
[i
];
1018 case UTIL_FORMAT_SWIZZLE_0
:
1019 result
|= V_038010_SQ_SEL_0
<< swizzle_shift
[i
];
1021 case UTIL_FORMAT_SWIZZLE_1
:
1022 result
|= V_038010_SQ_SEL_1
<< swizzle_shift
[i
];
1024 default: /* UTIL_FORMAT_SWIZZLE_X */
1025 result
|= swizzle_bit
[0] << swizzle_shift
[i
];
1031 /* texture format translate */
1032 uint32_t r600_translate_texformat(struct pipe_screen
*screen
,
1033 enum pipe_format format
,
1034 const unsigned char *swizzle_view
,
1035 uint32_t *word4_p
, uint32_t *yuv_format_p
)
1037 uint32_t result
= 0, word4
= 0, yuv_format
= 0;
1038 const struct util_format_description
*desc
;
1039 boolean uniform
= TRUE
;
1040 static int r600_enable_s3tc
= -1;
1041 bool is_srgb_valid
= FALSE
;
1044 const uint32_t sign_bit
[4] = {
1045 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED
),
1046 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED
),
1047 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED
),
1048 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED
)
1050 desc
= util_format_description(format
);
1052 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
);
1054 /* Colorspace (return non-RGB formats directly). */
1055 switch (desc
->colorspace
) {
1056 /* Depth stencil formats */
1057 case UTIL_FORMAT_COLORSPACE_ZS
:
1059 case PIPE_FORMAT_Z16_UNORM
:
1062 case PIPE_FORMAT_X24S8_UINT
:
1063 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1064 case PIPE_FORMAT_Z24X8_UNORM
:
1065 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1068 case PIPE_FORMAT_S8X24_UINT
:
1069 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1070 case PIPE_FORMAT_X8Z24_UNORM
:
1071 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1074 case PIPE_FORMAT_S8_UINT
:
1076 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1078 case PIPE_FORMAT_Z32_FLOAT
:
1079 result
= FMT_32_FLOAT
;
1081 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1082 result
= FMT_X24_8_32_FLOAT
;
1088 case UTIL_FORMAT_COLORSPACE_YUV
:
1089 yuv_format
|= (1 << 30);
1091 case PIPE_FORMAT_UYVY
:
1092 case PIPE_FORMAT_YUYV
:
1096 goto out_unknown
; /* XXX */
1098 case UTIL_FORMAT_COLORSPACE_SRGB
:
1099 word4
|= S_038010_FORCE_DEGAMMA(1);
1106 if (r600_enable_s3tc
== -1) {
1107 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
1108 if (rscreen
->info
.drm_minor
>= 9)
1109 r600_enable_s3tc
= 1;
1111 r600_enable_s3tc
= debug_get_bool_option("R600_ENABLE_S3TC", FALSE
);
1114 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1115 if (!r600_enable_s3tc
)
1119 case PIPE_FORMAT_RGTC1_SNORM
:
1120 case PIPE_FORMAT_LATC1_SNORM
:
1121 word4
|= sign_bit
[0];
1122 case PIPE_FORMAT_RGTC1_UNORM
:
1123 case PIPE_FORMAT_LATC1_UNORM
:
1126 case PIPE_FORMAT_RGTC2_SNORM
:
1127 case PIPE_FORMAT_LATC2_SNORM
:
1128 word4
|= sign_bit
[0] | sign_bit
[1];
1129 case PIPE_FORMAT_RGTC2_UNORM
:
1130 case PIPE_FORMAT_LATC2_UNORM
:
1138 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1140 if (!r600_enable_s3tc
)
1143 if (!util_format_s3tc_enabled
) {
1148 case PIPE_FORMAT_DXT1_RGB
:
1149 case PIPE_FORMAT_DXT1_RGBA
:
1150 case PIPE_FORMAT_DXT1_SRGB
:
1151 case PIPE_FORMAT_DXT1_SRGBA
:
1153 is_srgb_valid
= TRUE
;
1155 case PIPE_FORMAT_DXT3_RGBA
:
1156 case PIPE_FORMAT_DXT3_SRGBA
:
1158 is_srgb_valid
= TRUE
;
1160 case PIPE_FORMAT_DXT5_RGBA
:
1161 case PIPE_FORMAT_DXT5_SRGBA
:
1163 is_srgb_valid
= TRUE
;
1170 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
1172 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
1173 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
1176 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
1177 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
1185 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1186 result
= FMT_5_9_9_9_SHAREDEXP
;
1188 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1189 result
= FMT_10_11_11_FLOAT
;
1194 for (i
= 0; i
< desc
->nr_channels
; i
++) {
1195 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1196 word4
|= sign_bit
[i
];
1200 /* R8G8Bx_SNORM - XXX CxV8U8 */
1202 /* See whether the components are of the same size. */
1203 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1204 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1207 /* Non-uniform formats. */
1209 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
1210 desc
->channel
[0].pure_integer
)
1211 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1212 switch(desc
->nr_channels
) {
1214 if (desc
->channel
[0].size
== 5 &&
1215 desc
->channel
[1].size
== 6 &&
1216 desc
->channel
[2].size
== 5) {
1222 if (desc
->channel
[0].size
== 5 &&
1223 desc
->channel
[1].size
== 5 &&
1224 desc
->channel
[2].size
== 5 &&
1225 desc
->channel
[3].size
== 1) {
1226 result
= FMT_1_5_5_5
;
1229 if (desc
->channel
[0].size
== 10 &&
1230 desc
->channel
[1].size
== 10 &&
1231 desc
->channel
[2].size
== 10 &&
1232 desc
->channel
[3].size
== 2) {
1233 result
= FMT_2_10_10_10
;
1241 /* Find the first non-VOID channel. */
1242 for (i
= 0; i
< 4; i
++) {
1243 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1251 /* uniform formats */
1252 switch (desc
->channel
[i
].type
) {
1253 case UTIL_FORMAT_TYPE_UNSIGNED
:
1254 case UTIL_FORMAT_TYPE_SIGNED
:
1256 if (!desc
->channel
[i
].normalized
&&
1257 desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
) {
1261 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
1262 desc
->channel
[i
].pure_integer
)
1263 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1265 switch (desc
->channel
[i
].size
) {
1267 switch (desc
->nr_channels
) {
1272 result
= FMT_4_4_4_4
;
1277 switch (desc
->nr_channels
) {
1285 result
= FMT_8_8_8_8
;
1286 is_srgb_valid
= TRUE
;
1291 switch (desc
->nr_channels
) {
1299 result
= FMT_16_16_16_16
;
1304 switch (desc
->nr_channels
) {
1312 result
= FMT_32_32_32_32
;
1318 case UTIL_FORMAT_TYPE_FLOAT
:
1319 switch (desc
->channel
[i
].size
) {
1321 switch (desc
->nr_channels
) {
1323 result
= FMT_16_FLOAT
;
1326 result
= FMT_16_16_FLOAT
;
1329 result
= FMT_16_16_16_16_FLOAT
;
1334 switch (desc
->nr_channels
) {
1336 result
= FMT_32_FLOAT
;
1339 result
= FMT_32_32_FLOAT
;
1342 result
= FMT_32_32_32_32_FLOAT
;
1351 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
&& !is_srgb_valid
)
1356 *yuv_format_p
= yuv_format
;
1359 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */