158ae227b1d78e51a0554339fad4d8b0af541ced
[mesa.git] / src / gallium / drivers / r600 / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include <errno.h>
28 #include <pipe/p_screen.h>
29 #include <util/u_format.h>
30 #include <util/u_math.h>
31 #include <util/u_inlines.h>
32 #include <util/u_memory.h>
33 #include "state_tracker/drm_driver.h"
34 #include "r600_screen.h"
35 #include "r600_context.h"
36 #include "r600_resource.h"
37 #include "r600_state_inlines.h"
38 #include "r600d.h"
39
40 extern struct u_resource_vtbl r600_texture_vtbl;
41
42 /* Copy from a tiled texture to a detiled one. */
43 static void r600_copy_from_tiled_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
44 {
45 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
46 struct pipe_resource *texture = transfer->resource;
47 struct pipe_subresource subdst;
48
49 subdst.face = 0;
50 subdst.level = 0;
51 ctx->resource_copy_region(ctx, rtransfer->linear_texture,
52 subdst, 0, 0, 0, texture, transfer->sr,
53 transfer->box.x, transfer->box.y, transfer->box.z,
54 transfer->box.width, transfer->box.height);
55 }
56
57 static unsigned long r600_texture_get_offset(struct r600_resource_texture *rtex,
58 unsigned level, unsigned zslice,
59 unsigned face)
60 {
61 unsigned long offset = rtex->offset[level];
62
63 switch (rtex->resource.base.b.target) {
64 case PIPE_TEXTURE_3D:
65 assert(face == 0);
66 return offset + zslice * rtex->layer_size[level];
67 case PIPE_TEXTURE_CUBE:
68 assert(zslice == 0);
69 return offset + face * rtex->layer_size[level];
70 default:
71 assert(zslice == 0 && face == 0);
72 return offset;
73 }
74 }
75
76 static void r600_setup_miptree(struct r600_resource_texture *rtex)
77 {
78 struct pipe_resource *ptex = &rtex->resource.base.b;
79 unsigned long w, h, pitch, size, layer_size, i, offset;
80
81 rtex->bpt = util_format_get_blocksize(ptex->format);
82 for (i = 0, offset = 0; i <= ptex->last_level; i++) {
83 w = u_minify(ptex->width0, i);
84 h = u_minify(ptex->height0, i);
85 h = util_next_power_of_two(h);
86 pitch = util_format_get_stride(ptex->format, align(w, 64));
87 pitch = align(pitch, 256);
88 layer_size = pitch * h;
89 if (ptex->target == PIPE_TEXTURE_CUBE)
90 size = layer_size * 6;
91 else
92 size = layer_size * u_minify(ptex->depth0, i);
93 rtex->offset[i] = offset;
94 rtex->layer_size[i] = layer_size;
95 rtex->pitch[i] = pitch;
96 rtex->width[i] = w;
97 rtex->height[i] = h;
98 offset += size;
99 }
100 rtex->size = offset;
101 }
102
103 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
104 const struct pipe_resource *templ)
105 {
106 struct r600_resource_texture *rtex;
107 struct r600_resource *resource;
108 struct radeon *radeon = (struct radeon *)screen->winsys;
109
110 rtex = CALLOC_STRUCT(r600_resource_texture);
111 if (!rtex) {
112 return NULL;
113 }
114 resource = &rtex->resource;
115 resource->base.b = *templ;
116 resource->base.vtbl = &r600_texture_vtbl;
117 pipe_reference_init(&resource->base.b.reference, 1);
118 resource->base.b.screen = screen;
119 r600_setup_miptree(rtex);
120
121 /* FIXME alignment 4096 enought ? too much ? */
122 resource->domain = r600_domain_from_usage(resource->base.b.bind);
123 resource->bo = radeon_bo(radeon, 0, rtex->size, 4096, NULL);
124 if (resource->bo == NULL) {
125 FREE(rtex);
126 return NULL;
127 }
128 return &resource->base.b;
129 }
130
131 static void r600_texture_destroy_state(struct pipe_resource *ptexture)
132 {
133 struct r600_resource_texture *rtexture = (struct r600_resource_texture*)ptexture;
134
135 for (int i = 0; i < PIPE_MAX_TEXTURE_LEVELS; i++) {
136 radeon_state_fini(&rtexture->scissor[i]);
137 radeon_state_fini(&rtexture->db[i]);
138 for (int j = 0; j < 8; j++) {
139 radeon_state_fini(&rtexture->cb[j][i]);
140 }
141 }
142 }
143
144 static void r600_texture_destroy(struct pipe_screen *screen,
145 struct pipe_resource *ptex)
146 {
147 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
148 struct r600_resource *resource = &rtex->resource;
149 struct radeon *radeon = (struct radeon *)screen->winsys;
150
151 if (resource->bo) {
152 radeon_bo_decref(radeon, resource->bo);
153 }
154 if (rtex->uncompressed) {
155 radeon_bo_decref(radeon, rtex->uncompressed);
156 }
157 r600_texture_destroy_state(ptex);
158 FREE(rtex);
159 }
160
161 static struct pipe_surface *r600_get_tex_surface(struct pipe_screen *screen,
162 struct pipe_resource *texture,
163 unsigned face, unsigned level,
164 unsigned zslice, unsigned flags)
165 {
166 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
167 struct pipe_surface *surface = CALLOC_STRUCT(pipe_surface);
168 unsigned long offset;
169
170 if (surface == NULL)
171 return NULL;
172 offset = r600_texture_get_offset(rtex, level, zslice, face);
173 pipe_reference_init(&surface->reference, 1);
174 pipe_resource_reference(&surface->texture, texture);
175 surface->format = texture->format;
176 surface->width = u_minify(texture->width0, level);
177 surface->height = u_minify(texture->height0, level);
178 surface->offset = offset;
179 surface->usage = flags;
180 surface->zslice = zslice;
181 surface->texture = texture;
182 surface->face = face;
183 surface->level = level;
184 return surface;
185 }
186
187 static void r600_tex_surface_destroy(struct pipe_surface *surface)
188 {
189 pipe_resource_reference(&surface->texture, NULL);
190 FREE(surface);
191 }
192
193 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
194 const struct pipe_resource *templ,
195 struct winsys_handle *whandle)
196 {
197 struct radeon *rw = (struct radeon*)screen->winsys;
198 struct r600_resource_texture *rtex;
199 struct r600_resource *resource;
200 struct radeon_bo *bo = NULL;
201
202 /* Support only 2D textures without mipmaps */
203 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
204 templ->depth0 != 1 || templ->last_level != 0)
205 return NULL;
206
207 rtex = CALLOC_STRUCT(r600_resource_texture);
208 if (rtex == NULL)
209 return NULL;
210
211 bo = radeon_bo(rw, whandle->handle, 0, 0, NULL);
212 if (bo == NULL) {
213 FREE(rtex);
214 return NULL;
215 }
216
217 resource = &rtex->resource;
218 resource->base.b = *templ;
219 resource->base.vtbl = &r600_texture_vtbl;
220 pipe_reference_init(&resource->base.b.reference, 1);
221 resource->base.b.screen = screen;
222 resource->bo = bo;
223 rtex->depth = 0;
224 rtex->pitch_override = whandle->stride;
225 rtex->bpt = util_format_get_blocksize(templ->format);
226 rtex->pitch[0] = whandle->stride;
227 rtex->width[0] = templ->width0;
228 rtex->height[0] = templ->height0;
229 rtex->offset[0] = 0;
230 rtex->size = align(rtex->pitch[0] * templ->height0, 64);
231
232 return &resource->base.b;
233 }
234
235 static unsigned int r600_texture_is_referenced(struct pipe_context *context,
236 struct pipe_resource *texture,
237 unsigned face, unsigned level)
238 {
239 /* FIXME */
240 return PIPE_REFERENCED_FOR_READ | PIPE_REFERENCED_FOR_WRITE;
241 }
242
243 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
244 struct pipe_resource *texture,
245 struct pipe_subresource sr,
246 unsigned usage,
247 const struct pipe_box *box)
248 {
249 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
250 struct pipe_resource resource;
251 struct r600_transfer *trans;
252
253 trans = CALLOC_STRUCT(r600_transfer);
254 if (trans == NULL)
255 return NULL;
256 pipe_resource_reference(&trans->transfer.resource, texture);
257 trans->transfer.sr = sr;
258 trans->transfer.usage = usage;
259 trans->transfer.box = *box;
260 trans->transfer.stride = rtex->pitch[sr.level];
261 trans->offset = r600_texture_get_offset(rtex, sr.level, box->z, sr.face);
262 if (rtex->tilled && !rtex->depth) {
263 resource.target = PIPE_TEXTURE_2D;
264 resource.format = texture->format;
265 resource.width0 = box->width;
266 resource.height0 = box->height;
267 resource.depth0 = 0;
268 resource.last_level = 0;
269 resource.nr_samples = 0;
270 resource.usage = PIPE_USAGE_DYNAMIC;
271 resource.bind = 0;
272 resource.flags = 0;
273 /* For texture reading, the temporary (detiled) texture is used as
274 * a render target when blitting from a tiled texture. */
275 if (usage & PIPE_TRANSFER_READ) {
276 resource.bind |= PIPE_BIND_RENDER_TARGET;
277 }
278 /* For texture writing, the temporary texture is used as a sampler
279 * when blitting into a tiled texture. */
280 if (usage & PIPE_TRANSFER_WRITE) {
281 resource.bind |= PIPE_BIND_SAMPLER_VIEW;
282 }
283 /* Create the temporary texture. */
284 trans->linear_texture = ctx->screen->resource_create(ctx->screen, &resource);
285 if (trans->linear_texture == NULL) {
286 R600_ERR("failed to create temporary texture to hold untiled copy\n");
287 pipe_resource_reference(&trans->transfer.resource, NULL);
288 FREE(trans);
289 return NULL;
290 }
291 if (usage & PIPE_TRANSFER_READ) {
292 /* We cannot map a tiled texture directly because the data is
293 * in a different order, therefore we do detiling using a blit. */
294 r600_copy_from_tiled_texture(ctx, trans);
295 /* Always referenced in the blit. */
296 ctx->flush(ctx, 0, NULL);
297 }
298 }
299 return &trans->transfer;
300 }
301
302 void r600_texture_transfer_destroy(struct pipe_context *ctx,
303 struct pipe_transfer *transfer)
304 {
305 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
306
307 if (rtransfer->linear_texture) {
308 pipe_resource_reference(&rtransfer->linear_texture, NULL);
309 }
310 pipe_resource_reference(&transfer->resource, NULL);
311 FREE(transfer);
312 }
313
314 void* r600_texture_transfer_map(struct pipe_context *ctx,
315 struct pipe_transfer* transfer)
316 {
317 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
318 struct radeon_bo *bo;
319 enum pipe_format format = transfer->resource->format;
320 struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
321 struct r600_resource_texture *rtex;
322 unsigned long offset = 0;
323 char *map;
324 int r;
325
326 r600_flush(ctx, 0, NULL);
327 if (rtransfer->linear_texture) {
328 bo = ((struct r600_resource *)rtransfer->linear_texture)->bo;
329 } else {
330 rtex = (struct r600_resource_texture*)transfer->resource;
331 if (rtex->depth) {
332 r = r600_texture_from_depth(ctx, rtex, transfer->sr.level);
333 if (r) {
334 return NULL;
335 }
336 r600_flush(ctx, 0, NULL);
337 bo = rtex->uncompressed;
338 } else {
339 bo = ((struct r600_resource *)transfer->resource)->bo;
340 }
341 offset = rtransfer->offset +
342 transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
343 transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
344 }
345 if (radeon_bo_map(radeon, bo)) {
346 return NULL;
347 }
348 radeon_bo_wait(radeon, bo);
349
350 map = bo->data;
351 return map + offset;
352 }
353
354 void r600_texture_transfer_unmap(struct pipe_context *ctx,
355 struct pipe_transfer* transfer)
356 {
357 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
358 struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
359 struct r600_resource_texture *rtex;
360 struct radeon_bo *bo;
361
362 if (rtransfer->linear_texture) {
363 bo = ((struct r600_resource *)rtransfer->linear_texture)->bo;
364 } else {
365 rtex = (struct r600_resource_texture*)transfer->resource;
366 if (rtex->depth) {
367 bo = rtex->uncompressed;
368 } else {
369 bo = ((struct r600_resource *)transfer->resource)->bo;
370 }
371 }
372 radeon_bo_unmap(radeon, bo);
373 }
374
375 struct u_resource_vtbl r600_texture_vtbl =
376 {
377 u_default_resource_get_handle, /* get_handle */
378 r600_texture_destroy, /* resource_destroy */
379 r600_texture_is_referenced, /* is_resource_referenced */
380 r600_texture_get_transfer, /* get_transfer */
381 r600_texture_transfer_destroy, /* transfer_destroy */
382 r600_texture_transfer_map, /* transfer_map */
383 u_default_transfer_flush_region,/* transfer_flush_region */
384 r600_texture_transfer_unmap, /* transfer_unmap */
385 u_default_transfer_inline_write /* transfer_inline_write */
386 };
387
388 void r600_init_screen_texture_functions(struct pipe_screen *screen)
389 {
390 screen->get_tex_surface = r600_get_tex_surface;
391 screen->tex_surface_destroy = r600_tex_surface_destroy;
392 }
393
394 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
395 const unsigned char *swizzle_view)
396 {
397 unsigned i;
398 unsigned char swizzle[4];
399 unsigned result = 0;
400 const uint32_t swizzle_shift[4] = {
401 16, 19, 22, 25,
402 };
403 const uint32_t swizzle_bit[4] = {
404 0, 1, 2, 3,
405 };
406
407 if (swizzle_view) {
408 /* Combine two sets of swizzles. */
409 for (i = 0; i < 4; i++) {
410 swizzle[i] = swizzle_view[i] <= UTIL_FORMAT_SWIZZLE_W ?
411 swizzle_format[swizzle_view[i]] : swizzle_view[i];
412 }
413 } else {
414 memcpy(swizzle, swizzle_format, 4);
415 }
416
417 /* Get swizzle. */
418 for (i = 0; i < 4; i++) {
419 switch (swizzle[i]) {
420 case UTIL_FORMAT_SWIZZLE_Y:
421 result |= swizzle_bit[1] << swizzle_shift[i];
422 break;
423 case UTIL_FORMAT_SWIZZLE_Z:
424 result |= swizzle_bit[2] << swizzle_shift[i];
425 break;
426 case UTIL_FORMAT_SWIZZLE_W:
427 result |= swizzle_bit[3] << swizzle_shift[i];
428 break;
429 case UTIL_FORMAT_SWIZZLE_0:
430 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
431 break;
432 case UTIL_FORMAT_SWIZZLE_1:
433 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
434 break;
435 default: /* UTIL_FORMAT_SWIZZLE_X */
436 result |= swizzle_bit[0] << swizzle_shift[i];
437 }
438 }
439 return result;
440 }
441
442 /* texture format translate */
443 uint32_t r600_translate_texformat(enum pipe_format format,
444 const unsigned char *swizzle_view,
445 uint32_t *word4_p, uint32_t *yuv_format_p)
446 {
447 uint32_t result = 0, word4 = 0, yuv_format = 0;
448 const struct util_format_description *desc;
449 boolean uniform = TRUE;
450 int i;
451 const uint32_t sign_bit[4] = {
452 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
453 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
454 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
455 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
456 };
457 desc = util_format_description(format);
458
459 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
460
461 /* Colorspace (return non-RGB formats directly). */
462 switch (desc->colorspace) {
463 /* Depth stencil formats */
464 case UTIL_FORMAT_COLORSPACE_ZS:
465 switch (format) {
466 case PIPE_FORMAT_Z16_UNORM:
467 result = V_0280A0_COLOR_16;
468 goto out_word4;
469 case PIPE_FORMAT_Z24X8_UNORM:
470 result = V_0280A0_COLOR_8_24;
471 goto out_word4;
472 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
473 result = V_0280A0_COLOR_8_24;
474 goto out_word4;
475 default:
476 goto out_unknown;
477 }
478
479 case UTIL_FORMAT_COLORSPACE_YUV:
480 yuv_format |= (1 << 30);
481 switch (format) {
482 case PIPE_FORMAT_UYVY:
483 case PIPE_FORMAT_YUYV:
484 default:
485 break;
486 }
487 goto out_unknown; /* TODO */
488
489 case UTIL_FORMAT_COLORSPACE_SRGB:
490 word4 |= S_038010_FORCE_DEGAMMA(1);
491 if (format == PIPE_FORMAT_L8A8_SRGB || format == PIPE_FORMAT_L8_SRGB)
492 goto out_unknown; /* fails for some reason - TODO */
493 break;
494
495 default:
496 break;
497 }
498
499 /* S3TC formats. TODO */
500 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
501 goto out_unknown;
502 }
503
504
505 for (i = 0; i < desc->nr_channels; i++) {
506 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
507 word4 |= sign_bit[i];
508 }
509 }
510
511 /* R8G8Bx_SNORM - TODO CxV8U8 */
512
513 /* RGTC - TODO */
514
515 /* See whether the components are of the same size. */
516 for (i = 1; i < desc->nr_channels; i++) {
517 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
518 }
519
520 /* Non-uniform formats. */
521 if (!uniform) {
522 switch(desc->nr_channels) {
523 case 3:
524 if (desc->channel[0].size == 5 &&
525 desc->channel[1].size == 6 &&
526 desc->channel[2].size == 5) {
527 result = V_0280A0_COLOR_5_6_5;
528 goto out_word4;
529 }
530 goto out_unknown;
531 case 4:
532 if (desc->channel[0].size == 5 &&
533 desc->channel[1].size == 5 &&
534 desc->channel[2].size == 5 &&
535 desc->channel[3].size == 1) {
536 result = V_0280A0_COLOR_1_5_5_5;
537 goto out_word4;
538 }
539 if (desc->channel[0].size == 10 &&
540 desc->channel[1].size == 10 &&
541 desc->channel[2].size == 10 &&
542 desc->channel[3].size == 2) {
543 result = V_0280A0_COLOR_10_10_10_2;
544 goto out_word4;
545 }
546 goto out_unknown;
547 }
548 goto out_unknown;
549 }
550
551 /* uniform formats */
552 switch (desc->channel[0].type) {
553 case UTIL_FORMAT_TYPE_UNSIGNED:
554 case UTIL_FORMAT_TYPE_SIGNED:
555 if (!desc->channel[0].normalized &&
556 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
557 goto out_unknown;
558 }
559
560 switch (desc->channel[0].size) {
561 case 4:
562 switch (desc->nr_channels) {
563 case 2:
564 result = V_0280A0_COLOR_4_4;
565 goto out_word4;
566 case 4:
567 result = V_0280A0_COLOR_4_4_4_4;
568 goto out_word4;
569 }
570 goto out_unknown;
571 case 8:
572 switch (desc->nr_channels) {
573 case 1:
574 result = V_0280A0_COLOR_8;
575 goto out_word4;
576 case 2:
577 result = V_0280A0_COLOR_8_8;
578 goto out_word4;
579 case 4:
580 result = V_0280A0_COLOR_8_8_8_8;
581 goto out_word4;
582 }
583 goto out_unknown;
584 case 16:
585 switch (desc->nr_channels) {
586 case 1:
587 result = V_0280A0_COLOR_16;
588 goto out_word4;
589 case 2:
590 result = V_0280A0_COLOR_16_16;
591 goto out_word4;
592 case 4:
593 result = V_0280A0_COLOR_16_16_16_16;
594 goto out_word4;
595 }
596 }
597 goto out_unknown;
598
599 case UTIL_FORMAT_TYPE_FLOAT:
600 switch (desc->channel[0].size) {
601 case 16:
602 switch (desc->nr_channels) {
603 case 1:
604 result = V_0280A0_COLOR_16_FLOAT;
605 goto out_word4;
606 case 2:
607 result = V_0280A0_COLOR_16_16_FLOAT;
608 goto out_word4;
609 case 4:
610 result = V_0280A0_COLOR_16_16_16_16_FLOAT;
611 goto out_word4;
612 }
613 goto out_unknown;
614 case 32:
615 switch (desc->nr_channels) {
616 case 1:
617 result = V_0280A0_COLOR_32_FLOAT;
618 goto out_word4;
619 case 2:
620 result = V_0280A0_COLOR_32_32_FLOAT;
621 goto out_word4;
622 case 4:
623 result = V_0280A0_COLOR_32_32_32_32_FLOAT;
624 goto out_word4;
625 }
626 }
627
628 }
629 out_word4:
630 if (word4_p)
631 *word4_p = word4;
632 if (yuv_format_p)
633 *yuv_format_p = yuv_format;
634 return result;
635 out_unknown:
636 // R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format));
637 return ~0;
638 }
639
640 int r600_texture_from_depth(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
641 {
642 struct r600_screen *rscreen = r600_screen(ctx->screen);
643 int r;
644
645 if (!rtexture->depth) {
646 /* This shouldn't happen maybe print a warning */
647 return 0;
648 }
649 if (rtexture->uncompressed && !rtexture->dirty) {
650 /* Uncompressed bo already in good state */
651 return 0;
652 }
653
654 /* allocate uncompressed texture */
655 if (rtexture->uncompressed == NULL) {
656 rtexture->uncompressed = radeon_bo(rscreen->rw, 0, rtexture->size, 4096, NULL);
657 if (rtexture->uncompressed == NULL) {
658 return -ENOMEM;
659 }
660 }
661
662 /* render a rectangle covering whole buffer to uncompress depth */
663 r = r600_blit_uncompress_depth(ctx, rtexture, level);
664 if (r) {
665 return r;
666 }
667
668 rtexture->dirty = 0;
669 return 0;
670 }
671
672
673
674 int r600_texture_scissor(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
675 {
676 struct r600_screen *rscreen = r600_screen(ctx->screen);
677 struct r600_context *rctx = r600_context(ctx);
678
679 if (!rtexture->scissor[level].cpm4) {
680 rctx->vtbl->texture_state_scissor(rscreen, rtexture, level);
681 }
682 return 0;
683 }
684
685 int r600_texture_cb(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned cb, unsigned level)
686 {
687 struct r600_screen *rscreen = r600_screen(ctx->screen);
688 struct r600_context *rctx = r600_context(ctx);
689
690 if (!rtexture->cb[cb][level].cpm4) {
691 rctx->vtbl->texture_state_cb(rscreen, rtexture, cb, level);
692 }
693 return 0;
694 }
695
696 int r600_texture_db(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
697 {
698 struct r600_screen *rscreen = r600_screen(ctx->screen);
699 struct r600_context *rctx = r600_context(ctx);
700
701 if (!rtexture->db[level].cpm4) {
702 rctx->vtbl->texture_state_db(rscreen, rtexture, level);
703 }
704 return 0;
705 }
706
707 int r600_texture_viewport(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
708 {
709 struct r600_screen *rscreen = r600_screen(ctx->screen);
710 struct r600_context *rctx = r600_context(ctx);
711
712 if (!rtexture->viewport[level].cpm4) {
713 rctx->vtbl->texture_state_viewport(rscreen, rtexture, level);
714 }
715 return 0;
716 }