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18460419f859937fa71cc3eec476051b7f8777e9
[mesa.git] / src / gallium / drivers / r600 / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include <errno.h>
28 #include <pipe/p_screen.h>
29 #include <util/u_format.h>
30 #include <util/u_format_s3tc.h>
31 #include <util/u_math.h>
32 #include <util/u_inlines.h>
33 #include <util/u_memory.h>
34 #include "state_tracker/drm_driver.h"
35 #include "pipebuffer/pb_buffer.h"
36 #include "r600_pipe.h"
37 #include "r600_resource.h"
38 #include "r600d.h"
39 #include "r600_formats.h"
40
41 /* Copy from a full GPU texture to a transfer's staging one. */
42 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
43 {
44 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
45 struct pipe_resource *texture = transfer->resource;
46
47 ctx->resource_copy_region(ctx, rtransfer->staging_texture,
48 0, 0, 0, 0, texture, transfer->level,
49 &transfer->box);
50 }
51
52
53 /* Copy from a transfer's staging texture to a full GPU one. */
54 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
55 {
56 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
57 struct pipe_resource *texture = transfer->resource;
58 struct pipe_box sbox;
59
60 sbox.x = sbox.y = sbox.z = 0;
61 sbox.width = transfer->box.width;
62 sbox.height = transfer->box.height;
63 /* XXX that might be wrong */
64 sbox.depth = 1;
65 ctx->resource_copy_region(ctx, texture, transfer->level,
66 transfer->box.x, transfer->box.y, transfer->box.z,
67 rtransfer->staging_texture,
68 0, &sbox);
69
70 ctx->flush(ctx, NULL);
71 }
72
73 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
74 unsigned level, unsigned layer)
75 {
76 unsigned offset = rtex->offset[level];
77
78 switch (rtex->resource.b.b.b.target) {
79 case PIPE_TEXTURE_3D:
80 case PIPE_TEXTURE_CUBE:
81 default:
82 return offset + layer * rtex->layer_size[level];
83 }
84 }
85
86 static unsigned r600_get_block_alignment(struct pipe_screen *screen,
87 enum pipe_format format,
88 unsigned array_mode)
89 {
90 struct r600_screen* rscreen = (struct r600_screen *)screen;
91 unsigned pixsize = util_format_get_blocksize(format);
92 int p_align;
93
94 switch(array_mode) {
95 case V_038000_ARRAY_1D_TILED_THIN1:
96 p_align = MAX2(8,
97 ((rscreen->tiling_info->group_bytes / 8 / pixsize)));
98 break;
99 case V_038000_ARRAY_2D_TILED_THIN1:
100 p_align = MAX2(rscreen->tiling_info->num_banks,
101 (((rscreen->tiling_info->group_bytes / 8 / pixsize)) *
102 rscreen->tiling_info->num_banks)) * 8;
103 break;
104 case V_038000_ARRAY_LINEAR_ALIGNED:
105 p_align = MAX2(64, rscreen->tiling_info->group_bytes / pixsize);
106 break;
107 case V_038000_ARRAY_LINEAR_GENERAL:
108 default:
109 p_align = rscreen->tiling_info->group_bytes / pixsize;
110 break;
111 }
112 return p_align;
113 }
114
115 static unsigned r600_get_height_alignment(struct pipe_screen *screen,
116 unsigned array_mode)
117 {
118 struct r600_screen* rscreen = (struct r600_screen *)screen;
119 int h_align;
120
121 switch (array_mode) {
122 case V_038000_ARRAY_2D_TILED_THIN1:
123 h_align = rscreen->tiling_info->num_channels * 8;
124 break;
125 case V_038000_ARRAY_1D_TILED_THIN1:
126 case V_038000_ARRAY_LINEAR_ALIGNED:
127 h_align = 8;
128 break;
129 case V_038000_ARRAY_LINEAR_GENERAL:
130 default:
131 h_align = 1;
132 break;
133 }
134 return h_align;
135 }
136
137 static unsigned r600_get_base_alignment(struct pipe_screen *screen,
138 enum pipe_format format,
139 unsigned array_mode)
140 {
141 struct r600_screen* rscreen = (struct r600_screen *)screen;
142 unsigned pixsize = util_format_get_blocksize(format);
143 int p_align = r600_get_block_alignment(screen, format, array_mode);
144 int h_align = r600_get_height_alignment(screen, array_mode);
145 int b_align;
146
147 switch (array_mode) {
148 case V_038000_ARRAY_2D_TILED_THIN1:
149 b_align = MAX2(rscreen->tiling_info->num_banks * rscreen->tiling_info->num_channels * 8 * 8 * pixsize,
150 p_align * pixsize * h_align);
151 break;
152 case V_038000_ARRAY_1D_TILED_THIN1:
153 case V_038000_ARRAY_LINEAR_ALIGNED:
154 case V_038000_ARRAY_LINEAR_GENERAL:
155 default:
156 b_align = rscreen->tiling_info->group_bytes;
157 break;
158 }
159 return b_align;
160 }
161
162 static unsigned mip_minify(unsigned size, unsigned level)
163 {
164 unsigned val;
165 val = u_minify(size, level);
166 if (level > 0)
167 val = util_next_power_of_two(val);
168 return val;
169 }
170
171 static unsigned r600_texture_get_nblocksx(struct pipe_screen *screen,
172 struct r600_resource_texture *rtex,
173 unsigned level)
174 {
175 struct pipe_resource *ptex = &rtex->resource.b.b.b;
176 unsigned nblocksx, block_align, width;
177 unsigned blocksize = util_format_get_blocksize(ptex->format);
178
179 if (rtex->pitch_override)
180 return rtex->pitch_override / blocksize;
181
182 width = mip_minify(ptex->width0, level);
183 nblocksx = util_format_get_nblocksx(ptex->format, width);
184
185 block_align = r600_get_block_alignment(screen, ptex->format,
186 rtex->array_mode[level]);
187 nblocksx = align(nblocksx, block_align);
188 return nblocksx;
189 }
190
191 static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen,
192 struct r600_resource_texture *rtex,
193 unsigned level)
194 {
195 struct pipe_resource *ptex = &rtex->resource.b.b.b;
196 unsigned height, tile_height;
197
198 height = mip_minify(ptex->height0, level);
199 height = util_format_get_nblocksy(ptex->format, height);
200 tile_height = r600_get_height_alignment(screen,
201 rtex->array_mode[level]);
202 height = align(height, tile_height);
203 return height;
204 }
205
206 static void r600_texture_set_array_mode(struct pipe_screen *screen,
207 struct r600_resource_texture *rtex,
208 unsigned level, unsigned array_mode)
209 {
210 struct pipe_resource *ptex = &rtex->resource.b.b.b;
211
212 switch (array_mode) {
213 case V_0280A0_ARRAY_LINEAR_GENERAL:
214 case V_0280A0_ARRAY_LINEAR_ALIGNED:
215 case V_0280A0_ARRAY_1D_TILED_THIN1:
216 default:
217 rtex->array_mode[level] = array_mode;
218 break;
219 case V_0280A0_ARRAY_2D_TILED_THIN1:
220 {
221 unsigned w, h, tile_height, tile_width;
222
223 tile_height = r600_get_height_alignment(screen, array_mode);
224 tile_width = r600_get_block_alignment(screen, ptex->format, array_mode);
225
226 w = mip_minify(ptex->width0, level);
227 h = mip_minify(ptex->height0, level);
228 if (w <= tile_width || h <= tile_height)
229 rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1;
230 else
231 rtex->array_mode[level] = array_mode;
232 }
233 break;
234 }
235 }
236
237 static void r600_setup_miptree(struct pipe_screen *screen,
238 struct r600_resource_texture *rtex,
239 unsigned array_mode)
240 {
241 struct pipe_resource *ptex = &rtex->resource.b.b.b;
242 struct radeon *radeon = (struct radeon *)screen->winsys;
243 enum chip_class chipc = r600_get_family_class(radeon);
244 unsigned size, layer_size, i, offset;
245 unsigned nblocksx, nblocksy, extra_size = 0;
246
247 for (i = 0, offset = 0; i <= ptex->last_level; i++) {
248 unsigned blocksize = util_format_get_blocksize(ptex->format);
249 unsigned base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
250
251 r600_texture_set_array_mode(screen, rtex, i, array_mode);
252
253 nblocksx = r600_texture_get_nblocksx(screen, rtex, i);
254 nblocksy = r600_texture_get_nblocksy(screen, rtex, i);
255
256 layer_size = nblocksx * nblocksy * blocksize;
257 if (ptex->target == PIPE_TEXTURE_CUBE) {
258 if (chipc >= R700)
259 size = layer_size * 8;
260 else
261 size = layer_size * 6;
262 }
263 else if (ptex->target == PIPE_TEXTURE_3D)
264 size = layer_size * u_minify(ptex->depth0, i);
265 else
266 size = layer_size * ptex->array_size;
267
268 /* evergreen stores depth and stencil separately */
269 if ((chipc >= EVERGREEN) && util_format_is_depth_or_stencil(ptex->format))
270 extra_size = align(extra_size + (nblocksx * nblocksy * 1), base_align);
271
272 /* align base image and start of miptree */
273 if ((i == 0) || (i == 1))
274 offset = align(offset, base_align);
275 rtex->offset[i] = offset;
276 rtex->layer_size[i] = layer_size;
277 rtex->pitch_in_blocks[i] = nblocksx; /* CB talks in elements */
278 rtex->pitch_in_bytes[i] = nblocksx * blocksize;
279
280 offset += size;
281 }
282 rtex->size = offset + extra_size;
283 }
284
285 /* Figure out whether u_blitter will fallback to a transfer operation.
286 * If so, don't use a staging resource.
287 */
288 static boolean permit_hardware_blit(struct pipe_screen *screen,
289 const struct pipe_resource *res)
290 {
291 unsigned bind;
292
293 if (util_format_is_depth_or_stencil(res->format))
294 bind = PIPE_BIND_DEPTH_STENCIL;
295 else
296 bind = PIPE_BIND_RENDER_TARGET;
297
298 /* hackaround for S3TC */
299 if (util_format_is_compressed(res->format))
300 return TRUE;
301
302 if (!screen->is_format_supported(screen,
303 res->format,
304 res->target,
305 res->nr_samples,
306 bind))
307 return FALSE;
308
309 if (!screen->is_format_supported(screen,
310 res->format,
311 res->target,
312 res->nr_samples,
313 PIPE_BIND_SAMPLER_VIEW))
314 return FALSE;
315
316 return TRUE;
317 }
318
319 static boolean r600_texture_get_handle(struct pipe_screen* screen,
320 struct pipe_resource *ptex,
321 struct winsys_handle *whandle)
322 {
323 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
324 struct r600_resource *resource = &rtex->resource;
325 struct radeon *radeon = (struct radeon *)screen->winsys;
326
327 return r600_bo_get_winsys_handle(radeon, resource->bo,
328 rtex->pitch_in_bytes[0], whandle);
329 }
330
331 static void r600_texture_destroy(struct pipe_screen *screen,
332 struct pipe_resource *ptex)
333 {
334 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
335 struct r600_resource *resource = &rtex->resource;
336 struct radeon *radeon = (struct radeon *)screen->winsys;
337
338 if (rtex->flushed_depth_texture)
339 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
340
341 if (resource->bo) {
342 r600_bo_reference(radeon, &resource->bo, NULL);
343 }
344 FREE(rtex);
345 }
346
347 static const struct u_resource_vtbl r600_texture_vtbl =
348 {
349 r600_texture_get_handle, /* get_handle */
350 r600_texture_destroy, /* resource_destroy */
351 r600_texture_get_transfer, /* get_transfer */
352 r600_texture_transfer_destroy, /* transfer_destroy */
353 r600_texture_transfer_map, /* transfer_map */
354 u_default_transfer_flush_region,/* transfer_flush_region */
355 r600_texture_transfer_unmap, /* transfer_unmap */
356 u_default_transfer_inline_write /* transfer_inline_write */
357 };
358
359 static struct r600_resource_texture *
360 r600_texture_create_object(struct pipe_screen *screen,
361 const struct pipe_resource *base,
362 unsigned array_mode,
363 unsigned pitch_in_bytes_override,
364 unsigned max_buffer_size,
365 struct r600_bo *bo)
366 {
367 struct r600_resource_texture *rtex;
368 struct r600_resource *resource;
369 struct radeon *radeon = (struct radeon *)screen->winsys;
370
371 rtex = CALLOC_STRUCT(r600_resource_texture);
372 if (rtex == NULL)
373 return NULL;
374
375 resource = &rtex->resource;
376 resource->b.b.b = *base;
377 resource->b.b.vtbl = &r600_texture_vtbl;
378 pipe_reference_init(&resource->b.b.b.reference, 1);
379 resource->b.b.b.screen = screen;
380 resource->bo = bo;
381 rtex->pitch_override = pitch_in_bytes_override;
382 /* only mark depth textures the HW can hit as depth textures */
383 if (util_format_is_depth_or_stencil(base->format) && permit_hardware_blit(screen, base))
384 rtex->depth = 1;
385
386 r600_setup_miptree(screen, rtex, array_mode);
387
388 resource->size = rtex->size;
389
390 if (!resource->bo) {
391 struct pipe_resource *ptex = &rtex->resource.b.b.b;
392 int base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
393
394 resource->bo = r600_bo(radeon, rtex->size, base_align, base->bind, base->usage);
395 if (!resource->bo) {
396 FREE(rtex);
397 return NULL;
398 }
399 }
400 return rtex;
401 }
402
403 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
404 const struct pipe_resource *templ)
405 {
406 unsigned array_mode = 0;
407 static int force_tiling = -1;
408
409 /* Would like some magic "get_bool_option_once" routine.
410 */
411 if (force_tiling == -1) {
412 #if 0
413 /* reenable when 2D tiling is fixed better */
414 struct r600_screen *rscreen = (struct r600_screen *)screen;
415 if (r600_get_minor_version(rscreen->radeon) >= 9)
416 force_tiling = debug_get_bool_option("R600_TILING", TRUE);
417 #endif
418 force_tiling = debug_get_bool_option("R600_TILING", FALSE);
419 }
420
421 if (force_tiling && permit_hardware_blit(screen, templ)) {
422 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
423 !(templ->bind & PIPE_BIND_SCANOUT)) {
424 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
425 }
426 }
427
428 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
429 util_format_is_compressed(templ->format))
430 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
431
432 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
433 0, 0, NULL);
434
435 }
436
437 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
438 struct pipe_resource *texture,
439 const struct pipe_surface *surf_tmpl)
440 {
441 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
442 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
443 unsigned level = surf_tmpl->u.tex.level;
444
445 assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
446 if (surface == NULL)
447 return NULL;
448 /* XXX no offset */
449 /* offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/
450 pipe_reference_init(&surface->base.reference, 1);
451 pipe_resource_reference(&surface->base.texture, texture);
452 surface->base.context = pipe;
453 surface->base.format = surf_tmpl->format;
454 surface->base.width = mip_minify(texture->width0, level);
455 surface->base.height = mip_minify(texture->height0, level);
456 surface->base.usage = surf_tmpl->usage;
457 surface->base.texture = texture;
458 surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
459 surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
460 surface->base.u.tex.level = level;
461
462 surface->aligned_height = r600_texture_get_nblocksy(pipe->screen,
463 rtex, level);
464 return &surface->base;
465 }
466
467 static void r600_surface_destroy(struct pipe_context *pipe,
468 struct pipe_surface *surface)
469 {
470 pipe_resource_reference(&surface->texture, NULL);
471 FREE(surface);
472 }
473
474
475 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
476 const struct pipe_resource *templ,
477 struct winsys_handle *whandle)
478 {
479 struct radeon *rw = (struct radeon*)screen->winsys;
480 struct r600_bo *bo = NULL;
481 unsigned array_mode = 0;
482
483 /* Support only 2D textures without mipmaps */
484 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
485 templ->depth0 != 1 || templ->last_level != 0)
486 return NULL;
487
488 bo = r600_bo_handle(rw, whandle->handle, &array_mode);
489 if (bo == NULL) {
490 return NULL;
491 }
492
493 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
494 whandle->stride,
495 0,
496 bo);
497 }
498
499 int r600_texture_depth_flush(struct pipe_context *ctx,
500 struct pipe_resource *texture, boolean just_create)
501 {
502 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
503 struct pipe_resource resource;
504
505 if (rtex->flushed_depth_texture)
506 goto out;
507
508 resource.target = PIPE_TEXTURE_2D;
509 resource.format = texture->format;
510 resource.width0 = texture->width0;
511 resource.height0 = texture->height0;
512 resource.depth0 = 1;
513 resource.array_size = 1;
514 resource.last_level = texture->last_level;
515 resource.nr_samples = 0;
516 resource.usage = PIPE_USAGE_DYNAMIC;
517 resource.bind = 0;
518 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
519
520 resource.bind |= PIPE_BIND_DEPTH_STENCIL;
521
522 rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
523 if (rtex->flushed_depth_texture == NULL) {
524 R600_ERR("failed to create temporary texture to hold untiled copy\n");
525 return -ENOMEM;
526 }
527
528 ((struct r600_resource_texture *)rtex->flushed_depth_texture)->is_flushing_texture = TRUE;
529 out:
530 if (just_create)
531 return 0;
532
533 /* XXX: only do this if the depth texture has actually changed:
534 */
535 r600_blit_uncompress_depth(ctx, rtex);
536 return 0;
537 }
538
539 /* Needs adjustment for pixelformat:
540 */
541 static INLINE unsigned u_box_volume( const struct pipe_box *box )
542 {
543 return box->width * box->depth * box->height;
544 };
545
546 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
547 struct pipe_resource *texture,
548 unsigned level,
549 unsigned usage,
550 const struct pipe_box *box)
551 {
552 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
553 struct pipe_resource resource;
554 struct r600_transfer *trans;
555 int r;
556 boolean use_staging_texture = FALSE;
557
558 /* We cannot map a tiled texture directly because the data is
559 * in a different order, therefore we do detiling using a blit.
560 *
561 * Also, use a temporary in GTT memory for read transfers, as
562 * the CPU is much happier reading out of cached system memory
563 * than uncached VRAM.
564 */
565 if (R600_TEX_IS_TILED(rtex, level))
566 use_staging_texture = TRUE;
567
568 if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024)
569 use_staging_texture = TRUE;
570
571 /* XXX: Use a staging texture for uploads if the underlying BO
572 * is busy. No interface for checking that currently? so do
573 * it eagerly whenever the transfer doesn't require a readback
574 * and might block.
575 */
576 if ((usage & PIPE_TRANSFER_WRITE) &&
577 !(usage & (PIPE_TRANSFER_READ |
578 PIPE_TRANSFER_DONTBLOCK |
579 PIPE_TRANSFER_UNSYNCHRONIZED)))
580 use_staging_texture = TRUE;
581
582 if (!permit_hardware_blit(ctx->screen, texture) ||
583 (texture->flags & R600_RESOURCE_FLAG_TRANSFER))
584 use_staging_texture = FALSE;
585
586 trans = CALLOC_STRUCT(r600_transfer);
587 if (trans == NULL)
588 return NULL;
589 pipe_resource_reference(&trans->transfer.resource, texture);
590 trans->transfer.level = level;
591 trans->transfer.usage = usage;
592 trans->transfer.box = *box;
593 if (rtex->depth) {
594 /* XXX: only readback the rectangle which is being mapped?
595 */
596 /* XXX: when discard is true, no need to read back from depth texture
597 */
598 r = r600_texture_depth_flush(ctx, texture, FALSE);
599 if (r < 0) {
600 R600_ERR("failed to create temporary texture to hold untiled copy\n");
601 pipe_resource_reference(&trans->transfer.resource, NULL);
602 FREE(trans);
603 return NULL;
604 }
605 trans->transfer.stride = rtex->flushed_depth_texture->pitch_in_bytes[level];
606 trans->offset = r600_texture_get_offset(rtex->flushed_depth_texture, level, box->z);
607 return &trans->transfer;
608 } else if (use_staging_texture) {
609 resource.target = PIPE_TEXTURE_2D;
610 resource.format = texture->format;
611 resource.width0 = box->width;
612 resource.height0 = box->height;
613 resource.depth0 = 1;
614 resource.array_size = 1;
615 resource.last_level = 0;
616 resource.nr_samples = 0;
617 resource.usage = PIPE_USAGE_STAGING;
618 resource.bind = 0;
619 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
620 /* For texture reading, the temporary (detiled) texture is used as
621 * a render target when blitting from a tiled texture. */
622 if (usage & PIPE_TRANSFER_READ) {
623 resource.bind |= PIPE_BIND_RENDER_TARGET;
624 }
625 /* For texture writing, the temporary texture is used as a sampler
626 * when blitting into a tiled texture. */
627 if (usage & PIPE_TRANSFER_WRITE) {
628 resource.bind |= PIPE_BIND_SAMPLER_VIEW;
629 }
630 /* Create the temporary texture. */
631 trans->staging_texture = ctx->screen->resource_create(ctx->screen, &resource);
632 if (trans->staging_texture == NULL) {
633 R600_ERR("failed to create temporary texture to hold untiled copy\n");
634 pipe_resource_reference(&trans->transfer.resource, NULL);
635 FREE(trans);
636 return NULL;
637 }
638
639 trans->transfer.stride =
640 ((struct r600_resource_texture *)trans->staging_texture)->pitch_in_bytes[0];
641 if (usage & PIPE_TRANSFER_READ) {
642 r600_copy_to_staging_texture(ctx, trans);
643 /* Always referenced in the blit. */
644 ctx->flush(ctx, NULL);
645 }
646 return &trans->transfer;
647 }
648 trans->transfer.stride = rtex->pitch_in_bytes[level];
649 trans->transfer.layer_stride = rtex->layer_size[level];
650 trans->offset = r600_texture_get_offset(rtex, level, box->z);
651 return &trans->transfer;
652 }
653
654 void r600_texture_transfer_destroy(struct pipe_context *ctx,
655 struct pipe_transfer *transfer)
656 {
657 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
658 struct pipe_resource *texture = transfer->resource;
659 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
660
661 if (rtransfer->staging_texture) {
662 if (transfer->usage & PIPE_TRANSFER_WRITE) {
663 r600_copy_from_staging_texture(ctx, rtransfer);
664 }
665 pipe_resource_reference(&rtransfer->staging_texture, NULL);
666 }
667
668 if (rtex->depth && !rtex->is_flushing_texture) {
669 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtex->flushed_depth_texture)
670 r600_blit_push_depth(ctx, rtex);
671 }
672
673 pipe_resource_reference(&transfer->resource, NULL);
674 FREE(transfer);
675 }
676
677 void* r600_texture_transfer_map(struct pipe_context *ctx,
678 struct pipe_transfer* transfer)
679 {
680 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
681 struct r600_bo *bo;
682 enum pipe_format format = transfer->resource->format;
683 struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
684 unsigned offset = 0;
685 unsigned usage = 0;
686 char *map;
687
688 if (rtransfer->staging_texture) {
689 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
690 } else {
691 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
692
693 if (rtex->flushed_depth_texture)
694 bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
695 else
696 bo = ((struct r600_resource *)transfer->resource)->bo;
697
698 offset = rtransfer->offset +
699 transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
700 transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
701 }
702
703 if (transfer->usage & PIPE_TRANSFER_WRITE) {
704 usage |= PB_USAGE_CPU_WRITE;
705
706 if (transfer->usage & PIPE_TRANSFER_DISCARD) {
707 }
708
709 if (transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT) {
710 }
711 }
712
713 if (transfer->usage & PIPE_TRANSFER_READ) {
714 usage |= PB_USAGE_CPU_READ;
715 }
716
717 if (transfer->usage & PIPE_TRANSFER_DONTBLOCK) {
718 usage |= PB_USAGE_DONTBLOCK;
719 }
720
721 if (transfer->usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
722 usage |= PB_USAGE_UNSYNCHRONIZED;
723 }
724
725 map = r600_bo_map(radeon, bo, usage, ctx);
726 if (!map) {
727 return NULL;
728 }
729
730 return map + offset;
731 }
732
733 void r600_texture_transfer_unmap(struct pipe_context *ctx,
734 struct pipe_transfer* transfer)
735 {
736 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
737 struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
738 struct r600_bo *bo;
739
740 if (rtransfer->staging_texture) {
741 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
742 } else {
743 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
744
745 if (rtex->flushed_depth_texture) {
746 bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
747 } else {
748 bo = ((struct r600_resource *)transfer->resource)->bo;
749 }
750 }
751 r600_bo_unmap(radeon, bo);
752 }
753
754 void r600_init_surface_functions(struct r600_pipe_context *r600)
755 {
756 r600->context.create_surface = r600_create_surface;
757 r600->context.surface_destroy = r600_surface_destroy;
758 }
759
760 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
761 const unsigned char *swizzle_view)
762 {
763 unsigned i;
764 unsigned char swizzle[4];
765 unsigned result = 0;
766 const uint32_t swizzle_shift[4] = {
767 16, 19, 22, 25,
768 };
769 const uint32_t swizzle_bit[4] = {
770 0, 1, 2, 3,
771 };
772
773 if (swizzle_view) {
774 /* Combine two sets of swizzles. */
775 for (i = 0; i < 4; i++) {
776 swizzle[i] = swizzle_view[i] <= UTIL_FORMAT_SWIZZLE_W ?
777 swizzle_format[swizzle_view[i]] : swizzle_view[i];
778 }
779 } else {
780 memcpy(swizzle, swizzle_format, 4);
781 }
782
783 /* Get swizzle. */
784 for (i = 0; i < 4; i++) {
785 switch (swizzle[i]) {
786 case UTIL_FORMAT_SWIZZLE_Y:
787 result |= swizzle_bit[1] << swizzle_shift[i];
788 break;
789 case UTIL_FORMAT_SWIZZLE_Z:
790 result |= swizzle_bit[2] << swizzle_shift[i];
791 break;
792 case UTIL_FORMAT_SWIZZLE_W:
793 result |= swizzle_bit[3] << swizzle_shift[i];
794 break;
795 case UTIL_FORMAT_SWIZZLE_0:
796 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
797 break;
798 case UTIL_FORMAT_SWIZZLE_1:
799 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
800 break;
801 default: /* UTIL_FORMAT_SWIZZLE_X */
802 result |= swizzle_bit[0] << swizzle_shift[i];
803 }
804 }
805 return result;
806 }
807
808 /* texture format translate */
809 uint32_t r600_translate_texformat(struct pipe_screen *screen,
810 enum pipe_format format,
811 const unsigned char *swizzle_view,
812 uint32_t *word4_p, uint32_t *yuv_format_p)
813 {
814 uint32_t result = 0, word4 = 0, yuv_format = 0;
815 const struct util_format_description *desc;
816 boolean uniform = TRUE;
817 static int r600_enable_s3tc = -1;
818
819 int i;
820 const uint32_t sign_bit[4] = {
821 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
822 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
823 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
824 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
825 };
826 desc = util_format_description(format);
827
828 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
829
830 /* Colorspace (return non-RGB formats directly). */
831 switch (desc->colorspace) {
832 /* Depth stencil formats */
833 case UTIL_FORMAT_COLORSPACE_ZS:
834 switch (format) {
835 case PIPE_FORMAT_Z16_UNORM:
836 result = FMT_16;
837 goto out_word4;
838 case PIPE_FORMAT_X24S8_USCALED:
839 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
840 case PIPE_FORMAT_Z24X8_UNORM:
841 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
842 result = FMT_8_24;
843 goto out_word4;
844 case PIPE_FORMAT_S8X24_USCALED:
845 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
846 case PIPE_FORMAT_X8Z24_UNORM:
847 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
848 result = FMT_24_8;
849 goto out_word4;
850 case PIPE_FORMAT_S8_USCALED:
851 result = FMT_8;
852 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
853 goto out_word4;
854 default:
855 goto out_unknown;
856 }
857
858 case UTIL_FORMAT_COLORSPACE_YUV:
859 yuv_format |= (1 << 30);
860 switch (format) {
861 case PIPE_FORMAT_UYVY:
862 case PIPE_FORMAT_YUYV:
863 default:
864 break;
865 }
866 goto out_unknown; /* TODO */
867
868 case UTIL_FORMAT_COLORSPACE_SRGB:
869 word4 |= S_038010_FORCE_DEGAMMA(1);
870 break;
871
872 default:
873 break;
874 }
875
876 if (r600_enable_s3tc == -1) {
877 struct r600_screen *rscreen = (struct r600_screen *)screen;
878 if (r600_get_minor_version(rscreen->radeon) >= 9)
879 r600_enable_s3tc = 1;
880 else
881 r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
882 }
883
884 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
885 if (!r600_enable_s3tc)
886 goto out_unknown;
887
888 switch (format) {
889 case PIPE_FORMAT_RGTC1_SNORM:
890 case PIPE_FORMAT_LATC1_SNORM:
891 word4 |= sign_bit[0];
892 case PIPE_FORMAT_RGTC1_UNORM:
893 case PIPE_FORMAT_LATC1_UNORM:
894 result = FMT_BC4;
895 goto out_word4;
896 case PIPE_FORMAT_RGTC2_SNORM:
897 case PIPE_FORMAT_LATC2_SNORM:
898 word4 |= sign_bit[0] | sign_bit[1];
899 case PIPE_FORMAT_RGTC2_UNORM:
900 case PIPE_FORMAT_LATC2_UNORM:
901 result = FMT_BC5;
902 goto out_word4;
903 default:
904 goto out_unknown;
905 }
906 }
907
908 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
909
910 if (!r600_enable_s3tc)
911 goto out_unknown;
912
913 if (!util_format_s3tc_enabled) {
914 goto out_unknown;
915 }
916
917 switch (format) {
918 case PIPE_FORMAT_DXT1_RGB:
919 case PIPE_FORMAT_DXT1_RGBA:
920 case PIPE_FORMAT_DXT1_SRGB:
921 case PIPE_FORMAT_DXT1_SRGBA:
922 result = FMT_BC1;
923 goto out_word4;
924 case PIPE_FORMAT_DXT3_RGBA:
925 case PIPE_FORMAT_DXT3_SRGBA:
926 result = FMT_BC2;
927 goto out_word4;
928 case PIPE_FORMAT_DXT5_RGBA:
929 case PIPE_FORMAT_DXT5_SRGBA:
930 result = FMT_BC3;
931 goto out_word4;
932 default:
933 goto out_unknown;
934 }
935 }
936
937 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
938 result = FMT_5_9_9_9_SHAREDEXP;
939 goto out_word4;
940 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
941 result = FMT_10_11_11_FLOAT;
942 goto out_word4;
943 }
944
945
946 for (i = 0; i < desc->nr_channels; i++) {
947 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
948 word4 |= sign_bit[i];
949 }
950 }
951
952 /* R8G8Bx_SNORM - TODO CxV8U8 */
953
954 /* See whether the components are of the same size. */
955 for (i = 1; i < desc->nr_channels; i++) {
956 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
957 }
958
959 /* Non-uniform formats. */
960 if (!uniform) {
961 switch(desc->nr_channels) {
962 case 3:
963 if (desc->channel[0].size == 5 &&
964 desc->channel[1].size == 6 &&
965 desc->channel[2].size == 5) {
966 result = FMT_5_6_5;
967 goto out_word4;
968 }
969 goto out_unknown;
970 case 4:
971 if (desc->channel[0].size == 5 &&
972 desc->channel[1].size == 5 &&
973 desc->channel[2].size == 5 &&
974 desc->channel[3].size == 1) {
975 result = FMT_1_5_5_5;
976 goto out_word4;
977 }
978 if (desc->channel[0].size == 10 &&
979 desc->channel[1].size == 10 &&
980 desc->channel[2].size == 10 &&
981 desc->channel[3].size == 2) {
982 result = FMT_2_10_10_10;
983 goto out_word4;
984 }
985 goto out_unknown;
986 }
987 goto out_unknown;
988 }
989
990 /* Find the first non-VOID channel. */
991 for (i = 0; i < 4; i++) {
992 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
993 break;
994 }
995 }
996
997 if (i == 4)
998 goto out_unknown;
999
1000 /* uniform formats */
1001 switch (desc->channel[i].type) {
1002 case UTIL_FORMAT_TYPE_UNSIGNED:
1003 case UTIL_FORMAT_TYPE_SIGNED:
1004 if (!desc->channel[i].normalized &&
1005 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
1006 goto out_unknown;
1007 }
1008
1009 switch (desc->channel[i].size) {
1010 case 4:
1011 switch (desc->nr_channels) {
1012 case 2:
1013 result = FMT_4_4;
1014 goto out_word4;
1015 case 4:
1016 result = FMT_4_4_4_4;
1017 goto out_word4;
1018 }
1019 goto out_unknown;
1020 case 8:
1021 switch (desc->nr_channels) {
1022 case 1:
1023 result = FMT_8;
1024 goto out_word4;
1025 case 2:
1026 result = FMT_8_8;
1027 goto out_word4;
1028 case 4:
1029 result = FMT_8_8_8_8;
1030 goto out_word4;
1031 }
1032 goto out_unknown;
1033 case 16:
1034 switch (desc->nr_channels) {
1035 case 1:
1036 result = FMT_16;
1037 goto out_word4;
1038 case 2:
1039 result = FMT_16_16;
1040 goto out_word4;
1041 case 4:
1042 result = FMT_16_16_16_16;
1043 goto out_word4;
1044 }
1045 goto out_unknown;
1046 case 32:
1047 switch (desc->nr_channels) {
1048 case 1:
1049 result = FMT_32;
1050 goto out_word4;
1051 case 2:
1052 result = FMT_32_32;
1053 goto out_word4;
1054 case 4:
1055 result = FMT_32_32_32_32;
1056 goto out_word4;
1057 }
1058 }
1059 goto out_unknown;
1060
1061 case UTIL_FORMAT_TYPE_FLOAT:
1062 switch (desc->channel[i].size) {
1063 case 16:
1064 switch (desc->nr_channels) {
1065 case 1:
1066 result = FMT_16_FLOAT;
1067 goto out_word4;
1068 case 2:
1069 result = FMT_16_16_FLOAT;
1070 goto out_word4;
1071 case 4:
1072 result = FMT_16_16_16_16_FLOAT;
1073 goto out_word4;
1074 }
1075 goto out_unknown;
1076 case 32:
1077 switch (desc->nr_channels) {
1078 case 1:
1079 result = FMT_32_FLOAT;
1080 goto out_word4;
1081 case 2:
1082 result = FMT_32_32_FLOAT;
1083 goto out_word4;
1084 case 4:
1085 result = FMT_32_32_32_32_FLOAT;
1086 goto out_word4;
1087 }
1088 }
1089 goto out_unknown;
1090 }
1091
1092 out_word4:
1093 if (word4_p)
1094 *word4_p = word4;
1095 if (yuv_format_p)
1096 *yuv_format_p = yuv_format;
1097 return result;
1098 out_unknown:
1099 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1100 return ~0;
1101 }