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r600g: indentation fix
[mesa.git] / src / gallium / drivers / r600 / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include <errno.h>
28 #include <pipe/p_screen.h>
29 #include <util/u_format.h>
30 #include <util/u_math.h>
31 #include <util/u_inlines.h>
32 #include <util/u_memory.h>
33 #include "state_tracker/drm_driver.h"
34 #include "pipebuffer/pb_buffer.h"
35 #include "r600_pipe.h"
36 #include "r600_resource.h"
37 #include "r600_state_inlines.h"
38 #include "r600d.h"
39 #include "r600_formats.h"
40
41 extern struct u_resource_vtbl r600_texture_vtbl;
42
43 /* Copy from a full GPU texture to a transfer's staging one. */
44 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
45 {
46 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
47 struct pipe_resource *texture = transfer->resource;
48
49 ctx->resource_copy_region(ctx, rtransfer->staging_texture,
50 0, 0, 0, 0, texture, transfer->level,
51 &transfer->box);
52 }
53
54
55 /* Copy from a transfer's staging texture to a full GPU one. */
56 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
57 {
58 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
59 struct pipe_resource *texture = transfer->resource;
60 struct pipe_box sbox;
61
62 sbox.x = sbox.y = sbox.z = 0;
63 sbox.width = transfer->box.width;
64 sbox.height = transfer->box.height;
65 /* XXX that might be wrong */
66 sbox.depth = 1;
67 ctx->resource_copy_region(ctx, texture, transfer->level,
68 transfer->box.x, transfer->box.y, transfer->box.z,
69 rtransfer->staging_texture,
70 0, &sbox);
71
72 ctx->flush(ctx, 0, NULL);
73 }
74
75 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
76 unsigned level, unsigned layer)
77 {
78 unsigned offset = rtex->offset[level];
79
80 switch (rtex->resource.base.b.target) {
81 case PIPE_TEXTURE_3D:
82 case PIPE_TEXTURE_CUBE:
83 return offset + layer * rtex->layer_size[level];
84 default:
85 assert(layer == 0);
86 return offset;
87 }
88 }
89
90 static unsigned r600_get_pixel_alignment(struct pipe_screen *screen,
91 enum pipe_format format,
92 unsigned array_mode)
93 {
94 struct r600_screen* rscreen = (struct r600_screen *)screen;
95 unsigned pixsize = util_format_get_blocksize(format);
96 int p_align;
97
98 switch(array_mode) {
99 case V_038000_ARRAY_1D_TILED_THIN1:
100 p_align = MAX2(8,
101 ((rscreen->tiling_info->group_bytes / 8 / pixsize)));
102 break;
103 case V_038000_ARRAY_2D_TILED_THIN1:
104 p_align = MAX2(rscreen->tiling_info->num_banks,
105 (((rscreen->tiling_info->group_bytes / 8 / pixsize)) *
106 rscreen->tiling_info->num_banks)) * 8;
107 break;
108 case V_038000_ARRAY_LINEAR_GENERAL:
109 default:
110 p_align = rscreen->tiling_info->group_bytes / pixsize;
111 break;
112 }
113 return p_align;
114 }
115
116 static unsigned r600_get_height_alignment(struct pipe_screen *screen,
117 unsigned array_mode)
118 {
119 struct r600_screen* rscreen = (struct r600_screen *)screen;
120 int h_align;
121
122 switch (array_mode) {
123 case V_038000_ARRAY_2D_TILED_THIN1:
124 h_align = rscreen->tiling_info->num_channels * 8;
125 break;
126 case V_038000_ARRAY_1D_TILED_THIN1:
127 h_align = 8;
128 break;
129 default:
130 h_align = 1;
131 break;
132 }
133 return h_align;
134 }
135
136 static unsigned r600_get_base_alignment(struct pipe_screen *screen,
137 enum pipe_format format,
138 unsigned array_mode)
139 {
140 struct r600_screen* rscreen = (struct r600_screen *)screen;
141 unsigned pixsize = util_format_get_blocksize(format);
142 int p_align = r600_get_pixel_alignment(screen, format, array_mode);
143 int h_align = r600_get_height_alignment(screen, array_mode);
144 int b_align;
145
146 switch (array_mode) {
147 case V_038000_ARRAY_2D_TILED_THIN1:
148 b_align = MAX2(rscreen->tiling_info->num_banks * rscreen->tiling_info->num_channels * 8 * 8 * pixsize,
149 p_align * pixsize * h_align);
150 break;
151 case V_038000_ARRAY_1D_TILED_THIN1:
152 default:
153 b_align = rscreen->tiling_info->group_bytes;
154 break;
155 }
156 return b_align;
157 }
158
159 static unsigned mip_minify(unsigned size, unsigned level)
160 {
161 unsigned val;
162 val = u_minify(size, level);
163 if (level > 0)
164 val = util_next_power_of_two(val);
165 return val;
166 }
167
168 static unsigned r600_texture_get_stride(struct pipe_screen *screen,
169 struct r600_resource_texture *rtex,
170 unsigned level)
171 {
172 struct pipe_resource *ptex = &rtex->resource.base.b;
173 struct radeon *radeon = (struct radeon *)screen->winsys;
174 enum chip_class chipc = r600_get_family_class(radeon);
175 unsigned width, stride, tile_width;
176
177 if (rtex->pitch_override)
178 return rtex->pitch_override;
179
180 width = mip_minify(ptex->width0, level);
181 if (util_format_is_plain(ptex->format)) {
182 tile_width = r600_get_pixel_alignment(screen, ptex->format,
183 rtex->array_mode[level]);
184 width = align(width, tile_width);
185 }
186 stride = util_format_get_stride(ptex->format, width);
187
188 return stride;
189 }
190
191 static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen,
192 struct r600_resource_texture *rtex,
193 unsigned level)
194 {
195 struct pipe_resource *ptex = &rtex->resource.base.b;
196 unsigned height, tile_height;
197
198 height = mip_minify(ptex->height0, level);
199 if (util_format_is_plain(ptex->format)) {
200 tile_height = r600_get_height_alignment(screen,
201 rtex->array_mode[level]);
202 height = align(height, tile_height);
203 }
204 return util_format_get_nblocksy(ptex->format, height);
205 }
206
207 /* Get a width in pixels from a stride in bytes. */
208 static unsigned pitch_to_width(enum pipe_format format, unsigned pitch_in_bytes)
209 {
210 return (pitch_in_bytes / util_format_get_blocksize(format)) *
211 util_format_get_blockwidth(format);
212 }
213
214 static void r600_texture_set_array_mode(struct pipe_screen *screen,
215 struct r600_resource_texture *rtex,
216 unsigned level, unsigned array_mode)
217 {
218 struct pipe_resource *ptex = &rtex->resource.base.b;
219
220 switch (array_mode) {
221 case V_0280A0_ARRAY_LINEAR_GENERAL:
222 case V_0280A0_ARRAY_LINEAR_ALIGNED:
223 case V_0280A0_ARRAY_1D_TILED_THIN1:
224 default:
225 rtex->array_mode[level] = array_mode;
226 break;
227 case V_0280A0_ARRAY_2D_TILED_THIN1:
228 {
229 unsigned w, h, tile_height, tile_width;
230
231 tile_height = r600_get_height_alignment(screen, array_mode);
232 tile_width = r600_get_pixel_alignment(screen, ptex->format, array_mode);
233
234 w = mip_minify(ptex->width0, level);
235 h = mip_minify(ptex->height0, level);
236 if (w < tile_width || h < tile_height)
237 rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1;
238 else
239 rtex->array_mode[level] = array_mode;
240 }
241 break;
242 }
243 }
244
245 static void r600_setup_miptree(struct pipe_screen *screen,
246 struct r600_resource_texture *rtex,
247 unsigned array_mode)
248 {
249 struct pipe_resource *ptex = &rtex->resource.base.b;
250 struct radeon *radeon = (struct radeon *)screen->winsys;
251 enum chip_class chipc = r600_get_family_class(radeon);
252 unsigned pitch, size, layer_size, i, offset;
253 unsigned nblocksy;
254
255 for (i = 0, offset = 0; i <= ptex->last_level; i++) {
256 r600_texture_set_array_mode(screen, rtex, i, array_mode);
257
258 pitch = r600_texture_get_stride(screen, rtex, i);
259 nblocksy = r600_texture_get_nblocksy(screen, rtex, i);
260
261 layer_size = pitch * nblocksy;
262
263 if (ptex->target == PIPE_TEXTURE_CUBE) {
264 if (chipc >= R700)
265 size = layer_size * 8;
266 else
267 size = layer_size * 6;
268 }
269 else
270 size = layer_size * u_minify(ptex->depth0, i);
271 /* align base image and start of miptree */
272 if ((i == 0) || (i == 1))
273 offset = align(offset, r600_get_base_alignment(screen, ptex->format, array_mode));
274 rtex->offset[i] = offset;
275 rtex->layer_size[i] = layer_size;
276 rtex->pitch_in_bytes[i] = pitch;
277 rtex->pitch_in_pixels[i] = pitch_to_width(ptex->format, pitch);
278 offset += size;
279 }
280 rtex->size = offset;
281 }
282
283 static struct r600_resource_texture *
284 r600_texture_create_object(struct pipe_screen *screen,
285 const struct pipe_resource *base,
286 unsigned array_mode,
287 unsigned pitch_in_bytes_override,
288 unsigned max_buffer_size,
289 struct r600_bo *bo)
290 {
291 struct r600_resource_texture *rtex;
292 struct r600_resource *resource;
293 struct radeon *radeon = (struct radeon *)screen->winsys;
294
295 rtex = CALLOC_STRUCT(r600_resource_texture);
296 if (rtex == NULL)
297 return NULL;
298
299 resource = &rtex->resource;
300 resource->base.b = *base;
301 resource->base.vtbl = &r600_texture_vtbl;
302 pipe_reference_init(&resource->base.b.reference, 1);
303 resource->base.b.screen = screen;
304 resource->bo = bo;
305 rtex->pitch_override = pitch_in_bytes_override;
306
307 if (array_mode)
308 rtex->tiled = 1;
309 r600_setup_miptree(screen, rtex, array_mode);
310
311 resource->size = rtex->size;
312
313 if (!resource->bo) {
314 struct pipe_resource *ptex = &rtex->resource.base.b;
315 int base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
316
317 resource->bo = r600_bo(radeon, rtex->size, base_align, base->bind, base->usage);
318 if (!resource->bo) {
319 FREE(rtex);
320 return NULL;
321 }
322 }
323 return rtex;
324 }
325
326 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
327 const struct pipe_resource *templ)
328 {
329 unsigned array_mode = 0;
330 static int force_tiling = -1;
331
332 /* Would like some magic "get_bool_option_once" routine.
333 */
334 if (force_tiling == -1)
335 force_tiling = debug_get_bool_option("R600_FORCE_TILING", FALSE);
336
337 if (force_tiling) {
338 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
339 !(templ->bind & PIPE_BIND_SCANOUT)) {
340 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
341 }
342 }
343
344 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
345 0, 0, NULL);
346
347 }
348
349 static void r600_texture_destroy(struct pipe_screen *screen,
350 struct pipe_resource *ptex)
351 {
352 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
353 struct r600_resource *resource = &rtex->resource;
354 struct radeon *radeon = (struct radeon *)screen->winsys;
355
356 if (rtex->flushed_depth_texture)
357 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
358
359 if (resource->bo) {
360 r600_bo_reference(radeon, &resource->bo, NULL);
361 }
362 FREE(rtex);
363 }
364
365 static boolean r600_texture_get_handle(struct pipe_screen* screen,
366 struct pipe_resource *ptex,
367 struct winsys_handle *whandle)
368 {
369 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
370 struct r600_resource *resource = &rtex->resource;
371 struct radeon *radeon = (struct radeon *)screen->winsys;
372
373 return r600_bo_get_winsys_handle(radeon, resource->bo,
374 rtex->pitch_in_bytes[0], whandle);
375 }
376
377 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
378 struct pipe_resource *texture,
379 const struct pipe_surface *surf_tmpl)
380 {
381 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
382 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
383 unsigned tile_height;
384 unsigned level = surf_tmpl->u.tex.level;
385
386 assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
387 if (surface == NULL)
388 return NULL;
389 /* XXX no offset */
390 /* offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/
391 pipe_reference_init(&surface->base.reference, 1);
392 pipe_resource_reference(&surface->base.texture, texture);
393 surface->base.context = pipe;
394 surface->base.format = surf_tmpl->format;
395 surface->base.width = mip_minify(texture->width0, level);
396 surface->base.height = mip_minify(texture->height0, level);
397 surface->base.usage = surf_tmpl->usage;
398 surface->base.texture = texture;
399 surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
400 surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
401 surface->base.u.tex.level = level;
402
403 tile_height = r600_get_height_alignment(pipe->screen, rtex->array_mode[level]);
404 surface->aligned_height = align(surface->base.height, tile_height);
405 return &surface->base;
406 }
407
408 static void r600_surface_destroy(struct pipe_context *pipe,
409 struct pipe_surface *surface)
410 {
411 pipe_resource_reference(&surface->texture, NULL);
412 FREE(surface);
413 }
414
415
416 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
417 const struct pipe_resource *templ,
418 struct winsys_handle *whandle)
419 {
420 struct radeon *rw = (struct radeon*)screen->winsys;
421 struct r600_bo *bo = NULL;
422 unsigned array_mode = 0;
423
424 /* Support only 2D textures without mipmaps */
425 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
426 templ->depth0 != 1 || templ->last_level != 0)
427 return NULL;
428
429 bo = r600_bo_handle(rw, whandle->handle, &array_mode);
430 if (bo == NULL) {
431 return NULL;
432 }
433
434 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
435 whandle->stride,
436 0,
437 bo);
438 }
439
440 static unsigned int r600_texture_is_referenced(struct pipe_context *context,
441 struct pipe_resource *texture,
442 unsigned level, int layer)
443 {
444 /* FIXME */
445 return PIPE_REFERENCED_FOR_READ | PIPE_REFERENCED_FOR_WRITE;
446 }
447
448 int (*r600_blit_uncompress_depth_ptr)(struct pipe_context *ctx, struct r600_resource_texture *texture);
449
450 int r600_texture_depth_flush(struct pipe_context *ctx,
451 struct pipe_resource *texture)
452 {
453 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
454 struct pipe_resource resource;
455
456 if (rtex->flushed_depth_texture)
457 goto out;
458
459 resource.target = PIPE_TEXTURE_2D;
460 resource.format = texture->format;
461 resource.width0 = texture->width0;
462 resource.height0 = texture->height0;
463 resource.depth0 = 1;
464 resource.last_level = 0;
465 resource.nr_samples = 0;
466 resource.usage = PIPE_USAGE_DYNAMIC;
467 resource.bind = 0;
468 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
469
470 resource.bind |= PIPE_BIND_DEPTH_STENCIL;
471
472 rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
473 if (rtex->flushed_depth_texture == NULL) {
474 R600_ERR("failed to create temporary texture to hold untiled copy\n");
475 return -ENOMEM;
476 }
477
478 out:
479 /* XXX: only do this if the depth texture has actually changed:
480 */
481 r600_blit_uncompress_depth_ptr(ctx, rtex);
482 return 0;
483 }
484
485 /* Needs adjustment for pixelformat:
486 */
487 static INLINE unsigned u_box_volume( const struct pipe_box *box )
488 {
489 return box->width * box->depth * box->height;
490 };
491
492
493 /* Figure out whether u_blitter will fallback to a transfer operation.
494 * If so, don't use a staging resource.
495 */
496 static boolean permit_hardware_blit(struct pipe_screen *screen,
497 struct pipe_resource *res)
498 {
499 unsigned bind;
500
501 if (util_format_is_depth_or_stencil(res->format))
502 bind = PIPE_BIND_DEPTH_STENCIL;
503 else
504 bind = PIPE_BIND_RENDER_TARGET;
505
506 /* See r600_resource_copy_region: there is something wrong
507 * with depth resource copies at the moment so avoid them for
508 * now.
509 */
510 if (util_format_get_component_bits(res->format,
511 UTIL_FORMAT_COLORSPACE_ZS,
512 0) != 0)
513 return FALSE;
514
515 if (!screen->is_format_supported(screen,
516 res->format,
517 res->target,
518 res->nr_samples,
519 bind, 0))
520 return FALSE;
521
522 if (!screen->is_format_supported(screen,
523 res->format,
524 res->target,
525 res->nr_samples,
526 PIPE_BIND_SAMPLER_VIEW, 0))
527 return FALSE;
528
529 return TRUE;
530 }
531
532 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
533 struct pipe_resource *texture,
534 unsigned level,
535 unsigned usage,
536 const struct pipe_box *box)
537 {
538 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
539 struct pipe_resource resource;
540 struct r600_transfer *trans;
541 int r;
542 boolean use_staging_texture = FALSE;
543
544 /* We cannot map a tiled texture directly because the data is
545 * in a different order, therefore we do detiling using a blit.
546 *
547 * Also, use a temporary in GTT memory for read transfers, as
548 * the CPU is much happier reading out of cached system memory
549 * than uncached VRAM.
550 */
551 if (rtex->tiled)
552 use_staging_texture = TRUE;
553
554 if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024)
555 use_staging_texture = TRUE;
556
557 /* XXX: Use a staging texture for uploads if the underlying BO
558 * is busy. No interface for checking that currently? so do
559 * it eagerly whenever the transfer doesn't require a readback
560 * and might block.
561 */
562 if ((usage & PIPE_TRANSFER_WRITE) &&
563 !(usage & (PIPE_TRANSFER_READ |
564 PIPE_TRANSFER_DONTBLOCK |
565 PIPE_TRANSFER_UNSYNCHRONIZED)))
566 use_staging_texture = TRUE;
567
568 if (!permit_hardware_blit(ctx->screen, texture) ||
569 (texture->flags & R600_RESOURCE_FLAG_TRANSFER))
570 use_staging_texture = FALSE;
571
572 trans = CALLOC_STRUCT(r600_transfer);
573 if (trans == NULL)
574 return NULL;
575 pipe_resource_reference(&trans->transfer.resource, texture);
576 trans->transfer.level = level;
577 trans->transfer.usage = usage;
578 trans->transfer.box = *box;
579 if (rtex->depth) {
580 /* XXX: only readback the rectangle which is being mapped?
581 */
582 /* XXX: when discard is true, no need to read back from depth texture
583 */
584 r = r600_texture_depth_flush(ctx, texture);
585 if (r < 0) {
586 R600_ERR("failed to create temporary texture to hold untiled copy\n");
587 pipe_resource_reference(&trans->transfer.resource, NULL);
588 FREE(trans);
589 return NULL;
590 }
591 } else if (use_staging_texture) {
592 resource.target = PIPE_TEXTURE_2D;
593 resource.format = texture->format;
594 resource.width0 = box->width;
595 resource.height0 = box->height;
596 resource.depth0 = 1;
597 resource.array_size = 1;
598 resource.last_level = 0;
599 resource.nr_samples = 0;
600 resource.usage = PIPE_USAGE_STAGING;
601 resource.bind = 0;
602 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
603 /* For texture reading, the temporary (detiled) texture is used as
604 * a render target when blitting from a tiled texture. */
605 if (usage & PIPE_TRANSFER_READ) {
606 resource.bind |= PIPE_BIND_RENDER_TARGET;
607 }
608 /* For texture writing, the temporary texture is used as a sampler
609 * when blitting into a tiled texture. */
610 if (usage & PIPE_TRANSFER_WRITE) {
611 resource.bind |= PIPE_BIND_SAMPLER_VIEW;
612 }
613 /* Create the temporary texture. */
614 trans->staging_texture = ctx->screen->resource_create(ctx->screen, &resource);
615 if (trans->staging_texture == NULL) {
616 R600_ERR("failed to create temporary texture to hold untiled copy\n");
617 pipe_resource_reference(&trans->transfer.resource, NULL);
618 FREE(trans);
619 return NULL;
620 }
621
622 trans->transfer.stride =
623 ((struct r600_resource_texture *)trans->staging_texture)->pitch_in_bytes[0];
624 if (usage & PIPE_TRANSFER_READ) {
625 r600_copy_to_staging_texture(ctx, trans);
626 /* Always referenced in the blit. */
627 ctx->flush(ctx, 0, NULL);
628 }
629 return &trans->transfer;
630 }
631 trans->transfer.stride = rtex->pitch_in_bytes[level];
632 trans->offset = r600_texture_get_offset(rtex, level, box->z);
633 return &trans->transfer;
634 }
635
636 void r600_texture_transfer_destroy(struct pipe_context *ctx,
637 struct pipe_transfer *transfer)
638 {
639 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
640 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
641
642 if (rtransfer->staging_texture) {
643 if (transfer->usage & PIPE_TRANSFER_WRITE) {
644 r600_copy_from_staging_texture(ctx, rtransfer);
645 }
646 pipe_resource_reference(&rtransfer->staging_texture, NULL);
647 }
648 if (rtex->flushed_depth_texture) {
649 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
650 }
651 pipe_resource_reference(&transfer->resource, NULL);
652 FREE(transfer);
653 }
654
655 void* r600_texture_transfer_map(struct pipe_context *ctx,
656 struct pipe_transfer* transfer)
657 {
658 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
659 struct r600_bo *bo;
660 enum pipe_format format = transfer->resource->format;
661 struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
662 unsigned offset = 0;
663 unsigned usage = 0;
664 char *map;
665
666 if (rtransfer->staging_texture) {
667 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
668 } else {
669 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
670
671 if (rtex->flushed_depth_texture)
672 bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
673 else
674 bo = ((struct r600_resource *)transfer->resource)->bo;
675
676 offset = rtransfer->offset +
677 transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
678 transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
679 }
680
681 if (transfer->usage & PIPE_TRANSFER_WRITE) {
682 usage |= PB_USAGE_CPU_WRITE;
683
684 if (transfer->usage & PIPE_TRANSFER_DISCARD) {
685 }
686
687 if (transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT) {
688 }
689 }
690
691 if (transfer->usage & PIPE_TRANSFER_READ) {
692 usage |= PB_USAGE_CPU_READ;
693 }
694
695 if (transfer->usage & PIPE_TRANSFER_DONTBLOCK) {
696 usage |= PB_USAGE_DONTBLOCK;
697 }
698
699 if (transfer->usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
700 usage |= PB_USAGE_UNSYNCHRONIZED;
701 }
702
703 map = r600_bo_map(radeon, bo, usage, ctx);
704 if (!map) {
705 return NULL;
706 }
707
708 return map + offset;
709 }
710
711 void r600_texture_transfer_unmap(struct pipe_context *ctx,
712 struct pipe_transfer* transfer)
713 {
714 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
715 struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
716 struct r600_bo *bo;
717
718 if (rtransfer->staging_texture) {
719 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
720 } else {
721 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
722
723 if (rtex->flushed_depth_texture) {
724 bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
725 } else {
726 bo = ((struct r600_resource *)transfer->resource)->bo;
727 }
728 }
729 r600_bo_unmap(radeon, bo);
730 }
731
732 struct u_resource_vtbl r600_texture_vtbl =
733 {
734 r600_texture_get_handle, /* get_handle */
735 r600_texture_destroy, /* resource_destroy */
736 r600_texture_is_referenced, /* is_resource_referenced */
737 r600_texture_get_transfer, /* get_transfer */
738 r600_texture_transfer_destroy, /* transfer_destroy */
739 r600_texture_transfer_map, /* transfer_map */
740 u_default_transfer_flush_region,/* transfer_flush_region */
741 r600_texture_transfer_unmap, /* transfer_unmap */
742 u_default_transfer_inline_write /* transfer_inline_write */
743 };
744
745 void r600_init_surface_functions(struct r600_pipe_context *r600)
746 {
747 r600->context.create_surface = r600_create_surface;
748 r600->context.surface_destroy = r600_surface_destroy;
749 }
750
751 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
752 const unsigned char *swizzle_view)
753 {
754 unsigned i;
755 unsigned char swizzle[4];
756 unsigned result = 0;
757 const uint32_t swizzle_shift[4] = {
758 16, 19, 22, 25,
759 };
760 const uint32_t swizzle_bit[4] = {
761 0, 1, 2, 3,
762 };
763
764 if (swizzle_view) {
765 /* Combine two sets of swizzles. */
766 for (i = 0; i < 4; i++) {
767 swizzle[i] = swizzle_view[i] <= UTIL_FORMAT_SWIZZLE_W ?
768 swizzle_format[swizzle_view[i]] : swizzle_view[i];
769 }
770 } else {
771 memcpy(swizzle, swizzle_format, 4);
772 }
773
774 /* Get swizzle. */
775 for (i = 0; i < 4; i++) {
776 switch (swizzle[i]) {
777 case UTIL_FORMAT_SWIZZLE_Y:
778 result |= swizzle_bit[1] << swizzle_shift[i];
779 break;
780 case UTIL_FORMAT_SWIZZLE_Z:
781 result |= swizzle_bit[2] << swizzle_shift[i];
782 break;
783 case UTIL_FORMAT_SWIZZLE_W:
784 result |= swizzle_bit[3] << swizzle_shift[i];
785 break;
786 case UTIL_FORMAT_SWIZZLE_0:
787 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
788 break;
789 case UTIL_FORMAT_SWIZZLE_1:
790 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
791 break;
792 default: /* UTIL_FORMAT_SWIZZLE_X */
793 result |= swizzle_bit[0] << swizzle_shift[i];
794 }
795 }
796 return result;
797 }
798
799 /* texture format translate */
800 uint32_t r600_translate_texformat(enum pipe_format format,
801 const unsigned char *swizzle_view,
802 uint32_t *word4_p, uint32_t *yuv_format_p)
803 {
804 uint32_t result = 0, word4 = 0, yuv_format = 0;
805 const struct util_format_description *desc;
806 boolean uniform = TRUE;
807 int i;
808 const uint32_t sign_bit[4] = {
809 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
810 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
811 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
812 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
813 };
814 desc = util_format_description(format);
815
816 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
817
818 /* Colorspace (return non-RGB formats directly). */
819 switch (desc->colorspace) {
820 /* Depth stencil formats */
821 case UTIL_FORMAT_COLORSPACE_ZS:
822 switch (format) {
823 case PIPE_FORMAT_Z16_UNORM:
824 result = FMT_16;
825 goto out_word4;
826 case PIPE_FORMAT_X24S8_USCALED:
827 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
828 case PIPE_FORMAT_Z24X8_UNORM:
829 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
830 result = FMT_8_24;
831 goto out_word4;
832 case PIPE_FORMAT_S8X24_USCALED:
833 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
834 case PIPE_FORMAT_X8Z24_UNORM:
835 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
836 result = FMT_24_8;
837 goto out_word4;
838 case PIPE_FORMAT_S8_USCALED:
839 result = FMT_8;
840 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
841 goto out_word4;
842 default:
843 goto out_unknown;
844 }
845
846 case UTIL_FORMAT_COLORSPACE_YUV:
847 yuv_format |= (1 << 30);
848 switch (format) {
849 case PIPE_FORMAT_UYVY:
850 case PIPE_FORMAT_YUYV:
851 default:
852 break;
853 }
854 goto out_unknown; /* TODO */
855
856 case UTIL_FORMAT_COLORSPACE_SRGB:
857 word4 |= S_038010_FORCE_DEGAMMA(1);
858 if (format == PIPE_FORMAT_L8A8_SRGB || format == PIPE_FORMAT_L8_SRGB)
859 goto out_unknown; /* fails for some reason - TODO */
860 break;
861
862 default:
863 break;
864 }
865
866 /* S3TC formats. TODO */
867 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
868 static int r600_enable_s3tc = -1;
869
870 if (r600_enable_s3tc == -1)
871 r600_enable_s3tc =
872 debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
873
874 if (!r600_enable_s3tc)
875 goto out_unknown;
876
877 switch (format) {
878 case PIPE_FORMAT_DXT1_RGB:
879 case PIPE_FORMAT_DXT1_RGBA:
880 result = FMT_BC1;
881 goto out_word4;
882 case PIPE_FORMAT_DXT3_RGBA:
883 result = FMT_BC2;
884 goto out_word4;
885 case PIPE_FORMAT_DXT5_RGBA:
886 result = FMT_BC3;
887 goto out_word4;
888 default:
889 goto out_unknown;
890 }
891 }
892
893
894 for (i = 0; i < desc->nr_channels; i++) {
895 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
896 word4 |= sign_bit[i];
897 }
898 }
899
900 /* R8G8Bx_SNORM - TODO CxV8U8 */
901
902 /* RGTC - TODO */
903
904 /* See whether the components are of the same size. */
905 for (i = 1; i < desc->nr_channels; i++) {
906 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
907 }
908
909 /* Non-uniform formats. */
910 if (!uniform) {
911 switch(desc->nr_channels) {
912 case 3:
913 if (desc->channel[0].size == 5 &&
914 desc->channel[1].size == 6 &&
915 desc->channel[2].size == 5) {
916 result = FMT_5_6_5;
917 goto out_word4;
918 }
919 goto out_unknown;
920 case 4:
921 if (desc->channel[0].size == 5 &&
922 desc->channel[1].size == 5 &&
923 desc->channel[2].size == 5 &&
924 desc->channel[3].size == 1) {
925 result = FMT_1_5_5_5;
926 goto out_word4;
927 }
928 if (desc->channel[0].size == 10 &&
929 desc->channel[1].size == 10 &&
930 desc->channel[2].size == 10 &&
931 desc->channel[3].size == 2) {
932 result = FMT_10_10_10_2;
933 goto out_word4;
934 }
935 goto out_unknown;
936 }
937 goto out_unknown;
938 }
939
940 /* Find the first non-VOID channel. */
941 for (i = 0; i < 4; i++) {
942 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
943 break;
944 }
945 }
946
947 if (i == 4)
948 goto out_unknown;
949
950 /* uniform formats */
951 switch (desc->channel[i].type) {
952 case UTIL_FORMAT_TYPE_UNSIGNED:
953 case UTIL_FORMAT_TYPE_SIGNED:
954 if (!desc->channel[i].normalized &&
955 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
956 goto out_unknown;
957 }
958
959 switch (desc->channel[i].size) {
960 case 4:
961 switch (desc->nr_channels) {
962 case 2:
963 result = FMT_4_4;
964 goto out_word4;
965 case 4:
966 result = FMT_4_4_4_4;
967 goto out_word4;
968 }
969 goto out_unknown;
970 case 8:
971 switch (desc->nr_channels) {
972 case 1:
973 result = FMT_8;
974 goto out_word4;
975 case 2:
976 result = FMT_8_8;
977 goto out_word4;
978 case 4:
979 result = FMT_8_8_8_8;
980 goto out_word4;
981 }
982 goto out_unknown;
983 case 16:
984 switch (desc->nr_channels) {
985 case 1:
986 result = FMT_16;
987 goto out_word4;
988 case 2:
989 result = FMT_16_16;
990 goto out_word4;
991 case 4:
992 result = FMT_16_16_16_16;
993 goto out_word4;
994 }
995 }
996 goto out_unknown;
997
998 case UTIL_FORMAT_TYPE_FLOAT:
999 switch (desc->channel[i].size) {
1000 case 16:
1001 switch (desc->nr_channels) {
1002 case 1:
1003 result = FMT_16_FLOAT;
1004 goto out_word4;
1005 case 2:
1006 result = FMT_16_16_FLOAT;
1007 goto out_word4;
1008 case 4:
1009 result = FMT_16_16_16_16_FLOAT;
1010 goto out_word4;
1011 }
1012 goto out_unknown;
1013 case 32:
1014 switch (desc->nr_channels) {
1015 case 1:
1016 result = FMT_32_FLOAT;
1017 goto out_word4;
1018 case 2:
1019 result = FMT_32_32_FLOAT;
1020 goto out_word4;
1021 case 4:
1022 result = FMT_32_32_32_32_FLOAT;
1023 goto out_word4;
1024 }
1025 }
1026
1027 }
1028 out_word4:
1029 if (word4_p)
1030 *word4_p = word4;
1031 if (yuv_format_p)
1032 *yuv_format_p = yuv_format;
1033 return result;
1034 out_unknown:
1035 // R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format));
1036 return ~0;
1037 }