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r600g: Close a memory leak of llvm byte streams
[mesa.git] / src / gallium / drivers / r600 / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_formats.h"
28 #include "r600d.h"
29
30 #include <errno.h>
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33
34 /* Copy from a full GPU texture to a transfer's staging one. */
35 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
36 {
37 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
38 struct pipe_resource *texture = transfer->resource;
39
40 ctx->resource_copy_region(ctx, &rtransfer->staging->b.b,
41 0, 0, 0, 0, texture, transfer->level,
42 &transfer->box);
43 }
44
45
46 /* Copy from a transfer's staging texture to a full GPU one. */
47 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
48 {
49 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
50 struct pipe_resource *texture = transfer->resource;
51 struct pipe_box sbox;
52
53 u_box_origin_2d(transfer->box.width, transfer->box.height, &sbox);
54
55 ctx->resource_copy_region(ctx, texture, transfer->level,
56 transfer->box.x, transfer->box.y, transfer->box.z,
57 &rtransfer->staging->b.b,
58 0, &sbox);
59 }
60
61 unsigned r600_texture_get_offset(struct r600_texture *rtex,
62 unsigned level, unsigned layer)
63 {
64 return rtex->surface.level[level].offset +
65 layer * rtex->surface.level[level].slice_size;
66 }
67
68 static int r600_init_surface(struct r600_screen *rscreen,
69 struct radeon_surface *surface,
70 const struct pipe_resource *ptex,
71 unsigned array_mode,
72 bool is_transfer, bool is_flushed_depth)
73 {
74 const struct util_format_description *desc =
75 util_format_description(ptex->format);
76 bool is_depth, is_stencil;
77
78 is_depth = util_format_has_depth(desc);
79 is_stencil = util_format_has_stencil(desc);
80
81 surface->npix_x = ptex->width0;
82 surface->npix_y = ptex->height0;
83 surface->npix_z = ptex->depth0;
84 surface->blk_w = util_format_get_blockwidth(ptex->format);
85 surface->blk_h = util_format_get_blockheight(ptex->format);
86 surface->blk_d = 1;
87 surface->array_size = 1;
88 surface->last_level = ptex->last_level;
89
90 if (rscreen->chip_class >= EVERGREEN &&
91 !is_transfer && !is_flushed_depth &&
92 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
93 surface->bpe = 4; /* stencil is allocated separately on evergreen */
94 } else {
95 surface->bpe = util_format_get_blocksize(ptex->format);
96 /* align byte per element on dword */
97 if (surface->bpe == 3) {
98 surface->bpe = 4;
99 }
100 }
101
102 surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1;
103 surface->flags = 0;
104
105 switch (array_mode) {
106 case V_038000_ARRAY_1D_TILED_THIN1:
107 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
108 break;
109 case V_038000_ARRAY_2D_TILED_THIN1:
110 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
111 break;
112 case V_038000_ARRAY_LINEAR_ALIGNED:
113 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
114 break;
115 case V_038000_ARRAY_LINEAR_GENERAL:
116 default:
117 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE);
118 break;
119 }
120 switch (ptex->target) {
121 case PIPE_TEXTURE_1D:
122 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
123 break;
124 case PIPE_TEXTURE_RECT:
125 case PIPE_TEXTURE_2D:
126 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
127 break;
128 case PIPE_TEXTURE_3D:
129 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
130 break;
131 case PIPE_TEXTURE_1D_ARRAY:
132 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
133 surface->array_size = ptex->array_size;
134 break;
135 case PIPE_TEXTURE_2D_ARRAY:
136 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
137 surface->array_size = ptex->array_size;
138 break;
139 case PIPE_TEXTURE_CUBE:
140 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
141 break;
142 case PIPE_BUFFER:
143 default:
144 return -EINVAL;
145 }
146 if (ptex->bind & PIPE_BIND_SCANOUT) {
147 surface->flags |= RADEON_SURF_SCANOUT;
148 }
149
150 if (!is_transfer && !is_flushed_depth && is_depth) {
151 surface->flags |= RADEON_SURF_ZBUFFER;
152
153 if (is_stencil) {
154 surface->flags |= RADEON_SURF_SBUFFER;
155 }
156 }
157 return 0;
158 }
159
160 static int r600_setup_surface(struct pipe_screen *screen,
161 struct r600_texture *rtex,
162 unsigned pitch_in_bytes_override)
163 {
164 struct pipe_resource *ptex = &rtex->resource.b.b;
165 struct r600_screen *rscreen = (struct r600_screen*)screen;
166 unsigned i;
167 int r;
168
169 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
170 if (r) {
171 return r;
172 }
173 rtex->size = rtex->surface.bo_size;
174 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
175 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
176 * for those
177 */
178 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
179 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
180 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
181 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
182 rtex->surface.stencil_offset = rtex->surface.level[0].slice_size;
183 }
184 }
185 for (i = 0; i <= ptex->last_level; i++) {
186 switch (rtex->surface.level[i].mode) {
187 case RADEON_SURF_MODE_LINEAR_ALIGNED:
188 rtex->array_mode[i] = V_038000_ARRAY_LINEAR_ALIGNED;
189 break;
190 case RADEON_SURF_MODE_1D:
191 rtex->array_mode[i] = V_038000_ARRAY_1D_TILED_THIN1;
192 break;
193 case RADEON_SURF_MODE_2D:
194 rtex->array_mode[i] = V_038000_ARRAY_2D_TILED_THIN1;
195 break;
196 default:
197 case RADEON_SURF_MODE_LINEAR:
198 rtex->array_mode[i] = 0;
199 break;
200 }
201 }
202 return 0;
203 }
204
205 static boolean r600_texture_get_handle(struct pipe_screen* screen,
206 struct pipe_resource *ptex,
207 struct winsys_handle *whandle)
208 {
209 struct r600_texture *rtex = (struct r600_texture*)ptex;
210 struct r600_resource *resource = &rtex->resource;
211 struct radeon_surface *surface = &rtex->surface;
212 struct r600_screen *rscreen = (struct r600_screen*)screen;
213
214 rscreen->ws->buffer_set_tiling(resource->buf,
215 NULL,
216 surface->level[0].mode >= RADEON_SURF_MODE_1D ?
217 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
218 surface->level[0].mode >= RADEON_SURF_MODE_2D ?
219 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
220 surface->bankw, surface->bankh,
221 surface->tile_split,
222 surface->stencil_tile_split,
223 surface->mtilea,
224 rtex->surface.level[0].pitch_bytes);
225
226 return rscreen->ws->buffer_get_handle(resource->buf,
227 rtex->surface.level[0].pitch_bytes, whandle);
228 }
229
230 static void r600_texture_destroy(struct pipe_screen *screen,
231 struct pipe_resource *ptex)
232 {
233 struct r600_texture *rtex = (struct r600_texture*)ptex;
234 struct r600_resource *resource = &rtex->resource;
235
236 if (rtex->flushed_depth_texture)
237 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
238
239 pb_reference(&resource->buf, NULL);
240 FREE(rtex);
241 }
242
243 static const struct u_resource_vtbl r600_texture_vtbl =
244 {
245 r600_texture_get_handle, /* get_handle */
246 r600_texture_destroy, /* resource_destroy */
247 r600_texture_get_transfer, /* get_transfer */
248 r600_texture_transfer_destroy, /* transfer_destroy */
249 r600_texture_transfer_map, /* transfer_map */
250 NULL, /* transfer_flush_region */
251 r600_texture_transfer_unmap, /* transfer_unmap */
252 NULL /* transfer_inline_write */
253 };
254
255 /* The number of samples can be specified independently of the texture. */
256 void r600_texture_get_fmask_info(struct r600_screen *rscreen,
257 struct r600_texture *rtex,
258 unsigned nr_samples,
259 struct r600_fmask_info *out)
260 {
261 /* FMASK is allocated pretty much like an ordinary texture.
262 * Here we use bpe in the units of bits, not bytes. */
263 struct radeon_surface fmask = rtex->surface;
264
265 switch (nr_samples) {
266 case 2:
267 /* This should be 8,1, but we should set nsamples > 1
268 * for the allocator to treat it as a multisample surface.
269 * Let's set 4,2 then. */
270 case 4:
271 fmask.bpe = 4;
272 fmask.nsamples = 2;
273 break;
274 case 8:
275 fmask.bpe = 8;
276 fmask.nsamples = 4;
277 break;
278 case 16:
279 fmask.bpe = 16;
280 fmask.nsamples = 4;
281 break;
282 default:
283 R600_ERR("Invalid sample count for FMASK allocation.\n");
284 return;
285 }
286
287 /* R600-R700 errata? Anyway, this fixes colorbuffer corruption. */
288 if (rscreen->chip_class <= R700) {
289 fmask.bpe *= 2;
290 }
291
292 if (rscreen->chip_class >= EVERGREEN) {
293 fmask.bankh = nr_samples <= 4 ? 4 : 1;
294 }
295
296 if (rscreen->ws->surface_init(rscreen->ws, &fmask)) {
297 R600_ERR("Got error in surface_init while allocating FMASK.\n");
298 return;
299 }
300 assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
301
302 out->bank_height = fmask.bankh;
303 out->alignment = MAX2(256, fmask.bo_alignment);
304 out->size = (fmask.bo_size + 7) / 8;
305 }
306
307 static void r600_texture_allocate_fmask(struct r600_screen *rscreen,
308 struct r600_texture *rtex)
309 {
310 struct r600_fmask_info fmask;
311
312 r600_texture_get_fmask_info(rscreen, rtex,
313 rtex->resource.b.b.nr_samples, &fmask);
314
315 /* Reserve space for FMASK while converting bits back to bytes. */
316 rtex->fmask_bank_height = fmask.bank_height;
317 rtex->fmask_offset = align(rtex->size, fmask.alignment);
318 rtex->fmask_size = fmask.size;
319 rtex->size = rtex->fmask_offset + rtex->fmask_size;
320 #if 0
321 printf("FMASK width=%u, height=%i, bits=%u, size=%u\n",
322 fmask.npix_x, fmask.npix_y, fmask.bpe * fmask.nsamples, rtex->fmask_size);
323 #endif
324 }
325
326 void r600_texture_get_cmask_info(struct r600_screen *rscreen,
327 struct r600_texture *rtex,
328 struct r600_cmask_info *out)
329 {
330 unsigned cmask_tile_width = 8;
331 unsigned cmask_tile_height = 8;
332 unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
333 unsigned element_bits = 4;
334 unsigned cmask_cache_bits = 1024;
335 unsigned num_pipes = rscreen->tiling_info.num_channels;
336 unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
337
338 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
339 unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
340 unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
341 unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
342 unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
343
344 unsigned pitch_elements = align(rtex->surface.npix_x, macro_tile_width);
345 unsigned height = align(rtex->surface.npix_y, macro_tile_height);
346
347 unsigned base_align = num_pipes * pipe_interleave_bytes;
348 unsigned slice_bytes =
349 ((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
350
351 assert(macro_tile_width % 128 == 0);
352 assert(macro_tile_height % 128 == 0);
353
354 out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
355 out->alignment = MAX2(256, base_align);
356 out->size = rtex->surface.array_size * align(slice_bytes, base_align);
357 }
358
359 static void r600_texture_allocate_cmask(struct r600_screen *rscreen,
360 struct r600_texture *rtex)
361 {
362 struct r600_cmask_info cmask;
363
364 r600_texture_get_cmask_info(rscreen, rtex, &cmask);
365
366 rtex->cmask_slice_tile_max = cmask.slice_tile_max;
367 rtex->cmask_offset = align(rtex->size, cmask.alignment);
368 rtex->cmask_size = cmask.size;
369 rtex->size = rtex->cmask_offset + rtex->cmask_size;
370 #if 0
371 printf("CMASK: macro tile width = %u, macro tile height = %u, "
372 "pitch elements = %u, height = %u, slice tile max = %u\n",
373 macro_tile_width, macro_tile_height, pitch_elements, height,
374 rtex->cmask_slice_tile_max);
375 #endif
376 }
377
378 static struct r600_texture *
379 r600_texture_create_object(struct pipe_screen *screen,
380 const struct pipe_resource *base,
381 unsigned pitch_in_bytes_override,
382 struct pb_buffer *buf,
383 boolean alloc_bo,
384 struct radeon_surface *surface)
385 {
386 struct r600_texture *rtex;
387 struct r600_resource *resource;
388 struct r600_screen *rscreen = (struct r600_screen*)screen;
389 int r;
390
391 rtex = CALLOC_STRUCT(r600_texture);
392 if (rtex == NULL)
393 return NULL;
394
395 resource = &rtex->resource;
396 resource->b.b = *base;
397 resource->b.vtbl = &r600_texture_vtbl;
398 pipe_reference_init(&resource->b.b.reference, 1);
399 resource->b.b.screen = screen;
400 rtex->pitch_override = pitch_in_bytes_override;
401
402 /* don't include stencil-only formats which we don't support for rendering */
403 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
404
405 rtex->surface = *surface;
406 r = r600_setup_surface(screen, rtex,
407 pitch_in_bytes_override);
408 if (r) {
409 FREE(rtex);
410 return NULL;
411 }
412
413 if (base->nr_samples > 1 && !rtex->is_depth && alloc_bo) {
414 r600_texture_allocate_cmask(rscreen, rtex);
415 r600_texture_allocate_fmask(rscreen, rtex);
416 }
417
418 if (!rtex->is_depth && base->nr_samples > 1 &&
419 (!rtex->fmask_size || !rtex->cmask_size)) {
420 FREE(rtex);
421 return NULL;
422 }
423
424 /* Now create the backing buffer. */
425 if (!buf && alloc_bo) {
426 unsigned base_align = rtex->surface.bo_alignment;
427 unsigned usage = R600_TEX_IS_TILED(rtex, 0) ? PIPE_USAGE_STATIC : base->usage;
428
429 if (!r600_init_resource(rscreen, resource, rtex->size, base_align, base->bind, usage)) {
430 FREE(rtex);
431 return NULL;
432 }
433 } else if (buf) {
434 resource->buf = buf;
435 resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);
436 resource->domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM;
437 }
438
439 if (rtex->cmask_size) {
440 /* Initialize the cmask to 0xCC (= compressed state). */
441 char *ptr = rscreen->ws->buffer_map(resource->cs_buf, NULL, PIPE_TRANSFER_WRITE);
442 memset(ptr + rtex->cmask_offset, 0xCC, rtex->cmask_size);
443 rscreen->ws->buffer_unmap(resource->cs_buf);
444 }
445 return rtex;
446 }
447
448 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
449 const struct pipe_resource *templ)
450 {
451 struct r600_screen *rscreen = (struct r600_screen*)screen;
452 struct radeon_surface surface;
453 unsigned array_mode = 0;
454 int r;
455
456 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER)) {
457 if (!(templ->bind & PIPE_BIND_SCANOUT) &&
458 templ->usage != PIPE_USAGE_STAGING &&
459 templ->usage != PIPE_USAGE_STREAM) {
460 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
461 } else if (util_format_is_compressed(templ->format)) {
462 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
463 }
464 }
465
466 /* XXX tiling is broken for the 422 formats */
467 if (util_format_description(templ->format)->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED)
468 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
469
470 r = r600_init_surface(rscreen, &surface, templ, array_mode,
471 templ->flags & R600_RESOURCE_FLAG_TRANSFER,
472 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
473 if (r) {
474 return NULL;
475 }
476 r = rscreen->ws->surface_best(rscreen->ws, &surface);
477 if (r) {
478 return NULL;
479 }
480 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
481 0, NULL, TRUE, &surface);
482 }
483
484 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
485 struct pipe_resource *texture,
486 const struct pipe_surface *templ)
487 {
488 struct r600_texture *rtex = (struct r600_texture*)texture;
489 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
490 unsigned level = templ->u.tex.level;
491
492 assert(templ->u.tex.first_layer == templ->u.tex.last_layer);
493 if (surface == NULL)
494 return NULL;
495 pipe_reference_init(&surface->base.reference, 1);
496 pipe_resource_reference(&surface->base.texture, texture);
497 surface->base.context = pipe;
498 surface->base.format = templ->format;
499 surface->base.width = rtex->surface.level[level].npix_x;
500 surface->base.height = rtex->surface.level[level].npix_y;
501 surface->base.usage = templ->usage;
502 surface->base.u = templ->u;
503 return &surface->base;
504 }
505
506 static void r600_surface_destroy(struct pipe_context *pipe,
507 struct pipe_surface *surface)
508 {
509 struct r600_surface *surf = (struct r600_surface*)surface;
510 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, NULL);
511 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, NULL);
512 pipe_resource_reference(&surface->texture, NULL);
513 FREE(surface);
514 }
515
516 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
517 const struct pipe_resource *templ,
518 struct winsys_handle *whandle)
519 {
520 struct r600_screen *rscreen = (struct r600_screen*)screen;
521 struct pb_buffer *buf = NULL;
522 unsigned stride = 0;
523 unsigned array_mode = 0;
524 enum radeon_bo_layout micro, macro;
525 struct radeon_surface surface;
526 int r;
527
528 /* Support only 2D textures without mipmaps */
529 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
530 templ->depth0 != 1 || templ->last_level != 0)
531 return NULL;
532
533 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
534 if (!buf)
535 return NULL;
536
537 rscreen->ws->buffer_get_tiling(buf, &micro, &macro,
538 &surface.bankw, &surface.bankh,
539 &surface.tile_split,
540 &surface.stencil_tile_split,
541 &surface.mtilea);
542
543 if (macro == RADEON_LAYOUT_TILED)
544 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
545 else if (micro == RADEON_LAYOUT_TILED)
546 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
547 else
548 array_mode = 0;
549
550 r = r600_init_surface(rscreen, &surface, templ, array_mode, false, false);
551 if (r) {
552 return NULL;
553 }
554 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
555 stride, buf, FALSE, &surface);
556 }
557
558 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
559 struct pipe_resource *texture,
560 struct r600_texture **staging)
561 {
562 struct r600_texture *rtex = (struct r600_texture*)texture;
563 struct pipe_resource resource;
564 struct r600_texture **flushed_depth_texture = staging ?
565 staging : &rtex->flushed_depth_texture;
566
567 if (!staging && rtex->flushed_depth_texture)
568 return true; /* it's ready */
569
570 resource.target = texture->target;
571 resource.format = texture->format;
572 resource.width0 = texture->width0;
573 resource.height0 = texture->height0;
574 resource.depth0 = texture->depth0;
575 resource.array_size = texture->array_size;
576 resource.last_level = texture->last_level;
577 resource.nr_samples = texture->nr_samples;
578 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_STATIC;
579 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
580 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
581
582 if (staging)
583 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
584
585 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
586 if (*flushed_depth_texture == NULL) {
587 R600_ERR("failed to create temporary texture to hold flushed depth\n");
588 return false;
589 }
590
591 (*flushed_depth_texture)->is_flushing_texture = TRUE;
592 return true;
593 }
594
595 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
596 struct pipe_resource *texture,
597 unsigned level,
598 unsigned usage,
599 const struct pipe_box *box)
600 {
601 struct r600_context *rctx = (struct r600_context*)ctx;
602 struct r600_texture *rtex = (struct r600_texture*)texture;
603 struct pipe_resource resource;
604 struct r600_transfer *trans;
605 boolean use_staging_texture = FALSE;
606
607 /* We cannot map a tiled texture directly because the data is
608 * in a different order, therefore we do detiling using a blit.
609 *
610 * Also, use a temporary in GTT memory for read transfers, as
611 * the CPU is much happier reading out of cached system memory
612 * than uncached VRAM.
613 */
614 if (R600_TEX_IS_TILED(rtex, level)) {
615 use_staging_texture = TRUE;
616 }
617
618 /* Use a staging texture for uploads if the underlying BO is busy. */
619 if (!(usage & PIPE_TRANSFER_READ) &&
620 (rctx->ws->cs_is_buffer_referenced(rctx->cs, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) ||
621 rctx->ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE))) {
622 use_staging_texture = TRUE;
623 }
624
625 if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) {
626 use_staging_texture = FALSE;
627 }
628
629 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) {
630 return NULL;
631 }
632
633 trans = CALLOC_STRUCT(r600_transfer);
634 if (trans == NULL)
635 return NULL;
636 pipe_resource_reference(&trans->transfer.resource, texture);
637 trans->transfer.level = level;
638 trans->transfer.usage = usage;
639 trans->transfer.box = *box;
640 if (rtex->is_depth) {
641 /* XXX: only readback the rectangle which is being mapped?
642 */
643 /* XXX: when discard is true, no need to read back from depth texture
644 */
645 struct r600_texture *staging_depth;
646
647 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
648 R600_ERR("failed to create temporary texture to hold untiled copy\n");
649 pipe_resource_reference(&trans->transfer.resource, NULL);
650 FREE(trans);
651 return NULL;
652 }
653
654 r600_blit_decompress_depth(ctx, rtex, staging_depth,
655 level, level,
656 box->z, box->z + box->depth - 1,
657 0, 0);
658
659 trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
660 trans->offset = r600_texture_get_offset(staging_depth, level, box->z);
661 trans->staging = (struct r600_resource*)staging_depth;
662 return &trans->transfer;
663 } else if (use_staging_texture) {
664 resource.target = PIPE_TEXTURE_2D;
665 resource.format = texture->format;
666 resource.width0 = box->width;
667 resource.height0 = box->height;
668 resource.depth0 = 1;
669 resource.array_size = 1;
670 resource.last_level = 0;
671 resource.nr_samples = 0;
672 resource.usage = PIPE_USAGE_STAGING;
673 resource.bind = 0;
674 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
675 /* For texture reading, the temporary (detiled) texture is used as
676 * a render target when blitting from a tiled texture. */
677 if (usage & PIPE_TRANSFER_READ) {
678 resource.bind |= PIPE_BIND_RENDER_TARGET;
679 }
680 /* For texture writing, the temporary texture is used as a sampler
681 * when blitting into a tiled texture. */
682 if (usage & PIPE_TRANSFER_WRITE) {
683 resource.bind |= PIPE_BIND_SAMPLER_VIEW;
684 }
685 /* Create the temporary texture. */
686 trans->staging = (struct r600_resource*)ctx->screen->resource_create(ctx->screen, &resource);
687 if (trans->staging == NULL) {
688 R600_ERR("failed to create temporary texture to hold untiled copy\n");
689 pipe_resource_reference(&trans->transfer.resource, NULL);
690 FREE(trans);
691 return NULL;
692 }
693
694 trans->transfer.stride =
695 ((struct r600_texture *)trans->staging)->surface.level[0].pitch_bytes;
696 if (usage & PIPE_TRANSFER_READ) {
697 r600_copy_to_staging_texture(ctx, trans);
698 /* Always referenced in the blit. */
699 r600_flush(ctx, NULL, 0);
700 }
701 return &trans->transfer;
702 }
703 trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
704 trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
705 trans->offset = r600_texture_get_offset(rtex, level, box->z);
706 return &trans->transfer;
707 }
708
709 void r600_texture_transfer_destroy(struct pipe_context *ctx,
710 struct pipe_transfer *transfer)
711 {
712 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
713 struct pipe_resource *texture = transfer->resource;
714 struct r600_texture *rtex = (struct r600_texture*)texture;
715
716 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
717 if (rtex->is_depth) {
718 ctx->resource_copy_region(ctx, texture, transfer->level,
719 transfer->box.x, transfer->box.y, transfer->box.z,
720 &rtransfer->staging->b.b, transfer->level,
721 &transfer->box);
722 } else {
723 r600_copy_from_staging_texture(ctx, rtransfer);
724 }
725 }
726
727 if (rtransfer->staging)
728 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
729
730 pipe_resource_reference(&transfer->resource, NULL);
731 FREE(transfer);
732 }
733
734 void* r600_texture_transfer_map(struct pipe_context *ctx,
735 struct pipe_transfer* transfer)
736 {
737 struct r600_context *rctx = (struct r600_context *)ctx;
738 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
739 struct radeon_winsys_cs_handle *buf;
740 struct r600_texture *rtex =
741 (struct r600_texture*)transfer->resource;
742 enum pipe_format format = transfer->resource->format;
743 unsigned offset = 0;
744 char *map;
745
746 if ((transfer->resource->bind & PIPE_BIND_GLOBAL) && transfer->resource->target == PIPE_BUFFER) {
747 return r600_compute_global_transfer_map(ctx, transfer);
748 }
749
750 if (rtransfer->staging) {
751 buf = ((struct r600_resource *)rtransfer->staging)->cs_buf;
752 } else {
753 buf = ((struct r600_resource *)transfer->resource)->cs_buf;
754 }
755
756 if (rtex->is_depth || !rtransfer->staging)
757 offset = rtransfer->offset +
758 transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
759 transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
760
761 if (!(map = rctx->ws->buffer_map(buf, rctx->cs, transfer->usage))) {
762 return NULL;
763 }
764
765 return map + offset;
766 }
767
768 void r600_texture_transfer_unmap(struct pipe_context *ctx,
769 struct pipe_transfer* transfer)
770 {
771 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
772 struct r600_context *rctx = (struct r600_context*)ctx;
773 struct radeon_winsys_cs_handle *buf;
774
775 if ((transfer->resource->bind & PIPE_BIND_GLOBAL) && transfer->resource->target == PIPE_BUFFER) {
776 return r600_compute_global_transfer_unmap(ctx, transfer);
777 }
778
779 if (rtransfer->staging) {
780 buf = ((struct r600_resource *)rtransfer->staging)->cs_buf;
781 } else {
782 buf = ((struct r600_resource *)transfer->resource)->cs_buf;
783 }
784 rctx->ws->buffer_unmap(buf);
785 }
786
787 void r600_init_surface_functions(struct r600_context *r600)
788 {
789 r600->context.create_surface = r600_create_surface;
790 r600->context.surface_destroy = r600_surface_destroy;
791 }
792
793 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
794 const unsigned char *swizzle_view)
795 {
796 unsigned i;
797 unsigned char swizzle[4];
798 unsigned result = 0;
799 const uint32_t swizzle_shift[4] = {
800 16, 19, 22, 25,
801 };
802 const uint32_t swizzle_bit[4] = {
803 0, 1, 2, 3,
804 };
805
806 if (swizzle_view) {
807 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
808 } else {
809 memcpy(swizzle, swizzle_format, 4);
810 }
811
812 /* Get swizzle. */
813 for (i = 0; i < 4; i++) {
814 switch (swizzle[i]) {
815 case UTIL_FORMAT_SWIZZLE_Y:
816 result |= swizzle_bit[1] << swizzle_shift[i];
817 break;
818 case UTIL_FORMAT_SWIZZLE_Z:
819 result |= swizzle_bit[2] << swizzle_shift[i];
820 break;
821 case UTIL_FORMAT_SWIZZLE_W:
822 result |= swizzle_bit[3] << swizzle_shift[i];
823 break;
824 case UTIL_FORMAT_SWIZZLE_0:
825 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
826 break;
827 case UTIL_FORMAT_SWIZZLE_1:
828 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
829 break;
830 default: /* UTIL_FORMAT_SWIZZLE_X */
831 result |= swizzle_bit[0] << swizzle_shift[i];
832 }
833 }
834 return result;
835 }
836
837 /* texture format translate */
838 uint32_t r600_translate_texformat(struct pipe_screen *screen,
839 enum pipe_format format,
840 const unsigned char *swizzle_view,
841 uint32_t *word4_p, uint32_t *yuv_format_p)
842 {
843 uint32_t result = 0, word4 = 0, yuv_format = 0;
844 const struct util_format_description *desc;
845 boolean uniform = TRUE;
846 static int r600_enable_s3tc = -1;
847 bool is_srgb_valid = FALSE;
848
849 int i;
850 const uint32_t sign_bit[4] = {
851 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
852 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
853 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
854 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
855 };
856 desc = util_format_description(format);
857
858 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
859
860 /* Colorspace (return non-RGB formats directly). */
861 switch (desc->colorspace) {
862 /* Depth stencil formats */
863 case UTIL_FORMAT_COLORSPACE_ZS:
864 switch (format) {
865 case PIPE_FORMAT_Z16_UNORM:
866 result = FMT_16;
867 goto out_word4;
868 case PIPE_FORMAT_X24S8_UINT:
869 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
870 case PIPE_FORMAT_Z24X8_UNORM:
871 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
872 result = FMT_8_24;
873 goto out_word4;
874 case PIPE_FORMAT_S8X24_UINT:
875 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
876 case PIPE_FORMAT_X8Z24_UNORM:
877 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
878 result = FMT_24_8;
879 goto out_word4;
880 case PIPE_FORMAT_S8_UINT:
881 result = FMT_8;
882 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
883 goto out_word4;
884 case PIPE_FORMAT_Z32_FLOAT:
885 result = FMT_32_FLOAT;
886 goto out_word4;
887 case PIPE_FORMAT_X32_S8X24_UINT:
888 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
889 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
890 result = FMT_X24_8_32_FLOAT;
891 goto out_word4;
892 default:
893 goto out_unknown;
894 }
895
896 case UTIL_FORMAT_COLORSPACE_YUV:
897 yuv_format |= (1 << 30);
898 switch (format) {
899 case PIPE_FORMAT_UYVY:
900 case PIPE_FORMAT_YUYV:
901 default:
902 break;
903 }
904 goto out_unknown; /* XXX */
905
906 case UTIL_FORMAT_COLORSPACE_SRGB:
907 word4 |= S_038010_FORCE_DEGAMMA(1);
908 break;
909
910 default:
911 break;
912 }
913
914 if (r600_enable_s3tc == -1) {
915 struct r600_screen *rscreen = (struct r600_screen *)screen;
916 if (rscreen->info.drm_minor >= 9)
917 r600_enable_s3tc = 1;
918 else
919 r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
920 }
921
922 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
923 if (!r600_enable_s3tc)
924 goto out_unknown;
925
926 switch (format) {
927 case PIPE_FORMAT_RGTC1_SNORM:
928 case PIPE_FORMAT_LATC1_SNORM:
929 word4 |= sign_bit[0];
930 case PIPE_FORMAT_RGTC1_UNORM:
931 case PIPE_FORMAT_LATC1_UNORM:
932 result = FMT_BC4;
933 goto out_word4;
934 case PIPE_FORMAT_RGTC2_SNORM:
935 case PIPE_FORMAT_LATC2_SNORM:
936 word4 |= sign_bit[0] | sign_bit[1];
937 case PIPE_FORMAT_RGTC2_UNORM:
938 case PIPE_FORMAT_LATC2_UNORM:
939 result = FMT_BC5;
940 goto out_word4;
941 default:
942 goto out_unknown;
943 }
944 }
945
946 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
947
948 if (!r600_enable_s3tc)
949 goto out_unknown;
950
951 if (!util_format_s3tc_enabled) {
952 goto out_unknown;
953 }
954
955 switch (format) {
956 case PIPE_FORMAT_DXT1_RGB:
957 case PIPE_FORMAT_DXT1_RGBA:
958 case PIPE_FORMAT_DXT1_SRGB:
959 case PIPE_FORMAT_DXT1_SRGBA:
960 result = FMT_BC1;
961 is_srgb_valid = TRUE;
962 goto out_word4;
963 case PIPE_FORMAT_DXT3_RGBA:
964 case PIPE_FORMAT_DXT3_SRGBA:
965 result = FMT_BC2;
966 is_srgb_valid = TRUE;
967 goto out_word4;
968 case PIPE_FORMAT_DXT5_RGBA:
969 case PIPE_FORMAT_DXT5_SRGBA:
970 result = FMT_BC3;
971 is_srgb_valid = TRUE;
972 goto out_word4;
973 default:
974 goto out_unknown;
975 }
976 }
977
978 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
979 switch (format) {
980 case PIPE_FORMAT_R8G8_B8G8_UNORM:
981 case PIPE_FORMAT_G8R8_B8R8_UNORM:
982 result = FMT_GB_GR;
983 goto out_word4;
984 case PIPE_FORMAT_G8R8_G8B8_UNORM:
985 case PIPE_FORMAT_R8G8_R8B8_UNORM:
986 result = FMT_BG_RG;
987 goto out_word4;
988 default:
989 goto out_unknown;
990 }
991 }
992
993 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
994 result = FMT_5_9_9_9_SHAREDEXP;
995 goto out_word4;
996 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
997 result = FMT_10_11_11_FLOAT;
998 goto out_word4;
999 }
1000
1001
1002 for (i = 0; i < desc->nr_channels; i++) {
1003 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1004 word4 |= sign_bit[i];
1005 }
1006 }
1007
1008 /* R8G8Bx_SNORM - XXX CxV8U8 */
1009
1010 /* See whether the components are of the same size. */
1011 for (i = 1; i < desc->nr_channels; i++) {
1012 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1013 }
1014
1015 /* Non-uniform formats. */
1016 if (!uniform) {
1017 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1018 desc->channel[0].pure_integer)
1019 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1020 switch(desc->nr_channels) {
1021 case 3:
1022 if (desc->channel[0].size == 5 &&
1023 desc->channel[1].size == 6 &&
1024 desc->channel[2].size == 5) {
1025 result = FMT_5_6_5;
1026 goto out_word4;
1027 }
1028 goto out_unknown;
1029 case 4:
1030 if (desc->channel[0].size == 5 &&
1031 desc->channel[1].size == 5 &&
1032 desc->channel[2].size == 5 &&
1033 desc->channel[3].size == 1) {
1034 result = FMT_1_5_5_5;
1035 goto out_word4;
1036 }
1037 if (desc->channel[0].size == 10 &&
1038 desc->channel[1].size == 10 &&
1039 desc->channel[2].size == 10 &&
1040 desc->channel[3].size == 2) {
1041 result = FMT_2_10_10_10;
1042 goto out_word4;
1043 }
1044 goto out_unknown;
1045 }
1046 goto out_unknown;
1047 }
1048
1049 /* Find the first non-VOID channel. */
1050 for (i = 0; i < 4; i++) {
1051 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1052 break;
1053 }
1054 }
1055
1056 if (i == 4)
1057 goto out_unknown;
1058
1059 /* uniform formats */
1060 switch (desc->channel[i].type) {
1061 case UTIL_FORMAT_TYPE_UNSIGNED:
1062 case UTIL_FORMAT_TYPE_SIGNED:
1063 #if 0
1064 if (!desc->channel[i].normalized &&
1065 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
1066 goto out_unknown;
1067 }
1068 #endif
1069 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1070 desc->channel[i].pure_integer)
1071 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1072
1073 switch (desc->channel[i].size) {
1074 case 4:
1075 switch (desc->nr_channels) {
1076 case 2:
1077 result = FMT_4_4;
1078 goto out_word4;
1079 case 4:
1080 result = FMT_4_4_4_4;
1081 goto out_word4;
1082 }
1083 goto out_unknown;
1084 case 8:
1085 switch (desc->nr_channels) {
1086 case 1:
1087 result = FMT_8;
1088 goto out_word4;
1089 case 2:
1090 result = FMT_8_8;
1091 goto out_word4;
1092 case 4:
1093 result = FMT_8_8_8_8;
1094 is_srgb_valid = TRUE;
1095 goto out_word4;
1096 }
1097 goto out_unknown;
1098 case 16:
1099 switch (desc->nr_channels) {
1100 case 1:
1101 result = FMT_16;
1102 goto out_word4;
1103 case 2:
1104 result = FMT_16_16;
1105 goto out_word4;
1106 case 4:
1107 result = FMT_16_16_16_16;
1108 goto out_word4;
1109 }
1110 goto out_unknown;
1111 case 32:
1112 switch (desc->nr_channels) {
1113 case 1:
1114 result = FMT_32;
1115 goto out_word4;
1116 case 2:
1117 result = FMT_32_32;
1118 goto out_word4;
1119 case 4:
1120 result = FMT_32_32_32_32;
1121 goto out_word4;
1122 }
1123 }
1124 goto out_unknown;
1125
1126 case UTIL_FORMAT_TYPE_FLOAT:
1127 switch (desc->channel[i].size) {
1128 case 16:
1129 switch (desc->nr_channels) {
1130 case 1:
1131 result = FMT_16_FLOAT;
1132 goto out_word4;
1133 case 2:
1134 result = FMT_16_16_FLOAT;
1135 goto out_word4;
1136 case 4:
1137 result = FMT_16_16_16_16_FLOAT;
1138 goto out_word4;
1139 }
1140 goto out_unknown;
1141 case 32:
1142 switch (desc->nr_channels) {
1143 case 1:
1144 result = FMT_32_FLOAT;
1145 goto out_word4;
1146 case 2:
1147 result = FMT_32_32_FLOAT;
1148 goto out_word4;
1149 case 4:
1150 result = FMT_32_32_32_32_FLOAT;
1151 goto out_word4;
1152 }
1153 }
1154 goto out_unknown;
1155 }
1156
1157 out_word4:
1158
1159 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid)
1160 return ~0;
1161 if (word4_p)
1162 *word4_p = word4;
1163 if (yuv_format_p)
1164 *yuv_format_p = yuv_format;
1165 return result;
1166 out_unknown:
1167 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1168 return ~0;
1169 }