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1d04cc06014a1dced9c0f3a1d90a731dc110bb73
[mesa.git] / src / gallium / drivers / r600 / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_formats.h"
28 #include "r600d.h"
29
30 #include <errno.h>
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33
34
35 /* Copy from a full GPU texture to a transfer's staging one. */
36 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
37 {
38 struct r600_context *rctx = (struct r600_context*)ctx;
39 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
40 struct pipe_resource *dst = &rtransfer->staging->b.b;
41 struct pipe_resource *src = transfer->resource;
42
43 if (src->nr_samples <= 1) {
44 if (!rctx->screen->dma_blit(ctx, dst, 0, 0, 0, 0,
45 src, transfer->level,
46 &transfer->box)) {
47 /* async dma could not be use */
48 ctx->resource_copy_region(ctx, dst, 0, 0, 0, 0,
49 src, transfer->level, &transfer->box);
50 }
51 } else {
52 /* Resolve the resource. */
53 struct pipe_blit_info blit;
54
55 memset(&blit, 0, sizeof(blit));
56 blit.src.resource = src;
57 blit.src.format = src->format;
58 blit.src.level = transfer->level;
59 blit.src.box = transfer->box;
60 blit.dst.resource = dst;
61 blit.dst.format = dst->format;
62 blit.dst.box.width = transfer->box.width;
63 blit.dst.box.height = transfer->box.height;
64 blit.dst.box.depth = transfer->box.depth;
65 blit.mask = PIPE_MASK_RGBA;
66 blit.filter = PIPE_TEX_FILTER_NEAREST;
67
68 ctx->blit(ctx, &blit);
69 }
70 }
71
72 /* Copy from a transfer's staging texture to a full GPU one. */
73 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
74 {
75 struct r600_context *rctx = (struct r600_context*)ctx;
76 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
77 struct pipe_resource *texture = transfer->resource;
78 struct pipe_box sbox;
79
80 u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
81
82 if (!rctx->screen->dma_blit(ctx, texture, transfer->level,
83 transfer->box.x, transfer->box.y, transfer->box.z,
84 &rtransfer->staging->b.b, 0, &sbox)) {
85 /* async dma could not be use */
86 ctx->resource_copy_region(ctx, texture, transfer->level,
87 transfer->box.x, transfer->box.y, transfer->box.z,
88 &rtransfer->staging->b.b,
89 0, &sbox);
90 }
91 }
92
93 unsigned r600_texture_get_offset(struct r600_texture *rtex,
94 unsigned level, unsigned layer)
95 {
96 return rtex->surface.level[level].offset +
97 layer * rtex->surface.level[level].slice_size;
98 }
99
100 static int r600_init_surface(struct r600_screen *rscreen,
101 struct radeon_surface *surface,
102 const struct pipe_resource *ptex,
103 unsigned array_mode,
104 bool is_flushed_depth)
105 {
106 const struct util_format_description *desc =
107 util_format_description(ptex->format);
108 bool is_depth, is_stencil;
109
110 is_depth = util_format_has_depth(desc);
111 is_stencil = util_format_has_stencil(desc);
112
113 surface->npix_x = ptex->width0;
114 surface->npix_y = ptex->height0;
115 surface->npix_z = ptex->depth0;
116 surface->blk_w = util_format_get_blockwidth(ptex->format);
117 surface->blk_h = util_format_get_blockheight(ptex->format);
118 surface->blk_d = 1;
119 surface->array_size = 1;
120 surface->last_level = ptex->last_level;
121
122 if (rscreen->chip_class >= EVERGREEN && !is_flushed_depth &&
123 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
124 surface->bpe = 4; /* stencil is allocated separately on evergreen */
125 } else {
126 surface->bpe = util_format_get_blocksize(ptex->format);
127 /* align byte per element on dword */
128 if (surface->bpe == 3) {
129 surface->bpe = 4;
130 }
131 }
132
133 surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1;
134 surface->flags = 0;
135
136 switch (array_mode) {
137 case V_038000_ARRAY_1D_TILED_THIN1:
138 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
139 break;
140 case V_038000_ARRAY_2D_TILED_THIN1:
141 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
142 break;
143 case V_038000_ARRAY_LINEAR_ALIGNED:
144 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
145 break;
146 case V_038000_ARRAY_LINEAR_GENERAL:
147 default:
148 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE);
149 break;
150 }
151 switch (ptex->target) {
152 case PIPE_TEXTURE_1D:
153 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
154 break;
155 case PIPE_TEXTURE_RECT:
156 case PIPE_TEXTURE_2D:
157 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
158 break;
159 case PIPE_TEXTURE_3D:
160 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
161 break;
162 case PIPE_TEXTURE_1D_ARRAY:
163 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
164 surface->array_size = ptex->array_size;
165 break;
166 case PIPE_TEXTURE_2D_ARRAY:
167 case PIPE_TEXTURE_CUBE_ARRAY: /* cube array layout like 2d layout for now */
168 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
169 surface->array_size = ptex->array_size;
170 break;
171 case PIPE_TEXTURE_CUBE:
172 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
173 break;
174 case PIPE_BUFFER:
175 default:
176 return -EINVAL;
177 }
178 if (ptex->bind & PIPE_BIND_SCANOUT) {
179 surface->flags |= RADEON_SURF_SCANOUT;
180 }
181
182 if (!is_flushed_depth && is_depth) {
183 surface->flags |= RADEON_SURF_ZBUFFER;
184
185 if (is_stencil) {
186 surface->flags |= RADEON_SURF_SBUFFER |
187 RADEON_SURF_HAS_SBUFFER_MIPTREE;
188 }
189 }
190 return 0;
191 }
192
193 static int r600_setup_surface(struct pipe_screen *screen,
194 struct r600_texture *rtex,
195 unsigned pitch_in_bytes_override)
196 {
197 struct pipe_resource *ptex = &rtex->resource.b.b;
198 struct r600_screen *rscreen = (struct r600_screen*)screen;
199 unsigned i;
200 int r;
201
202 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
203 if (r) {
204 return r;
205 }
206 rtex->size = rtex->surface.bo_size;
207 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
208 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
209 * for those
210 */
211 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
212 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
213 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
214 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
215 rtex->surface.stencil_offset =
216 rtex->surface.stencil_level[0].offset = rtex->surface.level[0].slice_size;
217 }
218 }
219 for (i = 0; i <= ptex->last_level; i++) {
220 switch (rtex->surface.level[i].mode) {
221 case RADEON_SURF_MODE_LINEAR_ALIGNED:
222 rtex->array_mode[i] = V_038000_ARRAY_LINEAR_ALIGNED;
223 break;
224 case RADEON_SURF_MODE_1D:
225 rtex->array_mode[i] = V_038000_ARRAY_1D_TILED_THIN1;
226 break;
227 case RADEON_SURF_MODE_2D:
228 rtex->array_mode[i] = V_038000_ARRAY_2D_TILED_THIN1;
229 break;
230 default:
231 case RADEON_SURF_MODE_LINEAR:
232 rtex->array_mode[i] = 0;
233 break;
234 }
235 }
236 return 0;
237 }
238
239 static boolean r600_texture_get_handle(struct pipe_screen* screen,
240 struct pipe_resource *ptex,
241 struct winsys_handle *whandle)
242 {
243 struct r600_texture *rtex = (struct r600_texture*)ptex;
244 struct r600_resource *resource = &rtex->resource;
245 struct radeon_surface *surface = &rtex->surface;
246 struct r600_screen *rscreen = (struct r600_screen*)screen;
247
248 rscreen->ws->buffer_set_tiling(resource->buf,
249 NULL,
250 surface->level[0].mode >= RADEON_SURF_MODE_1D ?
251 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
252 surface->level[0].mode >= RADEON_SURF_MODE_2D ?
253 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
254 surface->bankw, surface->bankh,
255 surface->tile_split,
256 surface->stencil_tile_split,
257 surface->mtilea,
258 rtex->surface.level[0].pitch_bytes);
259
260 return rscreen->ws->buffer_get_handle(resource->buf,
261 rtex->surface.level[0].pitch_bytes, whandle);
262 }
263
264 static void r600_texture_destroy(struct pipe_screen *screen,
265 struct pipe_resource *ptex)
266 {
267 struct r600_texture *rtex = (struct r600_texture*)ptex;
268 struct r600_resource *resource = &rtex->resource;
269
270 if (rtex->flushed_depth_texture)
271 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
272
273 pb_reference(&resource->buf, NULL);
274 FREE(rtex);
275 }
276
277 static const struct u_resource_vtbl r600_texture_vtbl;
278
279 /* The number of samples can be specified independently of the texture. */
280 void r600_texture_get_fmask_info(struct r600_screen *rscreen,
281 struct r600_texture *rtex,
282 unsigned nr_samples,
283 struct r600_fmask_info *out)
284 {
285 /* FMASK is allocated pretty much like an ordinary texture.
286 * Here we use bpe in the units of bits, not bytes. */
287 struct radeon_surface fmask = rtex->surface;
288
289 switch (nr_samples) {
290 case 2:
291 /* This should be 8,1, but we should set nsamples > 1
292 * for the allocator to treat it as a multisample surface.
293 * Let's set 4,2 then. */
294 case 4:
295 fmask.bpe = 4;
296 fmask.nsamples = 2;
297 break;
298 case 8:
299 fmask.bpe = 8;
300 fmask.nsamples = 4;
301 break;
302 case 16:
303 fmask.bpe = 16;
304 fmask.nsamples = 4;
305 break;
306 default:
307 R600_ERR("Invalid sample count for FMASK allocation.\n");
308 return;
309 }
310
311 /* R600-R700 errata? Anyway, this fixes colorbuffer corruption. */
312 if (rscreen->chip_class <= R700) {
313 fmask.bpe *= 2;
314 }
315
316 if (rscreen->chip_class >= EVERGREEN) {
317 fmask.bankh = nr_samples <= 4 ? 4 : 1;
318 }
319
320 if (rscreen->ws->surface_init(rscreen->ws, &fmask)) {
321 R600_ERR("Got error in surface_init while allocating FMASK.\n");
322 return;
323 }
324 assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
325
326 out->bank_height = fmask.bankh;
327 out->alignment = MAX2(256, fmask.bo_alignment);
328 out->size = (fmask.bo_size + 7) / 8;
329 }
330
331 static void r600_texture_allocate_fmask(struct r600_screen *rscreen,
332 struct r600_texture *rtex)
333 {
334 struct r600_fmask_info fmask;
335
336 r600_texture_get_fmask_info(rscreen, rtex,
337 rtex->resource.b.b.nr_samples, &fmask);
338
339 rtex->fmask_bank_height = fmask.bank_height;
340 rtex->fmask_offset = align(rtex->size, fmask.alignment);
341 rtex->fmask_size = fmask.size;
342 rtex->size = rtex->fmask_offset + rtex->fmask_size;
343 #if 0
344 printf("FMASK width=%u, height=%i, bits=%u, size=%u\n",
345 fmask.npix_x, fmask.npix_y, fmask.bpe * fmask.nsamples, rtex->fmask_size);
346 #endif
347 }
348
349 void r600_texture_get_cmask_info(struct r600_screen *rscreen,
350 struct r600_texture *rtex,
351 struct r600_cmask_info *out)
352 {
353 unsigned cmask_tile_width = 8;
354 unsigned cmask_tile_height = 8;
355 unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
356 unsigned element_bits = 4;
357 unsigned cmask_cache_bits = 1024;
358 unsigned num_pipes = rscreen->tiling_info.num_channels;
359 unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
360
361 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
362 unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
363 unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
364 unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
365 unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
366
367 unsigned pitch_elements = align(rtex->surface.npix_x, macro_tile_width);
368 unsigned height = align(rtex->surface.npix_y, macro_tile_height);
369
370 unsigned base_align = num_pipes * pipe_interleave_bytes;
371 unsigned slice_bytes =
372 ((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
373
374 assert(macro_tile_width % 128 == 0);
375 assert(macro_tile_height % 128 == 0);
376
377 out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
378 out->alignment = MAX2(256, base_align);
379 out->size = rtex->surface.array_size * align(slice_bytes, base_align);
380 }
381
382 static void r600_texture_allocate_cmask(struct r600_screen *rscreen,
383 struct r600_texture *rtex)
384 {
385 struct r600_cmask_info cmask;
386
387 r600_texture_get_cmask_info(rscreen, rtex, &cmask);
388
389 rtex->cmask_slice_tile_max = cmask.slice_tile_max;
390 rtex->cmask_offset = align(rtex->size, cmask.alignment);
391 rtex->cmask_size = cmask.size;
392 rtex->size = rtex->cmask_offset + rtex->cmask_size;
393 #if 0
394 printf("CMASK: macro tile width = %u, macro tile height = %u, "
395 "pitch elements = %u, height = %u, slice tile max = %u\n",
396 macro_tile_width, macro_tile_height, pitch_elements, height,
397 rtex->cmask_slice_tile_max);
398 #endif
399 }
400
401 DEBUG_GET_ONCE_BOOL_OPTION(print_texdepth, "R600_PRINT_TEXDEPTH", FALSE);
402
403 static struct r600_texture *
404 r600_texture_create_object(struct pipe_screen *screen,
405 const struct pipe_resource *base,
406 unsigned pitch_in_bytes_override,
407 struct pb_buffer *buf,
408 struct radeon_surface *surface)
409 {
410 struct r600_texture *rtex;
411 struct r600_resource *resource;
412 struct r600_screen *rscreen = (struct r600_screen*)screen;
413 int r;
414
415 rtex = CALLOC_STRUCT(r600_texture);
416 if (rtex == NULL)
417 return NULL;
418
419 resource = &rtex->resource;
420 resource->b.b = *base;
421 resource->b.vtbl = &r600_texture_vtbl;
422 pipe_reference_init(&resource->b.b.reference, 1);
423 resource->b.b.screen = screen;
424 rtex->pitch_override = pitch_in_bytes_override;
425
426 /* don't include stencil-only formats which we don't support for rendering */
427 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
428
429 rtex->surface = *surface;
430 r = r600_setup_surface(screen, rtex,
431 pitch_in_bytes_override);
432 if (r) {
433 FREE(rtex);
434 return NULL;
435 }
436
437 if (base->nr_samples > 1 && !rtex->is_depth && !buf) {
438 r600_texture_allocate_cmask(rscreen, rtex);
439 r600_texture_allocate_fmask(rscreen, rtex);
440 }
441
442 if (!rtex->is_depth && base->nr_samples > 1 &&
443 (!rtex->fmask_size || !rtex->cmask_size)) {
444 FREE(rtex);
445 return NULL;
446 }
447
448 /* Tiled depth textures utilize the non-displayable tile order. */
449 rtex->non_disp_tiling = rtex->is_depth && rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D;
450
451 /* only enable hyperz for PIPE_TEXTURE_2D not for PIPE_TEXTURE_2D_ARRAY
452 * Thought it might still be interessting to use hyperz for texture
453 * array without using fast clear features
454 */
455 rtex->htile = NULL;
456 if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER | R600_RESOURCE_FLAG_FLUSHED_DEPTH)) &&
457 util_format_is_depth_or_stencil(base->format) &&
458 rscreen->use_hyperz &&
459 base->target == PIPE_TEXTURE_2D &&
460 rtex->surface.level[0].nblk_x >= 32 &&
461 rtex->surface.level[0].nblk_y >= 32) {
462 unsigned sw = rtex->surface.level[0].nblk_x * rtex->surface.blk_w;
463 unsigned sh = rtex->surface.level[0].nblk_y * rtex->surface.blk_h;
464 unsigned htile_size;
465 unsigned npipes = rscreen->info.r600_num_tile_pipes;
466
467 /* this alignment and htile size only apply to linear htile buffer */
468 sw = align(sw, 16 << 3);
469 sh = align(sh, npipes << 3);
470 htile_size = (sw >> 3) * (sh >> 3) * 4;
471 /* must be aligned with 2K * npipes */
472 htile_size = align(htile_size, (2 << 10) * npipes);
473
474 rtex->htile = (struct r600_resource*)pipe_buffer_create(&rscreen->screen, PIPE_BIND_CUSTOM,
475 PIPE_USAGE_STATIC, htile_size);
476 if (rtex->htile == NULL) {
477 /* this is not a fatal error as we can still keep rendering
478 * without htile buffer
479 */
480 R600_ERR("r600: failed to create bo for htile buffers\n");
481 } else {
482 void *ptr;
483 ptr = rscreen->ws->buffer_map(rtex->htile->cs_buf, NULL, PIPE_TRANSFER_WRITE);
484 memset(ptr, 0x0, htile_size);
485 rscreen->ws->buffer_unmap(rtex->htile->cs_buf);
486 }
487 }
488
489 /* Now create the backing buffer. */
490 if (!buf) {
491 unsigned base_align = rtex->surface.bo_alignment;
492 unsigned usage = R600_TEX_IS_TILED(rtex, 0) ? PIPE_USAGE_STATIC : base->usage;
493
494 if (!r600_init_resource(rscreen, resource, rtex->size, base_align, FALSE, usage)) {
495 FREE(rtex);
496 return NULL;
497 }
498 } else {
499 /* This is usually the window framebuffer. We want it in VRAM, always. */
500 resource->buf = buf;
501 resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);
502 resource->domains = RADEON_DOMAIN_VRAM;
503 }
504
505 if (rtex->cmask_size) {
506 /* Initialize the cmask to 0xCC (= compressed state). */
507 char *ptr = rscreen->ws->buffer_map(resource->cs_buf, NULL, PIPE_TRANSFER_WRITE);
508 memset(ptr + rtex->cmask_offset, 0xCC, rtex->cmask_size);
509 rscreen->ws->buffer_unmap(resource->cs_buf);
510 }
511
512 if (debug_get_option_print_texdepth() && rtex->is_depth && rtex->non_disp_tiling) {
513 printf("Texture: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
514 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
515 "bpe=%u, nsamples=%u, flags=%u\n",
516 rtex->surface.npix_x, rtex->surface.npix_y,
517 rtex->surface.npix_z, rtex->surface.blk_w,
518 rtex->surface.blk_h, rtex->surface.blk_d,
519 rtex->surface.array_size, rtex->surface.last_level,
520 rtex->surface.bpe, rtex->surface.nsamples,
521 rtex->surface.flags);
522 if (rtex->surface.flags & RADEON_SURF_ZBUFFER) {
523 for (int i = 0; i <= rtex->surface.last_level; i++) {
524 printf(" Z %i: offset=%llu, slice_size=%llu, npix_x=%u, "
525 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
526 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
527 i, (unsigned long long)rtex->surface.level[i].offset,
528 (unsigned long long)rtex->surface.level[i].slice_size,
529 u_minify(rtex->resource.b.b.width0, i),
530 u_minify(rtex->resource.b.b.height0, i),
531 u_minify(rtex->resource.b.b.depth0, i),
532 rtex->surface.level[i].nblk_x,
533 rtex->surface.level[i].nblk_y,
534 rtex->surface.level[i].nblk_z,
535 rtex->surface.level[i].pitch_bytes,
536 rtex->surface.level[i].mode);
537 }
538 }
539 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
540 for (int i = 0; i <= rtex->surface.last_level; i++) {
541 printf(" S %i: offset=%llu, slice_size=%llu, npix_x=%u, "
542 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
543 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
544 i, (unsigned long long)rtex->surface.stencil_level[i].offset,
545 (unsigned long long)rtex->surface.stencil_level[i].slice_size,
546 u_minify(rtex->resource.b.b.width0, i),
547 u_minify(rtex->resource.b.b.height0, i),
548 u_minify(rtex->resource.b.b.depth0, i),
549 rtex->surface.stencil_level[i].nblk_x,
550 rtex->surface.stencil_level[i].nblk_y,
551 rtex->surface.stencil_level[i].nblk_z,
552 rtex->surface.stencil_level[i].pitch_bytes,
553 rtex->surface.stencil_level[i].mode);
554 }
555 }
556 }
557 return rtex;
558 }
559
560 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
561 const struct pipe_resource *templ)
562 {
563 struct r600_screen *rscreen = (struct r600_screen*)screen;
564 struct radeon_surface surface;
565 const struct util_format_description *desc = util_format_description(templ->format);
566 unsigned array_mode;
567 int r;
568
569 /* Default tiling mode for staging textures. */
570 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
571
572 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats. That's not an issue,
573 * because 422 formats are used for videos, which prefer linear buffers
574 * for fast uploads anyway. */
575 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
576 desc->layout != UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
577 if (templ->flags & R600_RESOURCE_FLAG_FORCE_TILING) {
578 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
579 } else if (!(templ->bind & PIPE_BIND_SCANOUT) &&
580 templ->usage != PIPE_USAGE_STAGING &&
581 templ->usage != PIPE_USAGE_STREAM &&
582 templ->target != PIPE_TEXTURE_1D &&
583 templ->target != PIPE_TEXTURE_1D_ARRAY &&
584 templ->height0 > 3) {
585 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
586 } else if (util_format_is_compressed(templ->format)) {
587 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
588 }
589 }
590
591 r = r600_init_surface(rscreen, &surface, templ, array_mode,
592 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
593 if (r) {
594 return NULL;
595 }
596 r = rscreen->ws->surface_best(rscreen->ws, &surface);
597 if (r) {
598 return NULL;
599 }
600 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
601 0, NULL, &surface);
602 }
603
604 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
605 struct pipe_resource *texture,
606 const struct pipe_surface *templ,
607 unsigned width, unsigned height)
608 {
609 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
610
611 assert(templ->u.tex.first_layer <= u_max_layer(texture, templ->u.tex.level));
612 assert(templ->u.tex.last_layer <= u_max_layer(texture, templ->u.tex.level));
613 assert(templ->u.tex.first_layer == templ->u.tex.last_layer);
614 if (surface == NULL)
615 return NULL;
616 pipe_reference_init(&surface->base.reference, 1);
617 pipe_resource_reference(&surface->base.texture, texture);
618 surface->base.context = pipe;
619 surface->base.format = templ->format;
620 surface->base.width = width;
621 surface->base.height = height;
622 surface->base.u = templ->u;
623 return &surface->base;
624 }
625
626 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
627 struct pipe_resource *tex,
628 const struct pipe_surface *templ)
629 {
630 unsigned level = templ->u.tex.level;
631
632 return r600_create_surface_custom(pipe, tex, templ,
633 u_minify(tex->width0, level),
634 u_minify(tex->height0, level));
635 }
636
637 static void r600_surface_destroy(struct pipe_context *pipe,
638 struct pipe_surface *surface)
639 {
640 struct r600_surface *surf = (struct r600_surface*)surface;
641 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, NULL);
642 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, NULL);
643 pipe_resource_reference(&surface->texture, NULL);
644 FREE(surface);
645 }
646
647 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
648 const struct pipe_resource *templ,
649 struct winsys_handle *whandle)
650 {
651 struct r600_screen *rscreen = (struct r600_screen*)screen;
652 struct pb_buffer *buf = NULL;
653 unsigned stride = 0;
654 unsigned array_mode = 0;
655 enum radeon_bo_layout micro, macro;
656 struct radeon_surface surface;
657 int r;
658
659 /* Support only 2D textures without mipmaps */
660 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
661 templ->depth0 != 1 || templ->last_level != 0)
662 return NULL;
663
664 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
665 if (!buf)
666 return NULL;
667
668 rscreen->ws->buffer_get_tiling(buf, &micro, &macro,
669 &surface.bankw, &surface.bankh,
670 &surface.tile_split,
671 &surface.stencil_tile_split,
672 &surface.mtilea);
673
674 if (macro == RADEON_LAYOUT_TILED)
675 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
676 else if (micro == RADEON_LAYOUT_TILED)
677 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
678 else
679 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
680
681 r = r600_init_surface(rscreen, &surface, templ, array_mode, false);
682 if (r) {
683 return NULL;
684 }
685 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
686 stride, buf, &surface);
687 }
688
689 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
690 struct pipe_resource *texture,
691 struct r600_texture **staging)
692 {
693 struct r600_texture *rtex = (struct r600_texture*)texture;
694 struct pipe_resource resource;
695 struct r600_texture **flushed_depth_texture = staging ?
696 staging : &rtex->flushed_depth_texture;
697
698 if (!staging && rtex->flushed_depth_texture)
699 return true; /* it's ready */
700
701 resource.target = texture->target;
702 resource.format = texture->format;
703 resource.width0 = texture->width0;
704 resource.height0 = texture->height0;
705 resource.depth0 = texture->depth0;
706 resource.array_size = texture->array_size;
707 resource.last_level = texture->last_level;
708 resource.nr_samples = texture->nr_samples;
709 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_STATIC;
710 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
711 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
712
713 if (staging)
714 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
715
716 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
717 if (*flushed_depth_texture == NULL) {
718 R600_ERR("failed to create temporary texture to hold flushed depth\n");
719 return false;
720 }
721
722 (*flushed_depth_texture)->is_flushing_texture = TRUE;
723 (*flushed_depth_texture)->non_disp_tiling = false;
724 return true;
725 }
726
727 static void *r600_texture_transfer_map(struct pipe_context *ctx,
728 struct pipe_resource *texture,
729 unsigned level,
730 unsigned usage,
731 const struct pipe_box *box,
732 struct pipe_transfer **ptransfer)
733 {
734 struct r600_context *rctx = (struct r600_context*)ctx;
735 struct r600_texture *rtex = (struct r600_texture*)texture;
736 struct r600_transfer *trans;
737 boolean use_staging_texture = FALSE;
738 enum pipe_format format = texture->format;
739 struct r600_resource *buf;
740 unsigned offset = 0;
741 char *map;
742
743 if ((texture->bind & PIPE_BIND_GLOBAL) && texture->target == PIPE_BUFFER) {
744 return r600_compute_global_transfer_map(ctx, texture, level, usage, box, ptransfer);
745 }
746
747 /* We cannot map a tiled texture directly because the data is
748 * in a different order, therefore we do detiling using a blit.
749 *
750 * Also, use a temporary in GTT memory for read transfers, as
751 * the CPU is much happier reading out of cached system memory
752 * than uncached VRAM.
753 */
754 if (R600_TEX_IS_TILED(rtex, level)) {
755 use_staging_texture = TRUE;
756 }
757
758 /* Use a staging texture for uploads if the underlying BO is busy. */
759 if (!(usage & PIPE_TRANSFER_READ) &&
760 (r600_rings_is_buffer_referenced(rctx, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) ||
761 rctx->ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE))) {
762 use_staging_texture = TRUE;
763 }
764
765 if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) {
766 use_staging_texture = FALSE;
767 }
768
769 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) {
770 return NULL;
771 }
772
773 trans = CALLOC_STRUCT(r600_transfer);
774 if (trans == NULL)
775 return NULL;
776 trans->transfer.resource = texture;
777 trans->transfer.level = level;
778 trans->transfer.usage = usage;
779 trans->transfer.box = *box;
780 if (rtex->is_depth) {
781 /* XXX: only readback the rectangle which is being mapped?
782 */
783 /* XXX: when discard is true, no need to read back from depth texture
784 */
785 struct r600_texture *staging_depth;
786
787 assert(rtex->resource.b.b.nr_samples <= 1);
788 if (rtex->resource.b.b.nr_samples > 1) {
789 R600_ERR("mapping MSAA zbuffer unimplemented\n");
790 FREE(trans);
791 return NULL;
792 }
793
794 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
795 R600_ERR("failed to create temporary texture to hold untiled copy\n");
796 FREE(trans);
797 return NULL;
798 }
799
800 r600_blit_decompress_depth(ctx, rtex, staging_depth,
801 level, level,
802 box->z, box->z + box->depth - 1,
803 0, 0);
804
805 trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
806 trans->transfer.layer_stride = staging_depth->surface.level[level].slice_size;
807 trans->offset = r600_texture_get_offset(staging_depth, level, box->z);
808 trans->staging = (struct r600_resource*)staging_depth;
809 } else if (use_staging_texture) {
810 struct pipe_resource resource;
811 struct r600_texture *staging;
812
813 memset(&resource, 0, sizeof(resource));
814 resource.format = texture->format;
815 resource.width0 = box->width;
816 resource.height0 = box->height;
817 resource.depth0 = 1;
818 resource.array_size = 1;
819 resource.usage = PIPE_USAGE_STAGING;
820 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
821
822 /* We must set the correct texture target and dimensions if needed for a 3D transfer. */
823 if (box->depth > 1 && u_max_layer(texture, level) > 0)
824 resource.target = texture->target;
825 else
826 resource.target = PIPE_TEXTURE_2D;
827
828 switch (resource.target) {
829 case PIPE_TEXTURE_1D_ARRAY:
830 case PIPE_TEXTURE_2D_ARRAY:
831 case PIPE_TEXTURE_CUBE_ARRAY:
832 resource.array_size = box->depth;
833 break;
834 case PIPE_TEXTURE_3D:
835 resource.depth0 = box->depth;
836 break;
837 default:;
838 }
839
840
841 /* Create the temporary texture. */
842 staging = (struct r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
843 if (staging == NULL) {
844 R600_ERR("failed to create temporary texture to hold untiled copy\n");
845 FREE(trans);
846 return NULL;
847 }
848 trans->staging = &staging->resource;
849 trans->transfer.stride = staging->surface.level[0].pitch_bytes;
850 trans->transfer.layer_stride = staging->surface.level[0].slice_size;
851 if (usage & PIPE_TRANSFER_READ) {
852 r600_copy_to_staging_texture(ctx, trans);
853 /* flush gfx & dma ring, order does not matter as only one can be live */
854 if (rctx->rings.dma.cs) {
855 rctx->rings.dma.flush(rctx, 0);
856 }
857 rctx->rings.gfx.flush(rctx, 0);
858 }
859 } else {
860 trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
861 trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
862 trans->offset = r600_texture_get_offset(rtex, level, box->z);
863 }
864
865 if (trans->staging) {
866 buf = trans->staging;
867 } else {
868 buf = &rtex->resource;
869 }
870
871 if (rtex->is_depth || !trans->staging)
872 offset = trans->offset +
873 box->y / util_format_get_blockheight(format) * trans->transfer.stride +
874 box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
875
876 if (!(map = r600_buffer_mmap_sync_with_rings(rctx, buf, usage))) {
877 pipe_resource_reference((struct pipe_resource**)&trans->staging, NULL);
878 FREE(trans);
879 return NULL;
880 }
881
882 *ptransfer = &trans->transfer;
883 return map + offset;
884 }
885
886 static void r600_texture_transfer_unmap(struct pipe_context *ctx,
887 struct pipe_transfer* transfer)
888 {
889 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
890 struct r600_context *rctx = (struct r600_context*)ctx;
891 struct radeon_winsys_cs_handle *buf;
892 struct pipe_resource *texture = transfer->resource;
893 struct r600_texture *rtex = (struct r600_texture*)texture;
894
895 if ((transfer->resource->bind & PIPE_BIND_GLOBAL) && transfer->resource->target == PIPE_BUFFER) {
896 return r600_compute_global_transfer_unmap(ctx, transfer);
897 }
898
899 if (rtransfer->staging) {
900 buf = ((struct r600_resource *)rtransfer->staging)->cs_buf;
901 } else {
902 buf = ((struct r600_resource *)transfer->resource)->cs_buf;
903 }
904 rctx->ws->buffer_unmap(buf);
905
906 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
907 if (rtex->is_depth) {
908 ctx->resource_copy_region(ctx, texture, transfer->level,
909 transfer->box.x, transfer->box.y, transfer->box.z,
910 &rtransfer->staging->b.b, transfer->level,
911 &transfer->box);
912 } else {
913 r600_copy_from_staging_texture(ctx, rtransfer);
914 }
915 }
916
917 if (rtransfer->staging)
918 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
919
920 FREE(transfer);
921 }
922
923 void r600_init_surface_functions(struct r600_context *r600)
924 {
925 r600->context.create_surface = r600_create_surface;
926 r600->context.surface_destroy = r600_surface_destroy;
927 }
928
929 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
930 const unsigned char *swizzle_view,
931 boolean vtx)
932 {
933 unsigned i;
934 unsigned char swizzle[4];
935 unsigned result = 0;
936 const uint32_t tex_swizzle_shift[4] = {
937 16, 19, 22, 25,
938 };
939 const uint32_t vtx_swizzle_shift[4] = {
940 3, 6, 9, 12,
941 };
942 const uint32_t swizzle_bit[4] = {
943 0, 1, 2, 3,
944 };
945 const uint32_t *swizzle_shift = tex_swizzle_shift;
946
947 if (vtx)
948 swizzle_shift = vtx_swizzle_shift;
949
950 if (swizzle_view) {
951 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
952 } else {
953 memcpy(swizzle, swizzle_format, 4);
954 }
955
956 /* Get swizzle. */
957 for (i = 0; i < 4; i++) {
958 switch (swizzle[i]) {
959 case UTIL_FORMAT_SWIZZLE_Y:
960 result |= swizzle_bit[1] << swizzle_shift[i];
961 break;
962 case UTIL_FORMAT_SWIZZLE_Z:
963 result |= swizzle_bit[2] << swizzle_shift[i];
964 break;
965 case UTIL_FORMAT_SWIZZLE_W:
966 result |= swizzle_bit[3] << swizzle_shift[i];
967 break;
968 case UTIL_FORMAT_SWIZZLE_0:
969 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
970 break;
971 case UTIL_FORMAT_SWIZZLE_1:
972 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
973 break;
974 default: /* UTIL_FORMAT_SWIZZLE_X */
975 result |= swizzle_bit[0] << swizzle_shift[i];
976 }
977 }
978 return result;
979 }
980
981 /* texture format translate */
982 uint32_t r600_translate_texformat(struct pipe_screen *screen,
983 enum pipe_format format,
984 const unsigned char *swizzle_view,
985 uint32_t *word4_p, uint32_t *yuv_format_p)
986 {
987 uint32_t result = 0, word4 = 0, yuv_format = 0;
988 const struct util_format_description *desc;
989 boolean uniform = TRUE;
990 static int r600_enable_s3tc = -1;
991 bool is_srgb_valid = FALSE;
992
993 int i;
994 const uint32_t sign_bit[4] = {
995 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
996 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
997 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
998 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
999 };
1000 desc = util_format_description(format);
1001
1002 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view, FALSE);
1003
1004 /* Colorspace (return non-RGB formats directly). */
1005 switch (desc->colorspace) {
1006 /* Depth stencil formats */
1007 case UTIL_FORMAT_COLORSPACE_ZS:
1008 switch (format) {
1009 case PIPE_FORMAT_Z16_UNORM:
1010 result = FMT_16;
1011 goto out_word4;
1012 case PIPE_FORMAT_X24S8_UINT:
1013 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1014 case PIPE_FORMAT_Z24X8_UNORM:
1015 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1016 result = FMT_8_24;
1017 goto out_word4;
1018 case PIPE_FORMAT_S8X24_UINT:
1019 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1020 case PIPE_FORMAT_X8Z24_UNORM:
1021 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1022 result = FMT_24_8;
1023 goto out_word4;
1024 case PIPE_FORMAT_S8_UINT:
1025 result = FMT_8;
1026 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1027 goto out_word4;
1028 case PIPE_FORMAT_Z32_FLOAT:
1029 result = FMT_32_FLOAT;
1030 goto out_word4;
1031 case PIPE_FORMAT_X32_S8X24_UINT:
1032 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1033 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1034 result = FMT_X24_8_32_FLOAT;
1035 goto out_word4;
1036 default:
1037 goto out_unknown;
1038 }
1039
1040 case UTIL_FORMAT_COLORSPACE_YUV:
1041 yuv_format |= (1 << 30);
1042 switch (format) {
1043 case PIPE_FORMAT_UYVY:
1044 case PIPE_FORMAT_YUYV:
1045 default:
1046 break;
1047 }
1048 goto out_unknown; /* XXX */
1049
1050 case UTIL_FORMAT_COLORSPACE_SRGB:
1051 word4 |= S_038010_FORCE_DEGAMMA(1);
1052 break;
1053
1054 default:
1055 break;
1056 }
1057
1058 if (r600_enable_s3tc == -1) {
1059 struct r600_screen *rscreen = (struct r600_screen *)screen;
1060 if (rscreen->info.drm_minor >= 9)
1061 r600_enable_s3tc = 1;
1062 else
1063 r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
1064 }
1065
1066 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1067 if (!r600_enable_s3tc)
1068 goto out_unknown;
1069
1070 switch (format) {
1071 case PIPE_FORMAT_RGTC1_SNORM:
1072 case PIPE_FORMAT_LATC1_SNORM:
1073 word4 |= sign_bit[0];
1074 case PIPE_FORMAT_RGTC1_UNORM:
1075 case PIPE_FORMAT_LATC1_UNORM:
1076 result = FMT_BC4;
1077 goto out_word4;
1078 case PIPE_FORMAT_RGTC2_SNORM:
1079 case PIPE_FORMAT_LATC2_SNORM:
1080 word4 |= sign_bit[0] | sign_bit[1];
1081 case PIPE_FORMAT_RGTC2_UNORM:
1082 case PIPE_FORMAT_LATC2_UNORM:
1083 result = FMT_BC5;
1084 goto out_word4;
1085 default:
1086 goto out_unknown;
1087 }
1088 }
1089
1090 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1091
1092 if (!r600_enable_s3tc)
1093 goto out_unknown;
1094
1095 if (!util_format_s3tc_enabled) {
1096 goto out_unknown;
1097 }
1098
1099 switch (format) {
1100 case PIPE_FORMAT_DXT1_RGB:
1101 case PIPE_FORMAT_DXT1_RGBA:
1102 case PIPE_FORMAT_DXT1_SRGB:
1103 case PIPE_FORMAT_DXT1_SRGBA:
1104 result = FMT_BC1;
1105 is_srgb_valid = TRUE;
1106 goto out_word4;
1107 case PIPE_FORMAT_DXT3_RGBA:
1108 case PIPE_FORMAT_DXT3_SRGBA:
1109 result = FMT_BC2;
1110 is_srgb_valid = TRUE;
1111 goto out_word4;
1112 case PIPE_FORMAT_DXT5_RGBA:
1113 case PIPE_FORMAT_DXT5_SRGBA:
1114 result = FMT_BC3;
1115 is_srgb_valid = TRUE;
1116 goto out_word4;
1117 default:
1118 goto out_unknown;
1119 }
1120 }
1121
1122 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1123 switch (format) {
1124 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1125 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1126 result = FMT_GB_GR;
1127 goto out_word4;
1128 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1129 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1130 result = FMT_BG_RG;
1131 goto out_word4;
1132 default:
1133 goto out_unknown;
1134 }
1135 }
1136
1137 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1138 result = FMT_5_9_9_9_SHAREDEXP;
1139 goto out_word4;
1140 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1141 result = FMT_10_11_11_FLOAT;
1142 goto out_word4;
1143 }
1144
1145
1146 for (i = 0; i < desc->nr_channels; i++) {
1147 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1148 word4 |= sign_bit[i];
1149 }
1150 }
1151
1152 /* R8G8Bx_SNORM - XXX CxV8U8 */
1153
1154 /* See whether the components are of the same size. */
1155 for (i = 1; i < desc->nr_channels; i++) {
1156 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1157 }
1158
1159 /* Non-uniform formats. */
1160 if (!uniform) {
1161 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1162 desc->channel[0].pure_integer)
1163 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1164 switch(desc->nr_channels) {
1165 case 3:
1166 if (desc->channel[0].size == 5 &&
1167 desc->channel[1].size == 6 &&
1168 desc->channel[2].size == 5) {
1169 result = FMT_5_6_5;
1170 goto out_word4;
1171 }
1172 goto out_unknown;
1173 case 4:
1174 if (desc->channel[0].size == 5 &&
1175 desc->channel[1].size == 5 &&
1176 desc->channel[2].size == 5 &&
1177 desc->channel[3].size == 1) {
1178 result = FMT_1_5_5_5;
1179 goto out_word4;
1180 }
1181 if (desc->channel[0].size == 10 &&
1182 desc->channel[1].size == 10 &&
1183 desc->channel[2].size == 10 &&
1184 desc->channel[3].size == 2) {
1185 result = FMT_2_10_10_10;
1186 goto out_word4;
1187 }
1188 goto out_unknown;
1189 }
1190 goto out_unknown;
1191 }
1192
1193 /* Find the first non-VOID channel. */
1194 for (i = 0; i < 4; i++) {
1195 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1196 break;
1197 }
1198 }
1199
1200 if (i == 4)
1201 goto out_unknown;
1202
1203 /* uniform formats */
1204 switch (desc->channel[i].type) {
1205 case UTIL_FORMAT_TYPE_UNSIGNED:
1206 case UTIL_FORMAT_TYPE_SIGNED:
1207 #if 0
1208 if (!desc->channel[i].normalized &&
1209 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
1210 goto out_unknown;
1211 }
1212 #endif
1213 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1214 desc->channel[i].pure_integer)
1215 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1216
1217 switch (desc->channel[i].size) {
1218 case 4:
1219 switch (desc->nr_channels) {
1220 case 2:
1221 result = FMT_4_4;
1222 goto out_word4;
1223 case 4:
1224 result = FMT_4_4_4_4;
1225 goto out_word4;
1226 }
1227 goto out_unknown;
1228 case 8:
1229 switch (desc->nr_channels) {
1230 case 1:
1231 result = FMT_8;
1232 goto out_word4;
1233 case 2:
1234 result = FMT_8_8;
1235 goto out_word4;
1236 case 4:
1237 result = FMT_8_8_8_8;
1238 is_srgb_valid = TRUE;
1239 goto out_word4;
1240 }
1241 goto out_unknown;
1242 case 16:
1243 switch (desc->nr_channels) {
1244 case 1:
1245 result = FMT_16;
1246 goto out_word4;
1247 case 2:
1248 result = FMT_16_16;
1249 goto out_word4;
1250 case 4:
1251 result = FMT_16_16_16_16;
1252 goto out_word4;
1253 }
1254 goto out_unknown;
1255 case 32:
1256 switch (desc->nr_channels) {
1257 case 1:
1258 result = FMT_32;
1259 goto out_word4;
1260 case 2:
1261 result = FMT_32_32;
1262 goto out_word4;
1263 case 4:
1264 result = FMT_32_32_32_32;
1265 goto out_word4;
1266 }
1267 }
1268 goto out_unknown;
1269
1270 case UTIL_FORMAT_TYPE_FLOAT:
1271 switch (desc->channel[i].size) {
1272 case 16:
1273 switch (desc->nr_channels) {
1274 case 1:
1275 result = FMT_16_FLOAT;
1276 goto out_word4;
1277 case 2:
1278 result = FMT_16_16_FLOAT;
1279 goto out_word4;
1280 case 4:
1281 result = FMT_16_16_16_16_FLOAT;
1282 goto out_word4;
1283 }
1284 goto out_unknown;
1285 case 32:
1286 switch (desc->nr_channels) {
1287 case 1:
1288 result = FMT_32_FLOAT;
1289 goto out_word4;
1290 case 2:
1291 result = FMT_32_32_FLOAT;
1292 goto out_word4;
1293 case 4:
1294 result = FMT_32_32_32_32_FLOAT;
1295 goto out_word4;
1296 }
1297 }
1298 goto out_unknown;
1299 }
1300
1301 out_word4:
1302
1303 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid)
1304 return ~0;
1305 if (word4_p)
1306 *word4_p = word4;
1307 if (yuv_format_p)
1308 *yuv_format_p = yuv_format;
1309 return result;
1310 out_unknown:
1311 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1312 return ~0;
1313 }
1314
1315 static const struct u_resource_vtbl r600_texture_vtbl =
1316 {
1317 r600_texture_get_handle, /* get_handle */
1318 r600_texture_destroy, /* resource_destroy */
1319 r600_texture_transfer_map, /* transfer_map */
1320 NULL, /* transfer_flush_region */
1321 r600_texture_transfer_unmap, /* transfer_unmap */
1322 NULL /* transfer_inline_write */
1323 };