projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
r600g: move streamout state to drivers/radeon
[mesa.git] / src / gallium / drivers / r600 / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_formats.h"
28 #include "evergreen_compute.h"
29 #include "r600d.h"
30
31 #include <errno.h>
32 #include "util/u_format_s3tc.h"
33 #include "util/u_memory.h"
34
35
36 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
37 static void r600_copy_region_with_blit(struct pipe_context *pipe,
38 struct pipe_resource *dst,
39 unsigned dst_level,
40 unsigned dstx, unsigned dsty, unsigned dstz,
41 struct pipe_resource *src,
42 unsigned src_level,
43 const struct pipe_box *src_box)
44 {
45 struct pipe_blit_info blit;
46
47 memset(&blit, 0, sizeof(blit));
48 blit.src.resource = src;
49 blit.src.format = src->format;
50 blit.src.level = src_level;
51 blit.src.box = *src_box;
52 blit.dst.resource = dst;
53 blit.dst.format = dst->format;
54 blit.dst.level = dst_level;
55 blit.dst.box.x = dstx;
56 blit.dst.box.y = dsty;
57 blit.dst.box.z = dstz;
58 blit.dst.box.width = src_box->width;
59 blit.dst.box.height = src_box->height;
60 blit.dst.box.depth = src_box->depth;
61 blit.mask = util_format_get_mask(src->format) &
62 util_format_get_mask(dst->format);
63 blit.filter = PIPE_TEX_FILTER_NEAREST;
64
65 if (blit.mask) {
66 pipe->blit(pipe, &blit);
67 }
68 }
69
70 /* Copy from a full GPU texture to a transfer's staging one. */
71 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
72 {
73 struct r600_context *rctx = (struct r600_context*)ctx;
74 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
75 struct pipe_resource *dst = &rtransfer->staging->b.b;
76 struct pipe_resource *src = transfer->resource;
77
78 if (src->nr_samples > 1) {
79 r600_copy_region_with_blit(ctx, dst, 0, 0, 0, 0,
80 src, transfer->level, &transfer->box);
81 return;
82 }
83
84 if (!rctx->screen->dma_blit(ctx, dst, 0, 0, 0, 0,
85 src, transfer->level,
86 &transfer->box)) {
87 ctx->resource_copy_region(ctx, dst, 0, 0, 0, 0,
88 src, transfer->level, &transfer->box);
89 }
90 }
91
92 /* Copy from a transfer's staging texture to a full GPU one. */
93 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
94 {
95 struct r600_context *rctx = (struct r600_context*)ctx;
96 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
97 struct pipe_resource *dst = transfer->resource;
98 struct pipe_resource *src = &rtransfer->staging->b.b;
99 struct pipe_box sbox;
100
101 u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
102
103 if (dst->nr_samples > 1) {
104 r600_copy_region_with_blit(ctx, dst, transfer->level,
105 transfer->box.x, transfer->box.y, transfer->box.z,
106 src, 0, &sbox);
107 return;
108 }
109
110 if (!rctx->screen->dma_blit(ctx, dst, transfer->level,
111 transfer->box.x, transfer->box.y, transfer->box.z,
112 src, 0, &sbox)) {
113 ctx->resource_copy_region(ctx, dst, transfer->level,
114 transfer->box.x, transfer->box.y, transfer->box.z,
115 src, 0, &sbox);
116 }
117 }
118
119 static unsigned r600_texture_get_offset(struct r600_texture *rtex, unsigned level,
120 const struct pipe_box *box)
121 {
122 enum pipe_format format = rtex->resource.b.b.format;
123
124 return rtex->surface.level[level].offset +
125 box->z * rtex->surface.level[level].slice_size +
126 box->y / util_format_get_blockheight(format) * rtex->surface.level[level].pitch_bytes +
127 box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
128 }
129
130 static int r600_init_surface(struct r600_screen *rscreen,
131 struct radeon_surface *surface,
132 const struct pipe_resource *ptex,
133 unsigned array_mode,
134 bool is_flushed_depth)
135 {
136 const struct util_format_description *desc =
137 util_format_description(ptex->format);
138 bool is_depth, is_stencil;
139
140 is_depth = util_format_has_depth(desc);
141 is_stencil = util_format_has_stencil(desc);
142
143 surface->npix_x = ptex->width0;
144 surface->npix_y = ptex->height0;
145 surface->npix_z = ptex->depth0;
146 surface->blk_w = util_format_get_blockwidth(ptex->format);
147 surface->blk_h = util_format_get_blockheight(ptex->format);
148 surface->blk_d = 1;
149 surface->array_size = 1;
150 surface->last_level = ptex->last_level;
151
152 if (rscreen->b.chip_class >= EVERGREEN && !is_flushed_depth &&
153 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
154 surface->bpe = 4; /* stencil is allocated separately on evergreen */
155 } else {
156 surface->bpe = util_format_get_blocksize(ptex->format);
157 /* align byte per element on dword */
158 if (surface->bpe == 3) {
159 surface->bpe = 4;
160 }
161 }
162
163 surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1;
164 surface->flags = 0;
165
166 switch (array_mode) {
167 case V_038000_ARRAY_1D_TILED_THIN1:
168 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
169 break;
170 case V_038000_ARRAY_2D_TILED_THIN1:
171 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
172 break;
173 case V_038000_ARRAY_LINEAR_ALIGNED:
174 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
175 break;
176 case V_038000_ARRAY_LINEAR_GENERAL:
177 default:
178 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE);
179 break;
180 }
181 switch (ptex->target) {
182 case PIPE_TEXTURE_1D:
183 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
184 break;
185 case PIPE_TEXTURE_RECT:
186 case PIPE_TEXTURE_2D:
187 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
188 break;
189 case PIPE_TEXTURE_3D:
190 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
191 break;
192 case PIPE_TEXTURE_1D_ARRAY:
193 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
194 surface->array_size = ptex->array_size;
195 break;
196 case PIPE_TEXTURE_2D_ARRAY:
197 case PIPE_TEXTURE_CUBE_ARRAY: /* cube array layout like 2d layout for now */
198 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
199 surface->array_size = ptex->array_size;
200 break;
201 case PIPE_TEXTURE_CUBE:
202 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
203 break;
204 case PIPE_BUFFER:
205 default:
206 return -EINVAL;
207 }
208 if (ptex->bind & PIPE_BIND_SCANOUT) {
209 surface->flags |= RADEON_SURF_SCANOUT;
210 }
211
212 if (!is_flushed_depth && is_depth) {
213 surface->flags |= RADEON_SURF_ZBUFFER;
214
215 if (is_stencil) {
216 surface->flags |= RADEON_SURF_SBUFFER |
217 RADEON_SURF_HAS_SBUFFER_MIPTREE;
218 }
219 }
220 return 0;
221 }
222
223 static int r600_setup_surface(struct pipe_screen *screen,
224 struct r600_texture *rtex,
225 unsigned pitch_in_bytes_override)
226 {
227 struct pipe_resource *ptex = &rtex->resource.b.b;
228 struct r600_screen *rscreen = (struct r600_screen*)screen;
229 unsigned i;
230 int r;
231
232 r = rscreen->b.ws->surface_init(rscreen->b.ws, &rtex->surface);
233 if (r) {
234 return r;
235 }
236 rtex->size = rtex->surface.bo_size;
237 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
238 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
239 * for those
240 */
241 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
242 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
243 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
244 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
245 rtex->surface.stencil_offset =
246 rtex->surface.stencil_level[0].offset = rtex->surface.level[0].slice_size;
247 }
248 }
249 for (i = 0; i <= ptex->last_level; i++) {
250 switch (rtex->surface.level[i].mode) {
251 case RADEON_SURF_MODE_LINEAR_ALIGNED:
252 rtex->array_mode[i] = V_038000_ARRAY_LINEAR_ALIGNED;
253 break;
254 case RADEON_SURF_MODE_1D:
255 rtex->array_mode[i] = V_038000_ARRAY_1D_TILED_THIN1;
256 break;
257 case RADEON_SURF_MODE_2D:
258 rtex->array_mode[i] = V_038000_ARRAY_2D_TILED_THIN1;
259 break;
260 default:
261 case RADEON_SURF_MODE_LINEAR:
262 rtex->array_mode[i] = 0;
263 break;
264 }
265 }
266 return 0;
267 }
268
269 static boolean r600_texture_get_handle(struct pipe_screen* screen,
270 struct pipe_resource *ptex,
271 struct winsys_handle *whandle)
272 {
273 struct r600_texture *rtex = (struct r600_texture*)ptex;
274 struct r600_resource *resource = &rtex->resource;
275 struct radeon_surface *surface = &rtex->surface;
276 struct r600_screen *rscreen = (struct r600_screen*)screen;
277
278 rscreen->b.ws->buffer_set_tiling(resource->buf,
279 NULL,
280 surface->level[0].mode >= RADEON_SURF_MODE_1D ?
281 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
282 surface->level[0].mode >= RADEON_SURF_MODE_2D ?
283 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
284 surface->bankw, surface->bankh,
285 surface->tile_split,
286 surface->stencil_tile_split,
287 surface->mtilea,
288 rtex->surface.level[0].pitch_bytes);
289
290 return rscreen->b.ws->buffer_get_handle(resource->buf,
291 rtex->surface.level[0].pitch_bytes, whandle);
292 }
293
294 static void r600_texture_destroy(struct pipe_screen *screen,
295 struct pipe_resource *ptex)
296 {
297 struct r600_texture *rtex = (struct r600_texture*)ptex;
298 struct r600_resource *resource = &rtex->resource;
299
300 if (rtex->flushed_depth_texture)
301 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
302
303 pipe_resource_reference((struct pipe_resource**)&rtex->htile, NULL);
304 pb_reference(&resource->buf, NULL);
305 FREE(rtex);
306 }
307
308 static const struct u_resource_vtbl r600_texture_vtbl;
309
310 /* The number of samples can be specified independently of the texture. */
311 void r600_texture_get_fmask_info(struct r600_screen *rscreen,
312 struct r600_texture *rtex,
313 unsigned nr_samples,
314 struct r600_fmask_info *out)
315 {
316 /* FMASK is allocated like an ordinary texture. */
317 struct radeon_surface fmask = rtex->surface;
318
319 memset(out, 0, sizeof(*out));
320
321 fmask.bo_alignment = 0;
322 fmask.bo_size = 0;
323 fmask.nsamples = 1;
324 fmask.flags |= RADEON_SURF_FMASK;
325
326 switch (nr_samples) {
327 case 2:
328 case 4:
329 fmask.bpe = 1;
330 fmask.bankh = 4;
331 break;
332 case 8:
333 fmask.bpe = 4;
334 break;
335 default:
336 R600_ERR("Invalid sample count for FMASK allocation.\n");
337 return;
338 }
339
340 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
341 * This can be fixed by writing a separate FMASK allocator specifically
342 * for R600-R700 asics. */
343 if (rscreen->b.chip_class <= R700) {
344 fmask.bpe *= 2;
345 }
346
347 if (rscreen->b.ws->surface_init(rscreen->b.ws, &fmask)) {
348 R600_ERR("Got error in surface_init while allocating FMASK.\n");
349 return;
350 }
351
352 assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
353
354 out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) / 64;
355 if (out->slice_tile_max)
356 out->slice_tile_max -= 1;
357
358 out->bank_height = fmask.bankh;
359 out->alignment = MAX2(256, fmask.bo_alignment);
360 out->size = fmask.bo_size;
361 }
362
363 static void r600_texture_allocate_fmask(struct r600_screen *rscreen,
364 struct r600_texture *rtex)
365 {
366 struct r600_fmask_info fmask;
367
368 r600_texture_get_fmask_info(rscreen, rtex,
369 rtex->resource.b.b.nr_samples, &fmask);
370
371 rtex->fmask_bank_height = fmask.bank_height;
372 rtex->fmask_slice_tile_max = fmask.slice_tile_max;
373 rtex->fmask_offset = align(rtex->size, fmask.alignment);
374 rtex->fmask_size = fmask.size;
375 rtex->size = rtex->fmask_offset + rtex->fmask_size;
376 #if 0
377 printf("FMASK width=%u, height=%i, bits=%u, size=%u\n",
378 fmask.npix_x, fmask.npix_y, fmask.bpe * fmask.nsamples, rtex->fmask_size);
379 #endif
380 }
381
382 void r600_texture_get_cmask_info(struct r600_screen *rscreen,
383 struct r600_texture *rtex,
384 struct r600_cmask_info *out)
385 {
386 unsigned cmask_tile_width = 8;
387 unsigned cmask_tile_height = 8;
388 unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
389 unsigned element_bits = 4;
390 unsigned cmask_cache_bits = 1024;
391 unsigned num_pipes = rscreen->tiling_info.num_channels;
392 unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
393
394 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
395 unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
396 unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
397 unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
398 unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
399
400 unsigned pitch_elements = align(rtex->surface.npix_x, macro_tile_width);
401 unsigned height = align(rtex->surface.npix_y, macro_tile_height);
402
403 unsigned base_align = num_pipes * pipe_interleave_bytes;
404 unsigned slice_bytes =
405 ((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
406
407 assert(macro_tile_width % 128 == 0);
408 assert(macro_tile_height % 128 == 0);
409
410 out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
411 out->alignment = MAX2(256, base_align);
412 out->size = rtex->surface.array_size * align(slice_bytes, base_align);
413 }
414
415 static void r600_texture_allocate_cmask(struct r600_screen *rscreen,
416 struct r600_texture *rtex)
417 {
418 struct r600_cmask_info cmask;
419
420 r600_texture_get_cmask_info(rscreen, rtex, &cmask);
421
422 rtex->cmask_slice_tile_max = cmask.slice_tile_max;
423 rtex->cmask_offset = align(rtex->size, cmask.alignment);
424 rtex->cmask_size = cmask.size;
425 rtex->size = rtex->cmask_offset + rtex->cmask_size;
426 #if 0
427 printf("CMASK: macro tile width = %u, macro tile height = %u, "
428 "pitch elements = %u, height = %u, slice tile max = %u\n",
429 macro_tile_width, macro_tile_height, pitch_elements, height,
430 rtex->cmask_slice_tile_max);
431 #endif
432 }
433
434 static struct r600_texture *
435 r600_texture_create_object(struct pipe_screen *screen,
436 const struct pipe_resource *base,
437 unsigned pitch_in_bytes_override,
438 struct pb_buffer *buf,
439 struct radeon_surface *surface)
440 {
441 struct r600_texture *rtex;
442 struct r600_resource *resource;
443 struct r600_screen *rscreen = (struct r600_screen*)screen;
444 int r;
445
446 rtex = CALLOC_STRUCT(r600_texture);
447 if (rtex == NULL)
448 return NULL;
449
450 resource = &rtex->resource;
451 resource->b.b = *base;
452 resource->b.vtbl = &r600_texture_vtbl;
453 pipe_reference_init(&resource->b.b.reference, 1);
454 resource->b.b.screen = screen;
455 rtex->pitch_override = pitch_in_bytes_override;
456
457 /* don't include stencil-only formats which we don't support for rendering */
458 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
459
460 rtex->surface = *surface;
461 r = r600_setup_surface(screen, rtex, pitch_in_bytes_override);
462 if (r) {
463 FREE(rtex);
464 return NULL;
465 }
466
467 if (base->nr_samples > 1 && !rtex->is_depth && !buf) {
468 r600_texture_allocate_fmask(rscreen, rtex);
469 r600_texture_allocate_cmask(rscreen, rtex);
470 }
471
472 if (!rtex->is_depth && base->nr_samples > 1 &&
473 (!rtex->fmask_size || !rtex->cmask_size)) {
474 FREE(rtex);
475 return NULL;
476 }
477
478 /* Tiled depth textures utilize the non-displayable tile order. */
479 rtex->non_disp_tiling = rtex->is_depth && rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D;
480
481 /* only enable hyperz for PIPE_TEXTURE_2D not for PIPE_TEXTURE_2D_ARRAY
482 * Thought it might still be interessting to use hyperz for texture
483 * array without using fast clear features
484 */
485 rtex->htile = NULL;
486 if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER | R600_RESOURCE_FLAG_FLUSHED_DEPTH)) &&
487 util_format_is_depth_or_stencil(base->format) &&
488 rscreen->b.info.drm_minor >= 26 &&
489 !(rscreen->debug_flags & DBG_NO_HYPERZ) &&
490 base->target == PIPE_TEXTURE_2D &&
491 rtex->surface.level[0].nblk_x >= 32 &&
492 rtex->surface.level[0].nblk_y >= 32) {
493 unsigned sw = rtex->surface.level[0].nblk_x * rtex->surface.blk_w;
494 unsigned sh = rtex->surface.level[0].nblk_y * rtex->surface.blk_h;
495 unsigned htile_size;
496 unsigned npipes = rscreen->b.info.r600_num_tile_pipes;
497
498 /* this alignment and htile size only apply to linear htile buffer */
499 sw = align(sw, 16 << 3);
500 sh = align(sh, npipes << 3);
501 htile_size = (sw >> 3) * (sh >> 3) * 4;
502 /* must be aligned with 2K * npipes */
503 htile_size = align(htile_size, (2 << 10) * npipes);
504
505 rtex->htile = (struct r600_resource*)pipe_buffer_create(&rscreen->b.b, PIPE_BIND_CUSTOM,
506 PIPE_USAGE_STATIC, htile_size);
507 if (rtex->htile == NULL) {
508 /* this is not a fatal error as we can still keep rendering
509 * without htile buffer
510 */
511 R600_ERR("r600: failed to create bo for htile buffers\n");
512 } else {
513 r600_screen_clear_buffer(rscreen, &rtex->htile->b.b, 0, htile_size, 0);
514 }
515 }
516
517 /* Now create the backing buffer. */
518 if (!buf) {
519 unsigned base_align = rtex->surface.bo_alignment;
520 unsigned usage = R600_TEX_IS_TILED(rtex, 0) ? PIPE_USAGE_STATIC : base->usage;
521
522 if (!r600_init_resource(rscreen, resource, rtex->size, base_align, FALSE, usage)) {
523 FREE(rtex);
524 return NULL;
525 }
526 } else {
527 /* This is usually the window framebuffer. We want it in VRAM, always. */
528 resource->buf = buf;
529 resource->cs_buf = rscreen->b.ws->buffer_get_cs_handle(buf);
530 resource->domains = RADEON_DOMAIN_VRAM;
531 }
532
533 if (rtex->cmask_size) {
534 /* Initialize the cmask to 0xCC (= compressed state). */
535 r600_screen_clear_buffer(rscreen, &rtex->resource.b.b,
536 rtex->cmask_offset, rtex->cmask_size, 0xCC);
537 }
538
539 if (rscreen->debug_flags & DBG_VM) {
540 fprintf(stderr, "VM start=0x%llX end=0x%llX | Texture %ix%ix%i, %i levels, %i samples, %s\n",
541 r600_resource_va(screen, &rtex->resource.b.b),
542 r600_resource_va(screen, &rtex->resource.b.b) + rtex->resource.buf->size,
543 base->width0, base->height0, util_max_layer(base, 0)+1, base->last_level+1,
544 base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));
545 }
546
547 if (rscreen->debug_flags & DBG_TEX_DEPTH && rtex->is_depth && rtex->non_disp_tiling) {
548 printf("Texture: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
549 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
550 "bpe=%u, nsamples=%u, flags=%u\n",
551 rtex->surface.npix_x, rtex->surface.npix_y,
552 rtex->surface.npix_z, rtex->surface.blk_w,
553 rtex->surface.blk_h, rtex->surface.blk_d,
554 rtex->surface.array_size, rtex->surface.last_level,
555 rtex->surface.bpe, rtex->surface.nsamples,
556 rtex->surface.flags);
557 if (rtex->surface.flags & RADEON_SURF_ZBUFFER) {
558 for (int i = 0; i <= rtex->surface.last_level; i++) {
559 printf(" Z %i: offset=%llu, slice_size=%llu, npix_x=%u, "
560 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
561 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
562 i, (unsigned long long)rtex->surface.level[i].offset,
563 (unsigned long long)rtex->surface.level[i].slice_size,
564 u_minify(rtex->resource.b.b.width0, i),
565 u_minify(rtex->resource.b.b.height0, i),
566 u_minify(rtex->resource.b.b.depth0, i),
567 rtex->surface.level[i].nblk_x,
568 rtex->surface.level[i].nblk_y,
569 rtex->surface.level[i].nblk_z,
570 rtex->surface.level[i].pitch_bytes,
571 rtex->surface.level[i].mode);
572 }
573 }
574 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
575 for (int i = 0; i <= rtex->surface.last_level; i++) {
576 printf(" S %i: offset=%llu, slice_size=%llu, npix_x=%u, "
577 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
578 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
579 i, (unsigned long long)rtex->surface.stencil_level[i].offset,
580 (unsigned long long)rtex->surface.stencil_level[i].slice_size,
581 u_minify(rtex->resource.b.b.width0, i),
582 u_minify(rtex->resource.b.b.height0, i),
583 u_minify(rtex->resource.b.b.depth0, i),
584 rtex->surface.stencil_level[i].nblk_x,
585 rtex->surface.stencil_level[i].nblk_y,
586 rtex->surface.stencil_level[i].nblk_z,
587 rtex->surface.stencil_level[i].pitch_bytes,
588 rtex->surface.stencil_level[i].mode);
589 }
590 }
591 }
592 return rtex;
593 }
594
595 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
596 const struct pipe_resource *templ)
597 {
598 struct r600_screen *rscreen = (struct r600_screen*)screen;
599 struct radeon_surface surface;
600 const struct util_format_description *desc = util_format_description(templ->format);
601 unsigned array_mode;
602 int r;
603
604 /* Default tiling mode for staging textures. */
605 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
606
607 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats. That's not an issue,
608 * because 422 formats are used for videos, which prefer linear buffers
609 * for fast uploads anyway. */
610 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
611 desc->layout != UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
612 if (templ->flags & R600_RESOURCE_FLAG_FORCE_TILING) {
613 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
614 } else if (!(templ->bind & PIPE_BIND_SCANOUT) &&
615 templ->usage != PIPE_USAGE_STAGING &&
616 templ->usage != PIPE_USAGE_STREAM &&
617 templ->target != PIPE_TEXTURE_1D &&
618 templ->target != PIPE_TEXTURE_1D_ARRAY &&
619 templ->height0 > 3) {
620 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
621 } else if (util_format_is_compressed(templ->format)) {
622 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
623 }
624 }
625
626 r = r600_init_surface(rscreen, &surface, templ, array_mode,
627 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
628 if (r) {
629 return NULL;
630 }
631 r = rscreen->b.ws->surface_best(rscreen->b.ws, &surface);
632 if (r) {
633 return NULL;
634 }
635 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
636 0, NULL, &surface);
637 }
638
639 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
640 struct pipe_resource *texture,
641 const struct pipe_surface *templ,
642 unsigned width, unsigned height)
643 {
644 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
645
646 assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level));
647 assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level));
648 assert(templ->u.tex.first_layer == templ->u.tex.last_layer);
649 if (surface == NULL)
650 return NULL;
651 pipe_reference_init(&surface->base.reference, 1);
652 pipe_resource_reference(&surface->base.texture, texture);
653 surface->base.context = pipe;
654 surface->base.format = templ->format;
655 surface->base.width = width;
656 surface->base.height = height;
657 surface->base.u = templ->u;
658 return &surface->base;
659 }
660
661 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
662 struct pipe_resource *tex,
663 const struct pipe_surface *templ)
664 {
665 unsigned level = templ->u.tex.level;
666
667 return r600_create_surface_custom(pipe, tex, templ,
668 u_minify(tex->width0, level),
669 u_minify(tex->height0, level));
670 }
671
672 static void r600_surface_destroy(struct pipe_context *pipe,
673 struct pipe_surface *surface)
674 {
675 struct r600_surface *surf = (struct r600_surface*)surface;
676 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, NULL);
677 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, NULL);
678 pipe_resource_reference(&surface->texture, NULL);
679 FREE(surface);
680 }
681
682 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
683 const struct pipe_resource *templ,
684 struct winsys_handle *whandle)
685 {
686 struct r600_screen *rscreen = (struct r600_screen*)screen;
687 struct pb_buffer *buf = NULL;
688 unsigned stride = 0;
689 unsigned array_mode = 0;
690 enum radeon_bo_layout micro, macro;
691 struct radeon_surface surface;
692 int r;
693
694 /* Support only 2D textures without mipmaps */
695 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
696 templ->depth0 != 1 || templ->last_level != 0)
697 return NULL;
698
699 buf = rscreen->b.ws->buffer_from_handle(rscreen->b.ws, whandle, &stride);
700 if (!buf)
701 return NULL;
702
703 rscreen->b.ws->buffer_get_tiling(buf, &micro, &macro,
704 &surface.bankw, &surface.bankh,
705 &surface.tile_split,
706 &surface.stencil_tile_split,
707 &surface.mtilea);
708
709 if (macro == RADEON_LAYOUT_TILED)
710 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
711 else if (micro == RADEON_LAYOUT_TILED)
712 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
713 else
714 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
715
716 r = r600_init_surface(rscreen, &surface, templ, array_mode, false);
717 if (r) {
718 return NULL;
719 }
720 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
721 stride, buf, &surface);
722 }
723
724 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
725 struct pipe_resource *texture,
726 struct r600_texture **staging)
727 {
728 struct r600_texture *rtex = (struct r600_texture*)texture;
729 struct pipe_resource resource;
730 struct r600_texture **flushed_depth_texture = staging ?
731 staging : &rtex->flushed_depth_texture;
732
733 if (!staging && rtex->flushed_depth_texture)
734 return true; /* it's ready */
735
736 resource.target = texture->target;
737 resource.format = texture->format;
738 resource.width0 = texture->width0;
739 resource.height0 = texture->height0;
740 resource.depth0 = texture->depth0;
741 resource.array_size = texture->array_size;
742 resource.last_level = texture->last_level;
743 resource.nr_samples = texture->nr_samples;
744 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_STATIC;
745 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
746 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
747
748 if (staging)
749 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
750
751 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
752 if (*flushed_depth_texture == NULL) {
753 R600_ERR("failed to create temporary texture to hold flushed depth\n");
754 return false;
755 }
756
757 (*flushed_depth_texture)->is_flushing_texture = TRUE;
758 (*flushed_depth_texture)->non_disp_tiling = false;
759 return true;
760 }
761
762 /**
763 * Initialize the pipe_resource descriptor to be of the same size as the box,
764 * which is supposed to hold a subregion of the texture "orig" at the given
765 * mipmap level.
766 */
767 static void r600_init_temp_resource_from_box(struct pipe_resource *res,
768 struct pipe_resource *orig,
769 const struct pipe_box *box,
770 unsigned level, unsigned flags)
771 {
772 memset(res, 0, sizeof(*res));
773 res->format = orig->format;
774 res->width0 = box->width;
775 res->height0 = box->height;
776 res->depth0 = 1;
777 res->array_size = 1;
778 res->usage = flags & R600_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_STATIC;
779 res->flags = flags;
780
781 /* We must set the correct texture target and dimensions for a 3D box. */
782 if (box->depth > 1 && util_max_layer(orig, level) > 0)
783 res->target = orig->target;
784 else
785 res->target = PIPE_TEXTURE_2D;
786
787 switch (res->target) {
788 case PIPE_TEXTURE_1D_ARRAY:
789 case PIPE_TEXTURE_2D_ARRAY:
790 case PIPE_TEXTURE_CUBE_ARRAY:
791 res->array_size = box->depth;
792 break;
793 case PIPE_TEXTURE_3D:
794 res->depth0 = box->depth;
795 break;
796 default:;
797 }
798 }
799
800 static void *r600_texture_transfer_map(struct pipe_context *ctx,
801 struct pipe_resource *texture,
802 unsigned level,
803 unsigned usage,
804 const struct pipe_box *box,
805 struct pipe_transfer **ptransfer)
806 {
807 struct r600_context *rctx = (struct r600_context*)ctx;
808 struct r600_texture *rtex = (struct r600_texture*)texture;
809 struct r600_transfer *trans;
810 boolean use_staging_texture = FALSE;
811 struct r600_resource *buf;
812 unsigned offset = 0;
813 char *map;
814
815 if ((texture->bind & PIPE_BIND_GLOBAL) && texture->target == PIPE_BUFFER) {
816 return r600_compute_global_transfer_map(ctx, texture, level, usage, box, ptransfer);
817 }
818
819 /* We cannot map a tiled texture directly because the data is
820 * in a different order, therefore we do detiling using a blit.
821 *
822 * Also, use a temporary in GTT memory for read transfers, as
823 * the CPU is much happier reading out of cached system memory
824 * than uncached VRAM.
825 */
826 if (R600_TEX_IS_TILED(rtex, level)) {
827 use_staging_texture = TRUE;
828 }
829
830 /* Use a staging texture for uploads if the underlying BO is busy. */
831 if (!(usage & PIPE_TRANSFER_READ) &&
832 (r600_rings_is_buffer_referenced(rctx, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) ||
833 rctx->b.ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE))) {
834 use_staging_texture = TRUE;
835 }
836
837 if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) {
838 use_staging_texture = FALSE;
839 }
840
841 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) {
842 return NULL;
843 }
844
845 trans = CALLOC_STRUCT(r600_transfer);
846 if (trans == NULL)
847 return NULL;
848 trans->transfer.resource = texture;
849 trans->transfer.level = level;
850 trans->transfer.usage = usage;
851 trans->transfer.box = *box;
852
853 if (rtex->is_depth) {
854 struct r600_texture *staging_depth;
855
856 if (rtex->resource.b.b.nr_samples > 1) {
857 /* MSAA depth buffers need to be converted to single sample buffers.
858 *
859 * Mapping MSAA depth buffers can occur if ReadPixels is called
860 * with a multisample GLX visual.
861 *
862 * First downsample the depth buffer to a temporary texture,
863 * then decompress the temporary one to staging.
864 *
865 * Only the region being mapped is transfered.
866 */
867 struct pipe_resource resource;
868
869 r600_init_temp_resource_from_box(&resource, texture, box, level, 0);
870
871 if (!r600_init_flushed_depth_texture(ctx, &resource, &staging_depth)) {
872 R600_ERR("failed to create temporary texture to hold untiled copy\n");
873 FREE(trans);
874 return NULL;
875 }
876
877 if (usage & PIPE_TRANSFER_READ) {
878 struct pipe_resource *temp = ctx->screen->resource_create(ctx->screen, &resource);
879
880 r600_copy_region_with_blit(ctx, temp, 0, 0, 0, 0, texture, level, box);
881 r600_blit_decompress_depth(ctx, (struct r600_texture*)temp, staging_depth,
882 0, 0, 0, box->depth, 0, 0);
883 pipe_resource_reference((struct pipe_resource**)&temp, NULL);
884 }
885 }
886 else {
887 /* XXX: only readback the rectangle which is being mapped? */
888 /* XXX: when discard is true, no need to read back from depth texture */
889 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
890 R600_ERR("failed to create temporary texture to hold untiled copy\n");
891 FREE(trans);
892 return NULL;
893 }
894
895 r600_blit_decompress_depth(ctx, rtex, staging_depth,
896 level, level,
897 box->z, box->z + box->depth - 1,
898 0, 0);
899
900 offset = r600_texture_get_offset(staging_depth, level, box);
901 }
902
903 trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
904 trans->transfer.layer_stride = staging_depth->surface.level[level].slice_size;
905 trans->staging = (struct r600_resource*)staging_depth;
906 } else if (use_staging_texture) {
907 struct pipe_resource resource;
908 struct r600_texture *staging;
909
910 r600_init_temp_resource_from_box(&resource, texture, box, level,
911 R600_RESOURCE_FLAG_TRANSFER);
912
913 /* Create the temporary texture. */
914 staging = (struct r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
915 if (staging == NULL) {
916 R600_ERR("failed to create temporary texture to hold untiled copy\n");
917 FREE(trans);
918 return NULL;
919 }
920 trans->staging = &staging->resource;
921 trans->transfer.stride = staging->surface.level[0].pitch_bytes;
922 trans->transfer.layer_stride = staging->surface.level[0].slice_size;
923 if (usage & PIPE_TRANSFER_READ) {
924 r600_copy_to_staging_texture(ctx, trans);
925 }
926 } else {
927 /* the resource is mapped directly */
928 trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
929 trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
930 offset = r600_texture_get_offset(rtex, level, box);
931 }
932
933 if (trans->staging) {
934 buf = trans->staging;
935 } else {
936 buf = &rtex->resource;
937 }
938
939 if (!(map = r600_buffer_mmap_sync_with_rings(rctx, buf, usage))) {
940 pipe_resource_reference((struct pipe_resource**)&trans->staging, NULL);
941 FREE(trans);
942 return NULL;
943 }
944
945 *ptransfer = &trans->transfer;
946 return map + offset;
947 }
948
949 static void r600_texture_transfer_unmap(struct pipe_context *ctx,
950 struct pipe_transfer* transfer)
951 {
952 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
953 struct r600_context *rctx = (struct r600_context*)ctx;
954 struct radeon_winsys_cs_handle *buf;
955 struct pipe_resource *texture = transfer->resource;
956 struct r600_texture *rtex = (struct r600_texture*)texture;
957
958 if ((transfer->resource->bind & PIPE_BIND_GLOBAL) && transfer->resource->target == PIPE_BUFFER) {
959 return r600_compute_global_transfer_unmap(ctx, transfer);
960 }
961
962 if (rtransfer->staging) {
963 buf = ((struct r600_resource *)rtransfer->staging)->cs_buf;
964 } else {
965 buf = ((struct r600_resource *)transfer->resource)->cs_buf;
966 }
967 rctx->b.ws->buffer_unmap(buf);
968
969 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
970 if (rtex->is_depth && rtex->resource.b.b.nr_samples <= 1) {
971 ctx->resource_copy_region(ctx, texture, transfer->level,
972 transfer->box.x, transfer->box.y, transfer->box.z,
973 &rtransfer->staging->b.b, transfer->level,
974 &transfer->box);
975 } else {
976 r600_copy_from_staging_texture(ctx, rtransfer);
977 }
978 }
979
980 if (rtransfer->staging)
981 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
982
983 FREE(transfer);
984 }
985
986 void r600_init_surface_functions(struct r600_context *r600)
987 {
988 r600->b.b.create_surface = r600_create_surface;
989 r600->b.b.surface_destroy = r600_surface_destroy;
990 }
991
992 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
993 const unsigned char *swizzle_view,
994 boolean vtx)
995 {
996 unsigned i;
997 unsigned char swizzle[4];
998 unsigned result = 0;
999 const uint32_t tex_swizzle_shift[4] = {
1000 16, 19, 22, 25,
1001 };
1002 const uint32_t vtx_swizzle_shift[4] = {
1003 3, 6, 9, 12,
1004 };
1005 const uint32_t swizzle_bit[4] = {
1006 0, 1, 2, 3,
1007 };
1008 const uint32_t *swizzle_shift = tex_swizzle_shift;
1009
1010 if (vtx)
1011 swizzle_shift = vtx_swizzle_shift;
1012
1013 if (swizzle_view) {
1014 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
1015 } else {
1016 memcpy(swizzle, swizzle_format, 4);
1017 }
1018
1019 /* Get swizzle. */
1020 for (i = 0; i < 4; i++) {
1021 switch (swizzle[i]) {
1022 case UTIL_FORMAT_SWIZZLE_Y:
1023 result |= swizzle_bit[1] << swizzle_shift[i];
1024 break;
1025 case UTIL_FORMAT_SWIZZLE_Z:
1026 result |= swizzle_bit[2] << swizzle_shift[i];
1027 break;
1028 case UTIL_FORMAT_SWIZZLE_W:
1029 result |= swizzle_bit[3] << swizzle_shift[i];
1030 break;
1031 case UTIL_FORMAT_SWIZZLE_0:
1032 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
1033 break;
1034 case UTIL_FORMAT_SWIZZLE_1:
1035 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
1036 break;
1037 default: /* UTIL_FORMAT_SWIZZLE_X */
1038 result |= swizzle_bit[0] << swizzle_shift[i];
1039 }
1040 }
1041 return result;
1042 }
1043
1044 /* texture format translate */
1045 uint32_t r600_translate_texformat(struct pipe_screen *screen,
1046 enum pipe_format format,
1047 const unsigned char *swizzle_view,
1048 uint32_t *word4_p, uint32_t *yuv_format_p)
1049 {
1050 struct r600_screen *rscreen = (struct r600_screen *)screen;
1051 uint32_t result = 0, word4 = 0, yuv_format = 0;
1052 const struct util_format_description *desc;
1053 boolean uniform = TRUE;
1054 bool enable_s3tc = rscreen->b.info.drm_minor >= 9;
1055 bool is_srgb_valid = FALSE;
1056 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
1057 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
1058
1059 int i;
1060 const uint32_t sign_bit[4] = {
1061 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
1062 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
1063 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
1064 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
1065 };
1066 desc = util_format_description(format);
1067
1068 /* Depth and stencil swizzling is handled separately. */
1069 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS) {
1070 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view, FALSE);
1071 }
1072
1073 /* Colorspace (return non-RGB formats directly). */
1074 switch (desc->colorspace) {
1075 /* Depth stencil formats */
1076 case UTIL_FORMAT_COLORSPACE_ZS:
1077 switch (format) {
1078 /* Depth sampler formats. */
1079 case PIPE_FORMAT_Z16_UNORM:
1080 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1081 result = FMT_16;
1082 goto out_word4;
1083 case PIPE_FORMAT_Z24X8_UNORM:
1084 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1085 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1086 result = FMT_8_24;
1087 goto out_word4;
1088 case PIPE_FORMAT_X8Z24_UNORM:
1089 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1090 if (rscreen->b.chip_class < EVERGREEN)
1091 goto out_unknown;
1092 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
1093 result = FMT_24_8;
1094 goto out_word4;
1095 case PIPE_FORMAT_Z32_FLOAT:
1096 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1097 result = FMT_32_FLOAT;
1098 goto out_word4;
1099 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1100 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1101 result = FMT_X24_8_32_FLOAT;
1102 goto out_word4;
1103 /* Stencil sampler formats. */
1104 case PIPE_FORMAT_S8_UINT:
1105 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1106 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1107 result = FMT_8;
1108 goto out_word4;
1109 case PIPE_FORMAT_X24S8_UINT:
1110 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1111 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
1112 result = FMT_8_24;
1113 goto out_word4;
1114 case PIPE_FORMAT_S8X24_UINT:
1115 if (rscreen->b.chip_class < EVERGREEN)
1116 goto out_unknown;
1117 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1118 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1119 result = FMT_24_8;
1120 goto out_word4;
1121 case PIPE_FORMAT_X32_S8X24_UINT:
1122 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1123 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
1124 result = FMT_X24_8_32_FLOAT;
1125 goto out_word4;
1126 default:
1127 goto out_unknown;
1128 }
1129
1130 case UTIL_FORMAT_COLORSPACE_YUV:
1131 yuv_format |= (1 << 30);
1132 switch (format) {
1133 case PIPE_FORMAT_UYVY:
1134 case PIPE_FORMAT_YUYV:
1135 default:
1136 break;
1137 }
1138 goto out_unknown; /* XXX */
1139
1140 case UTIL_FORMAT_COLORSPACE_SRGB:
1141 word4 |= S_038010_FORCE_DEGAMMA(1);
1142 break;
1143
1144 default:
1145 break;
1146 }
1147
1148 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1149 if (!enable_s3tc)
1150 goto out_unknown;
1151
1152 switch (format) {
1153 case PIPE_FORMAT_RGTC1_SNORM:
1154 case PIPE_FORMAT_LATC1_SNORM:
1155 word4 |= sign_bit[0];
1156 case PIPE_FORMAT_RGTC1_UNORM:
1157 case PIPE_FORMAT_LATC1_UNORM:
1158 result = FMT_BC4;
1159 goto out_word4;
1160 case PIPE_FORMAT_RGTC2_SNORM:
1161 case PIPE_FORMAT_LATC2_SNORM:
1162 word4 |= sign_bit[0] | sign_bit[1];
1163 case PIPE_FORMAT_RGTC2_UNORM:
1164 case PIPE_FORMAT_LATC2_UNORM:
1165 result = FMT_BC5;
1166 goto out_word4;
1167 default:
1168 goto out_unknown;
1169 }
1170 }
1171
1172 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1173
1174 if (!enable_s3tc)
1175 goto out_unknown;
1176
1177 if (!util_format_s3tc_enabled) {
1178 goto out_unknown;
1179 }
1180
1181 switch (format) {
1182 case PIPE_FORMAT_DXT1_RGB:
1183 case PIPE_FORMAT_DXT1_RGBA:
1184 case PIPE_FORMAT_DXT1_SRGB:
1185 case PIPE_FORMAT_DXT1_SRGBA:
1186 result = FMT_BC1;
1187 is_srgb_valid = TRUE;
1188 goto out_word4;
1189 case PIPE_FORMAT_DXT3_RGBA:
1190 case PIPE_FORMAT_DXT3_SRGBA:
1191 result = FMT_BC2;
1192 is_srgb_valid = TRUE;
1193 goto out_word4;
1194 case PIPE_FORMAT_DXT5_RGBA:
1195 case PIPE_FORMAT_DXT5_SRGBA:
1196 result = FMT_BC3;
1197 is_srgb_valid = TRUE;
1198 goto out_word4;
1199 default:
1200 goto out_unknown;
1201 }
1202 }
1203
1204 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1205 switch (format) {
1206 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1207 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1208 result = FMT_GB_GR;
1209 goto out_word4;
1210 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1211 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1212 result = FMT_BG_RG;
1213 goto out_word4;
1214 default:
1215 goto out_unknown;
1216 }
1217 }
1218
1219 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1220 result = FMT_5_9_9_9_SHAREDEXP;
1221 goto out_word4;
1222 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1223 result = FMT_10_11_11_FLOAT;
1224 goto out_word4;
1225 }
1226
1227
1228 for (i = 0; i < desc->nr_channels; i++) {
1229 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1230 word4 |= sign_bit[i];
1231 }
1232 }
1233
1234 /* R8G8Bx_SNORM - XXX CxV8U8 */
1235
1236 /* See whether the components are of the same size. */
1237 for (i = 1; i < desc->nr_channels; i++) {
1238 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1239 }
1240
1241 /* Non-uniform formats. */
1242 if (!uniform) {
1243 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1244 desc->channel[0].pure_integer)
1245 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1246 switch(desc->nr_channels) {
1247 case 3:
1248 if (desc->channel[0].size == 5 &&
1249 desc->channel[1].size == 6 &&
1250 desc->channel[2].size == 5) {
1251 result = FMT_5_6_5;
1252 goto out_word4;
1253 }
1254 goto out_unknown;
1255 case 4:
1256 if (desc->channel[0].size == 5 &&
1257 desc->channel[1].size == 5 &&
1258 desc->channel[2].size == 5 &&
1259 desc->channel[3].size == 1) {
1260 result = FMT_1_5_5_5;
1261 goto out_word4;
1262 }
1263 if (desc->channel[0].size == 10 &&
1264 desc->channel[1].size == 10 &&
1265 desc->channel[2].size == 10 &&
1266 desc->channel[3].size == 2) {
1267 result = FMT_2_10_10_10;
1268 goto out_word4;
1269 }
1270 goto out_unknown;
1271 }
1272 goto out_unknown;
1273 }
1274
1275 /* Find the first non-VOID channel. */
1276 for (i = 0; i < 4; i++) {
1277 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1278 break;
1279 }
1280 }
1281
1282 if (i == 4)
1283 goto out_unknown;
1284
1285 /* uniform formats */
1286 switch (desc->channel[i].type) {
1287 case UTIL_FORMAT_TYPE_UNSIGNED:
1288 case UTIL_FORMAT_TYPE_SIGNED:
1289 #if 0
1290 if (!desc->channel[i].normalized &&
1291 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
1292 goto out_unknown;
1293 }
1294 #endif
1295 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1296 desc->channel[i].pure_integer)
1297 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1298
1299 switch (desc->channel[i].size) {
1300 case 4:
1301 switch (desc->nr_channels) {
1302 case 2:
1303 result = FMT_4_4;
1304 goto out_word4;
1305 case 4:
1306 result = FMT_4_4_4_4;
1307 goto out_word4;
1308 }
1309 goto out_unknown;
1310 case 8:
1311 switch (desc->nr_channels) {
1312 case 1:
1313 result = FMT_8;
1314 goto out_word4;
1315 case 2:
1316 result = FMT_8_8;
1317 goto out_word4;
1318 case 4:
1319 result = FMT_8_8_8_8;
1320 is_srgb_valid = TRUE;
1321 goto out_word4;
1322 }
1323 goto out_unknown;
1324 case 16:
1325 switch (desc->nr_channels) {
1326 case 1:
1327 result = FMT_16;
1328 goto out_word4;
1329 case 2:
1330 result = FMT_16_16;
1331 goto out_word4;
1332 case 4:
1333 result = FMT_16_16_16_16;
1334 goto out_word4;
1335 }
1336 goto out_unknown;
1337 case 32:
1338 switch (desc->nr_channels) {
1339 case 1:
1340 result = FMT_32;
1341 goto out_word4;
1342 case 2:
1343 result = FMT_32_32;
1344 goto out_word4;
1345 case 4:
1346 result = FMT_32_32_32_32;
1347 goto out_word4;
1348 }
1349 }
1350 goto out_unknown;
1351
1352 case UTIL_FORMAT_TYPE_FLOAT:
1353 switch (desc->channel[i].size) {
1354 case 16:
1355 switch (desc->nr_channels) {
1356 case 1:
1357 result = FMT_16_FLOAT;
1358 goto out_word4;
1359 case 2:
1360 result = FMT_16_16_FLOAT;
1361 goto out_word4;
1362 case 4:
1363 result = FMT_16_16_16_16_FLOAT;
1364 goto out_word4;
1365 }
1366 goto out_unknown;
1367 case 32:
1368 switch (desc->nr_channels) {
1369 case 1:
1370 result = FMT_32_FLOAT;
1371 goto out_word4;
1372 case 2:
1373 result = FMT_32_32_FLOAT;
1374 goto out_word4;
1375 case 4:
1376 result = FMT_32_32_32_32_FLOAT;
1377 goto out_word4;
1378 }
1379 }
1380 goto out_unknown;
1381 }
1382
1383 out_word4:
1384
1385 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid)
1386 return ~0;
1387 if (word4_p)
1388 *word4_p = word4;
1389 if (yuv_format_p)
1390 *yuv_format_p = yuv_format;
1391 return result;
1392 out_unknown:
1393 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1394 return ~0;
1395 }
1396
1397 static const struct u_resource_vtbl r600_texture_vtbl =
1398 {
1399 r600_texture_get_handle, /* get_handle */
1400 r600_texture_destroy, /* resource_destroy */
1401 r600_texture_transfer_map, /* transfer_map */
1402 NULL, /* transfer_flush_region */
1403 r600_texture_transfer_unmap, /* transfer_unmap */
1404 NULL /* transfer_inline_write */
1405 };