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26759153276bd6eb177c59ba0d35e1f5c17dd1ba
[mesa.git] / src / gallium / drivers / r600 / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include <errno.h>
28 #include "pipe/p_screen.h"
29 #include "util/u_format.h"
30 #include "util/u_format_s3tc.h"
31 #include "util/u_math.h"
32 #include "util/u_inlines.h"
33 #include "util/u_memory.h"
34 #include "pipebuffer/pb_buffer.h"
35 #include "r600_pipe.h"
36 #include "r600_resource.h"
37 #include "r600d.h"
38 #include "r600_formats.h"
39
40 /* Copy from a full GPU texture to a transfer's staging one. */
41 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
42 {
43 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
44 struct pipe_resource *texture = transfer->resource;
45
46 ctx->resource_copy_region(ctx, &rtransfer->staging->b.b.b,
47 0, 0, 0, 0, texture, transfer->level,
48 &transfer->box);
49 }
50
51
52 /* Copy from a transfer's staging texture to a full GPU one. */
53 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
54 {
55 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
56 struct pipe_resource *texture = transfer->resource;
57 struct pipe_box sbox;
58
59 sbox.x = sbox.y = sbox.z = 0;
60 sbox.width = transfer->box.width;
61 sbox.height = transfer->box.height;
62 /* XXX that might be wrong */
63 sbox.depth = 1;
64 ctx->resource_copy_region(ctx, texture, transfer->level,
65 transfer->box.x, transfer->box.y, transfer->box.z,
66 &rtransfer->staging->b.b.b,
67 0, &sbox);
68 }
69
70 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
71 unsigned level, unsigned layer)
72 {
73 unsigned offset = rtex->offset[level];
74
75 switch (rtex->resource.b.b.b.target) {
76 case PIPE_TEXTURE_3D:
77 case PIPE_TEXTURE_CUBE:
78 default:
79 return offset + layer * rtex->layer_size[level];
80 }
81 }
82
83 static unsigned r600_get_block_alignment(struct pipe_screen *screen,
84 enum pipe_format format,
85 unsigned array_mode)
86 {
87 struct r600_screen* rscreen = (struct r600_screen *)screen;
88 unsigned pixsize = util_format_get_blocksize(format);
89 int p_align;
90
91 switch(array_mode) {
92 case V_038000_ARRAY_1D_TILED_THIN1:
93 p_align = MAX2(8,
94 ((rscreen->tiling_info.group_bytes / 8 / pixsize)));
95 break;
96 case V_038000_ARRAY_2D_TILED_THIN1:
97 p_align = MAX2(rscreen->tiling_info.num_banks,
98 (((rscreen->tiling_info.group_bytes / 8 / pixsize)) *
99 rscreen->tiling_info.num_banks)) * 8;
100 break;
101 case V_038000_ARRAY_LINEAR_ALIGNED:
102 p_align = MAX2(64, rscreen->tiling_info.group_bytes / pixsize);
103 break;
104 case V_038000_ARRAY_LINEAR_GENERAL:
105 default:
106 p_align = rscreen->tiling_info.group_bytes / pixsize;
107 break;
108 }
109 return p_align;
110 }
111
112 static unsigned r600_get_height_alignment(struct pipe_screen *screen,
113 unsigned array_mode)
114 {
115 struct r600_screen* rscreen = (struct r600_screen *)screen;
116 int h_align;
117
118 switch (array_mode) {
119 case V_038000_ARRAY_2D_TILED_THIN1:
120 h_align = rscreen->tiling_info.num_channels * 8;
121 break;
122 case V_038000_ARRAY_1D_TILED_THIN1:
123 case V_038000_ARRAY_LINEAR_ALIGNED:
124 h_align = 8;
125 break;
126 case V_038000_ARRAY_LINEAR_GENERAL:
127 default:
128 h_align = 1;
129 break;
130 }
131 return h_align;
132 }
133
134 static unsigned r600_get_base_alignment(struct pipe_screen *screen,
135 enum pipe_format format,
136 unsigned array_mode)
137 {
138 struct r600_screen* rscreen = (struct r600_screen *)screen;
139 unsigned pixsize = util_format_get_blocksize(format);
140 int p_align = r600_get_block_alignment(screen, format, array_mode);
141 int h_align = r600_get_height_alignment(screen, array_mode);
142 int b_align;
143
144 switch (array_mode) {
145 case V_038000_ARRAY_2D_TILED_THIN1:
146 b_align = MAX2(rscreen->tiling_info.num_banks * rscreen->tiling_info.num_channels * 8 * 8 * pixsize,
147 p_align * pixsize * h_align);
148 break;
149 case V_038000_ARRAY_1D_TILED_THIN1:
150 case V_038000_ARRAY_LINEAR_ALIGNED:
151 case V_038000_ARRAY_LINEAR_GENERAL:
152 default:
153 b_align = rscreen->tiling_info.group_bytes;
154 break;
155 }
156 return b_align;
157 }
158
159 static unsigned mip_minify(unsigned size, unsigned level)
160 {
161 unsigned val;
162 val = u_minify(size, level);
163 if (level > 0)
164 val = util_next_power_of_two(val);
165 return val;
166 }
167
168 static unsigned r600_texture_get_nblocksx(struct pipe_screen *screen,
169 struct r600_resource_texture *rtex,
170 unsigned level)
171 {
172 struct pipe_resource *ptex = &rtex->resource.b.b.b;
173 unsigned nblocksx, block_align, width;
174 unsigned blocksize = util_format_get_blocksize(rtex->real_format);
175
176 if (rtex->pitch_override)
177 return rtex->pitch_override / blocksize;
178
179 width = mip_minify(ptex->width0, level);
180 nblocksx = util_format_get_nblocksx(rtex->real_format, width);
181
182 block_align = r600_get_block_alignment(screen, rtex->real_format,
183 rtex->array_mode[level]);
184 nblocksx = align(nblocksx, block_align);
185 return nblocksx;
186 }
187
188 static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen,
189 struct r600_resource_texture *rtex,
190 unsigned level)
191 {
192 struct pipe_resource *ptex = &rtex->resource.b.b.b;
193 unsigned height, tile_height;
194
195 height = mip_minify(ptex->height0, level);
196 height = util_format_get_nblocksy(rtex->real_format, height);
197 tile_height = r600_get_height_alignment(screen,
198 rtex->array_mode[level]);
199
200 /* XXX Hack around an alignment issue. Less tests fail with this.
201 *
202 * The thing is depth-stencil buffers should be tiled, i.e.
203 * the alignment should be >=8. If I make them tiled, stencil starts
204 * working because it no longer overlaps with the depth buffer
205 * in memory, but texturing like drawpix-stencil breaks. */
206 if (util_format_is_depth_or_stencil(rtex->real_format) && tile_height < 8)
207 tile_height = 8;
208
209 height = align(height, tile_height);
210 return height;
211 }
212
213 static void r600_texture_set_array_mode(struct pipe_screen *screen,
214 struct r600_resource_texture *rtex,
215 unsigned level, unsigned array_mode)
216 {
217 struct pipe_resource *ptex = &rtex->resource.b.b.b;
218
219 switch (array_mode) {
220 case V_0280A0_ARRAY_LINEAR_GENERAL:
221 case V_0280A0_ARRAY_LINEAR_ALIGNED:
222 case V_0280A0_ARRAY_1D_TILED_THIN1:
223 default:
224 rtex->array_mode[level] = array_mode;
225 break;
226 case V_0280A0_ARRAY_2D_TILED_THIN1:
227 {
228 unsigned w, h, tile_height, tile_width;
229
230 tile_height = r600_get_height_alignment(screen, array_mode);
231 tile_width = r600_get_block_alignment(screen, rtex->real_format, array_mode);
232
233 w = mip_minify(ptex->width0, level);
234 h = mip_minify(ptex->height0, level);
235 if (w <= tile_width || h <= tile_height)
236 rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1;
237 else
238 rtex->array_mode[level] = array_mode;
239 }
240 break;
241 }
242 }
243
244 static int r600_init_surface(struct radeon_surface *surface,
245 const struct pipe_resource *ptex,
246 unsigned array_mode)
247 {
248 surface->npix_x = ptex->width0;
249 surface->npix_y = ptex->height0;
250 surface->npix_z = ptex->depth0;
251 surface->blk_w = util_format_get_blockwidth(ptex->format);
252 surface->blk_h = util_format_get_blockheight(ptex->format);
253 surface->blk_d = 1;
254 surface->array_size = 1;
255 surface->last_level = ptex->last_level;
256 surface->bpe = util_format_get_blocksize(ptex->format);
257 /* align byte per element on dword */
258 if (surface->bpe == 3) {
259 surface->bpe = 4;
260 }
261 surface->nsamples = 1;
262 surface->flags = 0;
263 switch (array_mode) {
264 case V_038000_ARRAY_1D_TILED_THIN1:
265 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
266 break;
267 case V_038000_ARRAY_2D_TILED_THIN1:
268 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
269 break;
270 case V_038000_ARRAY_LINEAR_ALIGNED:
271 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
272 break;
273 case V_038000_ARRAY_LINEAR_GENERAL:
274 default:
275 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE);
276 break;
277 }
278 switch (ptex->target) {
279 case PIPE_TEXTURE_1D:
280 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
281 break;
282 case PIPE_TEXTURE_RECT:
283 case PIPE_TEXTURE_2D:
284 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
285 break;
286 case PIPE_TEXTURE_3D:
287 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
288 break;
289 case PIPE_TEXTURE_1D_ARRAY:
290 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
291 surface->array_size = ptex->array_size;
292 break;
293 case PIPE_TEXTURE_2D_ARRAY:
294 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
295 surface->array_size = ptex->array_size;
296 break;
297 case PIPE_TEXTURE_CUBE:
298 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
299 break;
300 case PIPE_BUFFER:
301 default:
302 return -EINVAL;
303 }
304 if (ptex->bind & PIPE_BIND_SCANOUT) {
305 surface->flags |= RADEON_SURF_SCANOUT;
306 }
307 if (util_format_is_depth_and_stencil(ptex->format)) {
308 surface->flags |= RADEON_SURF_ZBUFFER;
309 surface->flags |= RADEON_SURF_SBUFFER;
310 }
311
312 return 0;
313 }
314
315 static int r600_setup_surface(struct pipe_screen *screen,
316 struct r600_resource_texture *rtex,
317 unsigned array_mode,
318 unsigned pitch_in_bytes_override)
319 {
320 struct pipe_resource *ptex = &rtex->resource.b.b.b;
321 struct r600_screen *rscreen = (struct r600_screen*)screen;
322 unsigned i;
323 int r;
324
325 if (util_format_is_depth_or_stencil(rtex->real_format)) {
326 rtex->surface.flags |= RADEON_SURF_ZBUFFER;
327 rtex->surface.flags |= RADEON_SURF_SBUFFER;
328 }
329
330 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
331 if (r) {
332 return r;
333 }
334 rtex->size = rtex->surface.bo_size;
335 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
336 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
337 * for those
338 */
339 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
340 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
341 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
342 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
343 rtex->surface.stencil_offset = rtex->surface.level[0].slice_size;
344 }
345 }
346 for (i = 0; i <= ptex->last_level; i++) {
347 rtex->offset[i] = rtex->surface.level[i].offset;
348 rtex->layer_size[i] = rtex->surface.level[i].slice_size;
349 rtex->pitch_in_bytes[i] = rtex->surface.level[i].pitch_bytes;
350 switch (rtex->surface.level[i].mode) {
351 case RADEON_SURF_MODE_LINEAR_ALIGNED:
352 rtex->array_mode[i] = V_038000_ARRAY_LINEAR_ALIGNED;
353 break;
354 case RADEON_SURF_MODE_1D:
355 rtex->array_mode[i] = V_038000_ARRAY_1D_TILED_THIN1;
356 break;
357 case RADEON_SURF_MODE_2D:
358 rtex->array_mode[i] = V_038000_ARRAY_2D_TILED_THIN1;
359 break;
360 default:
361 case RADEON_SURF_MODE_LINEAR:
362 rtex->array_mode[i] = 0;
363 break;
364 }
365 }
366 return 0;
367 }
368
369 static void r600_setup_miptree(struct pipe_screen *screen,
370 struct r600_resource_texture *rtex,
371 unsigned array_mode)
372 {
373 struct pipe_resource *ptex = &rtex->resource.b.b.b;
374 enum chip_class chipc = ((struct r600_screen*)screen)->chip_class;
375 unsigned size, layer_size, i, offset;
376 unsigned nblocksx, nblocksy;
377
378 for (i = 0, offset = 0; i <= ptex->last_level; i++) {
379 unsigned blocksize = util_format_get_blocksize(rtex->real_format);
380 unsigned base_align = r600_get_base_alignment(screen, rtex->real_format, array_mode);
381
382 r600_texture_set_array_mode(screen, rtex, i, array_mode);
383
384 nblocksx = r600_texture_get_nblocksx(screen, rtex, i);
385 nblocksy = r600_texture_get_nblocksy(screen, rtex, i);
386
387 if (chipc >= EVERGREEN && array_mode == V_038000_ARRAY_LINEAR_GENERAL)
388 layer_size = align(nblocksx, 64) * nblocksy * blocksize;
389 else
390 layer_size = nblocksx * nblocksy * blocksize;
391
392 if (ptex->target == PIPE_TEXTURE_CUBE) {
393 if (chipc >= R700)
394 size = layer_size * 8;
395 else
396 size = layer_size * 6;
397 }
398 else if (ptex->target == PIPE_TEXTURE_3D)
399 size = layer_size * u_minify(ptex->depth0, i);
400 else
401 size = layer_size * ptex->array_size;
402
403 /* align base image and start of miptree */
404 if ((i == 0) || (i == 1))
405 offset = align(offset, base_align);
406 rtex->offset[i] = offset;
407 rtex->layer_size[i] = layer_size;
408 rtex->pitch_in_blocks[i] = nblocksx; /* CB talks in elements */
409 rtex->pitch_in_bytes[i] = nblocksx * blocksize;
410
411 offset += size;
412 }
413 rtex->size = offset;
414 }
415
416 /* Figure out whether u_blitter will fallback to a transfer operation.
417 * If so, don't use a staging resource.
418 */
419 static boolean permit_hardware_blit(struct pipe_screen *screen,
420 const struct pipe_resource *res)
421 {
422 unsigned bind;
423
424 if (util_format_is_depth_or_stencil(res->format))
425 bind = PIPE_BIND_DEPTH_STENCIL;
426 else
427 bind = PIPE_BIND_RENDER_TARGET;
428
429 /* hackaround for S3TC */
430 if (util_format_is_compressed(res->format))
431 return TRUE;
432
433 if (!screen->is_format_supported(screen,
434 res->format,
435 res->target,
436 res->nr_samples,
437 bind))
438 return FALSE;
439
440 if (!screen->is_format_supported(screen,
441 res->format,
442 res->target,
443 res->nr_samples,
444 PIPE_BIND_SAMPLER_VIEW))
445 return FALSE;
446
447 switch (res->usage) {
448 case PIPE_USAGE_STREAM:
449 case PIPE_USAGE_STAGING:
450 return FALSE;
451
452 default:
453 return TRUE;
454 }
455 }
456
457 static boolean r600_texture_get_handle(struct pipe_screen* screen,
458 struct pipe_resource *ptex,
459 struct winsys_handle *whandle)
460 {
461 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
462 struct r600_resource *resource = &rtex->resource;
463 struct r600_screen *rscreen = (struct r600_screen*)screen;
464
465 return rscreen->ws->buffer_get_handle(resource->buf,
466 rtex->pitch_in_bytes[0], whandle);
467 }
468
469 static void r600_texture_destroy(struct pipe_screen *screen,
470 struct pipe_resource *ptex)
471 {
472 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
473 struct r600_resource *resource = &rtex->resource;
474
475 if (rtex->flushed_depth_texture)
476 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
477
478 if (rtex->stencil)
479 pipe_resource_reference((struct pipe_resource **)&rtex->stencil, NULL);
480
481 pb_reference(&resource->buf, NULL);
482 FREE(rtex);
483 }
484
485 static const struct u_resource_vtbl r600_texture_vtbl =
486 {
487 r600_texture_get_handle, /* get_handle */
488 r600_texture_destroy, /* resource_destroy */
489 r600_texture_get_transfer, /* get_transfer */
490 r600_texture_transfer_destroy, /* transfer_destroy */
491 r600_texture_transfer_map, /* transfer_map */
492 NULL, /* transfer_flush_region */
493 r600_texture_transfer_unmap, /* transfer_unmap */
494 NULL /* transfer_inline_write */
495 };
496
497 static struct r600_resource_texture *
498 r600_texture_create_object(struct pipe_screen *screen,
499 const struct pipe_resource *base,
500 unsigned array_mode,
501 unsigned pitch_in_bytes_override,
502 unsigned max_buffer_size,
503 struct pb_buffer *buf,
504 boolean alloc_bo,
505 struct radeon_surface *surface)
506 {
507 struct r600_resource_texture *rtex;
508 struct r600_resource *resource;
509 struct r600_screen *rscreen = (struct r600_screen*)screen;
510 int r;
511
512 rtex = CALLOC_STRUCT(r600_resource_texture);
513 if (rtex == NULL)
514 return NULL;
515
516 resource = &rtex->resource;
517 resource->b.b.b = *base;
518 resource->b.b.vtbl = &r600_texture_vtbl;
519 pipe_reference_init(&resource->b.b.b.reference, 1);
520 resource->b.b.b.screen = screen;
521 rtex->pitch_override = pitch_in_bytes_override;
522 rtex->real_format = base->format;
523
524 /* We must split depth and stencil into two separate buffers on Evergreen. */
525 if (!(base->flags & R600_RESOURCE_FLAG_TRANSFER) &&
526 ((struct r600_screen*)screen)->chip_class >= EVERGREEN &&
527 util_format_is_depth_and_stencil(base->format) &&
528 !rscreen->use_surface_alloc) {
529 struct pipe_resource stencil;
530 unsigned stencil_pitch_override = 0;
531
532 switch (base->format) {
533 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
534 rtex->real_format = PIPE_FORMAT_Z24X8_UNORM;
535 break;
536 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
537 rtex->real_format = PIPE_FORMAT_X8Z24_UNORM;
538 break;
539 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
540 rtex->real_format = PIPE_FORMAT_Z32_FLOAT;
541 break;
542 default:
543 assert(0);
544 FREE(rtex);
545 return NULL;
546 }
547
548 /* Divide the pitch in bytes by 4 for stencil, because it has a smaller pixel size. */
549 if (pitch_in_bytes_override) {
550 assert(base->format == PIPE_FORMAT_Z24_UNORM_S8_UINT ||
551 base->format == PIPE_FORMAT_S8_UINT_Z24_UNORM);
552 stencil_pitch_override = pitch_in_bytes_override / 4;
553 }
554
555 /* Allocate the stencil buffer. */
556 stencil = *base;
557 stencil.format = PIPE_FORMAT_S8_UINT;
558 rtex->stencil = r600_texture_create_object(screen, &stencil, array_mode,
559 stencil_pitch_override,
560 max_buffer_size, NULL, FALSE, surface);
561 if (!rtex->stencil) {
562 FREE(rtex);
563 return NULL;
564 }
565 /* Proceed in creating the depth buffer. */
566 }
567
568 /* only mark depth textures the HW can hit as depth textures */
569 if (util_format_is_depth_or_stencil(rtex->real_format) && permit_hardware_blit(screen, base))
570 rtex->is_depth = true;
571
572 r600_setup_miptree(screen, rtex, array_mode);
573 if (rscreen->use_surface_alloc) {
574 rtex->surface = *surface;
575 r = r600_setup_surface(screen, rtex, array_mode, pitch_in_bytes_override);
576 if (r) {
577 FREE(rtex);
578 return NULL;
579 }
580 }
581
582 /* If we initialized separate stencil for Evergreen. place it after depth. */
583 if (rtex->stencil) {
584 unsigned stencil_align, stencil_offset;
585
586 stencil_align = r600_get_base_alignment(screen, rtex->stencil->real_format, array_mode);
587 stencil_offset = align(rtex->size, stencil_align);
588
589 for (unsigned i = 0; i <= rtex->stencil->resource.b.b.b.last_level; i++)
590 rtex->stencil->offset[i] += stencil_offset;
591
592 rtex->size = stencil_offset + rtex->stencil->size;
593 }
594
595 /* Now create the backing buffer. */
596 if (!buf && alloc_bo) {
597 struct pipe_resource *ptex = &rtex->resource.b.b.b;
598 unsigned base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
599
600 if (rscreen->use_surface_alloc) {
601 base_align = rtex->surface.bo_alignment;
602 } else if (util_format_is_depth_or_stencil(rtex->real_format)) {
603 /* ugly work around depth buffer need stencil room at end of bo */
604 rtex->size += ptex->width0 * ptex->height0;
605 }
606 if (!r600_init_resource(rscreen, resource, rtex->size, base_align, base->bind, base->usage)) {
607 pipe_resource_reference((struct pipe_resource**)&rtex->stencil, NULL);
608 FREE(rtex);
609 return NULL;
610 }
611 } else if (buf) {
612 resource->buf = buf;
613 resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);
614 resource->domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM;
615 }
616
617 if (rtex->stencil) {
618 pb_reference(&rtex->stencil->resource.buf, rtex->resource.buf);
619 rtex->stencil->resource.cs_buf = rtex->resource.cs_buf;
620 rtex->stencil->resource.domains = rtex->resource.domains;
621 }
622 return rtex;
623 }
624
625 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
626 const struct pipe_resource *templ)
627 {
628 struct r600_screen *rscreen = (struct r600_screen*)screen;
629 struct radeon_surface surface;
630 unsigned array_mode = 0;
631 int r;
632
633 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
634 !(templ->bind & PIPE_BIND_SCANOUT)) {
635 if (rscreen->use_surface_alloc) {
636 if (permit_hardware_blit(screen, templ)) {
637 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
638 }
639 } else if (util_format_is_compressed(templ->format)) {
640 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
641 }
642 }
643
644 r = r600_init_surface(&surface, templ, array_mode);
645 if (r) {
646 return NULL;
647 }
648 r = rscreen->ws->surface_best(rscreen->ws, &surface);
649 if (r) {
650 return NULL;
651 }
652 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
653 0, 0, NULL, TRUE, &surface);
654 }
655
656 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
657 struct pipe_resource *texture,
658 const struct pipe_surface *surf_tmpl)
659 {
660 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
661 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
662 unsigned level = surf_tmpl->u.tex.level;
663
664 assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
665 if (surface == NULL)
666 return NULL;
667 pipe_reference_init(&surface->base.reference, 1);
668 pipe_resource_reference(&surface->base.texture, texture);
669 surface->base.context = pipe;
670 surface->base.format = surf_tmpl->format;
671 surface->base.width = mip_minify(texture->width0, level);
672 surface->base.height = mip_minify(texture->height0, level);
673 surface->base.usage = surf_tmpl->usage;
674 surface->base.texture = texture;
675 surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
676 surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
677 surface->base.u.tex.level = level;
678
679 surface->aligned_height = r600_texture_get_nblocksy(pipe->screen,
680 rtex, level);
681 return &surface->base;
682 }
683
684 static void r600_surface_destroy(struct pipe_context *pipe,
685 struct pipe_surface *surface)
686 {
687 pipe_resource_reference(&surface->texture, NULL);
688 FREE(surface);
689 }
690
691 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
692 const struct pipe_resource *templ,
693 struct winsys_handle *whandle)
694 {
695 struct r600_screen *rscreen = (struct r600_screen*)screen;
696 struct pb_buffer *buf = NULL;
697 unsigned stride = 0;
698 unsigned array_mode = 0;
699 enum radeon_bo_layout micro, macro;
700 struct radeon_surface surface;
701 int r;
702
703 /* Support only 2D textures without mipmaps */
704 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
705 templ->depth0 != 1 || templ->last_level != 0)
706 return NULL;
707
708 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
709 if (!buf)
710 return NULL;
711
712 rscreen->ws->buffer_get_tiling(buf, &micro, &macro,
713 &surface.bankw, &surface.bankh,
714 &surface.tile_split,
715 &surface.stencil_tile_split,
716 &surface.mtilea);
717
718 if (macro == RADEON_LAYOUT_TILED)
719 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
720 else if (micro == RADEON_LAYOUT_TILED)
721 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
722 else
723 array_mode = 0;
724
725 r = r600_init_surface(&surface, templ, array_mode);
726 if (r) {
727 return NULL;
728 }
729 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
730 stride, 0, buf, FALSE, &surface);
731 }
732
733 int r600_texture_depth_flush(struct pipe_context *ctx,
734 struct pipe_resource *texture, boolean just_create)
735 {
736 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
737 struct pipe_resource resource;
738
739 if (rtex->flushed_depth_texture)
740 goto out;
741
742 resource.target = texture->target;
743 resource.format = texture->format;
744 resource.width0 = texture->width0;
745 resource.height0 = texture->height0;
746 resource.depth0 = texture->depth0;
747 resource.array_size = texture->array_size;
748 resource.last_level = texture->last_level;
749 resource.nr_samples = texture->nr_samples;
750 resource.usage = PIPE_USAGE_DYNAMIC;
751 resource.bind = texture->bind | PIPE_BIND_DEPTH_STENCIL;
752 resource.flags = R600_RESOURCE_FLAG_TRANSFER | texture->flags;
753
754 rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
755 if (rtex->flushed_depth_texture == NULL) {
756 R600_ERR("failed to create temporary texture to hold untiled copy\n");
757 return -ENOMEM;
758 }
759
760 ((struct r600_resource_texture *)rtex->flushed_depth_texture)->is_flushing_texture = TRUE;
761 out:
762 if (just_create)
763 return 0;
764
765 /* XXX: only do this if the depth texture has actually changed:
766 */
767 r600_blit_uncompress_depth(ctx, rtex);
768 return 0;
769 }
770
771 /* Needs adjustment for pixelformat:
772 */
773 static INLINE unsigned u_box_volume( const struct pipe_box *box )
774 {
775 return box->width * box->depth * box->height;
776 };
777
778 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
779 struct pipe_resource *texture,
780 unsigned level,
781 unsigned usage,
782 const struct pipe_box *box)
783 {
784 struct r600_context *rctx = (struct r600_context*)ctx;
785 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
786 struct pipe_resource resource;
787 struct r600_transfer *trans;
788 int r;
789 boolean use_staging_texture = FALSE;
790
791 /* We cannot map a tiled texture directly because the data is
792 * in a different order, therefore we do detiling using a blit.
793 *
794 * Also, use a temporary in GTT memory for read transfers, as
795 * the CPU is much happier reading out of cached system memory
796 * than uncached VRAM.
797 */
798 if (R600_TEX_IS_TILED(rtex, level))
799 use_staging_texture = TRUE;
800
801 if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024)
802 use_staging_texture = TRUE;
803
804 /* Use a staging texture for uploads if the underlying BO is busy. */
805 if (!(usage & PIPE_TRANSFER_READ) &&
806 (rctx->ws->cs_is_buffer_referenced(rctx->cs, rtex->resource.cs_buf) ||
807 rctx->ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE)))
808 use_staging_texture = TRUE;
809
810 if (!permit_hardware_blit(ctx->screen, texture) ||
811 (texture->flags & R600_RESOURCE_FLAG_TRANSFER))
812 use_staging_texture = FALSE;
813
814 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY))
815 return NULL;
816
817 trans = CALLOC_STRUCT(r600_transfer);
818 if (trans == NULL)
819 return NULL;
820 pipe_resource_reference(&trans->transfer.resource, texture);
821 trans->transfer.level = level;
822 trans->transfer.usage = usage;
823 trans->transfer.box = *box;
824 if (rtex->is_depth) {
825 /* XXX: only readback the rectangle which is being mapped?
826 */
827 /* XXX: when discard is true, no need to read back from depth texture
828 */
829 r = r600_texture_depth_flush(ctx, texture, FALSE);
830 if (r < 0) {
831 R600_ERR("failed to create temporary texture to hold untiled copy\n");
832 pipe_resource_reference(&trans->transfer.resource, NULL);
833 FREE(trans);
834 return NULL;
835 }
836 trans->transfer.stride = rtex->flushed_depth_texture->pitch_in_bytes[level];
837 trans->offset = r600_texture_get_offset(rtex->flushed_depth_texture, level, box->z);
838 return &trans->transfer;
839 } else if (use_staging_texture) {
840 resource.target = PIPE_TEXTURE_2D;
841 resource.format = texture->format;
842 resource.width0 = box->width;
843 resource.height0 = box->height;
844 resource.depth0 = 1;
845 resource.array_size = 1;
846 resource.last_level = 0;
847 resource.nr_samples = 0;
848 resource.usage = PIPE_USAGE_STAGING;
849 resource.bind = 0;
850 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
851 /* For texture reading, the temporary (detiled) texture is used as
852 * a render target when blitting from a tiled texture. */
853 if (usage & PIPE_TRANSFER_READ) {
854 resource.bind |= PIPE_BIND_RENDER_TARGET;
855 }
856 /* For texture writing, the temporary texture is used as a sampler
857 * when blitting into a tiled texture. */
858 if (usage & PIPE_TRANSFER_WRITE) {
859 resource.bind |= PIPE_BIND_SAMPLER_VIEW;
860 }
861 /* Create the temporary texture. */
862 trans->staging = (struct r600_resource*)ctx->screen->resource_create(ctx->screen, &resource);
863 if (trans->staging == NULL) {
864 R600_ERR("failed to create temporary texture to hold untiled copy\n");
865 pipe_resource_reference(&trans->transfer.resource, NULL);
866 FREE(trans);
867 return NULL;
868 }
869
870 trans->transfer.stride =
871 ((struct r600_resource_texture *)trans->staging)->pitch_in_bytes[0];
872 if (usage & PIPE_TRANSFER_READ) {
873 r600_copy_to_staging_texture(ctx, trans);
874 /* Always referenced in the blit. */
875 r600_flush(ctx, NULL, 0);
876 }
877 return &trans->transfer;
878 }
879 trans->transfer.stride = rtex->pitch_in_bytes[level];
880 trans->transfer.layer_stride = rtex->layer_size[level];
881 trans->offset = r600_texture_get_offset(rtex, level, box->z);
882 return &trans->transfer;
883 }
884
885 void r600_texture_transfer_destroy(struct pipe_context *ctx,
886 struct pipe_transfer *transfer)
887 {
888 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
889 struct pipe_resource *texture = transfer->resource;
890 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
891
892 if (rtransfer->staging) {
893 if (transfer->usage & PIPE_TRANSFER_WRITE) {
894 r600_copy_from_staging_texture(ctx, rtransfer);
895 }
896 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
897 }
898
899 if (rtex->is_depth && !rtex->is_flushing_texture) {
900 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtex->flushed_depth_texture)
901 r600_blit_push_depth(ctx, rtex);
902 }
903
904 pipe_resource_reference(&transfer->resource, NULL);
905 FREE(transfer);
906 }
907
908 void* r600_texture_transfer_map(struct pipe_context *ctx,
909 struct pipe_transfer* transfer)
910 {
911 struct r600_context *rctx = (struct r600_context *)ctx;
912 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
913 struct pb_buffer *buf;
914 enum pipe_format format = transfer->resource->format;
915 unsigned offset = 0;
916 char *map;
917
918 if (rtransfer->staging) {
919 buf = ((struct r600_resource *)rtransfer->staging)->buf;
920 } else {
921 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
922
923 if (rtex->flushed_depth_texture)
924 buf = ((struct r600_resource *)rtex->flushed_depth_texture)->buf;
925 else
926 buf = ((struct r600_resource *)transfer->resource)->buf;
927
928 offset = rtransfer->offset +
929 transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
930 transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
931 }
932
933 if (!(map = rctx->ws->buffer_map(buf, rctx->cs, transfer->usage))) {
934 return NULL;
935 }
936
937 return map + offset;
938 }
939
940 void r600_texture_transfer_unmap(struct pipe_context *ctx,
941 struct pipe_transfer* transfer)
942 {
943 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
944 struct r600_context *rctx = (struct r600_context*)ctx;
945 struct pb_buffer *buf;
946
947 if (rtransfer->staging) {
948 buf = ((struct r600_resource *)rtransfer->staging)->buf;
949 } else {
950 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
951
952 if (rtex->flushed_depth_texture) {
953 buf = ((struct r600_resource *)rtex->flushed_depth_texture)->buf;
954 } else {
955 buf = ((struct r600_resource *)transfer->resource)->buf;
956 }
957 }
958 rctx->ws->buffer_unmap(buf);
959 }
960
961 void r600_init_surface_functions(struct r600_context *r600)
962 {
963 r600->context.create_surface = r600_create_surface;
964 r600->context.surface_destroy = r600_surface_destroy;
965 }
966
967 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
968 const unsigned char *swizzle_view)
969 {
970 unsigned i;
971 unsigned char swizzle[4];
972 unsigned result = 0;
973 const uint32_t swizzle_shift[4] = {
974 16, 19, 22, 25,
975 };
976 const uint32_t swizzle_bit[4] = {
977 0, 1, 2, 3,
978 };
979
980 if (swizzle_view) {
981 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
982 } else {
983 memcpy(swizzle, swizzle_format, 4);
984 }
985
986 /* Get swizzle. */
987 for (i = 0; i < 4; i++) {
988 switch (swizzle[i]) {
989 case UTIL_FORMAT_SWIZZLE_Y:
990 result |= swizzle_bit[1] << swizzle_shift[i];
991 break;
992 case UTIL_FORMAT_SWIZZLE_Z:
993 result |= swizzle_bit[2] << swizzle_shift[i];
994 break;
995 case UTIL_FORMAT_SWIZZLE_W:
996 result |= swizzle_bit[3] << swizzle_shift[i];
997 break;
998 case UTIL_FORMAT_SWIZZLE_0:
999 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
1000 break;
1001 case UTIL_FORMAT_SWIZZLE_1:
1002 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
1003 break;
1004 default: /* UTIL_FORMAT_SWIZZLE_X */
1005 result |= swizzle_bit[0] << swizzle_shift[i];
1006 }
1007 }
1008 return result;
1009 }
1010
1011 /* texture format translate */
1012 uint32_t r600_translate_texformat(struct pipe_screen *screen,
1013 enum pipe_format format,
1014 const unsigned char *swizzle_view,
1015 uint32_t *word4_p, uint32_t *yuv_format_p)
1016 {
1017 uint32_t result = 0, word4 = 0, yuv_format = 0;
1018 const struct util_format_description *desc;
1019 boolean uniform = TRUE;
1020 static int r600_enable_s3tc = -1;
1021 bool is_srgb_valid = FALSE;
1022
1023 int i;
1024 const uint32_t sign_bit[4] = {
1025 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
1026 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
1027 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
1028 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
1029 };
1030 desc = util_format_description(format);
1031
1032 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
1033
1034 /* Colorspace (return non-RGB formats directly). */
1035 switch (desc->colorspace) {
1036 /* Depth stencil formats */
1037 case UTIL_FORMAT_COLORSPACE_ZS:
1038 switch (format) {
1039 case PIPE_FORMAT_Z16_UNORM:
1040 result = FMT_16;
1041 goto out_word4;
1042 case PIPE_FORMAT_X24S8_UINT:
1043 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1044 case PIPE_FORMAT_Z24X8_UNORM:
1045 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1046 result = FMT_8_24;
1047 goto out_word4;
1048 case PIPE_FORMAT_S8X24_UINT:
1049 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1050 case PIPE_FORMAT_X8Z24_UNORM:
1051 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1052 result = FMT_24_8;
1053 goto out_word4;
1054 case PIPE_FORMAT_S8_UINT:
1055 result = FMT_8;
1056 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1057 goto out_word4;
1058 case PIPE_FORMAT_Z32_FLOAT:
1059 result = FMT_32_FLOAT;
1060 goto out_word4;
1061 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1062 result = FMT_X24_8_32_FLOAT;
1063 goto out_word4;
1064 default:
1065 goto out_unknown;
1066 }
1067
1068 case UTIL_FORMAT_COLORSPACE_YUV:
1069 yuv_format |= (1 << 30);
1070 switch (format) {
1071 case PIPE_FORMAT_UYVY:
1072 case PIPE_FORMAT_YUYV:
1073 default:
1074 break;
1075 }
1076 goto out_unknown; /* XXX */
1077
1078 case UTIL_FORMAT_COLORSPACE_SRGB:
1079 word4 |= S_038010_FORCE_DEGAMMA(1);
1080 break;
1081
1082 default:
1083 break;
1084 }
1085
1086 if (r600_enable_s3tc == -1) {
1087 struct r600_screen *rscreen = (struct r600_screen *)screen;
1088 if (rscreen->info.drm_minor >= 9)
1089 r600_enable_s3tc = 1;
1090 else
1091 r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
1092 }
1093
1094 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1095 if (!r600_enable_s3tc)
1096 goto out_unknown;
1097
1098 switch (format) {
1099 case PIPE_FORMAT_RGTC1_SNORM:
1100 case PIPE_FORMAT_LATC1_SNORM:
1101 word4 |= sign_bit[0];
1102 case PIPE_FORMAT_RGTC1_UNORM:
1103 case PIPE_FORMAT_LATC1_UNORM:
1104 result = FMT_BC4;
1105 goto out_word4;
1106 case PIPE_FORMAT_RGTC2_SNORM:
1107 case PIPE_FORMAT_LATC2_SNORM:
1108 word4 |= sign_bit[0] | sign_bit[1];
1109 case PIPE_FORMAT_RGTC2_UNORM:
1110 case PIPE_FORMAT_LATC2_UNORM:
1111 result = FMT_BC5;
1112 goto out_word4;
1113 default:
1114 goto out_unknown;
1115 }
1116 }
1117
1118 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1119
1120 if (!r600_enable_s3tc)
1121 goto out_unknown;
1122
1123 if (!util_format_s3tc_enabled) {
1124 goto out_unknown;
1125 }
1126
1127 switch (format) {
1128 case PIPE_FORMAT_DXT1_RGB:
1129 case PIPE_FORMAT_DXT1_RGBA:
1130 case PIPE_FORMAT_DXT1_SRGB:
1131 case PIPE_FORMAT_DXT1_SRGBA:
1132 result = FMT_BC1;
1133 is_srgb_valid = TRUE;
1134 goto out_word4;
1135 case PIPE_FORMAT_DXT3_RGBA:
1136 case PIPE_FORMAT_DXT3_SRGBA:
1137 result = FMT_BC2;
1138 is_srgb_valid = TRUE;
1139 goto out_word4;
1140 case PIPE_FORMAT_DXT5_RGBA:
1141 case PIPE_FORMAT_DXT5_SRGBA:
1142 result = FMT_BC3;
1143 is_srgb_valid = TRUE;
1144 goto out_word4;
1145 default:
1146 goto out_unknown;
1147 }
1148 }
1149
1150 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1151 result = FMT_5_9_9_9_SHAREDEXP;
1152 goto out_word4;
1153 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1154 result = FMT_10_11_11_FLOAT;
1155 goto out_word4;
1156 }
1157
1158
1159 for (i = 0; i < desc->nr_channels; i++) {
1160 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1161 word4 |= sign_bit[i];
1162 }
1163 }
1164
1165 /* R8G8Bx_SNORM - XXX CxV8U8 */
1166
1167 /* See whether the components are of the same size. */
1168 for (i = 1; i < desc->nr_channels; i++) {
1169 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1170 }
1171
1172 /* Non-uniform formats. */
1173 if (!uniform) {
1174 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1175 desc->channel[0].pure_integer)
1176 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1177 switch(desc->nr_channels) {
1178 case 3:
1179 if (desc->channel[0].size == 5 &&
1180 desc->channel[1].size == 6 &&
1181 desc->channel[2].size == 5) {
1182 result = FMT_5_6_5;
1183 goto out_word4;
1184 }
1185 goto out_unknown;
1186 case 4:
1187 if (desc->channel[0].size == 5 &&
1188 desc->channel[1].size == 5 &&
1189 desc->channel[2].size == 5 &&
1190 desc->channel[3].size == 1) {
1191 result = FMT_1_5_5_5;
1192 goto out_word4;
1193 }
1194 if (desc->channel[0].size == 10 &&
1195 desc->channel[1].size == 10 &&
1196 desc->channel[2].size == 10 &&
1197 desc->channel[3].size == 2) {
1198 result = FMT_2_10_10_10;
1199 goto out_word4;
1200 }
1201 goto out_unknown;
1202 }
1203 goto out_unknown;
1204 }
1205
1206 /* Find the first non-VOID channel. */
1207 for (i = 0; i < 4; i++) {
1208 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1209 break;
1210 }
1211 }
1212
1213 if (i == 4)
1214 goto out_unknown;
1215
1216 /* uniform formats */
1217 switch (desc->channel[i].type) {
1218 case UTIL_FORMAT_TYPE_UNSIGNED:
1219 case UTIL_FORMAT_TYPE_SIGNED:
1220 #if 0
1221 if (!desc->channel[i].normalized &&
1222 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
1223 goto out_unknown;
1224 }
1225 #endif
1226 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1227 desc->channel[i].pure_integer)
1228 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1229
1230 switch (desc->channel[i].size) {
1231 case 4:
1232 switch (desc->nr_channels) {
1233 case 2:
1234 result = FMT_4_4;
1235 goto out_word4;
1236 case 4:
1237 result = FMT_4_4_4_4;
1238 goto out_word4;
1239 }
1240 goto out_unknown;
1241 case 8:
1242 switch (desc->nr_channels) {
1243 case 1:
1244 result = FMT_8;
1245 goto out_word4;
1246 case 2:
1247 result = FMT_8_8;
1248 goto out_word4;
1249 case 4:
1250 result = FMT_8_8_8_8;
1251 is_srgb_valid = TRUE;
1252 goto out_word4;
1253 }
1254 goto out_unknown;
1255 case 16:
1256 switch (desc->nr_channels) {
1257 case 1:
1258 result = FMT_16;
1259 goto out_word4;
1260 case 2:
1261 result = FMT_16_16;
1262 goto out_word4;
1263 case 4:
1264 result = FMT_16_16_16_16;
1265 goto out_word4;
1266 }
1267 goto out_unknown;
1268 case 32:
1269 switch (desc->nr_channels) {
1270 case 1:
1271 result = FMT_32;
1272 goto out_word4;
1273 case 2:
1274 result = FMT_32_32;
1275 goto out_word4;
1276 case 4:
1277 result = FMT_32_32_32_32;
1278 goto out_word4;
1279 }
1280 }
1281 goto out_unknown;
1282
1283 case UTIL_FORMAT_TYPE_FLOAT:
1284 switch (desc->channel[i].size) {
1285 case 16:
1286 switch (desc->nr_channels) {
1287 case 1:
1288 result = FMT_16_FLOAT;
1289 goto out_word4;
1290 case 2:
1291 result = FMT_16_16_FLOAT;
1292 goto out_word4;
1293 case 4:
1294 result = FMT_16_16_16_16_FLOAT;
1295 goto out_word4;
1296 }
1297 goto out_unknown;
1298 case 32:
1299 switch (desc->nr_channels) {
1300 case 1:
1301 result = FMT_32_FLOAT;
1302 goto out_word4;
1303 case 2:
1304 result = FMT_32_32_FLOAT;
1305 goto out_word4;
1306 case 4:
1307 result = FMT_32_32_32_32_FLOAT;
1308 goto out_word4;
1309 }
1310 }
1311 goto out_unknown;
1312 }
1313
1314 out_word4:
1315
1316 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid)
1317 return ~0;
1318 if (word4_p)
1319 *word4_p = word4;
1320 if (yuv_format_p)
1321 *yuv_format_p = yuv_format;
1322 return result;
1323 out_unknown:
1324 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1325 return ~0;
1326 }