2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "pipe/p_screen.h"
29 #include "util/u_format.h"
30 #include "util/u_format_s3tc.h"
31 #include "util/u_math.h"
32 #include "util/u_inlines.h"
33 #include "util/u_memory.h"
34 #include "pipebuffer/pb_buffer.h"
35 #include "r600_pipe.h"
36 #include "r600_resource.h"
38 #include "r600_formats.h"
40 /* Copy from a full GPU texture to a transfer's staging one. */
41 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
43 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
44 struct pipe_resource
*texture
= transfer
->resource
;
46 ctx
->resource_copy_region(ctx
, rtransfer
->staging_texture
,
47 0, 0, 0, 0, texture
, transfer
->level
,
52 /* Copy from a transfer's staging texture to a full GPU one. */
53 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
55 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
56 struct pipe_resource
*texture
= transfer
->resource
;
59 sbox
.x
= sbox
.y
= sbox
.z
= 0;
60 sbox
.width
= transfer
->box
.width
;
61 sbox
.height
= transfer
->box
.height
;
62 /* XXX that might be wrong */
64 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
65 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
66 rtransfer
->staging_texture
,
70 unsigned r600_texture_get_offset(struct r600_resource_texture
*rtex
,
71 unsigned level
, unsigned layer
)
73 unsigned offset
= rtex
->offset
[level
];
75 switch (rtex
->resource
.b
.b
.b
.target
) {
77 case PIPE_TEXTURE_CUBE
:
79 return offset
+ layer
* rtex
->layer_size
[level
];
83 static unsigned r600_get_block_alignment(struct pipe_screen
*screen
,
84 enum pipe_format format
,
87 struct r600_screen
* rscreen
= (struct r600_screen
*)screen
;
88 unsigned pixsize
= util_format_get_blocksize(format
);
92 case V_038000_ARRAY_1D_TILED_THIN1
:
94 ((rscreen
->tiling_info
.group_bytes
/ 8 / pixsize
)));
96 case V_038000_ARRAY_2D_TILED_THIN1
:
97 p_align
= MAX2(rscreen
->tiling_info
.num_banks
,
98 (((rscreen
->tiling_info
.group_bytes
/ 8 / pixsize
)) *
99 rscreen
->tiling_info
.num_banks
)) * 8;
101 case V_038000_ARRAY_LINEAR_ALIGNED
:
102 p_align
= MAX2(64, rscreen
->tiling_info
.group_bytes
/ pixsize
);
104 case V_038000_ARRAY_LINEAR_GENERAL
:
106 p_align
= rscreen
->tiling_info
.group_bytes
/ pixsize
;
112 static unsigned r600_get_height_alignment(struct pipe_screen
*screen
,
115 struct r600_screen
* rscreen
= (struct r600_screen
*)screen
;
118 switch (array_mode
) {
119 case V_038000_ARRAY_2D_TILED_THIN1
:
120 h_align
= rscreen
->tiling_info
.num_channels
* 8;
122 case V_038000_ARRAY_1D_TILED_THIN1
:
123 case V_038000_ARRAY_LINEAR_ALIGNED
:
126 case V_038000_ARRAY_LINEAR_GENERAL
:
134 static unsigned r600_get_base_alignment(struct pipe_screen
*screen
,
135 enum pipe_format format
,
138 struct r600_screen
* rscreen
= (struct r600_screen
*)screen
;
139 unsigned pixsize
= util_format_get_blocksize(format
);
140 int p_align
= r600_get_block_alignment(screen
, format
, array_mode
);
141 int h_align
= r600_get_height_alignment(screen
, array_mode
);
144 switch (array_mode
) {
145 case V_038000_ARRAY_2D_TILED_THIN1
:
146 b_align
= MAX2(rscreen
->tiling_info
.num_banks
* rscreen
->tiling_info
.num_channels
* 8 * 8 * pixsize
,
147 p_align
* pixsize
* h_align
);
149 case V_038000_ARRAY_1D_TILED_THIN1
:
150 case V_038000_ARRAY_LINEAR_ALIGNED
:
151 case V_038000_ARRAY_LINEAR_GENERAL
:
153 b_align
= rscreen
->tiling_info
.group_bytes
;
159 static unsigned mip_minify(unsigned size
, unsigned level
)
162 val
= u_minify(size
, level
);
164 val
= util_next_power_of_two(val
);
168 static unsigned r600_texture_get_nblocksx(struct pipe_screen
*screen
,
169 struct r600_resource_texture
*rtex
,
172 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
.b
;
173 unsigned nblocksx
, block_align
, width
;
174 unsigned blocksize
= util_format_get_blocksize(rtex
->real_format
);
176 if (rtex
->pitch_override
)
177 return rtex
->pitch_override
/ blocksize
;
179 width
= mip_minify(ptex
->width0
, level
);
180 nblocksx
= util_format_get_nblocksx(rtex
->real_format
, width
);
182 block_align
= r600_get_block_alignment(screen
, rtex
->real_format
,
183 rtex
->array_mode
[level
]);
184 nblocksx
= align(nblocksx
, block_align
);
188 static unsigned r600_texture_get_nblocksy(struct pipe_screen
*screen
,
189 struct r600_resource_texture
*rtex
,
192 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
.b
;
193 unsigned height
, tile_height
;
195 height
= mip_minify(ptex
->height0
, level
);
196 height
= util_format_get_nblocksy(rtex
->real_format
, height
);
197 tile_height
= r600_get_height_alignment(screen
,
198 rtex
->array_mode
[level
]);
200 /* XXX Hack around an alignment issue. Less tests fail with this.
202 * The thing is depth-stencil buffers should be tiled, i.e.
203 * the alignment should be >=8. If I make them tiled, stencil starts
204 * working because it no longer overlaps with the depth buffer
205 * in memory, but texturing like drawpix-stencil breaks. */
206 if (util_format_is_depth_or_stencil(rtex
->real_format
) && tile_height
< 8)
209 height
= align(height
, tile_height
);
213 static void r600_texture_set_array_mode(struct pipe_screen
*screen
,
214 struct r600_resource_texture
*rtex
,
215 unsigned level
, unsigned array_mode
)
217 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
.b
;
219 switch (array_mode
) {
220 case V_0280A0_ARRAY_LINEAR_GENERAL
:
221 case V_0280A0_ARRAY_LINEAR_ALIGNED
:
222 case V_0280A0_ARRAY_1D_TILED_THIN1
:
224 rtex
->array_mode
[level
] = array_mode
;
226 case V_0280A0_ARRAY_2D_TILED_THIN1
:
228 unsigned w
, h
, tile_height
, tile_width
;
230 tile_height
= r600_get_height_alignment(screen
, array_mode
);
231 tile_width
= r600_get_block_alignment(screen
, rtex
->real_format
, array_mode
);
233 w
= mip_minify(ptex
->width0
, level
);
234 h
= mip_minify(ptex
->height0
, level
);
235 if (w
<= tile_width
|| h
<= tile_height
)
236 rtex
->array_mode
[level
] = V_0280A0_ARRAY_1D_TILED_THIN1
;
238 rtex
->array_mode
[level
] = array_mode
;
244 static void r600_setup_miptree(struct pipe_screen
*screen
,
245 struct r600_resource_texture
*rtex
,
248 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
.b
;
249 enum chip_class chipc
= ((struct r600_screen
*)screen
)->chip_class
;
250 unsigned size
, layer_size
, i
, offset
;
251 unsigned nblocksx
, nblocksy
;
253 for (i
= 0, offset
= 0; i
<= ptex
->last_level
; i
++) {
254 unsigned blocksize
= util_format_get_blocksize(rtex
->real_format
);
255 unsigned base_align
= r600_get_base_alignment(screen
, rtex
->real_format
, array_mode
);
257 r600_texture_set_array_mode(screen
, rtex
, i
, array_mode
);
259 nblocksx
= r600_texture_get_nblocksx(screen
, rtex
, i
);
260 nblocksy
= r600_texture_get_nblocksy(screen
, rtex
, i
);
262 if (chipc
>= EVERGREEN
&& array_mode
== V_038000_ARRAY_LINEAR_GENERAL
)
263 layer_size
= align(nblocksx
, 64) * nblocksy
* blocksize
;
265 layer_size
= nblocksx
* nblocksy
* blocksize
;
267 if (ptex
->target
== PIPE_TEXTURE_CUBE
) {
269 size
= layer_size
* 8;
271 size
= layer_size
* 6;
273 else if (ptex
->target
== PIPE_TEXTURE_3D
)
274 size
= layer_size
* u_minify(ptex
->depth0
, i
);
276 size
= layer_size
* ptex
->array_size
;
278 /* align base image and start of miptree */
279 if ((i
== 0) || (i
== 1))
280 offset
= align(offset
, base_align
);
281 rtex
->offset
[i
] = offset
;
282 rtex
->layer_size
[i
] = layer_size
;
283 rtex
->pitch_in_blocks
[i
] = nblocksx
; /* CB talks in elements */
284 rtex
->pitch_in_bytes
[i
] = nblocksx
* blocksize
;
291 /* Figure out whether u_blitter will fallback to a transfer operation.
292 * If so, don't use a staging resource.
294 static boolean
permit_hardware_blit(struct pipe_screen
*screen
,
295 const struct pipe_resource
*res
)
299 if (util_format_is_depth_or_stencil(res
->format
))
300 bind
= PIPE_BIND_DEPTH_STENCIL
;
302 bind
= PIPE_BIND_RENDER_TARGET
;
304 /* hackaround for S3TC */
305 if (util_format_is_compressed(res
->format
))
308 if (!screen
->is_format_supported(screen
,
315 if (!screen
->is_format_supported(screen
,
319 PIPE_BIND_SAMPLER_VIEW
))
322 switch (res
->usage
) {
323 case PIPE_USAGE_STREAM
:
324 case PIPE_USAGE_STAGING
:
332 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
333 struct pipe_resource
*ptex
,
334 struct winsys_handle
*whandle
)
336 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)ptex
;
337 struct r600_resource
*resource
= &rtex
->resource
;
338 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
340 return rscreen
->ws
->buffer_get_handle(resource
->buf
,
341 rtex
->pitch_in_bytes
[0], whandle
);
344 static void r600_texture_destroy(struct pipe_screen
*screen
,
345 struct pipe_resource
*ptex
)
347 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)ptex
;
348 struct r600_resource
*resource
= &rtex
->resource
;
350 if (rtex
->flushed_depth_texture
)
351 pipe_resource_reference((struct pipe_resource
**)&rtex
->flushed_depth_texture
, NULL
);
354 pipe_resource_reference((struct pipe_resource
**)&rtex
->stencil
, NULL
);
356 pb_reference(&resource
->buf
, NULL
);
360 static const struct u_resource_vtbl r600_texture_vtbl
=
362 r600_texture_get_handle
, /* get_handle */
363 r600_texture_destroy
, /* resource_destroy */
364 r600_texture_get_transfer
, /* get_transfer */
365 r600_texture_transfer_destroy
, /* transfer_destroy */
366 r600_texture_transfer_map
, /* transfer_map */
367 u_default_transfer_flush_region
,/* transfer_flush_region */
368 r600_texture_transfer_unmap
, /* transfer_unmap */
369 u_default_transfer_inline_write
/* transfer_inline_write */
372 static struct r600_resource_texture
*
373 r600_texture_create_object(struct pipe_screen
*screen
,
374 const struct pipe_resource
*base
,
376 unsigned pitch_in_bytes_override
,
377 unsigned max_buffer_size
,
378 struct pb_buffer
*buf
,
381 struct r600_resource_texture
*rtex
;
382 struct r600_resource
*resource
;
383 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
385 rtex
= CALLOC_STRUCT(r600_resource_texture
);
389 resource
= &rtex
->resource
;
390 resource
->b
.b
.b
= *base
;
391 resource
->b
.b
.vtbl
= &r600_texture_vtbl
;
392 pipe_reference_init(&resource
->b
.b
.b
.reference
, 1);
393 resource
->b
.b
.b
.screen
= screen
;
394 rtex
->pitch_override
= pitch_in_bytes_override
;
395 rtex
->real_format
= base
->format
;
397 /* We must split depth and stencil into two separate buffers on Evergreen. */
398 if (!(base
->flags
& R600_RESOURCE_FLAG_TRANSFER
) &&
399 ((struct r600_screen
*)screen
)->chip_class
>= EVERGREEN
&&
400 util_format_is_depth_and_stencil(base
->format
)) {
401 struct pipe_resource stencil
;
402 unsigned stencil_pitch_override
= 0;
404 switch (base
->format
) {
405 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
406 rtex
->real_format
= PIPE_FORMAT_Z24X8_UNORM
;
408 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
409 rtex
->real_format
= PIPE_FORMAT_X8Z24_UNORM
;
411 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
412 rtex
->real_format
= PIPE_FORMAT_Z32_FLOAT
;
420 /* Divide the pitch in bytes by 4 for stencil, because it has a smaller pixel size. */
421 if (pitch_in_bytes_override
) {
422 assert(base
->format
== PIPE_FORMAT_Z24_UNORM_S8_UINT
||
423 base
->format
== PIPE_FORMAT_S8_UINT_Z24_UNORM
);
424 stencil_pitch_override
= pitch_in_bytes_override
/ 4;
427 /* Allocate the stencil buffer. */
429 stencil
.format
= PIPE_FORMAT_S8_UINT
;
430 rtex
->stencil
= r600_texture_create_object(screen
, &stencil
, array_mode
,
431 stencil_pitch_override
,
432 max_buffer_size
, NULL
, FALSE
);
433 if (!rtex
->stencil
) {
437 /* Proceed in creating the depth buffer. */
440 /* only mark depth textures the HW can hit as depth textures */
441 if (util_format_is_depth_or_stencil(rtex
->real_format
) && permit_hardware_blit(screen
, base
))
444 r600_setup_miptree(screen
, rtex
, array_mode
);
446 /* If we initialized separate stencil for Evergreen. place it after depth. */
448 unsigned stencil_align
, stencil_offset
;
450 stencil_align
= r600_get_base_alignment(screen
, rtex
->stencil
->real_format
, array_mode
);
451 stencil_offset
= align(rtex
->size
, stencil_align
);
453 for (unsigned i
= 0; i
<= rtex
->stencil
->resource
.b
.b
.b
.last_level
; i
++)
454 rtex
->stencil
->offset
[i
] += stencil_offset
;
456 rtex
->size
= stencil_offset
+ rtex
->stencil
->size
;
459 /* Now create the backing buffer. */
460 if (!buf
&& alloc_bo
) {
461 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
.b
;
462 unsigned base_align
= r600_get_base_alignment(screen
, ptex
->format
, array_mode
);
464 if (!r600_init_resource(rscreen
, resource
, rtex
->size
, base_align
, base
->bind
, base
->usage
)) {
465 pipe_resource_reference((struct pipe_resource
**)&rtex
->stencil
, NULL
);
471 resource
->cs_buf
= rscreen
->ws
->buffer_get_cs_handle(buf
);
475 pb_reference(&rtex
->stencil
->resource
.buf
, rtex
->resource
.buf
);
476 rtex
->stencil
->resource
.cs_buf
= rtex
->resource
.cs_buf
;
481 DEBUG_GET_ONCE_BOOL_OPTION(tiling_enabled
, "R600_TILING", FALSE
);
483 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
484 const struct pipe_resource
*templ
)
486 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
487 unsigned array_mode
= 0;
489 if (!(templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
) &&
490 !(templ
->bind
& PIPE_BIND_SCANOUT
)) {
491 if (util_format_is_compressed(templ
->format
)) {
492 array_mode
= V_038000_ARRAY_1D_TILED_THIN1
;
494 else if (debug_get_option_tiling_enabled() &&
495 rscreen
->info
.drm_minor
>= 9 &&
496 permit_hardware_blit(screen
, templ
)) {
497 array_mode
= V_038000_ARRAY_2D_TILED_THIN1
;
501 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
, array_mode
,
505 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
506 struct pipe_resource
*texture
,
507 const struct pipe_surface
*surf_tmpl
)
509 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
510 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
511 unsigned level
= surf_tmpl
->u
.tex
.level
;
513 assert(surf_tmpl
->u
.tex
.first_layer
== surf_tmpl
->u
.tex
.last_layer
);
517 /* offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/
518 pipe_reference_init(&surface
->base
.reference
, 1);
519 pipe_resource_reference(&surface
->base
.texture
, texture
);
520 surface
->base
.context
= pipe
;
521 surface
->base
.format
= surf_tmpl
->format
;
522 surface
->base
.width
= mip_minify(texture
->width0
, level
);
523 surface
->base
.height
= mip_minify(texture
->height0
, level
);
524 surface
->base
.usage
= surf_tmpl
->usage
;
525 surface
->base
.texture
= texture
;
526 surface
->base
.u
.tex
.first_layer
= surf_tmpl
->u
.tex
.first_layer
;
527 surface
->base
.u
.tex
.last_layer
= surf_tmpl
->u
.tex
.last_layer
;
528 surface
->base
.u
.tex
.level
= level
;
530 surface
->aligned_height
= r600_texture_get_nblocksy(pipe
->screen
,
532 return &surface
->base
;
535 static void r600_surface_destroy(struct pipe_context
*pipe
,
536 struct pipe_surface
*surface
)
538 pipe_resource_reference(&surface
->texture
, NULL
);
542 struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
543 const struct pipe_resource
*templ
,
544 struct winsys_handle
*whandle
)
546 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
547 struct pb_buffer
*buf
= NULL
;
549 unsigned array_mode
= 0;
550 enum radeon_bo_layout micro
, macro
;
552 /* Support only 2D textures without mipmaps */
553 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
554 templ
->depth0
!= 1 || templ
->last_level
!= 0)
557 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
);
561 rscreen
->ws
->buffer_get_tiling(buf
, µ
, ¯o
);
563 if (macro
== RADEON_LAYOUT_TILED
)
564 array_mode
= V_0280A0_ARRAY_2D_TILED_THIN1
;
565 else if (micro
== RADEON_LAYOUT_TILED
)
566 array_mode
= V_0280A0_ARRAY_1D_TILED_THIN1
;
570 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
, array_mode
,
571 stride
, 0, buf
, FALSE
);
574 int r600_texture_depth_flush(struct pipe_context
*ctx
,
575 struct pipe_resource
*texture
, boolean just_create
)
577 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
578 struct pipe_resource resource
;
580 if (rtex
->flushed_depth_texture
)
583 resource
.target
= texture
->target
;
584 resource
.format
= texture
->format
;
585 resource
.width0
= texture
->width0
;
586 resource
.height0
= texture
->height0
;
587 resource
.depth0
= texture
->depth0
;
588 resource
.array_size
= texture
->array_size
;
589 resource
.last_level
= texture
->last_level
;
590 resource
.nr_samples
= texture
->nr_samples
;
591 resource
.usage
= PIPE_USAGE_DYNAMIC
;
592 resource
.bind
= texture
->bind
| PIPE_BIND_DEPTH_STENCIL
;
593 resource
.flags
= R600_RESOURCE_FLAG_TRANSFER
| texture
->flags
;
595 rtex
->flushed_depth_texture
= (struct r600_resource_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
596 if (rtex
->flushed_depth_texture
== NULL
) {
597 R600_ERR("failed to create temporary texture to hold untiled copy\n");
601 ((struct r600_resource_texture
*)rtex
->flushed_depth_texture
)->is_flushing_texture
= TRUE
;
606 /* XXX: only do this if the depth texture has actually changed:
608 r600_blit_uncompress_depth(ctx
, rtex
);
612 /* Needs adjustment for pixelformat:
614 static INLINE
unsigned u_box_volume( const struct pipe_box
*box
)
616 return box
->width
* box
->depth
* box
->height
;
619 struct pipe_transfer
* r600_texture_get_transfer(struct pipe_context
*ctx
,
620 struct pipe_resource
*texture
,
623 const struct pipe_box
*box
)
625 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
626 struct pipe_resource resource
;
627 struct r600_transfer
*trans
;
629 boolean use_staging_texture
= FALSE
;
631 /* We cannot map a tiled texture directly because the data is
632 * in a different order, therefore we do detiling using a blit.
634 * Also, use a temporary in GTT memory for read transfers, as
635 * the CPU is much happier reading out of cached system memory
636 * than uncached VRAM.
638 if (R600_TEX_IS_TILED(rtex
, level
))
639 use_staging_texture
= TRUE
;
641 if ((usage
& PIPE_TRANSFER_READ
) && u_box_volume(box
) > 1024)
642 use_staging_texture
= TRUE
;
644 /* XXX: Use a staging texture for uploads if the underlying BO
645 * is busy. No interface for checking that currently? so do
646 * it eagerly whenever the transfer doesn't require a readback
649 if ((usage
& PIPE_TRANSFER_WRITE
) &&
650 !(usage
& (PIPE_TRANSFER_READ
|
651 PIPE_TRANSFER_DONTBLOCK
|
652 PIPE_TRANSFER_UNSYNCHRONIZED
)))
653 use_staging_texture
= TRUE
;
655 if (!permit_hardware_blit(ctx
->screen
, texture
) ||
656 (texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
))
657 use_staging_texture
= FALSE
;
659 if (use_staging_texture
&& (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
662 trans
= CALLOC_STRUCT(r600_transfer
);
665 pipe_resource_reference(&trans
->transfer
.resource
, texture
);
666 trans
->transfer
.level
= level
;
667 trans
->transfer
.usage
= usage
;
668 trans
->transfer
.box
= *box
;
670 /* XXX: only readback the rectangle which is being mapped?
672 /* XXX: when discard is true, no need to read back from depth texture
674 r
= r600_texture_depth_flush(ctx
, texture
, FALSE
);
676 R600_ERR("failed to create temporary texture to hold untiled copy\n");
677 pipe_resource_reference(&trans
->transfer
.resource
, NULL
);
681 trans
->transfer
.stride
= rtex
->flushed_depth_texture
->pitch_in_bytes
[level
];
682 trans
->offset
= r600_texture_get_offset(rtex
->flushed_depth_texture
, level
, box
->z
);
683 return &trans
->transfer
;
684 } else if (use_staging_texture
) {
685 resource
.target
= PIPE_TEXTURE_2D
;
686 resource
.format
= texture
->format
;
687 resource
.width0
= box
->width
;
688 resource
.height0
= box
->height
;
690 resource
.array_size
= 1;
691 resource
.last_level
= 0;
692 resource
.nr_samples
= 0;
693 resource
.usage
= PIPE_USAGE_STAGING
;
695 resource
.flags
= R600_RESOURCE_FLAG_TRANSFER
;
696 /* For texture reading, the temporary (detiled) texture is used as
697 * a render target when blitting from a tiled texture. */
698 if (usage
& PIPE_TRANSFER_READ
) {
699 resource
.bind
|= PIPE_BIND_RENDER_TARGET
;
701 /* For texture writing, the temporary texture is used as a sampler
702 * when blitting into a tiled texture. */
703 if (usage
& PIPE_TRANSFER_WRITE
) {
704 resource
.bind
|= PIPE_BIND_SAMPLER_VIEW
;
706 /* Create the temporary texture. */
707 trans
->staging_texture
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
708 if (trans
->staging_texture
== NULL
) {
709 R600_ERR("failed to create temporary texture to hold untiled copy\n");
710 pipe_resource_reference(&trans
->transfer
.resource
, NULL
);
715 trans
->transfer
.stride
=
716 ((struct r600_resource_texture
*)trans
->staging_texture
)->pitch_in_bytes
[0];
717 if (usage
& PIPE_TRANSFER_READ
) {
718 r600_copy_to_staging_texture(ctx
, trans
);
719 /* Always referenced in the blit. */
720 r600_flush(ctx
, NULL
, 0);
722 return &trans
->transfer
;
724 trans
->transfer
.stride
= rtex
->pitch_in_bytes
[level
];
725 trans
->transfer
.layer_stride
= rtex
->layer_size
[level
];
726 trans
->offset
= r600_texture_get_offset(rtex
, level
, box
->z
);
727 return &trans
->transfer
;
730 void r600_texture_transfer_destroy(struct pipe_context
*ctx
,
731 struct pipe_transfer
*transfer
)
733 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
734 struct pipe_resource
*texture
= transfer
->resource
;
735 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
737 if (rtransfer
->staging_texture
) {
738 if (transfer
->usage
& PIPE_TRANSFER_WRITE
) {
739 r600_copy_from_staging_texture(ctx
, rtransfer
);
741 pipe_resource_reference(&rtransfer
->staging_texture
, NULL
);
744 if (rtex
->depth
&& !rtex
->is_flushing_texture
) {
745 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtex
->flushed_depth_texture
)
746 r600_blit_push_depth(ctx
, rtex
);
749 pipe_resource_reference(&transfer
->resource
, NULL
);
753 void* r600_texture_transfer_map(struct pipe_context
*ctx
,
754 struct pipe_transfer
* transfer
)
756 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
757 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
758 struct pb_buffer
*buf
;
759 enum pipe_format format
= transfer
->resource
->format
;
763 if (rtransfer
->staging_texture
) {
764 buf
= ((struct r600_resource
*)rtransfer
->staging_texture
)->buf
;
766 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)transfer
->resource
;
768 if (rtex
->flushed_depth_texture
)
769 buf
= ((struct r600_resource
*)rtex
->flushed_depth_texture
)->buf
;
771 buf
= ((struct r600_resource
*)transfer
->resource
)->buf
;
773 offset
= rtransfer
->offset
+
774 transfer
->box
.y
/ util_format_get_blockheight(format
) * transfer
->stride
+
775 transfer
->box
.x
/ util_format_get_blockwidth(format
) * util_format_get_blocksize(format
);
778 if (!(map
= rctx
->ws
->buffer_map(buf
, rctx
->ctx
.cs
, transfer
->usage
))) {
785 void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
786 struct pipe_transfer
* transfer
)
788 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
789 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
790 struct pb_buffer
*buf
;
792 if (rtransfer
->staging_texture
) {
793 buf
= ((struct r600_resource
*)rtransfer
->staging_texture
)->buf
;
795 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)transfer
->resource
;
797 if (rtex
->flushed_depth_texture
) {
798 buf
= ((struct r600_resource
*)rtex
->flushed_depth_texture
)->buf
;
800 buf
= ((struct r600_resource
*)transfer
->resource
)->buf
;
803 rctx
->ws
->buffer_unmap(buf
);
806 void r600_init_surface_functions(struct r600_pipe_context
*r600
)
808 r600
->context
.create_surface
= r600_create_surface
;
809 r600
->context
.surface_destroy
= r600_surface_destroy
;
812 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
813 const unsigned char *swizzle_view
)
816 unsigned char swizzle
[4];
818 const uint32_t swizzle_shift
[4] = {
821 const uint32_t swizzle_bit
[4] = {
826 util_format_compose_swizzles(swizzle_format
, swizzle_view
, swizzle
);
828 memcpy(swizzle
, swizzle_format
, 4);
832 for (i
= 0; i
< 4; i
++) {
833 switch (swizzle
[i
]) {
834 case UTIL_FORMAT_SWIZZLE_Y
:
835 result
|= swizzle_bit
[1] << swizzle_shift
[i
];
837 case UTIL_FORMAT_SWIZZLE_Z
:
838 result
|= swizzle_bit
[2] << swizzle_shift
[i
];
840 case UTIL_FORMAT_SWIZZLE_W
:
841 result
|= swizzle_bit
[3] << swizzle_shift
[i
];
843 case UTIL_FORMAT_SWIZZLE_0
:
844 result
|= V_038010_SQ_SEL_0
<< swizzle_shift
[i
];
846 case UTIL_FORMAT_SWIZZLE_1
:
847 result
|= V_038010_SQ_SEL_1
<< swizzle_shift
[i
];
849 default: /* UTIL_FORMAT_SWIZZLE_X */
850 result
|= swizzle_bit
[0] << swizzle_shift
[i
];
856 /* texture format translate */
857 uint32_t r600_translate_texformat(struct pipe_screen
*screen
,
858 enum pipe_format format
,
859 const unsigned char *swizzle_view
,
860 uint32_t *word4_p
, uint32_t *yuv_format_p
)
862 uint32_t result
= 0, word4
= 0, yuv_format
= 0;
863 const struct util_format_description
*desc
;
864 boolean uniform
= TRUE
;
865 static int r600_enable_s3tc
= -1;
868 const uint32_t sign_bit
[4] = {
869 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED
),
870 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED
),
871 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED
),
872 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED
)
874 desc
= util_format_description(format
);
876 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
);
878 /* Colorspace (return non-RGB formats directly). */
879 switch (desc
->colorspace
) {
880 /* Depth stencil formats */
881 case UTIL_FORMAT_COLORSPACE_ZS
:
883 case PIPE_FORMAT_Z16_UNORM
:
886 case PIPE_FORMAT_X24S8_UINT
:
887 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
888 case PIPE_FORMAT_Z24X8_UNORM
:
889 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
892 case PIPE_FORMAT_S8X24_UINT
:
893 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
894 case PIPE_FORMAT_X8Z24_UNORM
:
895 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
898 case PIPE_FORMAT_S8_UINT
:
900 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
902 case PIPE_FORMAT_Z32_FLOAT
:
903 result
= FMT_32_FLOAT
;
905 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
906 result
= FMT_X24_8_32_FLOAT
;
912 case UTIL_FORMAT_COLORSPACE_YUV
:
913 yuv_format
|= (1 << 30);
915 case PIPE_FORMAT_UYVY
:
916 case PIPE_FORMAT_YUYV
:
920 goto out_unknown
; /* TODO */
922 case UTIL_FORMAT_COLORSPACE_SRGB
:
923 word4
|= S_038010_FORCE_DEGAMMA(1);
930 if (r600_enable_s3tc
== -1) {
931 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
932 if (rscreen
->info
.drm_minor
>= 9)
933 r600_enable_s3tc
= 1;
935 r600_enable_s3tc
= debug_get_bool_option("R600_ENABLE_S3TC", FALSE
);
938 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
939 if (!r600_enable_s3tc
)
943 case PIPE_FORMAT_RGTC1_SNORM
:
944 case PIPE_FORMAT_LATC1_SNORM
:
945 word4
|= sign_bit
[0];
946 case PIPE_FORMAT_RGTC1_UNORM
:
947 case PIPE_FORMAT_LATC1_UNORM
:
950 case PIPE_FORMAT_RGTC2_SNORM
:
951 case PIPE_FORMAT_LATC2_SNORM
:
952 word4
|= sign_bit
[0] | sign_bit
[1];
953 case PIPE_FORMAT_RGTC2_UNORM
:
954 case PIPE_FORMAT_LATC2_UNORM
:
962 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
964 if (!r600_enable_s3tc
)
967 if (!util_format_s3tc_enabled
) {
972 case PIPE_FORMAT_DXT1_RGB
:
973 case PIPE_FORMAT_DXT1_RGBA
:
974 case PIPE_FORMAT_DXT1_SRGB
:
975 case PIPE_FORMAT_DXT1_SRGBA
:
978 case PIPE_FORMAT_DXT3_RGBA
:
979 case PIPE_FORMAT_DXT3_SRGBA
:
982 case PIPE_FORMAT_DXT5_RGBA
:
983 case PIPE_FORMAT_DXT5_SRGBA
:
991 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
992 result
= FMT_5_9_9_9_SHAREDEXP
;
994 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
995 result
= FMT_10_11_11_FLOAT
;
1000 for (i
= 0; i
< desc
->nr_channels
; i
++) {
1001 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1002 word4
|= sign_bit
[i
];
1006 /* R8G8Bx_SNORM - TODO CxV8U8 */
1008 /* See whether the components are of the same size. */
1009 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1010 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1013 /* Non-uniform formats. */
1015 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
1016 desc
->channel
[0].pure_integer
)
1017 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1018 switch(desc
->nr_channels
) {
1020 if (desc
->channel
[0].size
== 5 &&
1021 desc
->channel
[1].size
== 6 &&
1022 desc
->channel
[2].size
== 5) {
1028 if (desc
->channel
[0].size
== 5 &&
1029 desc
->channel
[1].size
== 5 &&
1030 desc
->channel
[2].size
== 5 &&
1031 desc
->channel
[3].size
== 1) {
1032 result
= FMT_1_5_5_5
;
1035 if (desc
->channel
[0].size
== 10 &&
1036 desc
->channel
[1].size
== 10 &&
1037 desc
->channel
[2].size
== 10 &&
1038 desc
->channel
[3].size
== 2) {
1039 result
= FMT_2_10_10_10
;
1047 /* Find the first non-VOID channel. */
1048 for (i
= 0; i
< 4; i
++) {
1049 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1057 /* uniform formats */
1058 switch (desc
->channel
[i
].type
) {
1059 case UTIL_FORMAT_TYPE_UNSIGNED
:
1060 case UTIL_FORMAT_TYPE_SIGNED
:
1062 if (!desc
->channel
[i
].normalized
&&
1063 desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
) {
1067 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
1068 desc
->channel
[i
].pure_integer
)
1069 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1071 switch (desc
->channel
[i
].size
) {
1073 switch (desc
->nr_channels
) {
1078 result
= FMT_4_4_4_4
;
1083 switch (desc
->nr_channels
) {
1091 result
= FMT_8_8_8_8
;
1096 switch (desc
->nr_channels
) {
1104 result
= FMT_16_16_16_16
;
1109 switch (desc
->nr_channels
) {
1117 result
= FMT_32_32_32_32
;
1123 case UTIL_FORMAT_TYPE_FLOAT
:
1124 switch (desc
->channel
[i
].size
) {
1126 switch (desc
->nr_channels
) {
1128 result
= FMT_16_FLOAT
;
1131 result
= FMT_16_16_FLOAT
;
1134 result
= FMT_16_16_16_16_FLOAT
;
1139 switch (desc
->nr_channels
) {
1141 result
= FMT_32_FLOAT
;
1144 result
= FMT_32_32_FLOAT
;
1147 result
= FMT_32_32_32_32_FLOAT
;
1158 *yuv_format_p
= yuv_format
;
1161 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */