2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include <pipe/p_screen.h>
29 #include <util/u_format.h>
30 #include <util/u_math.h>
31 #include <util/u_inlines.h>
32 #include <util/u_memory.h>
33 #include "state_tracker/drm_driver.h"
34 #include "r600_screen.h"
35 #include "r600_context.h"
36 #include "r600_resource.h"
37 #include "r600_state_inlines.h"
40 extern struct u_resource_vtbl r600_texture_vtbl
;
42 /* Copy from a tiled texture to a detiled one. */
43 static void r600_copy_from_tiled_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
45 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
46 struct pipe_resource
*texture
= transfer
->resource
;
47 struct pipe_subresource subdst
;
51 ctx
->resource_copy_region(ctx
, rtransfer
->linear_texture
,
52 subdst
, 0, 0, 0, texture
, transfer
->sr
,
53 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
54 transfer
->box
.width
, transfer
->box
.height
);
57 static unsigned long r600_texture_get_offset(struct r600_resource_texture
*rtex
,
58 unsigned level
, unsigned zslice
,
61 unsigned long offset
= rtex
->offset
[level
];
63 switch (rtex
->resource
.base
.b
.target
) {
66 return offset
+ zslice
* rtex
->layer_size
[level
];
67 case PIPE_TEXTURE_CUBE
:
69 return offset
+ face
* rtex
->layer_size
[level
];
71 assert(zslice
== 0 && face
== 0);
76 static void r600_setup_miptree(struct r600_screen
*rscreen
, struct r600_resource_texture
*rtex
)
78 struct pipe_resource
*ptex
= &rtex
->resource
.base
.b
;
79 unsigned long w
, h
, pitch
, size
, layer_size
, i
, offset
;
81 rtex
->bpt
= util_format_get_blocksize(ptex
->format
);
82 for (i
= 0, offset
= 0; i
<= ptex
->last_level
; i
++) {
83 w
= u_minify(ptex
->width0
, i
);
84 h
= u_minify(ptex
->height0
, i
);
85 h
= util_next_power_of_two(h
);
86 pitch
= util_format_get_stride(ptex
->format
, align(w
, 64));
87 pitch
= align(pitch
, 256);
88 layer_size
= pitch
* h
;
89 if (ptex
->target
== PIPE_TEXTURE_CUBE
)
90 size
= layer_size
* 6;
92 size
= layer_size
* u_minify(ptex
->depth0
, i
);
93 rtex
->offset
[i
] = offset
;
94 rtex
->layer_size
[i
] = layer_size
;
95 rtex
->pitch
[i
] = pitch
;
103 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
104 const struct pipe_resource
*templ
)
106 struct r600_resource_texture
*rtex
;
107 struct r600_resource
*resource
;
108 struct r600_screen
*rscreen
= r600_screen(screen
);
110 rtex
= CALLOC_STRUCT(r600_resource_texture
);
114 resource
= &rtex
->resource
;
115 resource
->base
.b
= *templ
;
116 resource
->base
.vtbl
= &r600_texture_vtbl
;
117 pipe_reference_init(&resource
->base
.b
.reference
, 1);
118 resource
->base
.b
.screen
= screen
;
119 r600_setup_miptree(rscreen
, rtex
);
121 /* FIXME alignment 4096 enought ? too much ? */
122 resource
->domain
= r600_domain_from_usage(resource
->base
.b
.bind
);
123 resource
->bo
= radeon_bo(rscreen
->rw
, 0, rtex
->size
, 4096, NULL
);
124 if (resource
->bo
== NULL
) {
128 return &resource
->base
.b
;
131 static void r600_texture_destroy_state(struct pipe_resource
*ptexture
)
133 struct r600_resource_texture
*rtexture
= (struct r600_resource_texture
*)ptexture
;
135 for (int i
= 0; i
< PIPE_MAX_TEXTURE_LEVELS
; i
++) {
136 radeon_state_fini(&rtexture
->scissor
[i
]);
137 radeon_state_fini(&rtexture
->db
[i
]);
138 for (int j
= 0; j
< 8; j
++) {
139 radeon_state_fini(&rtexture
->cb
[j
][i
]);
144 static void r600_texture_destroy(struct pipe_screen
*screen
,
145 struct pipe_resource
*ptex
)
147 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)ptex
;
148 struct r600_resource
*resource
= &rtex
->resource
;
149 struct r600_screen
*rscreen
= r600_screen(screen
);
152 radeon_bo_decref(rscreen
->rw
, resource
->bo
);
154 if (rtex
->uncompressed
) {
155 radeon_bo_decref(rscreen
->rw
, rtex
->uncompressed
);
157 r600_texture_destroy_state(ptex
);
161 static struct pipe_surface
*r600_get_tex_surface(struct pipe_screen
*screen
,
162 struct pipe_resource
*texture
,
163 unsigned face
, unsigned level
,
164 unsigned zslice
, unsigned flags
)
166 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
167 struct pipe_surface
*surface
= CALLOC_STRUCT(pipe_surface
);
168 unsigned long offset
;
172 offset
= r600_texture_get_offset(rtex
, level
, zslice
, face
);
173 pipe_reference_init(&surface
->reference
, 1);
174 pipe_resource_reference(&surface
->texture
, texture
);
175 surface
->format
= texture
->format
;
176 surface
->width
= u_minify(texture
->width0
, level
);
177 surface
->height
= u_minify(texture
->height0
, level
);
178 surface
->offset
= offset
;
179 surface
->usage
= flags
;
180 surface
->zslice
= zslice
;
181 surface
->texture
= texture
;
182 surface
->face
= face
;
183 surface
->level
= level
;
187 static void r600_tex_surface_destroy(struct pipe_surface
*surface
)
189 pipe_resource_reference(&surface
->texture
, NULL
);
193 struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
194 const struct pipe_resource
*templ
,
195 struct winsys_handle
*whandle
)
197 struct radeon
*rw
= (struct radeon
*)screen
->winsys
;
198 struct r600_resource_texture
*rtex
;
199 struct r600_resource
*resource
;
200 struct radeon_bo
*bo
= NULL
;
202 /* Support only 2D textures without mipmaps */
203 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
204 templ
->depth0
!= 1 || templ
->last_level
!= 0)
207 rtex
= CALLOC_STRUCT(r600_resource_texture
);
211 bo
= radeon_bo(rw
, whandle
->handle
, 0, 0, NULL
);
217 resource
= &rtex
->resource
;
218 resource
->base
.b
= *templ
;
219 resource
->base
.vtbl
= &r600_texture_vtbl
;
220 pipe_reference_init(&resource
->base
.b
.reference
, 1);
221 resource
->base
.b
.screen
= screen
;
224 rtex
->pitch_override
= whandle
->stride
;
225 rtex
->bpt
= util_format_get_blocksize(templ
->format
);
226 rtex
->pitch
[0] = whandle
->stride
;
227 rtex
->width
[0] = templ
->width0
;
228 rtex
->height
[0] = templ
->height0
;
230 rtex
->size
= align(rtex
->pitch
[0] * templ
->height0
, 64);
232 return &resource
->base
.b
;
235 static unsigned int r600_texture_is_referenced(struct pipe_context
*context
,
236 struct pipe_resource
*texture
,
237 unsigned face
, unsigned level
)
240 return PIPE_REFERENCED_FOR_READ
| PIPE_REFERENCED_FOR_WRITE
;
243 struct pipe_transfer
* r600_texture_get_transfer(struct pipe_context
*ctx
,
244 struct pipe_resource
*texture
,
245 struct pipe_subresource sr
,
247 const struct pipe_box
*box
)
249 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
250 struct pipe_resource resource
;
251 struct r600_transfer
*trans
;
253 trans
= CALLOC_STRUCT(r600_transfer
);
256 pipe_resource_reference(&trans
->transfer
.resource
, texture
);
257 trans
->transfer
.sr
= sr
;
258 trans
->transfer
.usage
= usage
;
259 trans
->transfer
.box
= *box
;
260 trans
->transfer
.stride
= rtex
->pitch
[sr
.level
];
261 trans
->offset
= r600_texture_get_offset(rtex
, sr
.level
, box
->z
, sr
.face
);
262 if (rtex
->tilled
&& !rtex
->depth
) {
263 resource
.target
= PIPE_TEXTURE_2D
;
264 resource
.format
= texture
->format
;
265 resource
.width0
= box
->width
;
266 resource
.height0
= box
->height
;
268 resource
.last_level
= 0;
269 resource
.nr_samples
= 0;
270 resource
.usage
= PIPE_USAGE_DYNAMIC
;
273 /* For texture reading, the temporary (detiled) texture is used as
274 * a render target when blitting from a tiled texture. */
275 if (usage
& PIPE_TRANSFER_READ
) {
276 resource
.bind
|= PIPE_BIND_RENDER_TARGET
;
278 /* For texture writing, the temporary texture is used as a sampler
279 * when blitting into a tiled texture. */
280 if (usage
& PIPE_TRANSFER_WRITE
) {
281 resource
.bind
|= PIPE_BIND_SAMPLER_VIEW
;
283 /* Create the temporary texture. */
284 trans
->linear_texture
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
285 if (trans
->linear_texture
== NULL
) {
286 R600_ERR("failed to create temporary texture to hold untiled copy\n");
287 pipe_resource_reference(&trans
->transfer
.resource
, NULL
);
291 if (usage
& PIPE_TRANSFER_READ
) {
292 /* We cannot map a tiled texture directly because the data is
293 * in a different order, therefore we do detiling using a blit. */
294 r600_copy_from_tiled_texture(ctx
, trans
);
295 /* Always referenced in the blit. */
296 ctx
->flush(ctx
, 0, NULL
);
299 return &trans
->transfer
;
302 void r600_texture_transfer_destroy(struct pipe_context
*ctx
,
303 struct pipe_transfer
*transfer
)
305 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
307 if (rtransfer
->linear_texture
) {
308 pipe_resource_reference(&rtransfer
->linear_texture
, NULL
);
310 pipe_resource_reference(&transfer
->resource
, NULL
);
314 void* r600_texture_transfer_map(struct pipe_context
*ctx
,
315 struct pipe_transfer
* transfer
)
317 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
318 struct radeon_bo
*bo
;
319 enum pipe_format format
= transfer
->resource
->format
;
320 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
321 struct r600_resource_texture
*rtex
;
322 unsigned long offset
= 0;
326 r600_flush(ctx
, 0, NULL
);
327 if (rtransfer
->linear_texture
) {
328 bo
= ((struct r600_resource
*)rtransfer
->linear_texture
)->bo
;
330 rtex
= (struct r600_resource_texture
*)transfer
->resource
;
332 r
= r600_texture_from_depth(ctx
, rtex
, transfer
->sr
.level
);
336 r600_flush(ctx
, 0, NULL
);
337 bo
= rtex
->uncompressed
;
339 bo
= ((struct r600_resource
*)transfer
->resource
)->bo
;
341 offset
= rtransfer
->offset
+
342 transfer
->box
.y
/ util_format_get_blockheight(format
) * transfer
->stride
+
343 transfer
->box
.x
/ util_format_get_blockwidth(format
) * util_format_get_blocksize(format
);
345 if (radeon_bo_map(rscreen
->rw
, bo
)) {
348 radeon_bo_wait(rscreen
->rw
, bo
);
354 void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
355 struct pipe_transfer
* transfer
)
357 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
358 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
359 struct r600_resource_texture
*rtex
;
360 struct radeon_bo
*bo
;
362 if (rtransfer
->linear_texture
) {
363 bo
= ((struct r600_resource
*)rtransfer
->linear_texture
)->bo
;
365 rtex
= (struct r600_resource_texture
*)transfer
->resource
;
367 bo
= rtex
->uncompressed
;
369 bo
= ((struct r600_resource
*)transfer
->resource
)->bo
;
372 radeon_bo_unmap(rscreen
->rw
, bo
);
375 struct u_resource_vtbl r600_texture_vtbl
=
377 u_default_resource_get_handle
, /* get_handle */
378 r600_texture_destroy
, /* resource_destroy */
379 r600_texture_is_referenced
, /* is_resource_referenced */
380 r600_texture_get_transfer
, /* get_transfer */
381 r600_texture_transfer_destroy
, /* transfer_destroy */
382 r600_texture_transfer_map
, /* transfer_map */
383 u_default_transfer_flush_region
,/* transfer_flush_region */
384 r600_texture_transfer_unmap
, /* transfer_unmap */
385 u_default_transfer_inline_write
/* transfer_inline_write */
388 void r600_init_screen_texture_functions(struct pipe_screen
*screen
)
390 screen
->get_tex_surface
= r600_get_tex_surface
;
391 screen
->tex_surface_destroy
= r600_tex_surface_destroy
;
394 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
395 const unsigned char *swizzle_view
)
398 unsigned char swizzle
[4];
400 const uint32_t swizzle_shift
[4] = {
403 const uint32_t swizzle_bit
[4] = {
408 /* Combine two sets of swizzles. */
409 for (i
= 0; i
< 4; i
++) {
410 swizzle
[i
] = swizzle_view
[i
] <= UTIL_FORMAT_SWIZZLE_W
?
411 swizzle_format
[swizzle_view
[i
]] : swizzle_view
[i
];
414 memcpy(swizzle
, swizzle_format
, 4);
418 for (i
= 0; i
< 4; i
++) {
419 switch (swizzle
[i
]) {
420 case UTIL_FORMAT_SWIZZLE_Y
:
421 result
|= swizzle_bit
[1] << swizzle_shift
[i
];
423 case UTIL_FORMAT_SWIZZLE_Z
:
424 result
|= swizzle_bit
[2] << swizzle_shift
[i
];
426 case UTIL_FORMAT_SWIZZLE_W
:
427 result
|= swizzle_bit
[3] << swizzle_shift
[i
];
429 case UTIL_FORMAT_SWIZZLE_0
:
430 result
|= V_038010_SQ_SEL_0
<< swizzle_shift
[i
];
432 case UTIL_FORMAT_SWIZZLE_1
:
433 result
|= V_038010_SQ_SEL_1
<< swizzle_shift
[i
];
435 default: /* UTIL_FORMAT_SWIZZLE_X */
436 result
|= swizzle_bit
[0] << swizzle_shift
[i
];
442 /* texture format translate */
443 uint32_t r600_translate_texformat(enum pipe_format format
,
444 const unsigned char *swizzle_view
,
445 uint32_t *word4_p
, uint32_t *yuv_format_p
)
447 uint32_t result
= 0, word4
= 0, yuv_format
= 0;
448 const struct util_format_description
*desc
;
449 boolean uniform
= TRUE
;
451 const uint32_t sign_bit
[4] = {
452 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED
),
453 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED
),
454 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED
),
455 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED
)
457 desc
= util_format_description(format
);
459 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
);
461 /* Colorspace (return non-RGB formats directly). */
462 switch (desc
->colorspace
) {
463 /* Depth stencil formats */
464 case UTIL_FORMAT_COLORSPACE_ZS
:
466 case PIPE_FORMAT_Z16_UNORM
:
467 result
= V_0280A0_COLOR_16
;
469 case PIPE_FORMAT_Z24X8_UNORM
:
470 result
= V_0280A0_COLOR_8_24
;
472 case PIPE_FORMAT_Z24_UNORM_S8_USCALED
:
473 result
= V_0280A0_COLOR_8_24
;
479 case UTIL_FORMAT_COLORSPACE_YUV
:
480 yuv_format
|= (1 << 30);
482 case PIPE_FORMAT_UYVY
:
483 case PIPE_FORMAT_YUYV
:
487 goto out_unknown
; /* TODO */
489 case UTIL_FORMAT_COLORSPACE_SRGB
:
490 word4
|= S_038010_FORCE_DEGAMMA(1);
491 if (format
== PIPE_FORMAT_L8A8_SRGB
|| format
== PIPE_FORMAT_L8_SRGB
)
492 goto out_unknown
; /* fails for some reason - TODO */
499 /* S3TC formats. TODO */
500 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
505 for (i
= 0; i
< desc
->nr_channels
; i
++) {
506 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
507 word4
|= sign_bit
[i
];
511 /* R8G8Bx_SNORM - TODO CxV8U8 */
515 /* See whether the components are of the same size. */
516 for (i
= 1; i
< desc
->nr_channels
; i
++) {
517 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
520 /* Non-uniform formats. */
522 switch(desc
->nr_channels
) {
524 if (desc
->channel
[0].size
== 5 &&
525 desc
->channel
[1].size
== 6 &&
526 desc
->channel
[2].size
== 5) {
527 result
= V_0280A0_COLOR_5_6_5
;
532 if (desc
->channel
[0].size
== 5 &&
533 desc
->channel
[1].size
== 5 &&
534 desc
->channel
[2].size
== 5 &&
535 desc
->channel
[3].size
== 1) {
536 result
= V_0280A0_COLOR_1_5_5_5
;
539 if (desc
->channel
[0].size
== 10 &&
540 desc
->channel
[1].size
== 10 &&
541 desc
->channel
[2].size
== 10 &&
542 desc
->channel
[3].size
== 2) {
543 result
= V_0280A0_COLOR_10_10_10_2
;
551 /* uniform formats */
552 switch (desc
->channel
[0].type
) {
553 case UTIL_FORMAT_TYPE_UNSIGNED
:
554 case UTIL_FORMAT_TYPE_SIGNED
:
555 if (!desc
->channel
[0].normalized
&&
556 desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
) {
560 switch (desc
->channel
[0].size
) {
562 switch (desc
->nr_channels
) {
564 result
= V_0280A0_COLOR_4_4
;
567 result
= V_0280A0_COLOR_4_4_4_4
;
572 switch (desc
->nr_channels
) {
574 result
= V_0280A0_COLOR_8
;
577 result
= V_0280A0_COLOR_8_8
;
580 result
= V_0280A0_COLOR_8_8_8_8
;
585 switch (desc
->nr_channels
) {
587 result
= V_0280A0_COLOR_16
;
590 result
= V_0280A0_COLOR_16_16
;
593 result
= V_0280A0_COLOR_16_16_16_16
;
599 case UTIL_FORMAT_TYPE_FLOAT
:
600 switch (desc
->channel
[0].size
) {
602 switch (desc
->nr_channels
) {
604 result
= V_0280A0_COLOR_16_FLOAT
;
607 result
= V_0280A0_COLOR_16_16_FLOAT
;
610 result
= V_0280A0_COLOR_16_16_16_16_FLOAT
;
615 switch (desc
->nr_channels
) {
617 result
= V_0280A0_COLOR_32_FLOAT
;
620 result
= V_0280A0_COLOR_32_32_FLOAT
;
623 result
= V_0280A0_COLOR_32_32_32_32_FLOAT
;
633 *yuv_format_p
= yuv_format
;
636 // R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format));
640 int r600_texture_from_depth(struct pipe_context
*ctx
, struct r600_resource_texture
*rtexture
, unsigned level
)
642 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
645 if (!rtexture
->depth
) {
646 /* This shouldn't happen maybe print a warning */
649 if (rtexture
->uncompressed
&& !rtexture
->dirty
) {
650 /* Uncompressed bo already in good state */
654 /* allocate uncompressed texture */
655 if (rtexture
->uncompressed
== NULL
) {
656 rtexture
->uncompressed
= radeon_bo(rscreen
->rw
, 0, rtexture
->size
, 4096, NULL
);
657 if (rtexture
->uncompressed
== NULL
) {
662 /* render a rectangle covering whole buffer to uncompress depth */
663 r
= r600_blit_uncompress_depth(ctx
, rtexture
, level
);
672 static void r600_texture_state_scissor(struct r600_screen
*rscreen
,
673 struct r600_resource_texture
*rtexture
,
676 struct radeon_state
*rstate
= &rtexture
->scissor
[level
];
678 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_SCISSOR
, 0, 0);
679 /* set states (most default value are 0 and struct already
680 * initialized to 0, thus avoid resetting them)
682 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_0_BR
] = S_028244_BR_X(rtexture
->width
[level
]) | S_028244_BR_Y(rtexture
->height
[level
]);
683 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_0_TL
] = 0x80000000;
684 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_1_BR
] = S_028244_BR_X(rtexture
->width
[level
]) | S_028244_BR_Y(rtexture
->height
[level
]);
685 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_1_TL
] = 0x80000000;
686 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_2_BR
] = S_028244_BR_X(rtexture
->width
[level
]) | S_028244_BR_Y(rtexture
->height
[level
]);
687 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_2_TL
] = 0x80000000;
688 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_3_BR
] = S_028244_BR_X(rtexture
->width
[level
]) | S_028244_BR_Y(rtexture
->height
[level
]);
689 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_3_TL
] = 0x80000000;
690 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_RULE
] = 0x0000FFFF;
691 rstate
->states
[R600_SCISSOR__PA_SC_EDGERULE
] = 0xAAAAAAAA;
692 rstate
->states
[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR
] = S_028244_BR_X(rtexture
->width
[level
]) | S_028244_BR_Y(rtexture
->height
[level
]);
693 rstate
->states
[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL
] = 0x80000000;
694 rstate
->states
[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR
] = S_028244_BR_X(rtexture
->width
[level
]) | S_028244_BR_Y(rtexture
->height
[level
]);
695 rstate
->states
[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL
] = 0x80000000;
696 rstate
->states
[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR
] = S_028244_BR_X(rtexture
->width
[level
]) | S_028244_BR_Y(rtexture
->height
[level
]);
697 rstate
->states
[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL
] = 0x80000000;
698 rstate
->states
[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR
] = S_028244_BR_X(rtexture
->width
[level
]) | S_028244_BR_Y(rtexture
->height
[level
]);
699 rstate
->states
[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL
] = 0x80000000;
701 radeon_state_pm4(rstate
);
704 static void r600_texture_state_cb(struct r600_screen
*rscreen
, struct r600_resource_texture
*rtexture
, unsigned cb
, unsigned level
)
706 struct radeon_state
*rstate
;
707 struct r600_resource
*rbuffer
;
708 unsigned pitch
, slice
;
710 unsigned format
, swap
, ntype
;
711 const struct util_format_description
*desc
;
713 rstate
= &rtexture
->cb
[cb
][level
];
714 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_CB0
+ cb
, 0, 0);
715 rbuffer
= &rtexture
->resource
;
717 /* set states (most default value are 0 and struct already
718 * initialized to 0, thus avoid resetting them)
720 pitch
= (rtexture
->pitch
[level
] / rtexture
->bpt
) / 8 - 1;
721 slice
= (rtexture
->pitch
[level
] / rtexture
->bpt
) * rtexture
->height
[level
] / 64 - 1;
723 desc
= util_format_description(rbuffer
->base
.b
.format
);
724 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
725 ntype
= V_0280A0_NUMBER_SRGB
;
726 format
= r600_translate_colorformat(rtexture
->resource
.base
.b
.format
);
727 swap
= r600_translate_colorswap(rtexture
->resource
.base
.b
.format
);
728 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
729 rstate
->bo
[0] = radeon_bo_incref(rscreen
->rw
, rtexture
->uncompressed
);
730 rstate
->bo
[1] = radeon_bo_incref(rscreen
->rw
, rtexture
->uncompressed
);
731 rstate
->bo
[2] = radeon_bo_incref(rscreen
->rw
, rtexture
->uncompressed
);
732 rstate
->placement
[0] = RADEON_GEM_DOMAIN_GTT
;
733 rstate
->placement
[2] = RADEON_GEM_DOMAIN_GTT
;
734 rstate
->placement
[4] = RADEON_GEM_DOMAIN_GTT
;
738 rstate
->bo
[0] = radeon_bo_incref(rscreen
->rw
, rbuffer
->bo
);
739 rstate
->bo
[1] = radeon_bo_incref(rscreen
->rw
, rbuffer
->bo
);
740 rstate
->bo
[2] = radeon_bo_incref(rscreen
->rw
, rbuffer
->bo
);
741 rstate
->placement
[0] = RADEON_GEM_DOMAIN_GTT
;
742 rstate
->placement
[2] = RADEON_GEM_DOMAIN_GTT
;
743 rstate
->placement
[4] = RADEON_GEM_DOMAIN_GTT
;
745 color_info
= S_0280A0_SOURCE_FORMAT(1);
747 color_info
|= S_0280A0_FORMAT(format
) |
748 S_0280A0_COMP_SWAP(swap
) |
749 S_0280A0_BLEND_CLAMP(1) |
750 S_0280A0_NUMBER_TYPE(ntype
);
751 rstate
->states
[R600_CB0__CB_COLOR0_BASE
] = rtexture
->offset
[level
] >> 8;
752 rstate
->states
[R600_CB0__CB_COLOR0_INFO
] = color_info
;
753 rstate
->states
[R600_CB0__CB_COLOR0_SIZE
] = S_028060_PITCH_TILE_MAX(pitch
) |
754 S_028060_SLICE_TILE_MAX(slice
);
756 radeon_state_pm4(rstate
);
759 static void r600_texture_state_db(struct r600_screen
*rscreen
, struct r600_resource_texture
*rtexture
, unsigned level
)
761 struct radeon_state
*rstate
= &rtexture
->db
[level
];
762 struct r600_resource
*rbuffer
;
763 unsigned pitch
, slice
, format
;
765 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_DB
, 0, 0);
766 rbuffer
= &rtexture
->resource
;
767 rtexture
->tilled
= 1;
768 rtexture
->array_mode
= 2;
769 rtexture
->tile_type
= 1;
772 /* set states (most default value are 0 and struct already
773 * initialized to 0, thus avoid resetting them)
775 pitch
= (rtexture
->pitch
[level
] / rtexture
->bpt
) / 8 - 1;
776 slice
= (rtexture
->pitch
[level
] / rtexture
->bpt
) * rtexture
->height
[level
] / 64 - 1;
777 format
= r600_translate_dbformat(rbuffer
->base
.b
.format
);
778 rstate
->states
[R600_DB__DB_DEPTH_BASE
] = rtexture
->offset
[level
] >> 8;
779 rstate
->states
[R600_DB__DB_DEPTH_INFO
] = S_028010_ARRAY_MODE(rtexture
->array_mode
) |
780 S_028010_FORMAT(format
);
781 rstate
->states
[R600_DB__DB_DEPTH_VIEW
] = 0x00000000;
782 rstate
->states
[R600_DB__DB_PREFETCH_LIMIT
] = (rtexture
->height
[level
] / 8) -1;
783 rstate
->states
[R600_DB__DB_DEPTH_SIZE
] = S_028000_PITCH_TILE_MAX(pitch
) |
784 S_028000_SLICE_TILE_MAX(slice
);
785 rstate
->bo
[0] = radeon_bo_incref(rscreen
->rw
, rbuffer
->bo
);
786 rstate
->placement
[0] = RADEON_GEM_DOMAIN_GTT
;
789 radeon_state_pm4(rstate
);
792 int r600_texture_scissor(struct pipe_context
*ctx
, struct r600_resource_texture
*rtexture
, unsigned level
)
794 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
796 if (!rtexture
->scissor
[level
].cpm4
) {
797 r600_texture_state_scissor(rscreen
, rtexture
, level
);
802 static void r600_texture_state_viewport(struct r600_screen
*rscreen
, struct r600_resource_texture
*rtexture
, unsigned level
)
804 struct radeon_state
*rstate
= &rtexture
->viewport
[level
];
806 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_VIEWPORT
, 0, 0);
808 /* set states (most default value are 0 and struct already
809 * initialized to 0, thus avoid resetting them)
811 rstate
->states
[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0
] = fui((float)rtexture
->width
[level
]/2.0);
812 rstate
->states
[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0
] = fui((float)rtexture
->width
[level
]/2.0);
813 rstate
->states
[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0
] = fui((float)rtexture
->height
[level
]/2.0);
814 rstate
->states
[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0
] = fui((float)-rtexture
->height
[level
]/2.0);
815 rstate
->states
[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0
] = 0x3F000000;
816 rstate
->states
[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0
] = 0x3F000000;
817 rstate
->states
[R600_VIEWPORT__PA_CL_VTE_CNTL
] = 0x0000043F;
818 rstate
->states
[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0
] = 0x3F800000;
820 radeon_state_pm4(rstate
);
823 int r600_texture_cb(struct pipe_context
*ctx
, struct r600_resource_texture
*rtexture
, unsigned cb
, unsigned level
)
825 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
827 if (!rtexture
->cb
[cb
][level
].cpm4
) {
828 r600_texture_state_cb(rscreen
, rtexture
, cb
, level
);
833 int r600_texture_db(struct pipe_context
*ctx
, struct r600_resource_texture
*rtexture
, unsigned level
)
835 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
837 if (!rtexture
->db
[level
].cpm4
) {
838 r600_texture_state_db(rscreen
, rtexture
, level
);
843 int r600_texture_viewport(struct pipe_context
*ctx
, struct r600_resource_texture
*rtexture
, unsigned level
)
845 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
847 if (!rtexture
->viewport
[level
].cpm4
) {
848 r600_texture_state_viewport(rscreen
, rtexture
, level
);