2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "r600_formats.h"
28 #include "evergreen_compute.h"
32 #include "util/u_format_s3tc.h"
33 #include "util/u_memory.h"
36 /* Copy from a full GPU texture to a transfer's staging one. */
37 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
39 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
40 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
41 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
42 struct pipe_resource
*src
= transfer
->resource
;
44 if (src
->nr_samples
<= 1) {
45 if (!rctx
->screen
->dma_blit(ctx
, dst
, 0, 0, 0, 0,
48 /* async dma could not be use */
49 ctx
->resource_copy_region(ctx
, dst
, 0, 0, 0, 0,
50 src
, transfer
->level
, &transfer
->box
);
53 /* Resolve the resource. */
54 struct pipe_blit_info blit
;
56 memset(&blit
, 0, sizeof(blit
));
57 blit
.src
.resource
= src
;
58 blit
.src
.format
= src
->format
;
59 blit
.src
.level
= transfer
->level
;
60 blit
.src
.box
= transfer
->box
;
61 blit
.dst
.resource
= dst
;
62 blit
.dst
.format
= dst
->format
;
63 blit
.dst
.box
.width
= transfer
->box
.width
;
64 blit
.dst
.box
.height
= transfer
->box
.height
;
65 blit
.dst
.box
.depth
= transfer
->box
.depth
;
66 blit
.mask
= PIPE_MASK_RGBA
;
67 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
69 ctx
->blit(ctx
, &blit
);
73 /* Copy from a transfer's staging texture to a full GPU one. */
74 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
76 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
77 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
78 struct pipe_resource
*texture
= transfer
->resource
;
81 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
83 if (!rctx
->screen
->dma_blit(ctx
, texture
, transfer
->level
,
84 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
85 &rtransfer
->staging
->b
.b
, 0, &sbox
)) {
86 /* async dma could not be use */
87 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
88 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
89 &rtransfer
->staging
->b
.b
,
94 unsigned r600_texture_get_offset(struct r600_texture
*rtex
,
95 unsigned level
, unsigned layer
)
97 return rtex
->surface
.level
[level
].offset
+
98 layer
* rtex
->surface
.level
[level
].slice_size
;
101 static int r600_init_surface(struct r600_screen
*rscreen
,
102 struct radeon_surface
*surface
,
103 const struct pipe_resource
*ptex
,
105 bool is_flushed_depth
)
107 const struct util_format_description
*desc
=
108 util_format_description(ptex
->format
);
109 bool is_depth
, is_stencil
;
111 is_depth
= util_format_has_depth(desc
);
112 is_stencil
= util_format_has_stencil(desc
);
114 surface
->npix_x
= ptex
->width0
;
115 surface
->npix_y
= ptex
->height0
;
116 surface
->npix_z
= ptex
->depth0
;
117 surface
->blk_w
= util_format_get_blockwidth(ptex
->format
);
118 surface
->blk_h
= util_format_get_blockheight(ptex
->format
);
120 surface
->array_size
= 1;
121 surface
->last_level
= ptex
->last_level
;
123 if (rscreen
->chip_class
>= EVERGREEN
&& !is_flushed_depth
&&
124 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
125 surface
->bpe
= 4; /* stencil is allocated separately on evergreen */
127 surface
->bpe
= util_format_get_blocksize(ptex
->format
);
128 /* align byte per element on dword */
129 if (surface
->bpe
== 3) {
134 surface
->nsamples
= ptex
->nr_samples
? ptex
->nr_samples
: 1;
137 switch (array_mode
) {
138 case V_038000_ARRAY_1D_TILED_THIN1
:
139 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_1D
, MODE
);
141 case V_038000_ARRAY_2D_TILED_THIN1
:
142 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_2D
, MODE
);
144 case V_038000_ARRAY_LINEAR_ALIGNED
:
145 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED
, MODE
);
147 case V_038000_ARRAY_LINEAR_GENERAL
:
149 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR
, MODE
);
152 switch (ptex
->target
) {
153 case PIPE_TEXTURE_1D
:
154 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D
, TYPE
);
156 case PIPE_TEXTURE_RECT
:
157 case PIPE_TEXTURE_2D
:
158 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D
, TYPE
);
160 case PIPE_TEXTURE_3D
:
161 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_3D
, TYPE
);
163 case PIPE_TEXTURE_1D_ARRAY
:
164 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY
, TYPE
);
165 surface
->array_size
= ptex
->array_size
;
167 case PIPE_TEXTURE_2D_ARRAY
:
168 case PIPE_TEXTURE_CUBE_ARRAY
: /* cube array layout like 2d layout for now */
169 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY
, TYPE
);
170 surface
->array_size
= ptex
->array_size
;
172 case PIPE_TEXTURE_CUBE
:
173 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP
, TYPE
);
179 if (ptex
->bind
& PIPE_BIND_SCANOUT
) {
180 surface
->flags
|= RADEON_SURF_SCANOUT
;
183 if (!is_flushed_depth
&& is_depth
) {
184 surface
->flags
|= RADEON_SURF_ZBUFFER
;
187 surface
->flags
|= RADEON_SURF_SBUFFER
|
188 RADEON_SURF_HAS_SBUFFER_MIPTREE
;
194 static int r600_setup_surface(struct pipe_screen
*screen
,
195 struct r600_texture
*rtex
,
196 unsigned pitch_in_bytes_override
)
198 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
;
199 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
203 r
= rscreen
->ws
->surface_init(rscreen
->ws
, &rtex
->surface
);
207 rtex
->size
= rtex
->surface
.bo_size
;
208 if (pitch_in_bytes_override
&& pitch_in_bytes_override
!= rtex
->surface
.level
[0].pitch_bytes
) {
209 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
212 rtex
->surface
.level
[0].nblk_x
= pitch_in_bytes_override
/ rtex
->surface
.bpe
;
213 rtex
->surface
.level
[0].pitch_bytes
= pitch_in_bytes_override
;
214 rtex
->surface
.level
[0].slice_size
= pitch_in_bytes_override
* rtex
->surface
.level
[0].nblk_y
;
215 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
216 rtex
->surface
.stencil_offset
=
217 rtex
->surface
.stencil_level
[0].offset
= rtex
->surface
.level
[0].slice_size
;
220 for (i
= 0; i
<= ptex
->last_level
; i
++) {
221 switch (rtex
->surface
.level
[i
].mode
) {
222 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
223 rtex
->array_mode
[i
] = V_038000_ARRAY_LINEAR_ALIGNED
;
225 case RADEON_SURF_MODE_1D
:
226 rtex
->array_mode
[i
] = V_038000_ARRAY_1D_TILED_THIN1
;
228 case RADEON_SURF_MODE_2D
:
229 rtex
->array_mode
[i
] = V_038000_ARRAY_2D_TILED_THIN1
;
232 case RADEON_SURF_MODE_LINEAR
:
233 rtex
->array_mode
[i
] = 0;
240 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
241 struct pipe_resource
*ptex
,
242 struct winsys_handle
*whandle
)
244 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
245 struct r600_resource
*resource
= &rtex
->resource
;
246 struct radeon_surface
*surface
= &rtex
->surface
;
247 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
249 rscreen
->ws
->buffer_set_tiling(resource
->buf
,
251 surface
->level
[0].mode
>= RADEON_SURF_MODE_1D
?
252 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
,
253 surface
->level
[0].mode
>= RADEON_SURF_MODE_2D
?
254 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
,
255 surface
->bankw
, surface
->bankh
,
257 surface
->stencil_tile_split
,
259 rtex
->surface
.level
[0].pitch_bytes
);
261 return rscreen
->ws
->buffer_get_handle(resource
->buf
,
262 rtex
->surface
.level
[0].pitch_bytes
, whandle
);
265 static void r600_texture_destroy(struct pipe_screen
*screen
,
266 struct pipe_resource
*ptex
)
268 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
269 struct r600_resource
*resource
= &rtex
->resource
;
271 if (rtex
->flushed_depth_texture
)
272 pipe_resource_reference((struct pipe_resource
**)&rtex
->flushed_depth_texture
, NULL
);
274 pipe_resource_reference((struct pipe_resource
**)&rtex
->htile
, NULL
);
275 pb_reference(&resource
->buf
, NULL
);
279 static const struct u_resource_vtbl r600_texture_vtbl
;
281 /* The number of samples can be specified independently of the texture. */
282 void r600_texture_get_fmask_info(struct r600_screen
*rscreen
,
283 struct r600_texture
*rtex
,
285 struct r600_fmask_info
*out
)
287 /* FMASK is allocated pretty much like an ordinary texture.
288 * Here we use bpe in the units of bits, not bytes. */
289 struct radeon_surface fmask
= rtex
->surface
;
291 switch (nr_samples
) {
293 /* This should be 8,1, but we should set nsamples > 1
294 * for the allocator to treat it as a multisample surface.
295 * Let's set 4,2 then. */
309 R600_ERR("Invalid sample count for FMASK allocation.\n");
313 /* R600-R700 errata? Anyway, this fixes colorbuffer corruption. */
314 if (rscreen
->chip_class
<= R700
) {
318 if (rscreen
->chip_class
>= EVERGREEN
) {
319 fmask
.bankh
= nr_samples
<= 4 ? 4 : 1;
322 if (rscreen
->ws
->surface_init(rscreen
->ws
, &fmask
)) {
323 R600_ERR("Got error in surface_init while allocating FMASK.\n");
326 assert(fmask
.level
[0].mode
== RADEON_SURF_MODE_2D
);
328 out
->bank_height
= fmask
.bankh
;
329 out
->alignment
= MAX2(256, fmask
.bo_alignment
);
330 out
->size
= (fmask
.bo_size
+ 7) / 8;
333 static void r600_texture_allocate_fmask(struct r600_screen
*rscreen
,
334 struct r600_texture
*rtex
)
336 struct r600_fmask_info fmask
;
338 r600_texture_get_fmask_info(rscreen
, rtex
,
339 rtex
->resource
.b
.b
.nr_samples
, &fmask
);
341 rtex
->fmask_bank_height
= fmask
.bank_height
;
342 rtex
->fmask_offset
= align(rtex
->size
, fmask
.alignment
);
343 rtex
->fmask_size
= fmask
.size
;
344 rtex
->size
= rtex
->fmask_offset
+ rtex
->fmask_size
;
346 printf("FMASK width=%u, height=%i, bits=%u, size=%u\n",
347 fmask
.npix_x
, fmask
.npix_y
, fmask
.bpe
* fmask
.nsamples
, rtex
->fmask_size
);
351 void r600_texture_get_cmask_info(struct r600_screen
*rscreen
,
352 struct r600_texture
*rtex
,
353 struct r600_cmask_info
*out
)
355 unsigned cmask_tile_width
= 8;
356 unsigned cmask_tile_height
= 8;
357 unsigned cmask_tile_elements
= cmask_tile_width
* cmask_tile_height
;
358 unsigned element_bits
= 4;
359 unsigned cmask_cache_bits
= 1024;
360 unsigned num_pipes
= rscreen
->tiling_info
.num_channels
;
361 unsigned pipe_interleave_bytes
= rscreen
->tiling_info
.group_bytes
;
363 unsigned elements_per_macro_tile
= (cmask_cache_bits
/ element_bits
) * num_pipes
;
364 unsigned pixels_per_macro_tile
= elements_per_macro_tile
* cmask_tile_elements
;
365 unsigned sqrt_pixels_per_macro_tile
= sqrt(pixels_per_macro_tile
);
366 unsigned macro_tile_width
= util_next_power_of_two(sqrt_pixels_per_macro_tile
);
367 unsigned macro_tile_height
= pixels_per_macro_tile
/ macro_tile_width
;
369 unsigned pitch_elements
= align(rtex
->surface
.npix_x
, macro_tile_width
);
370 unsigned height
= align(rtex
->surface
.npix_y
, macro_tile_height
);
372 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
373 unsigned slice_bytes
=
374 ((pitch_elements
* height
* element_bits
+ 7) / 8) / cmask_tile_elements
;
376 assert(macro_tile_width
% 128 == 0);
377 assert(macro_tile_height
% 128 == 0);
379 out
->slice_tile_max
= ((pitch_elements
* height
) / (128*128)) - 1;
380 out
->alignment
= MAX2(256, base_align
);
381 out
->size
= rtex
->surface
.array_size
* align(slice_bytes
, base_align
);
384 static void r600_texture_allocate_cmask(struct r600_screen
*rscreen
,
385 struct r600_texture
*rtex
)
387 struct r600_cmask_info cmask
;
389 r600_texture_get_cmask_info(rscreen
, rtex
, &cmask
);
391 rtex
->cmask_slice_tile_max
= cmask
.slice_tile_max
;
392 rtex
->cmask_offset
= align(rtex
->size
, cmask
.alignment
);
393 rtex
->cmask_size
= cmask
.size
;
394 rtex
->size
= rtex
->cmask_offset
+ rtex
->cmask_size
;
396 printf("CMASK: macro tile width = %u, macro tile height = %u, "
397 "pitch elements = %u, height = %u, slice tile max = %u\n",
398 macro_tile_width
, macro_tile_height
, pitch_elements
, height
,
399 rtex
->cmask_slice_tile_max
);
403 static struct r600_texture
*
404 r600_texture_create_object(struct pipe_screen
*screen
,
405 const struct pipe_resource
*base
,
406 unsigned pitch_in_bytes_override
,
407 struct pb_buffer
*buf
,
408 struct radeon_surface
*surface
)
410 struct r600_texture
*rtex
;
411 struct r600_resource
*resource
;
412 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
415 rtex
= CALLOC_STRUCT(r600_texture
);
419 resource
= &rtex
->resource
;
420 resource
->b
.b
= *base
;
421 resource
->b
.vtbl
= &r600_texture_vtbl
;
422 pipe_reference_init(&resource
->b
.b
.reference
, 1);
423 resource
->b
.b
.screen
= screen
;
424 rtex
->pitch_override
= pitch_in_bytes_override
;
426 /* don't include stencil-only formats which we don't support for rendering */
427 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
429 rtex
->surface
= *surface
;
430 r
= r600_setup_surface(screen
, rtex
,
431 pitch_in_bytes_override
);
437 if (base
->nr_samples
> 1 && !rtex
->is_depth
&& !buf
) {
438 r600_texture_allocate_fmask(rscreen
, rtex
);
439 r600_texture_allocate_cmask(rscreen
, rtex
);
442 if (!rtex
->is_depth
&& base
->nr_samples
> 1 &&
443 (!rtex
->fmask_size
|| !rtex
->cmask_size
)) {
448 /* Tiled depth textures utilize the non-displayable tile order. */
449 rtex
->non_disp_tiling
= rtex
->is_depth
&& rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
;
451 /* only enable hyperz for PIPE_TEXTURE_2D not for PIPE_TEXTURE_2D_ARRAY
452 * Thought it might still be interessting to use hyperz for texture
453 * array without using fast clear features
456 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
)) &&
457 util_format_is_depth_or_stencil(base
->format
) &&
458 rscreen
->info
.drm_minor
>= 26 &&
459 !(rscreen
->debug_flags
& DBG_NO_HYPERZ
) &&
460 base
->target
== PIPE_TEXTURE_2D
&&
461 rtex
->surface
.level
[0].nblk_x
>= 32 &&
462 rtex
->surface
.level
[0].nblk_y
>= 32) {
463 unsigned sw
= rtex
->surface
.level
[0].nblk_x
* rtex
->surface
.blk_w
;
464 unsigned sh
= rtex
->surface
.level
[0].nblk_y
* rtex
->surface
.blk_h
;
466 unsigned npipes
= rscreen
->info
.r600_num_tile_pipes
;
468 /* this alignment and htile size only apply to linear htile buffer */
469 sw
= align(sw
, 16 << 3);
470 sh
= align(sh
, npipes
<< 3);
471 htile_size
= (sw
>> 3) * (sh
>> 3) * 4;
472 /* must be aligned with 2K * npipes */
473 htile_size
= align(htile_size
, (2 << 10) * npipes
);
475 rtex
->htile
= (struct r600_resource
*)pipe_buffer_create(&rscreen
->screen
, PIPE_BIND_CUSTOM
,
476 PIPE_USAGE_STATIC
, htile_size
);
477 if (rtex
->htile
== NULL
) {
478 /* this is not a fatal error as we can still keep rendering
479 * without htile buffer
481 R600_ERR("r600: failed to create bo for htile buffers\n");
484 ptr
= rscreen
->ws
->buffer_map(rtex
->htile
->cs_buf
, NULL
, PIPE_TRANSFER_WRITE
);
485 memset(ptr
, 0x0, htile_size
);
486 rscreen
->ws
->buffer_unmap(rtex
->htile
->cs_buf
);
490 /* Now create the backing buffer. */
492 unsigned base_align
= rtex
->surface
.bo_alignment
;
493 unsigned usage
= R600_TEX_IS_TILED(rtex
, 0) ? PIPE_USAGE_STATIC
: base
->usage
;
495 if (!r600_init_resource(rscreen
, resource
, rtex
->size
, base_align
, FALSE
, usage
)) {
500 /* This is usually the window framebuffer. We want it in VRAM, always. */
502 resource
->cs_buf
= rscreen
->ws
->buffer_get_cs_handle(buf
);
503 resource
->domains
= RADEON_DOMAIN_VRAM
;
506 if (rtex
->cmask_size
) {
507 /* Initialize the cmask to 0xCC (= compressed state). */
508 char *ptr
= rscreen
->ws
->buffer_map(resource
->cs_buf
, NULL
, PIPE_TRANSFER_WRITE
);
509 memset(ptr
+ rtex
->cmask_offset
, 0xCC, rtex
->cmask_size
);
510 rscreen
->ws
->buffer_unmap(resource
->cs_buf
);
513 if (rscreen
->debug_flags
& DBG_TEX_DEPTH
&& rtex
->is_depth
&& rtex
->non_disp_tiling
) {
514 printf("Texture: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
515 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
516 "bpe=%u, nsamples=%u, flags=%u\n",
517 rtex
->surface
.npix_x
, rtex
->surface
.npix_y
,
518 rtex
->surface
.npix_z
, rtex
->surface
.blk_w
,
519 rtex
->surface
.blk_h
, rtex
->surface
.blk_d
,
520 rtex
->surface
.array_size
, rtex
->surface
.last_level
,
521 rtex
->surface
.bpe
, rtex
->surface
.nsamples
,
522 rtex
->surface
.flags
);
523 if (rtex
->surface
.flags
& RADEON_SURF_ZBUFFER
) {
524 for (int i
= 0; i
<= rtex
->surface
.last_level
; i
++) {
525 printf(" Z %i: offset=%llu, slice_size=%llu, npix_x=%u, "
526 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
527 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
528 i
, (unsigned long long)rtex
->surface
.level
[i
].offset
,
529 (unsigned long long)rtex
->surface
.level
[i
].slice_size
,
530 u_minify(rtex
->resource
.b
.b
.width0
, i
),
531 u_minify(rtex
->resource
.b
.b
.height0
, i
),
532 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
533 rtex
->surface
.level
[i
].nblk_x
,
534 rtex
->surface
.level
[i
].nblk_y
,
535 rtex
->surface
.level
[i
].nblk_z
,
536 rtex
->surface
.level
[i
].pitch_bytes
,
537 rtex
->surface
.level
[i
].mode
);
540 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
541 for (int i
= 0; i
<= rtex
->surface
.last_level
; i
++) {
542 printf(" S %i: offset=%llu, slice_size=%llu, npix_x=%u, "
543 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
544 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
545 i
, (unsigned long long)rtex
->surface
.stencil_level
[i
].offset
,
546 (unsigned long long)rtex
->surface
.stencil_level
[i
].slice_size
,
547 u_minify(rtex
->resource
.b
.b
.width0
, i
),
548 u_minify(rtex
->resource
.b
.b
.height0
, i
),
549 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
550 rtex
->surface
.stencil_level
[i
].nblk_x
,
551 rtex
->surface
.stencil_level
[i
].nblk_y
,
552 rtex
->surface
.stencil_level
[i
].nblk_z
,
553 rtex
->surface
.stencil_level
[i
].pitch_bytes
,
554 rtex
->surface
.stencil_level
[i
].mode
);
561 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
562 const struct pipe_resource
*templ
)
564 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
565 struct radeon_surface surface
;
566 const struct util_format_description
*desc
= util_format_description(templ
->format
);
570 /* Default tiling mode for staging textures. */
571 array_mode
= V_038000_ARRAY_LINEAR_ALIGNED
;
573 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats. That's not an issue,
574 * because 422 formats are used for videos, which prefer linear buffers
575 * for fast uploads anyway. */
576 if (!(templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
) &&
577 desc
->layout
!= UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
578 if (templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
) {
579 array_mode
= V_038000_ARRAY_2D_TILED_THIN1
;
580 } else if (!(templ
->bind
& PIPE_BIND_SCANOUT
) &&
581 templ
->usage
!= PIPE_USAGE_STAGING
&&
582 templ
->usage
!= PIPE_USAGE_STREAM
&&
583 templ
->target
!= PIPE_TEXTURE_1D
&&
584 templ
->target
!= PIPE_TEXTURE_1D_ARRAY
&&
585 templ
->height0
> 3) {
586 array_mode
= V_038000_ARRAY_2D_TILED_THIN1
;
587 } else if (util_format_is_compressed(templ
->format
)) {
588 array_mode
= V_038000_ARRAY_1D_TILED_THIN1
;
592 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
,
593 templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
);
597 r
= rscreen
->ws
->surface_best(rscreen
->ws
, &surface
);
601 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
,
605 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
606 struct pipe_resource
*texture
,
607 const struct pipe_surface
*templ
,
608 unsigned width
, unsigned height
)
610 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
612 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
613 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
614 assert(templ
->u
.tex
.first_layer
== templ
->u
.tex
.last_layer
);
617 pipe_reference_init(&surface
->base
.reference
, 1);
618 pipe_resource_reference(&surface
->base
.texture
, texture
);
619 surface
->base
.context
= pipe
;
620 surface
->base
.format
= templ
->format
;
621 surface
->base
.width
= width
;
622 surface
->base
.height
= height
;
623 surface
->base
.u
= templ
->u
;
624 return &surface
->base
;
627 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
628 struct pipe_resource
*tex
,
629 const struct pipe_surface
*templ
)
631 unsigned level
= templ
->u
.tex
.level
;
633 return r600_create_surface_custom(pipe
, tex
, templ
,
634 u_minify(tex
->width0
, level
),
635 u_minify(tex
->height0
, level
));
638 static void r600_surface_destroy(struct pipe_context
*pipe
,
639 struct pipe_surface
*surface
)
641 struct r600_surface
*surf
= (struct r600_surface
*)surface
;
642 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_fmask
, NULL
);
643 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_cmask
, NULL
);
644 pipe_resource_reference(&surface
->texture
, NULL
);
648 struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
649 const struct pipe_resource
*templ
,
650 struct winsys_handle
*whandle
)
652 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
653 struct pb_buffer
*buf
= NULL
;
655 unsigned array_mode
= 0;
656 enum radeon_bo_layout micro
, macro
;
657 struct radeon_surface surface
;
660 /* Support only 2D textures without mipmaps */
661 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
662 templ
->depth0
!= 1 || templ
->last_level
!= 0)
665 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
);
669 rscreen
->ws
->buffer_get_tiling(buf
, µ
, ¯o
,
670 &surface
.bankw
, &surface
.bankh
,
672 &surface
.stencil_tile_split
,
675 if (macro
== RADEON_LAYOUT_TILED
)
676 array_mode
= V_0280A0_ARRAY_2D_TILED_THIN1
;
677 else if (micro
== RADEON_LAYOUT_TILED
)
678 array_mode
= V_0280A0_ARRAY_1D_TILED_THIN1
;
680 array_mode
= V_038000_ARRAY_LINEAR_ALIGNED
;
682 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
, false);
686 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
,
687 stride
, buf
, &surface
);
690 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
691 struct pipe_resource
*texture
,
692 struct r600_texture
**staging
)
694 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
695 struct pipe_resource resource
;
696 struct r600_texture
**flushed_depth_texture
= staging
?
697 staging
: &rtex
->flushed_depth_texture
;
699 if (!staging
&& rtex
->flushed_depth_texture
)
700 return true; /* it's ready */
702 resource
.target
= texture
->target
;
703 resource
.format
= texture
->format
;
704 resource
.width0
= texture
->width0
;
705 resource
.height0
= texture
->height0
;
706 resource
.depth0
= texture
->depth0
;
707 resource
.array_size
= texture
->array_size
;
708 resource
.last_level
= texture
->last_level
;
709 resource
.nr_samples
= texture
->nr_samples
;
710 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_STATIC
;
711 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
712 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
715 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
717 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
718 if (*flushed_depth_texture
== NULL
) {
719 R600_ERR("failed to create temporary texture to hold flushed depth\n");
723 (*flushed_depth_texture
)->is_flushing_texture
= TRUE
;
724 (*flushed_depth_texture
)->non_disp_tiling
= false;
728 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
729 struct pipe_resource
*texture
,
732 const struct pipe_box
*box
,
733 struct pipe_transfer
**ptransfer
)
735 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
736 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
737 struct r600_transfer
*trans
;
738 boolean use_staging_texture
= FALSE
;
739 enum pipe_format format
= texture
->format
;
740 struct r600_resource
*buf
;
744 if ((texture
->bind
& PIPE_BIND_GLOBAL
) && texture
->target
== PIPE_BUFFER
) {
745 return r600_compute_global_transfer_map(ctx
, texture
, level
, usage
, box
, ptransfer
);
748 /* We cannot map a tiled texture directly because the data is
749 * in a different order, therefore we do detiling using a blit.
751 * Also, use a temporary in GTT memory for read transfers, as
752 * the CPU is much happier reading out of cached system memory
753 * than uncached VRAM.
755 if (R600_TEX_IS_TILED(rtex
, level
)) {
756 use_staging_texture
= TRUE
;
759 /* Use a staging texture for uploads if the underlying BO is busy. */
760 if (!(usage
& PIPE_TRANSFER_READ
) &&
761 (r600_rings_is_buffer_referenced(rctx
, rtex
->resource
.cs_buf
, RADEON_USAGE_READWRITE
) ||
762 rctx
->ws
->buffer_is_busy(rtex
->resource
.buf
, RADEON_USAGE_READWRITE
))) {
763 use_staging_texture
= TRUE
;
766 if (texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
) {
767 use_staging_texture
= FALSE
;
770 if (use_staging_texture
&& (usage
& PIPE_TRANSFER_MAP_DIRECTLY
)) {
774 trans
= CALLOC_STRUCT(r600_transfer
);
777 trans
->transfer
.resource
= texture
;
778 trans
->transfer
.level
= level
;
779 trans
->transfer
.usage
= usage
;
780 trans
->transfer
.box
= *box
;
781 if (rtex
->is_depth
) {
782 /* XXX: only readback the rectangle which is being mapped?
784 /* XXX: when discard is true, no need to read back from depth texture
786 struct r600_texture
*staging_depth
;
788 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
789 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
790 R600_ERR("mapping MSAA zbuffer unimplemented\n");
795 if (!r600_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
796 R600_ERR("failed to create temporary texture to hold untiled copy\n");
801 r600_blit_decompress_depth(ctx
, rtex
, staging_depth
,
803 box
->z
, box
->z
+ box
->depth
- 1,
806 trans
->transfer
.stride
= staging_depth
->surface
.level
[level
].pitch_bytes
;
807 trans
->transfer
.layer_stride
= staging_depth
->surface
.level
[level
].slice_size
;
808 trans
->offset
= r600_texture_get_offset(staging_depth
, level
, box
->z
);
809 trans
->staging
= (struct r600_resource
*)staging_depth
;
810 } else if (use_staging_texture
) {
811 struct pipe_resource resource
;
812 struct r600_texture
*staging
;
814 memset(&resource
, 0, sizeof(resource
));
815 resource
.format
= texture
->format
;
816 resource
.width0
= box
->width
;
817 resource
.height0
= box
->height
;
819 resource
.array_size
= 1;
820 resource
.usage
= PIPE_USAGE_STAGING
;
821 resource
.flags
= R600_RESOURCE_FLAG_TRANSFER
;
823 /* We must set the correct texture target and dimensions if needed for a 3D transfer. */
824 if (box
->depth
> 1 && util_max_layer(texture
, level
) > 0)
825 resource
.target
= texture
->target
;
827 resource
.target
= PIPE_TEXTURE_2D
;
829 switch (resource
.target
) {
830 case PIPE_TEXTURE_1D_ARRAY
:
831 case PIPE_TEXTURE_2D_ARRAY
:
832 case PIPE_TEXTURE_CUBE_ARRAY
:
833 resource
.array_size
= box
->depth
;
835 case PIPE_TEXTURE_3D
:
836 resource
.depth0
= box
->depth
;
842 /* Create the temporary texture. */
843 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
844 if (staging
== NULL
) {
845 R600_ERR("failed to create temporary texture to hold untiled copy\n");
849 trans
->staging
= &staging
->resource
;
850 trans
->transfer
.stride
= staging
->surface
.level
[0].pitch_bytes
;
851 trans
->transfer
.layer_stride
= staging
->surface
.level
[0].slice_size
;
852 if (usage
& PIPE_TRANSFER_READ
) {
853 r600_copy_to_staging_texture(ctx
, trans
);
854 /* flush gfx & dma ring, order does not matter as only one can be live */
855 if (rctx
->rings
.dma
.cs
) {
856 rctx
->rings
.dma
.flush(rctx
, 0);
858 rctx
->rings
.gfx
.flush(rctx
, 0);
861 trans
->transfer
.stride
= rtex
->surface
.level
[level
].pitch_bytes
;
862 trans
->transfer
.layer_stride
= rtex
->surface
.level
[level
].slice_size
;
863 trans
->offset
= r600_texture_get_offset(rtex
, level
, box
->z
);
866 if (trans
->staging
) {
867 buf
= trans
->staging
;
869 buf
= &rtex
->resource
;
872 if (rtex
->is_depth
|| !trans
->staging
)
873 offset
= trans
->offset
+
874 box
->y
/ util_format_get_blockheight(format
) * trans
->transfer
.stride
+
875 box
->x
/ util_format_get_blockwidth(format
) * util_format_get_blocksize(format
);
877 if (!(map
= r600_buffer_mmap_sync_with_rings(rctx
, buf
, usage
))) {
878 pipe_resource_reference((struct pipe_resource
**)&trans
->staging
, NULL
);
883 *ptransfer
= &trans
->transfer
;
887 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
888 struct pipe_transfer
* transfer
)
890 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
891 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
892 struct radeon_winsys_cs_handle
*buf
;
893 struct pipe_resource
*texture
= transfer
->resource
;
894 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
896 if ((transfer
->resource
->bind
& PIPE_BIND_GLOBAL
) && transfer
->resource
->target
== PIPE_BUFFER
) {
897 return r600_compute_global_transfer_unmap(ctx
, transfer
);
900 if (rtransfer
->staging
) {
901 buf
= ((struct r600_resource
*)rtransfer
->staging
)->cs_buf
;
903 buf
= ((struct r600_resource
*)transfer
->resource
)->cs_buf
;
905 rctx
->ws
->buffer_unmap(buf
);
907 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
908 if (rtex
->is_depth
) {
909 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
910 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
911 &rtransfer
->staging
->b
.b
, transfer
->level
,
914 r600_copy_from_staging_texture(ctx
, rtransfer
);
918 if (rtransfer
->staging
)
919 pipe_resource_reference((struct pipe_resource
**)&rtransfer
->staging
, NULL
);
924 void r600_init_surface_functions(struct r600_context
*r600
)
926 r600
->context
.create_surface
= r600_create_surface
;
927 r600
->context
.surface_destroy
= r600_surface_destroy
;
930 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
931 const unsigned char *swizzle_view
,
935 unsigned char swizzle
[4];
937 const uint32_t tex_swizzle_shift
[4] = {
940 const uint32_t vtx_swizzle_shift
[4] = {
943 const uint32_t swizzle_bit
[4] = {
946 const uint32_t *swizzle_shift
= tex_swizzle_shift
;
949 swizzle_shift
= vtx_swizzle_shift
;
952 util_format_compose_swizzles(swizzle_format
, swizzle_view
, swizzle
);
954 memcpy(swizzle
, swizzle_format
, 4);
958 for (i
= 0; i
< 4; i
++) {
959 switch (swizzle
[i
]) {
960 case UTIL_FORMAT_SWIZZLE_Y
:
961 result
|= swizzle_bit
[1] << swizzle_shift
[i
];
963 case UTIL_FORMAT_SWIZZLE_Z
:
964 result
|= swizzle_bit
[2] << swizzle_shift
[i
];
966 case UTIL_FORMAT_SWIZZLE_W
:
967 result
|= swizzle_bit
[3] << swizzle_shift
[i
];
969 case UTIL_FORMAT_SWIZZLE_0
:
970 result
|= V_038010_SQ_SEL_0
<< swizzle_shift
[i
];
972 case UTIL_FORMAT_SWIZZLE_1
:
973 result
|= V_038010_SQ_SEL_1
<< swizzle_shift
[i
];
975 default: /* UTIL_FORMAT_SWIZZLE_X */
976 result
|= swizzle_bit
[0] << swizzle_shift
[i
];
982 /* texture format translate */
983 uint32_t r600_translate_texformat(struct pipe_screen
*screen
,
984 enum pipe_format format
,
985 const unsigned char *swizzle_view
,
986 uint32_t *word4_p
, uint32_t *yuv_format_p
)
988 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
989 uint32_t result
= 0, word4
= 0, yuv_format
= 0;
990 const struct util_format_description
*desc
;
991 boolean uniform
= TRUE
;
992 bool enable_s3tc
= rscreen
->info
.drm_minor
>= 9;
993 bool is_srgb_valid
= FALSE
;
994 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
995 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
998 const uint32_t sign_bit
[4] = {
999 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED
),
1000 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED
),
1001 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED
),
1002 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED
)
1004 desc
= util_format_description(format
);
1006 /* Depth and stencil swizzling is handled separately. */
1007 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
) {
1008 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
, FALSE
);
1011 /* Colorspace (return non-RGB formats directly). */
1012 switch (desc
->colorspace
) {
1013 /* Depth stencil formats */
1014 case UTIL_FORMAT_COLORSPACE_ZS
:
1016 /* Depth sampler formats. */
1017 case PIPE_FORMAT_Z16_UNORM
:
1018 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1021 case PIPE_FORMAT_Z24X8_UNORM
:
1022 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1023 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1026 case PIPE_FORMAT_X8Z24_UNORM
:
1027 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1028 if (rscreen
->chip_class
< EVERGREEN
)
1030 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
1033 case PIPE_FORMAT_Z32_FLOAT
:
1034 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1035 result
= FMT_32_FLOAT
;
1037 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1038 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1039 result
= FMT_X24_8_32_FLOAT
;
1041 /* Stencil sampler formats. */
1042 case PIPE_FORMAT_S8_UINT
:
1043 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1044 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1047 case PIPE_FORMAT_X24S8_UINT
:
1048 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1049 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
1052 case PIPE_FORMAT_S8X24_UINT
:
1053 if (rscreen
->chip_class
< EVERGREEN
)
1055 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1056 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1059 case PIPE_FORMAT_X32_S8X24_UINT
:
1060 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1061 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
1062 result
= FMT_X24_8_32_FLOAT
;
1068 case UTIL_FORMAT_COLORSPACE_YUV
:
1069 yuv_format
|= (1 << 30);
1071 case PIPE_FORMAT_UYVY
:
1072 case PIPE_FORMAT_YUYV
:
1076 goto out_unknown
; /* XXX */
1078 case UTIL_FORMAT_COLORSPACE_SRGB
:
1079 word4
|= S_038010_FORCE_DEGAMMA(1);
1086 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1091 case PIPE_FORMAT_RGTC1_SNORM
:
1092 case PIPE_FORMAT_LATC1_SNORM
:
1093 word4
|= sign_bit
[0];
1094 case PIPE_FORMAT_RGTC1_UNORM
:
1095 case PIPE_FORMAT_LATC1_UNORM
:
1098 case PIPE_FORMAT_RGTC2_SNORM
:
1099 case PIPE_FORMAT_LATC2_SNORM
:
1100 word4
|= sign_bit
[0] | sign_bit
[1];
1101 case PIPE_FORMAT_RGTC2_UNORM
:
1102 case PIPE_FORMAT_LATC2_UNORM
:
1110 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1115 if (!util_format_s3tc_enabled
) {
1120 case PIPE_FORMAT_DXT1_RGB
:
1121 case PIPE_FORMAT_DXT1_RGBA
:
1122 case PIPE_FORMAT_DXT1_SRGB
:
1123 case PIPE_FORMAT_DXT1_SRGBA
:
1125 is_srgb_valid
= TRUE
;
1127 case PIPE_FORMAT_DXT3_RGBA
:
1128 case PIPE_FORMAT_DXT3_SRGBA
:
1130 is_srgb_valid
= TRUE
;
1132 case PIPE_FORMAT_DXT5_RGBA
:
1133 case PIPE_FORMAT_DXT5_SRGBA
:
1135 is_srgb_valid
= TRUE
;
1142 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
1144 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
1145 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
1148 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
1149 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
1157 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1158 result
= FMT_5_9_9_9_SHAREDEXP
;
1160 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1161 result
= FMT_10_11_11_FLOAT
;
1166 for (i
= 0; i
< desc
->nr_channels
; i
++) {
1167 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1168 word4
|= sign_bit
[i
];
1172 /* R8G8Bx_SNORM - XXX CxV8U8 */
1174 /* See whether the components are of the same size. */
1175 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1176 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1179 /* Non-uniform formats. */
1181 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
1182 desc
->channel
[0].pure_integer
)
1183 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1184 switch(desc
->nr_channels
) {
1186 if (desc
->channel
[0].size
== 5 &&
1187 desc
->channel
[1].size
== 6 &&
1188 desc
->channel
[2].size
== 5) {
1194 if (desc
->channel
[0].size
== 5 &&
1195 desc
->channel
[1].size
== 5 &&
1196 desc
->channel
[2].size
== 5 &&
1197 desc
->channel
[3].size
== 1) {
1198 result
= FMT_1_5_5_5
;
1201 if (desc
->channel
[0].size
== 10 &&
1202 desc
->channel
[1].size
== 10 &&
1203 desc
->channel
[2].size
== 10 &&
1204 desc
->channel
[3].size
== 2) {
1205 result
= FMT_2_10_10_10
;
1213 /* Find the first non-VOID channel. */
1214 for (i
= 0; i
< 4; i
++) {
1215 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1223 /* uniform formats */
1224 switch (desc
->channel
[i
].type
) {
1225 case UTIL_FORMAT_TYPE_UNSIGNED
:
1226 case UTIL_FORMAT_TYPE_SIGNED
:
1228 if (!desc
->channel
[i
].normalized
&&
1229 desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
) {
1233 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
1234 desc
->channel
[i
].pure_integer
)
1235 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1237 switch (desc
->channel
[i
].size
) {
1239 switch (desc
->nr_channels
) {
1244 result
= FMT_4_4_4_4
;
1249 switch (desc
->nr_channels
) {
1257 result
= FMT_8_8_8_8
;
1258 is_srgb_valid
= TRUE
;
1263 switch (desc
->nr_channels
) {
1271 result
= FMT_16_16_16_16
;
1276 switch (desc
->nr_channels
) {
1284 result
= FMT_32_32_32_32
;
1290 case UTIL_FORMAT_TYPE_FLOAT
:
1291 switch (desc
->channel
[i
].size
) {
1293 switch (desc
->nr_channels
) {
1295 result
= FMT_16_FLOAT
;
1298 result
= FMT_16_16_FLOAT
;
1301 result
= FMT_16_16_16_16_FLOAT
;
1306 switch (desc
->nr_channels
) {
1308 result
= FMT_32_FLOAT
;
1311 result
= FMT_32_32_FLOAT
;
1314 result
= FMT_32_32_32_32_FLOAT
;
1323 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
&& !is_srgb_valid
)
1328 *yuv_format_p
= yuv_format
;
1331 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1335 static const struct u_resource_vtbl r600_texture_vtbl
=
1337 r600_texture_get_handle
, /* get_handle */
1338 r600_texture_destroy
, /* resource_destroy */
1339 r600_texture_transfer_map
, /* transfer_map */
1340 NULL
, /* transfer_flush_region */
1341 r600_texture_transfer_unmap
, /* transfer_unmap */
1342 NULL
/* transfer_inline_write */