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r600g: Emit dispatch state for compute directly to the cs
[mesa.git] / src / gallium / drivers / r600 / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_formats.h"
28 #include "r600d.h"
29
30 #include <errno.h>
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33
34 /* Copy from a full GPU texture to a transfer's staging one. */
35 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
36 {
37 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
38 struct pipe_resource *texture = transfer->resource;
39
40 ctx->resource_copy_region(ctx, &rtransfer->staging->b.b,
41 0, 0, 0, 0, texture, transfer->level,
42 &transfer->box);
43 }
44
45
46 /* Copy from a transfer's staging texture to a full GPU one. */
47 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
48 {
49 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
50 struct pipe_resource *texture = transfer->resource;
51 struct pipe_box sbox;
52
53 u_box_origin_2d(transfer->box.width, transfer->box.height, &sbox);
54
55 ctx->resource_copy_region(ctx, texture, transfer->level,
56 transfer->box.x, transfer->box.y, transfer->box.z,
57 &rtransfer->staging->b.b,
58 0, &sbox);
59 }
60
61 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
62 unsigned level, unsigned layer)
63 {
64 unsigned offset = rtex->offset[level];
65
66 switch (rtex->resource.b.b.target) {
67 case PIPE_TEXTURE_3D:
68 case PIPE_TEXTURE_CUBE:
69 default:
70 return offset + layer * rtex->layer_size[level];
71 }
72 }
73
74 static unsigned r600_get_block_alignment(struct pipe_screen *screen,
75 enum pipe_format format,
76 unsigned array_mode)
77 {
78 struct r600_screen* rscreen = (struct r600_screen *)screen;
79 unsigned pixsize = util_format_get_blocksize(format);
80 int p_align;
81
82 switch(array_mode) {
83 case V_038000_ARRAY_1D_TILED_THIN1:
84 p_align = MAX2(8,
85 ((rscreen->tiling_info.group_bytes / 8 / pixsize)));
86 break;
87 case V_038000_ARRAY_2D_TILED_THIN1:
88 p_align = MAX2(rscreen->tiling_info.num_banks,
89 (((rscreen->tiling_info.group_bytes / 8 / pixsize)) *
90 rscreen->tiling_info.num_banks)) * 8;
91 break;
92 case V_038000_ARRAY_LINEAR_ALIGNED:
93 p_align = MAX2(64, rscreen->tiling_info.group_bytes / pixsize);
94 break;
95 case V_038000_ARRAY_LINEAR_GENERAL:
96 default:
97 p_align = rscreen->tiling_info.group_bytes / pixsize;
98 break;
99 }
100 return p_align;
101 }
102
103 static unsigned r600_get_height_alignment(struct pipe_screen *screen,
104 unsigned array_mode)
105 {
106 struct r600_screen* rscreen = (struct r600_screen *)screen;
107 int h_align;
108
109 switch (array_mode) {
110 case V_038000_ARRAY_2D_TILED_THIN1:
111 h_align = rscreen->tiling_info.num_channels * 8;
112 break;
113 case V_038000_ARRAY_1D_TILED_THIN1:
114 case V_038000_ARRAY_LINEAR_ALIGNED:
115 h_align = 8;
116 break;
117 case V_038000_ARRAY_LINEAR_GENERAL:
118 default:
119 h_align = 1;
120 break;
121 }
122 return h_align;
123 }
124
125 static unsigned r600_get_base_alignment(struct pipe_screen *screen,
126 enum pipe_format format,
127 unsigned array_mode)
128 {
129 struct r600_screen* rscreen = (struct r600_screen *)screen;
130 unsigned pixsize = util_format_get_blocksize(format);
131 int p_align = r600_get_block_alignment(screen, format, array_mode);
132 int h_align = r600_get_height_alignment(screen, array_mode);
133 int b_align;
134
135 switch (array_mode) {
136 case V_038000_ARRAY_2D_TILED_THIN1:
137 b_align = MAX2(rscreen->tiling_info.num_banks * rscreen->tiling_info.num_channels * 8 * 8 * pixsize,
138 p_align * pixsize * h_align);
139 break;
140 case V_038000_ARRAY_1D_TILED_THIN1:
141 case V_038000_ARRAY_LINEAR_ALIGNED:
142 case V_038000_ARRAY_LINEAR_GENERAL:
143 default:
144 b_align = rscreen->tiling_info.group_bytes;
145 break;
146 }
147 return b_align;
148 }
149
150 static unsigned mip_minify(unsigned size, unsigned level)
151 {
152 unsigned val;
153 val = u_minify(size, level);
154 if (level > 0)
155 val = util_next_power_of_two(val);
156 return val;
157 }
158
159 static unsigned r600_texture_get_nblocksx(struct pipe_screen *screen,
160 struct r600_resource_texture *rtex,
161 unsigned level)
162 {
163 struct pipe_resource *ptex = &rtex->resource.b.b;
164 unsigned nblocksx, block_align, width;
165 unsigned blocksize = util_format_get_blocksize(rtex->real_format);
166
167 if (rtex->pitch_override)
168 return rtex->pitch_override / blocksize;
169
170 width = mip_minify(ptex->width0, level);
171 nblocksx = util_format_get_nblocksx(rtex->real_format, width);
172
173 block_align = r600_get_block_alignment(screen, rtex->real_format,
174 rtex->array_mode[level]);
175 nblocksx = align(nblocksx, block_align);
176 return nblocksx;
177 }
178
179 static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen,
180 struct r600_resource_texture *rtex,
181 unsigned level)
182 {
183 struct pipe_resource *ptex = &rtex->resource.b.b;
184 unsigned height, tile_height;
185
186 height = mip_minify(ptex->height0, level);
187 height = util_format_get_nblocksy(rtex->real_format, height);
188 tile_height = r600_get_height_alignment(screen,
189 rtex->array_mode[level]);
190
191 /* XXX Hack around an alignment issue. Less tests fail with this.
192 *
193 * The thing is depth-stencil buffers should be tiled, i.e.
194 * the alignment should be >=8. If I make them tiled, stencil starts
195 * working because it no longer overlaps with the depth buffer
196 * in memory, but texturing like drawpix-stencil breaks. */
197 if (util_format_is_depth_or_stencil(rtex->real_format) && tile_height < 8)
198 tile_height = 8;
199
200 height = align(height, tile_height);
201 return height;
202 }
203
204 static void r600_texture_set_array_mode(struct pipe_screen *screen,
205 struct r600_resource_texture *rtex,
206 unsigned level, unsigned array_mode)
207 {
208 struct pipe_resource *ptex = &rtex->resource.b.b;
209
210 switch (array_mode) {
211 case V_0280A0_ARRAY_LINEAR_GENERAL:
212 case V_0280A0_ARRAY_LINEAR_ALIGNED:
213 case V_0280A0_ARRAY_1D_TILED_THIN1:
214 default:
215 rtex->array_mode[level] = array_mode;
216 break;
217 case V_0280A0_ARRAY_2D_TILED_THIN1:
218 {
219 unsigned w, h, tile_height, tile_width;
220
221 tile_height = r600_get_height_alignment(screen, array_mode);
222 tile_width = r600_get_block_alignment(screen, rtex->real_format, array_mode);
223
224 w = mip_minify(ptex->width0, level);
225 h = mip_minify(ptex->height0, level);
226 if (w <= tile_width || h <= tile_height)
227 rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1;
228 else
229 rtex->array_mode[level] = array_mode;
230 }
231 break;
232 }
233 }
234
235 static int r600_init_surface(struct radeon_surface *surface,
236 const struct pipe_resource *ptex,
237 unsigned array_mode,
238 bool is_transfer, bool is_flushed_depth)
239 {
240 const struct util_format_description *desc =
241 util_format_description(ptex->format);
242 bool is_depth, is_stencil;
243
244 is_depth = util_format_has_depth(desc);
245 is_stencil = util_format_has_stencil(desc);
246
247 surface->npix_x = ptex->width0;
248 surface->npix_y = ptex->height0;
249 surface->npix_z = ptex->depth0;
250 surface->blk_w = util_format_get_blockwidth(ptex->format);
251 surface->blk_h = util_format_get_blockheight(ptex->format);
252 surface->blk_d = 1;
253 surface->array_size = 1;
254 surface->last_level = ptex->last_level;
255 surface->bpe = util_format_get_blocksize(ptex->format);
256 /* align byte per element on dword */
257 if (surface->bpe == 3) {
258 surface->bpe = 4;
259 }
260 surface->nsamples = 1;
261 surface->flags = 0;
262 switch (array_mode) {
263 case V_038000_ARRAY_1D_TILED_THIN1:
264 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
265 break;
266 case V_038000_ARRAY_2D_TILED_THIN1:
267 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
268 break;
269 case V_038000_ARRAY_LINEAR_ALIGNED:
270 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
271 break;
272 case V_038000_ARRAY_LINEAR_GENERAL:
273 default:
274 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE);
275 break;
276 }
277 switch (ptex->target) {
278 case PIPE_TEXTURE_1D:
279 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
280 break;
281 case PIPE_TEXTURE_RECT:
282 case PIPE_TEXTURE_2D:
283 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
284 break;
285 case PIPE_TEXTURE_3D:
286 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
287 break;
288 case PIPE_TEXTURE_1D_ARRAY:
289 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
290 surface->array_size = ptex->array_size;
291 break;
292 case PIPE_TEXTURE_2D_ARRAY:
293 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
294 surface->array_size = ptex->array_size;
295 break;
296 case PIPE_TEXTURE_CUBE:
297 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
298 break;
299 case PIPE_BUFFER:
300 default:
301 return -EINVAL;
302 }
303 if (ptex->bind & PIPE_BIND_SCANOUT) {
304 surface->flags |= RADEON_SURF_SCANOUT;
305 }
306
307 if (!is_transfer && !is_flushed_depth && is_depth) {
308 surface->flags |= RADEON_SURF_ZBUFFER;
309
310 if (is_stencil) {
311 surface->flags |= RADEON_SURF_SBUFFER;
312 }
313 }
314 return 0;
315 }
316
317 static int r600_setup_surface(struct pipe_screen *screen,
318 struct r600_resource_texture *rtex,
319 unsigned array_mode,
320 unsigned pitch_in_bytes_override)
321 {
322 struct pipe_resource *ptex = &rtex->resource.b.b;
323 struct r600_screen *rscreen = (struct r600_screen*)screen;
324 unsigned i;
325 int r;
326
327 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
328 if (r) {
329 return r;
330 }
331 rtex->size = rtex->surface.bo_size;
332 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
333 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
334 * for those
335 */
336 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
337 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
338 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
339 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
340 rtex->surface.stencil_offset = rtex->surface.level[0].slice_size;
341 }
342 }
343 for (i = 0; i <= ptex->last_level; i++) {
344 rtex->offset[i] = rtex->surface.level[i].offset;
345 rtex->layer_size[i] = rtex->surface.level[i].slice_size;
346 rtex->pitch_in_bytes[i] = rtex->surface.level[i].pitch_bytes;
347 switch (rtex->surface.level[i].mode) {
348 case RADEON_SURF_MODE_LINEAR_ALIGNED:
349 rtex->array_mode[i] = V_038000_ARRAY_LINEAR_ALIGNED;
350 break;
351 case RADEON_SURF_MODE_1D:
352 rtex->array_mode[i] = V_038000_ARRAY_1D_TILED_THIN1;
353 break;
354 case RADEON_SURF_MODE_2D:
355 rtex->array_mode[i] = V_038000_ARRAY_2D_TILED_THIN1;
356 break;
357 default:
358 case RADEON_SURF_MODE_LINEAR:
359 rtex->array_mode[i] = 0;
360 break;
361 }
362 }
363 return 0;
364 }
365
366 static void r600_setup_miptree(struct pipe_screen *screen,
367 struct r600_resource_texture *rtex,
368 unsigned array_mode)
369 {
370 struct pipe_resource *ptex = &rtex->resource.b.b;
371 enum chip_class chipc = ((struct r600_screen*)screen)->chip_class;
372 unsigned size, layer_size, i, offset;
373 unsigned nblocksx, nblocksy;
374
375 for (i = 0, offset = 0; i <= ptex->last_level; i++) {
376 unsigned blocksize = util_format_get_blocksize(rtex->real_format);
377 unsigned base_align = r600_get_base_alignment(screen, rtex->real_format, array_mode);
378
379 r600_texture_set_array_mode(screen, rtex, i, array_mode);
380
381 nblocksx = r600_texture_get_nblocksx(screen, rtex, i);
382 nblocksy = r600_texture_get_nblocksy(screen, rtex, i);
383
384 if (chipc >= EVERGREEN && array_mode == V_038000_ARRAY_LINEAR_GENERAL)
385 layer_size = align(nblocksx, 64) * nblocksy * blocksize;
386 else
387 layer_size = nblocksx * nblocksy * blocksize;
388
389 if (ptex->target == PIPE_TEXTURE_CUBE) {
390 if (chipc >= R700)
391 size = layer_size * 8;
392 else
393 size = layer_size * 6;
394 }
395 else if (ptex->target == PIPE_TEXTURE_3D)
396 size = layer_size * u_minify(ptex->depth0, i);
397 else
398 size = layer_size * ptex->array_size;
399
400 /* align base image and start of miptree */
401 if ((i == 0) || (i == 1))
402 offset = align(offset, base_align);
403 rtex->offset[i] = offset;
404 rtex->layer_size[i] = layer_size;
405 rtex->pitch_in_blocks[i] = nblocksx; /* CB talks in elements */
406 rtex->pitch_in_bytes[i] = nblocksx * blocksize;
407
408 offset += size;
409 }
410 rtex->size = offset;
411 }
412
413 /* Figure out whether u_blitter will fallback to a transfer operation.
414 * If so, don't use a staging resource.
415 */
416 static boolean permit_hardware_blit(struct pipe_screen *screen,
417 const struct pipe_resource *res)
418 {
419 unsigned bind;
420
421 if (util_format_is_depth_or_stencil(res->format))
422 bind = PIPE_BIND_DEPTH_STENCIL;
423 else
424 bind = PIPE_BIND_RENDER_TARGET;
425
426 /* hackaround for S3TC */
427 if (util_format_is_compressed(res->format))
428 return TRUE;
429
430 if (!screen->is_format_supported(screen,
431 res->format,
432 res->target,
433 res->nr_samples,
434 bind))
435 return FALSE;
436
437 if (!screen->is_format_supported(screen,
438 res->format,
439 res->target,
440 res->nr_samples,
441 PIPE_BIND_SAMPLER_VIEW))
442 return FALSE;
443
444 return TRUE;
445 }
446
447 static boolean r600_texture_get_handle(struct pipe_screen* screen,
448 struct pipe_resource *ptex,
449 struct winsys_handle *whandle)
450 {
451 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
452 struct r600_resource *resource = &rtex->resource;
453 struct radeon_surface *surface = &rtex->surface;
454 struct r600_screen *rscreen = (struct r600_screen*)screen;
455
456 rscreen->ws->buffer_set_tiling(resource->buf,
457 NULL,
458 surface->level[0].mode >= RADEON_SURF_MODE_1D ?
459 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
460 surface->level[0].mode >= RADEON_SURF_MODE_2D ?
461 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
462 surface->bankw, surface->bankh,
463 surface->tile_split,
464 surface->stencil_tile_split,
465 surface->mtilea,
466 rtex->pitch_in_bytes[0]);
467
468 return rscreen->ws->buffer_get_handle(resource->buf,
469 rtex->pitch_in_bytes[0], whandle);
470 }
471
472 static void r600_texture_destroy(struct pipe_screen *screen,
473 struct pipe_resource *ptex)
474 {
475 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
476 struct r600_resource *resource = &rtex->resource;
477
478 if (rtex->flushed_depth_texture)
479 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
480
481 if (rtex->stencil)
482 pipe_resource_reference((struct pipe_resource **)&rtex->stencil, NULL);
483
484 pb_reference(&resource->buf, NULL);
485 FREE(rtex);
486 }
487
488 static const struct u_resource_vtbl r600_texture_vtbl =
489 {
490 r600_texture_get_handle, /* get_handle */
491 r600_texture_destroy, /* resource_destroy */
492 r600_texture_get_transfer, /* get_transfer */
493 r600_texture_transfer_destroy, /* transfer_destroy */
494 r600_texture_transfer_map, /* transfer_map */
495 NULL, /* transfer_flush_region */
496 r600_texture_transfer_unmap, /* transfer_unmap */
497 NULL /* transfer_inline_write */
498 };
499
500 static struct r600_resource_texture *
501 r600_texture_create_object(struct pipe_screen *screen,
502 const struct pipe_resource *base,
503 unsigned array_mode,
504 unsigned pitch_in_bytes_override,
505 unsigned max_buffer_size,
506 struct pb_buffer *buf,
507 boolean alloc_bo,
508 struct radeon_surface *surface)
509 {
510 struct r600_resource_texture *rtex;
511 struct r600_resource *resource;
512 struct r600_screen *rscreen = (struct r600_screen*)screen;
513 int r;
514
515 rtex = CALLOC_STRUCT(r600_resource_texture);
516 if (rtex == NULL)
517 return NULL;
518
519 resource = &rtex->resource;
520 resource->b.b = *base;
521 resource->b.vtbl = &r600_texture_vtbl;
522 pipe_reference_init(&resource->b.b.reference, 1);
523 resource->b.b.screen = screen;
524 rtex->pitch_override = pitch_in_bytes_override;
525 rtex->real_format = base->format;
526
527 /* We must split depth and stencil into two separate buffers on Evergreen. */
528 if ((base->bind & PIPE_BIND_DEPTH_STENCIL) &&
529 ((struct r600_screen*)screen)->chip_class >= EVERGREEN &&
530 util_format_is_depth_and_stencil(base->format) &&
531 !rscreen->use_surface_alloc) {
532 struct pipe_resource stencil;
533 unsigned stencil_pitch_override = 0;
534
535 switch (base->format) {
536 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
537 rtex->real_format = PIPE_FORMAT_Z24X8_UNORM;
538 break;
539 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
540 rtex->real_format = PIPE_FORMAT_X8Z24_UNORM;
541 break;
542 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
543 rtex->real_format = PIPE_FORMAT_Z32_FLOAT;
544 break;
545 default:
546 assert(0);
547 FREE(rtex);
548 return NULL;
549 }
550
551 /* Divide the pitch in bytes by 4 for stencil, because it has a smaller pixel size. */
552 if (pitch_in_bytes_override) {
553 assert(base->format == PIPE_FORMAT_Z24_UNORM_S8_UINT ||
554 base->format == PIPE_FORMAT_S8_UINT_Z24_UNORM);
555 stencil_pitch_override = pitch_in_bytes_override / 4;
556 }
557
558 /* Allocate the stencil buffer. */
559 stencil = *base;
560 stencil.format = PIPE_FORMAT_S8_UINT;
561 rtex->stencil = r600_texture_create_object(screen, &stencil, array_mode,
562 stencil_pitch_override,
563 max_buffer_size, NULL, FALSE, surface);
564 if (!rtex->stencil) {
565 FREE(rtex);
566 return NULL;
567 }
568 /* Proceed in creating the depth buffer. */
569 }
570
571 /* only mark depth textures the HW can hit as depth textures */
572 if (util_format_is_depth_or_stencil(rtex->real_format) &&
573 permit_hardware_blit(screen, base))
574 rtex->is_depth = true;
575
576 r600_setup_miptree(screen, rtex, array_mode);
577 if (rscreen->use_surface_alloc) {
578 rtex->surface = *surface;
579 r = r600_setup_surface(screen, rtex, array_mode,
580 pitch_in_bytes_override);
581 if (r) {
582 FREE(rtex);
583 return NULL;
584 }
585 }
586
587 /* If we initialized separate stencil for Evergreen. place it after depth. */
588 if (rtex->stencil) {
589 unsigned stencil_align, stencil_offset;
590
591 stencil_align = r600_get_base_alignment(screen, rtex->stencil->real_format, array_mode);
592 stencil_offset = align(rtex->size, stencil_align);
593
594 for (unsigned i = 0; i <= rtex->stencil->resource.b.b.last_level; i++)
595 rtex->stencil->offset[i] += stencil_offset;
596
597 rtex->size = stencil_offset + rtex->stencil->size;
598 }
599
600 /* Now create the backing buffer. */
601 if (!buf && alloc_bo) {
602 struct pipe_resource *ptex = &rtex->resource.b.b;
603 unsigned base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
604
605 if (rscreen->use_surface_alloc) {
606 base_align = rtex->surface.bo_alignment;
607 } else if (util_format_is_depth_or_stencil(rtex->real_format)) {
608 /* ugly work around depth buffer need stencil room at end of bo */
609 rtex->size += ptex->width0 * ptex->height0;
610 }
611 if (!r600_init_resource(rscreen, resource, rtex->size, base_align, base->bind, base->usage)) {
612 pipe_resource_reference((struct pipe_resource**)&rtex->stencil, NULL);
613 FREE(rtex);
614 return NULL;
615 }
616 } else if (buf) {
617 resource->buf = buf;
618 resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);
619 resource->domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM;
620 }
621
622 if (rtex->stencil) {
623 pb_reference(&rtex->stencil->resource.buf, rtex->resource.buf);
624 rtex->stencil->resource.cs_buf = rtex->resource.cs_buf;
625 rtex->stencil->resource.domains = rtex->resource.domains;
626 }
627 return rtex;
628 }
629
630 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
631 const struct pipe_resource *templ)
632 {
633 struct r600_screen *rscreen = (struct r600_screen*)screen;
634 struct radeon_surface surface;
635 unsigned array_mode = 0;
636 int r;
637
638 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER)) {
639 if (rscreen->use_surface_alloc &&
640 !(templ->bind & PIPE_BIND_SCANOUT) &&
641 templ->usage != PIPE_USAGE_STAGING &&
642 templ->usage != PIPE_USAGE_STREAM &&
643 permit_hardware_blit(screen, templ)) {
644 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
645 } else if (util_format_is_compressed(templ->format)) {
646 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
647 }
648 }
649
650 r = r600_init_surface(&surface, templ, array_mode,
651 templ->flags & R600_RESOURCE_FLAG_TRANSFER,
652 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
653 if (r) {
654 return NULL;
655 }
656 r = rscreen->ws->surface_best(rscreen->ws, &surface);
657 if (r) {
658 return NULL;
659 }
660 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
661 0, 0, NULL, TRUE, &surface);
662 }
663
664 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
665 struct pipe_resource *texture,
666 const struct pipe_surface *surf_tmpl)
667 {
668 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
669 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
670 unsigned level = surf_tmpl->u.tex.level;
671
672 assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
673 if (surface == NULL)
674 return NULL;
675 pipe_reference_init(&surface->base.reference, 1);
676 pipe_resource_reference(&surface->base.texture, texture);
677 surface->base.context = pipe;
678 surface->base.format = surf_tmpl->format;
679 surface->base.width = mip_minify(texture->width0, level);
680 surface->base.height = mip_minify(texture->height0, level);
681 surface->base.usage = surf_tmpl->usage;
682 surface->base.texture = texture;
683 surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
684 surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
685 surface->base.u.tex.level = level;
686
687 surface->aligned_height = r600_texture_get_nblocksy(pipe->screen,
688 rtex, level);
689 return &surface->base;
690 }
691
692 static void r600_surface_destroy(struct pipe_context *pipe,
693 struct pipe_surface *surface)
694 {
695 pipe_resource_reference(&surface->texture, NULL);
696 FREE(surface);
697 }
698
699 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
700 const struct pipe_resource *templ,
701 struct winsys_handle *whandle)
702 {
703 struct r600_screen *rscreen = (struct r600_screen*)screen;
704 struct pb_buffer *buf = NULL;
705 unsigned stride = 0;
706 unsigned array_mode = 0;
707 enum radeon_bo_layout micro, macro;
708 struct radeon_surface surface;
709 int r;
710
711 /* Support only 2D textures without mipmaps */
712 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
713 templ->depth0 != 1 || templ->last_level != 0)
714 return NULL;
715
716 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
717 if (!buf)
718 return NULL;
719
720 rscreen->ws->buffer_get_tiling(buf, &micro, &macro,
721 &surface.bankw, &surface.bankh,
722 &surface.tile_split,
723 &surface.stencil_tile_split,
724 &surface.mtilea);
725
726 if (macro == RADEON_LAYOUT_TILED)
727 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
728 else if (micro == RADEON_LAYOUT_TILED)
729 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
730 else
731 array_mode = 0;
732
733 r = r600_init_surface(&surface, templ, array_mode, false, false);
734 if (r) {
735 return NULL;
736 }
737 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
738 stride, 0, buf, FALSE, &surface);
739 }
740
741 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
742 struct pipe_resource *texture,
743 struct r600_resource_texture **staging)
744 {
745 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
746 struct pipe_resource resource;
747 struct r600_resource_texture **flushed_depth_texture = staging ?
748 staging : &rtex->flushed_depth_texture;
749
750 if (!staging && rtex->flushed_depth_texture)
751 return true; /* it's ready */
752
753 resource.target = texture->target;
754 resource.format = texture->format;
755 resource.width0 = texture->width0;
756 resource.height0 = texture->height0;
757 resource.depth0 = texture->depth0;
758 resource.array_size = texture->array_size;
759 resource.last_level = texture->last_level;
760 resource.nr_samples = texture->nr_samples;
761 resource.usage = staging ? PIPE_USAGE_DYNAMIC : PIPE_USAGE_DEFAULT;
762 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
763 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
764
765 if (staging)
766 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
767
768 *flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
769 if (*flushed_depth_texture == NULL) {
770 R600_ERR("failed to create temporary texture to hold flushed depth\n");
771 return false;
772 }
773
774 (*flushed_depth_texture)->is_flushing_texture = TRUE;
775 return true;
776 }
777
778 /* Needs adjustment for pixelformat:
779 */
780 static INLINE unsigned u_box_volume( const struct pipe_box *box )
781 {
782 return box->width * box->depth * box->height;
783 }
784
785 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
786 struct pipe_resource *texture,
787 unsigned level,
788 unsigned usage,
789 const struct pipe_box *box)
790 {
791 struct r600_context *rctx = (struct r600_context*)ctx;
792 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
793 struct pipe_resource resource;
794 struct r600_transfer *trans;
795 boolean use_staging_texture = FALSE;
796
797 /* We cannot map a tiled texture directly because the data is
798 * in a different order, therefore we do detiling using a blit.
799 *
800 * Also, use a temporary in GTT memory for read transfers, as
801 * the CPU is much happier reading out of cached system memory
802 * than uncached VRAM.
803 */
804 if (R600_TEX_IS_TILED(rtex, level)) {
805 use_staging_texture = TRUE;
806 }
807
808 if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024)
809 use_staging_texture = TRUE;
810
811 /* Use a staging texture for uploads if the underlying BO is busy. */
812 if (!(usage & PIPE_TRANSFER_READ) &&
813 (rctx->ws->cs_is_buffer_referenced(rctx->cs, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) ||
814 rctx->ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE))) {
815 use_staging_texture = TRUE;
816 }
817
818 if (!permit_hardware_blit(ctx->screen, texture) ||
819 (texture->flags & R600_RESOURCE_FLAG_TRANSFER)) {
820 use_staging_texture = FALSE;
821 }
822
823 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) {
824 return NULL;
825 }
826
827 trans = CALLOC_STRUCT(r600_transfer);
828 if (trans == NULL)
829 return NULL;
830 pipe_resource_reference(&trans->transfer.resource, texture);
831 trans->transfer.level = level;
832 trans->transfer.usage = usage;
833 trans->transfer.box = *box;
834 if (rtex->is_depth) {
835 /* XXX: only readback the rectangle which is being mapped?
836 */
837 /* XXX: when discard is true, no need to read back from depth texture
838 */
839 struct r600_resource_texture *staging_depth;
840
841 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
842 R600_ERR("failed to create temporary texture to hold untiled copy\n");
843 pipe_resource_reference(&trans->transfer.resource, NULL);
844 FREE(trans);
845 return NULL;
846 }
847
848 r600_blit_uncompress_depth(ctx, rtex, staging_depth,
849 level, level,
850 box->z, box->z + box->depth - 1);
851
852 trans->transfer.stride = staging_depth->pitch_in_bytes[level];
853 trans->offset = r600_texture_get_offset(staging_depth, level, box->z);
854 trans->staging = (struct r600_resource*)staging_depth;
855 return &trans->transfer;
856 } else if (use_staging_texture) {
857 resource.target = PIPE_TEXTURE_2D;
858 resource.format = texture->format;
859 resource.width0 = box->width;
860 resource.height0 = box->height;
861 resource.depth0 = 1;
862 resource.array_size = 1;
863 resource.last_level = 0;
864 resource.nr_samples = 0;
865 resource.usage = PIPE_USAGE_STAGING;
866 resource.bind = 0;
867 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
868 /* For texture reading, the temporary (detiled) texture is used as
869 * a render target when blitting from a tiled texture. */
870 if (usage & PIPE_TRANSFER_READ) {
871 resource.bind |= PIPE_BIND_RENDER_TARGET;
872 }
873 /* For texture writing, the temporary texture is used as a sampler
874 * when blitting into a tiled texture. */
875 if (usage & PIPE_TRANSFER_WRITE) {
876 resource.bind |= PIPE_BIND_SAMPLER_VIEW;
877 }
878 /* Create the temporary texture. */
879 trans->staging = (struct r600_resource*)ctx->screen->resource_create(ctx->screen, &resource);
880 if (trans->staging == NULL) {
881 R600_ERR("failed to create temporary texture to hold untiled copy\n");
882 pipe_resource_reference(&trans->transfer.resource, NULL);
883 FREE(trans);
884 return NULL;
885 }
886
887 trans->transfer.stride =
888 ((struct r600_resource_texture *)trans->staging)->pitch_in_bytes[0];
889 if (usage & PIPE_TRANSFER_READ) {
890 r600_copy_to_staging_texture(ctx, trans);
891 /* Always referenced in the blit. */
892 r600_flush(ctx, NULL, 0);
893 }
894 return &trans->transfer;
895 }
896 trans->transfer.stride = rtex->pitch_in_bytes[level];
897 trans->transfer.layer_stride = rtex->layer_size[level];
898 trans->offset = r600_texture_get_offset(rtex, level, box->z);
899 return &trans->transfer;
900 }
901
902 void r600_texture_transfer_destroy(struct pipe_context *ctx,
903 struct pipe_transfer *transfer)
904 {
905 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
906 struct pipe_resource *texture = transfer->resource;
907 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
908
909 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
910 if (rtex->is_depth) {
911 ctx->resource_copy_region(ctx, texture, transfer->level,
912 transfer->box.x, transfer->box.y, transfer->box.z,
913 &rtransfer->staging->b.b, transfer->level,
914 &transfer->box);
915 } else {
916 r600_copy_from_staging_texture(ctx, rtransfer);
917 }
918 }
919
920 if (rtransfer->staging)
921 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
922
923 pipe_resource_reference(&transfer->resource, NULL);
924 FREE(transfer);
925 }
926
927 void* r600_texture_transfer_map(struct pipe_context *ctx,
928 struct pipe_transfer* transfer)
929 {
930 struct r600_context *rctx = (struct r600_context *)ctx;
931 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
932 struct radeon_winsys_cs_handle *buf;
933 struct r600_resource_texture *rtex =
934 (struct r600_resource_texture*)transfer->resource;
935 enum pipe_format format = transfer->resource->format;
936 unsigned offset = 0;
937 char *map;
938
939 if ((transfer->resource->bind & PIPE_BIND_GLOBAL) && transfer->resource->target == PIPE_BUFFER) {
940 return r600_compute_global_transfer_map(ctx, transfer);
941 }
942
943 if (rtransfer->staging) {
944 buf = ((struct r600_resource *)rtransfer->staging)->cs_buf;
945 } else {
946 buf = ((struct r600_resource *)transfer->resource)->cs_buf;
947 }
948
949 if (rtex->is_depth || !rtransfer->staging)
950 offset = rtransfer->offset +
951 transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
952 transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
953
954 if (!(map = rctx->ws->buffer_map(buf, rctx->cs, transfer->usage))) {
955 return NULL;
956 }
957
958 return map + offset;
959 }
960
961 void r600_texture_transfer_unmap(struct pipe_context *ctx,
962 struct pipe_transfer* transfer)
963 {
964 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
965 struct r600_context *rctx = (struct r600_context*)ctx;
966 struct radeon_winsys_cs_handle *buf;
967
968 if ((transfer->resource->bind & PIPE_BIND_GLOBAL) && transfer->resource->target == PIPE_BUFFER) {
969 return r600_compute_global_transfer_unmap(ctx, transfer);
970 }
971
972 if (rtransfer->staging) {
973 buf = ((struct r600_resource *)rtransfer->staging)->cs_buf;
974 } else {
975 buf = ((struct r600_resource *)transfer->resource)->cs_buf;
976 }
977 rctx->ws->buffer_unmap(buf);
978 }
979
980 void r600_init_surface_functions(struct r600_context *r600)
981 {
982 r600->context.create_surface = r600_create_surface;
983 r600->context.surface_destroy = r600_surface_destroy;
984 }
985
986 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
987 const unsigned char *swizzle_view)
988 {
989 unsigned i;
990 unsigned char swizzle[4];
991 unsigned result = 0;
992 const uint32_t swizzle_shift[4] = {
993 16, 19, 22, 25,
994 };
995 const uint32_t swizzle_bit[4] = {
996 0, 1, 2, 3,
997 };
998
999 if (swizzle_view) {
1000 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
1001 } else {
1002 memcpy(swizzle, swizzle_format, 4);
1003 }
1004
1005 /* Get swizzle. */
1006 for (i = 0; i < 4; i++) {
1007 switch (swizzle[i]) {
1008 case UTIL_FORMAT_SWIZZLE_Y:
1009 result |= swizzle_bit[1] << swizzle_shift[i];
1010 break;
1011 case UTIL_FORMAT_SWIZZLE_Z:
1012 result |= swizzle_bit[2] << swizzle_shift[i];
1013 break;
1014 case UTIL_FORMAT_SWIZZLE_W:
1015 result |= swizzle_bit[3] << swizzle_shift[i];
1016 break;
1017 case UTIL_FORMAT_SWIZZLE_0:
1018 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
1019 break;
1020 case UTIL_FORMAT_SWIZZLE_1:
1021 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
1022 break;
1023 default: /* UTIL_FORMAT_SWIZZLE_X */
1024 result |= swizzle_bit[0] << swizzle_shift[i];
1025 }
1026 }
1027 return result;
1028 }
1029
1030 /* texture format translate */
1031 uint32_t r600_translate_texformat(struct pipe_screen *screen,
1032 enum pipe_format format,
1033 const unsigned char *swizzle_view,
1034 uint32_t *word4_p, uint32_t *yuv_format_p)
1035 {
1036 uint32_t result = 0, word4 = 0, yuv_format = 0;
1037 const struct util_format_description *desc;
1038 boolean uniform = TRUE;
1039 static int r600_enable_s3tc = -1;
1040 bool is_srgb_valid = FALSE;
1041
1042 int i;
1043 const uint32_t sign_bit[4] = {
1044 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
1045 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
1046 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
1047 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
1048 };
1049 desc = util_format_description(format);
1050
1051 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
1052
1053 /* Colorspace (return non-RGB formats directly). */
1054 switch (desc->colorspace) {
1055 /* Depth stencil formats */
1056 case UTIL_FORMAT_COLORSPACE_ZS:
1057 switch (format) {
1058 case PIPE_FORMAT_Z16_UNORM:
1059 result = FMT_16;
1060 goto out_word4;
1061 case PIPE_FORMAT_X24S8_UINT:
1062 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1063 case PIPE_FORMAT_Z24X8_UNORM:
1064 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1065 result = FMT_8_24;
1066 goto out_word4;
1067 case PIPE_FORMAT_S8X24_UINT:
1068 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1069 case PIPE_FORMAT_X8Z24_UNORM:
1070 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1071 result = FMT_24_8;
1072 goto out_word4;
1073 case PIPE_FORMAT_S8_UINT:
1074 result = FMT_8;
1075 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1076 goto out_word4;
1077 case PIPE_FORMAT_Z32_FLOAT:
1078 result = FMT_32_FLOAT;
1079 goto out_word4;
1080 case PIPE_FORMAT_X32_S8X24_UINT:
1081 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1082 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1083 result = FMT_X24_8_32_FLOAT;
1084 goto out_word4;
1085 default:
1086 goto out_unknown;
1087 }
1088
1089 case UTIL_FORMAT_COLORSPACE_YUV:
1090 yuv_format |= (1 << 30);
1091 switch (format) {
1092 case PIPE_FORMAT_UYVY:
1093 case PIPE_FORMAT_YUYV:
1094 default:
1095 break;
1096 }
1097 goto out_unknown; /* XXX */
1098
1099 case UTIL_FORMAT_COLORSPACE_SRGB:
1100 word4 |= S_038010_FORCE_DEGAMMA(1);
1101 break;
1102
1103 default:
1104 break;
1105 }
1106
1107 if (r600_enable_s3tc == -1) {
1108 struct r600_screen *rscreen = (struct r600_screen *)screen;
1109 if (rscreen->info.drm_minor >= 9)
1110 r600_enable_s3tc = 1;
1111 else
1112 r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
1113 }
1114
1115 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1116 if (!r600_enable_s3tc)
1117 goto out_unknown;
1118
1119 switch (format) {
1120 case PIPE_FORMAT_RGTC1_SNORM:
1121 case PIPE_FORMAT_LATC1_SNORM:
1122 word4 |= sign_bit[0];
1123 case PIPE_FORMAT_RGTC1_UNORM:
1124 case PIPE_FORMAT_LATC1_UNORM:
1125 result = FMT_BC4;
1126 goto out_word4;
1127 case PIPE_FORMAT_RGTC2_SNORM:
1128 case PIPE_FORMAT_LATC2_SNORM:
1129 word4 |= sign_bit[0] | sign_bit[1];
1130 case PIPE_FORMAT_RGTC2_UNORM:
1131 case PIPE_FORMAT_LATC2_UNORM:
1132 result = FMT_BC5;
1133 goto out_word4;
1134 default:
1135 goto out_unknown;
1136 }
1137 }
1138
1139 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1140
1141 if (!r600_enable_s3tc)
1142 goto out_unknown;
1143
1144 if (!util_format_s3tc_enabled) {
1145 goto out_unknown;
1146 }
1147
1148 switch (format) {
1149 case PIPE_FORMAT_DXT1_RGB:
1150 case PIPE_FORMAT_DXT1_RGBA:
1151 case PIPE_FORMAT_DXT1_SRGB:
1152 case PIPE_FORMAT_DXT1_SRGBA:
1153 result = FMT_BC1;
1154 is_srgb_valid = TRUE;
1155 goto out_word4;
1156 case PIPE_FORMAT_DXT3_RGBA:
1157 case PIPE_FORMAT_DXT3_SRGBA:
1158 result = FMT_BC2;
1159 is_srgb_valid = TRUE;
1160 goto out_word4;
1161 case PIPE_FORMAT_DXT5_RGBA:
1162 case PIPE_FORMAT_DXT5_SRGBA:
1163 result = FMT_BC3;
1164 is_srgb_valid = TRUE;
1165 goto out_word4;
1166 default:
1167 goto out_unknown;
1168 }
1169 }
1170
1171 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1172 switch (format) {
1173 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1174 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1175 result = FMT_GB_GR;
1176 goto out_word4;
1177 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1178 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1179 result = FMT_BG_RG;
1180 goto out_word4;
1181 default:
1182 goto out_unknown;
1183 }
1184 }
1185
1186 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1187 result = FMT_5_9_9_9_SHAREDEXP;
1188 goto out_word4;
1189 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1190 result = FMT_10_11_11_FLOAT;
1191 goto out_word4;
1192 }
1193
1194
1195 for (i = 0; i < desc->nr_channels; i++) {
1196 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1197 word4 |= sign_bit[i];
1198 }
1199 }
1200
1201 /* R8G8Bx_SNORM - XXX CxV8U8 */
1202
1203 /* See whether the components are of the same size. */
1204 for (i = 1; i < desc->nr_channels; i++) {
1205 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1206 }
1207
1208 /* Non-uniform formats. */
1209 if (!uniform) {
1210 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1211 desc->channel[0].pure_integer)
1212 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1213 switch(desc->nr_channels) {
1214 case 3:
1215 if (desc->channel[0].size == 5 &&
1216 desc->channel[1].size == 6 &&
1217 desc->channel[2].size == 5) {
1218 result = FMT_5_6_5;
1219 goto out_word4;
1220 }
1221 goto out_unknown;
1222 case 4:
1223 if (desc->channel[0].size == 5 &&
1224 desc->channel[1].size == 5 &&
1225 desc->channel[2].size == 5 &&
1226 desc->channel[3].size == 1) {
1227 result = FMT_1_5_5_5;
1228 goto out_word4;
1229 }
1230 if (desc->channel[0].size == 10 &&
1231 desc->channel[1].size == 10 &&
1232 desc->channel[2].size == 10 &&
1233 desc->channel[3].size == 2) {
1234 result = FMT_2_10_10_10;
1235 goto out_word4;
1236 }
1237 goto out_unknown;
1238 }
1239 goto out_unknown;
1240 }
1241
1242 /* Find the first non-VOID channel. */
1243 for (i = 0; i < 4; i++) {
1244 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1245 break;
1246 }
1247 }
1248
1249 if (i == 4)
1250 goto out_unknown;
1251
1252 /* uniform formats */
1253 switch (desc->channel[i].type) {
1254 case UTIL_FORMAT_TYPE_UNSIGNED:
1255 case UTIL_FORMAT_TYPE_SIGNED:
1256 #if 0
1257 if (!desc->channel[i].normalized &&
1258 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
1259 goto out_unknown;
1260 }
1261 #endif
1262 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1263 desc->channel[i].pure_integer)
1264 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1265
1266 switch (desc->channel[i].size) {
1267 case 4:
1268 switch (desc->nr_channels) {
1269 case 2:
1270 result = FMT_4_4;
1271 goto out_word4;
1272 case 4:
1273 result = FMT_4_4_4_4;
1274 goto out_word4;
1275 }
1276 goto out_unknown;
1277 case 8:
1278 switch (desc->nr_channels) {
1279 case 1:
1280 result = FMT_8;
1281 goto out_word4;
1282 case 2:
1283 result = FMT_8_8;
1284 goto out_word4;
1285 case 4:
1286 result = FMT_8_8_8_8;
1287 is_srgb_valid = TRUE;
1288 goto out_word4;
1289 }
1290 goto out_unknown;
1291 case 16:
1292 switch (desc->nr_channels) {
1293 case 1:
1294 result = FMT_16;
1295 goto out_word4;
1296 case 2:
1297 result = FMT_16_16;
1298 goto out_word4;
1299 case 4:
1300 result = FMT_16_16_16_16;
1301 goto out_word4;
1302 }
1303 goto out_unknown;
1304 case 32:
1305 switch (desc->nr_channels) {
1306 case 1:
1307 result = FMT_32;
1308 goto out_word4;
1309 case 2:
1310 result = FMT_32_32;
1311 goto out_word4;
1312 case 4:
1313 result = FMT_32_32_32_32;
1314 goto out_word4;
1315 }
1316 }
1317 goto out_unknown;
1318
1319 case UTIL_FORMAT_TYPE_FLOAT:
1320 switch (desc->channel[i].size) {
1321 case 16:
1322 switch (desc->nr_channels) {
1323 case 1:
1324 result = FMT_16_FLOAT;
1325 goto out_word4;
1326 case 2:
1327 result = FMT_16_16_FLOAT;
1328 goto out_word4;
1329 case 4:
1330 result = FMT_16_16_16_16_FLOAT;
1331 goto out_word4;
1332 }
1333 goto out_unknown;
1334 case 32:
1335 switch (desc->nr_channels) {
1336 case 1:
1337 result = FMT_32_FLOAT;
1338 goto out_word4;
1339 case 2:
1340 result = FMT_32_32_FLOAT;
1341 goto out_word4;
1342 case 4:
1343 result = FMT_32_32_32_32_FLOAT;
1344 goto out_word4;
1345 }
1346 }
1347 goto out_unknown;
1348 }
1349
1350 out_word4:
1351
1352 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid)
1353 return ~0;
1354 if (word4_p)
1355 *word4_p = word4;
1356 if (yuv_format_p)
1357 *yuv_format_p = yuv_format;
1358 return result;
1359 out_unknown:
1360 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1361 return ~0;
1362 }