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[mesa.git] / src / gallium / drivers / r600 / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_formats.h"
28 #include "r600d.h"
29
30 #include <errno.h>
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33
34 /* Copy from a full GPU texture to a transfer's staging one. */
35 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
36 {
37 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
38 struct pipe_resource *texture = transfer->resource;
39
40 ctx->resource_copy_region(ctx, &rtransfer->staging->b.b,
41 0, 0, 0, 0, texture, transfer->level,
42 &transfer->box);
43 }
44
45
46 /* Copy from a transfer's staging texture to a full GPU one. */
47 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
48 {
49 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
50 struct pipe_resource *texture = transfer->resource;
51 struct pipe_box sbox;
52
53 u_box_origin_2d(transfer->box.width, transfer->box.height, &sbox);
54
55 ctx->resource_copy_region(ctx, texture, transfer->level,
56 transfer->box.x, transfer->box.y, transfer->box.z,
57 &rtransfer->staging->b.b,
58 0, &sbox);
59 }
60
61 unsigned r600_texture_get_offset(struct r600_texture *rtex,
62 unsigned level, unsigned layer)
63 {
64 return rtex->surface.level[level].offset +
65 layer * rtex->surface.level[level].slice_size;
66 }
67
68 static int r600_init_surface(struct r600_screen *rscreen,
69 struct radeon_surface *surface,
70 const struct pipe_resource *ptex,
71 unsigned array_mode,
72 bool is_transfer, bool is_flushed_depth)
73 {
74 const struct util_format_description *desc =
75 util_format_description(ptex->format);
76 bool is_depth, is_stencil;
77
78 is_depth = util_format_has_depth(desc);
79 is_stencil = util_format_has_stencil(desc);
80
81 surface->npix_x = ptex->width0;
82 surface->npix_y = ptex->height0;
83 surface->npix_z = ptex->depth0;
84 surface->blk_w = util_format_get_blockwidth(ptex->format);
85 surface->blk_h = util_format_get_blockheight(ptex->format);
86 surface->blk_d = 1;
87 surface->array_size = 1;
88 surface->last_level = ptex->last_level;
89
90 if (rscreen->chip_class >= EVERGREEN &&
91 !is_transfer && !is_flushed_depth &&
92 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
93 surface->bpe = 4; /* stencil is allocated separately on evergreen */
94 } else {
95 surface->bpe = util_format_get_blocksize(ptex->format);
96 /* align byte per element on dword */
97 if (surface->bpe == 3) {
98 surface->bpe = 4;
99 }
100 }
101
102 surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1;
103 surface->flags = 0;
104
105 switch (array_mode) {
106 case V_038000_ARRAY_1D_TILED_THIN1:
107 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
108 break;
109 case V_038000_ARRAY_2D_TILED_THIN1:
110 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
111 break;
112 case V_038000_ARRAY_LINEAR_ALIGNED:
113 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
114 break;
115 case V_038000_ARRAY_LINEAR_GENERAL:
116 default:
117 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE);
118 break;
119 }
120 switch (ptex->target) {
121 case PIPE_TEXTURE_1D:
122 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
123 break;
124 case PIPE_TEXTURE_RECT:
125 case PIPE_TEXTURE_2D:
126 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
127 break;
128 case PIPE_TEXTURE_3D:
129 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
130 break;
131 case PIPE_TEXTURE_1D_ARRAY:
132 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
133 surface->array_size = ptex->array_size;
134 break;
135 case PIPE_TEXTURE_2D_ARRAY:
136 case PIPE_TEXTURE_CUBE_ARRAY: /* cube array layout like 2d layout for now */
137 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
138 surface->array_size = ptex->array_size;
139 break;
140 case PIPE_TEXTURE_CUBE:
141 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
142 break;
143 case PIPE_BUFFER:
144 default:
145 return -EINVAL;
146 }
147 if (ptex->bind & PIPE_BIND_SCANOUT) {
148 surface->flags |= RADEON_SURF_SCANOUT;
149 }
150
151 if (!is_transfer && !is_flushed_depth && is_depth) {
152 surface->flags |= RADEON_SURF_ZBUFFER;
153
154 if (is_stencil) {
155 surface->flags |= RADEON_SURF_SBUFFER |
156 RADEON_SURF_HAS_SBUFFER_MIPTREE;
157 }
158 }
159 return 0;
160 }
161
162 static int r600_setup_surface(struct pipe_screen *screen,
163 struct r600_texture *rtex,
164 unsigned pitch_in_bytes_override)
165 {
166 struct pipe_resource *ptex = &rtex->resource.b.b;
167 struct r600_screen *rscreen = (struct r600_screen*)screen;
168 unsigned i;
169 int r;
170
171 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
172 if (r) {
173 return r;
174 }
175 rtex->size = rtex->surface.bo_size;
176 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
177 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
178 * for those
179 */
180 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
181 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
182 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
183 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
184 rtex->surface.stencil_offset =
185 rtex->surface.stencil_level[0].offset = rtex->surface.level[0].slice_size;
186 }
187 }
188 for (i = 0; i <= ptex->last_level; i++) {
189 switch (rtex->surface.level[i].mode) {
190 case RADEON_SURF_MODE_LINEAR_ALIGNED:
191 rtex->array_mode[i] = V_038000_ARRAY_LINEAR_ALIGNED;
192 break;
193 case RADEON_SURF_MODE_1D:
194 rtex->array_mode[i] = V_038000_ARRAY_1D_TILED_THIN1;
195 break;
196 case RADEON_SURF_MODE_2D:
197 rtex->array_mode[i] = V_038000_ARRAY_2D_TILED_THIN1;
198 break;
199 default:
200 case RADEON_SURF_MODE_LINEAR:
201 rtex->array_mode[i] = 0;
202 break;
203 }
204 }
205 return 0;
206 }
207
208 static boolean r600_texture_get_handle(struct pipe_screen* screen,
209 struct pipe_resource *ptex,
210 struct winsys_handle *whandle)
211 {
212 struct r600_texture *rtex = (struct r600_texture*)ptex;
213 struct r600_resource *resource = &rtex->resource;
214 struct radeon_surface *surface = &rtex->surface;
215 struct r600_screen *rscreen = (struct r600_screen*)screen;
216
217 rscreen->ws->buffer_set_tiling(resource->buf,
218 NULL,
219 surface->level[0].mode >= RADEON_SURF_MODE_1D ?
220 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
221 surface->level[0].mode >= RADEON_SURF_MODE_2D ?
222 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
223 surface->bankw, surface->bankh,
224 surface->tile_split,
225 surface->stencil_tile_split,
226 surface->mtilea,
227 rtex->surface.level[0].pitch_bytes);
228
229 return rscreen->ws->buffer_get_handle(resource->buf,
230 rtex->surface.level[0].pitch_bytes, whandle);
231 }
232
233 static void r600_texture_destroy(struct pipe_screen *screen,
234 struct pipe_resource *ptex)
235 {
236 struct r600_texture *rtex = (struct r600_texture*)ptex;
237 struct r600_resource *resource = &rtex->resource;
238
239 if (rtex->flushed_depth_texture)
240 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
241
242 pb_reference(&resource->buf, NULL);
243 FREE(rtex);
244 }
245
246 static const struct u_resource_vtbl r600_texture_vtbl;
247
248 /* The number of samples can be specified independently of the texture. */
249 void r600_texture_get_fmask_info(struct r600_screen *rscreen,
250 struct r600_texture *rtex,
251 unsigned nr_samples,
252 struct r600_fmask_info *out)
253 {
254 /* FMASK is allocated pretty much like an ordinary texture.
255 * Here we use bpe in the units of bits, not bytes. */
256 struct radeon_surface fmask = rtex->surface;
257
258 switch (nr_samples) {
259 case 2:
260 /* This should be 8,1, but we should set nsamples > 1
261 * for the allocator to treat it as a multisample surface.
262 * Let's set 4,2 then. */
263 case 4:
264 fmask.bpe = 4;
265 fmask.nsamples = 2;
266 break;
267 case 8:
268 fmask.bpe = 8;
269 fmask.nsamples = 4;
270 break;
271 case 16:
272 fmask.bpe = 16;
273 fmask.nsamples = 4;
274 break;
275 default:
276 R600_ERR("Invalid sample count for FMASK allocation.\n");
277 return;
278 }
279
280 /* R600-R700 errata? Anyway, this fixes colorbuffer corruption. */
281 if (rscreen->chip_class <= R700) {
282 fmask.bpe *= 2;
283 }
284
285 if (rscreen->chip_class >= EVERGREEN) {
286 fmask.bankh = nr_samples <= 4 ? 4 : 1;
287 }
288
289 if (rscreen->ws->surface_init(rscreen->ws, &fmask)) {
290 R600_ERR("Got error in surface_init while allocating FMASK.\n");
291 return;
292 }
293 assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
294
295 out->bank_height = fmask.bankh;
296 out->alignment = MAX2(256, fmask.bo_alignment);
297 out->size = (fmask.bo_size + 7) / 8;
298 }
299
300 static void r600_texture_allocate_fmask(struct r600_screen *rscreen,
301 struct r600_texture *rtex)
302 {
303 struct r600_fmask_info fmask;
304
305 r600_texture_get_fmask_info(rscreen, rtex,
306 rtex->resource.b.b.nr_samples, &fmask);
307
308 /* Reserve space for FMASK while converting bits back to bytes. */
309 rtex->fmask_bank_height = fmask.bank_height;
310 rtex->fmask_offset = align(rtex->size, fmask.alignment);
311 rtex->fmask_size = fmask.size;
312 rtex->size = rtex->fmask_offset + rtex->fmask_size;
313 #if 0
314 printf("FMASK width=%u, height=%i, bits=%u, size=%u\n",
315 fmask.npix_x, fmask.npix_y, fmask.bpe * fmask.nsamples, rtex->fmask_size);
316 #endif
317 }
318
319 void r600_texture_get_cmask_info(struct r600_screen *rscreen,
320 struct r600_texture *rtex,
321 struct r600_cmask_info *out)
322 {
323 unsigned cmask_tile_width = 8;
324 unsigned cmask_tile_height = 8;
325 unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
326 unsigned element_bits = 4;
327 unsigned cmask_cache_bits = 1024;
328 unsigned num_pipes = rscreen->tiling_info.num_channels;
329 unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
330
331 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
332 unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
333 unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
334 unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
335 unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
336
337 unsigned pitch_elements = align(rtex->surface.npix_x, macro_tile_width);
338 unsigned height = align(rtex->surface.npix_y, macro_tile_height);
339
340 unsigned base_align = num_pipes * pipe_interleave_bytes;
341 unsigned slice_bytes =
342 ((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
343
344 assert(macro_tile_width % 128 == 0);
345 assert(macro_tile_height % 128 == 0);
346
347 out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
348 out->alignment = MAX2(256, base_align);
349 out->size = rtex->surface.array_size * align(slice_bytes, base_align);
350 }
351
352 static void r600_texture_allocate_cmask(struct r600_screen *rscreen,
353 struct r600_texture *rtex)
354 {
355 struct r600_cmask_info cmask;
356
357 r600_texture_get_cmask_info(rscreen, rtex, &cmask);
358
359 rtex->cmask_slice_tile_max = cmask.slice_tile_max;
360 rtex->cmask_offset = align(rtex->size, cmask.alignment);
361 rtex->cmask_size = cmask.size;
362 rtex->size = rtex->cmask_offset + rtex->cmask_size;
363 #if 0
364 printf("CMASK: macro tile width = %u, macro tile height = %u, "
365 "pitch elements = %u, height = %u, slice tile max = %u\n",
366 macro_tile_width, macro_tile_height, pitch_elements, height,
367 rtex->cmask_slice_tile_max);
368 #endif
369 }
370
371 DEBUG_GET_ONCE_BOOL_OPTION(print_texdepth, "R600_PRINT_TEXDEPTH", FALSE);
372
373 static struct r600_texture *
374 r600_texture_create_object(struct pipe_screen *screen,
375 const struct pipe_resource *base,
376 unsigned pitch_in_bytes_override,
377 struct pb_buffer *buf,
378 boolean alloc_bo,
379 struct radeon_surface *surface)
380 {
381 struct r600_texture *rtex;
382 struct r600_resource *resource;
383 struct r600_screen *rscreen = (struct r600_screen*)screen;
384 int r;
385
386 rtex = CALLOC_STRUCT(r600_texture);
387 if (rtex == NULL)
388 return NULL;
389
390 resource = &rtex->resource;
391 resource->b.b = *base;
392 resource->b.vtbl = &r600_texture_vtbl;
393 pipe_reference_init(&resource->b.b.reference, 1);
394 resource->b.b.screen = screen;
395 rtex->pitch_override = pitch_in_bytes_override;
396
397 /* don't include stencil-only formats which we don't support for rendering */
398 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
399
400 rtex->surface = *surface;
401 r = r600_setup_surface(screen, rtex,
402 pitch_in_bytes_override);
403 if (r) {
404 FREE(rtex);
405 return NULL;
406 }
407
408 if (base->nr_samples > 1 && !rtex->is_depth && alloc_bo) {
409 r600_texture_allocate_cmask(rscreen, rtex);
410 r600_texture_allocate_fmask(rscreen, rtex);
411 }
412
413 if (!rtex->is_depth && base->nr_samples > 1 &&
414 (!rtex->fmask_size || !rtex->cmask_size)) {
415 FREE(rtex);
416 return NULL;
417 }
418
419 /* Tiled depth textures utilize the non-displayable tile order. */
420 rtex->non_disp_tiling = rtex->is_depth && rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D;
421
422 /* Now create the backing buffer. */
423 if (!buf && alloc_bo) {
424 unsigned base_align = rtex->surface.bo_alignment;
425 unsigned usage = R600_TEX_IS_TILED(rtex, 0) ? PIPE_USAGE_STATIC : base->usage;
426
427 if (!r600_init_resource(rscreen, resource, rtex->size, base_align, base->bind, usage)) {
428 FREE(rtex);
429 return NULL;
430 }
431 } else if (buf) {
432 /* This is usually the window framebuffer. We want it in VRAM, always. */
433 resource->buf = buf;
434 resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);
435 resource->domains = RADEON_DOMAIN_VRAM;
436 }
437
438 if (rtex->cmask_size) {
439 /* Initialize the cmask to 0xCC (= compressed state). */
440 char *ptr = rscreen->ws->buffer_map(resource->cs_buf, NULL, PIPE_TRANSFER_WRITE);
441 memset(ptr + rtex->cmask_offset, 0xCC, rtex->cmask_size);
442 rscreen->ws->buffer_unmap(resource->cs_buf);
443 }
444
445 if (debug_get_option_print_texdepth() && rtex->is_depth && rtex->non_disp_tiling) {
446 printf("Texture: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
447 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
448 "bpe=%u, nsamples=%u, flags=%u\n",
449 rtex->surface.npix_x, rtex->surface.npix_y,
450 rtex->surface.npix_z, rtex->surface.blk_w,
451 rtex->surface.blk_h, rtex->surface.blk_d,
452 rtex->surface.array_size, rtex->surface.last_level,
453 rtex->surface.bpe, rtex->surface.nsamples,
454 rtex->surface.flags);
455 if (rtex->surface.flags & RADEON_SURF_ZBUFFER) {
456 for (int i = 0; i <= rtex->surface.last_level; i++) {
457 printf(" Z %i: offset=%llu, slice_size=%llu, npix_x=%u, "
458 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
459 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
460 i, (unsigned long long)rtex->surface.level[i].offset,
461 (unsigned long long)rtex->surface.level[i].slice_size,
462 rtex->surface.level[i].npix_x,
463 rtex->surface.level[i].npix_y,
464 rtex->surface.level[i].npix_z,
465 rtex->surface.level[i].nblk_x,
466 rtex->surface.level[i].nblk_y,
467 rtex->surface.level[i].nblk_z,
468 rtex->surface.level[i].pitch_bytes,
469 rtex->surface.level[i].mode);
470 }
471 }
472 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
473 for (int i = 0; i <= rtex->surface.last_level; i++) {
474 printf(" S %i: offset=%llu, slice_size=%llu, npix_x=%u, "
475 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
476 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
477 i, (unsigned long long)rtex->surface.stencil_level[i].offset,
478 (unsigned long long)rtex->surface.stencil_level[i].slice_size,
479 rtex->surface.stencil_level[i].npix_x,
480 rtex->surface.stencil_level[i].npix_y,
481 rtex->surface.stencil_level[i].npix_z,
482 rtex->surface.stencil_level[i].nblk_x,
483 rtex->surface.stencil_level[i].nblk_y,
484 rtex->surface.stencil_level[i].nblk_z,
485 rtex->surface.stencil_level[i].pitch_bytes,
486 rtex->surface.stencil_level[i].mode);
487 }
488 }
489 }
490 return rtex;
491 }
492
493 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
494 const struct pipe_resource *templ)
495 {
496 struct r600_screen *rscreen = (struct r600_screen*)screen;
497 struct radeon_surface surface;
498 unsigned array_mode = 0;
499 int r;
500
501 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER)) {
502 if (!(templ->bind & PIPE_BIND_SCANOUT) &&
503 templ->usage != PIPE_USAGE_STAGING &&
504 templ->usage != PIPE_USAGE_STREAM) {
505 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
506 } else if (util_format_is_compressed(templ->format)) {
507 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
508 }
509 }
510
511 /* XXX tiling is broken for the 422 formats */
512 if (util_format_description(templ->format)->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED)
513 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
514
515 r = r600_init_surface(rscreen, &surface, templ, array_mode,
516 templ->flags & R600_RESOURCE_FLAG_TRANSFER,
517 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
518 if (r) {
519 return NULL;
520 }
521 r = rscreen->ws->surface_best(rscreen->ws, &surface);
522 if (r) {
523 return NULL;
524 }
525 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
526 0, NULL, TRUE, &surface);
527 }
528
529 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
530 struct pipe_resource *texture,
531 const struct pipe_surface *templ,
532 unsigned width, unsigned height)
533 {
534 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
535
536 assert(templ->u.tex.first_layer == templ->u.tex.last_layer);
537 if (surface == NULL)
538 return NULL;
539 pipe_reference_init(&surface->base.reference, 1);
540 pipe_resource_reference(&surface->base.texture, texture);
541 surface->base.context = pipe;
542 surface->base.format = templ->format;
543 surface->base.width = width;
544 surface->base.height = height;
545 surface->base.usage = templ->usage;
546 surface->base.u = templ->u;
547 return &surface->base;
548 }
549
550 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
551 struct pipe_resource *texture,
552 const struct pipe_surface *templ)
553 {
554 struct r600_texture *rtex = (struct r600_texture*)texture;
555 unsigned level = templ->u.tex.level;
556
557 return r600_create_surface_custom(pipe, texture, templ,
558 rtex->surface.level[level].npix_x,
559 rtex->surface.level[level].npix_y);
560 }
561
562 static void r600_surface_destroy(struct pipe_context *pipe,
563 struct pipe_surface *surface)
564 {
565 struct r600_surface *surf = (struct r600_surface*)surface;
566 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, NULL);
567 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, NULL);
568 pipe_resource_reference(&surface->texture, NULL);
569 FREE(surface);
570 }
571
572 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
573 const struct pipe_resource *templ,
574 struct winsys_handle *whandle)
575 {
576 struct r600_screen *rscreen = (struct r600_screen*)screen;
577 struct pb_buffer *buf = NULL;
578 unsigned stride = 0;
579 unsigned array_mode = 0;
580 enum radeon_bo_layout micro, macro;
581 struct radeon_surface surface;
582 int r;
583
584 /* Support only 2D textures without mipmaps */
585 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
586 templ->depth0 != 1 || templ->last_level != 0)
587 return NULL;
588
589 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
590 if (!buf)
591 return NULL;
592
593 rscreen->ws->buffer_get_tiling(buf, &micro, &macro,
594 &surface.bankw, &surface.bankh,
595 &surface.tile_split,
596 &surface.stencil_tile_split,
597 &surface.mtilea);
598
599 if (macro == RADEON_LAYOUT_TILED)
600 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
601 else if (micro == RADEON_LAYOUT_TILED)
602 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
603 else
604 array_mode = 0;
605
606 r = r600_init_surface(rscreen, &surface, templ, array_mode, false, false);
607 if (r) {
608 return NULL;
609 }
610 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
611 stride, buf, FALSE, &surface);
612 }
613
614 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
615 struct pipe_resource *texture,
616 struct r600_texture **staging)
617 {
618 struct r600_texture *rtex = (struct r600_texture*)texture;
619 struct pipe_resource resource;
620 struct r600_texture **flushed_depth_texture = staging ?
621 staging : &rtex->flushed_depth_texture;
622
623 if (!staging && rtex->flushed_depth_texture)
624 return true; /* it's ready */
625
626 resource.target = texture->target;
627 resource.format = texture->format;
628 resource.width0 = texture->width0;
629 resource.height0 = texture->height0;
630 resource.depth0 = texture->depth0;
631 resource.array_size = texture->array_size;
632 resource.last_level = texture->last_level;
633 resource.nr_samples = texture->nr_samples;
634 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_STATIC;
635 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
636 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
637
638 if (staging)
639 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
640
641 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
642 if (*flushed_depth_texture == NULL) {
643 R600_ERR("failed to create temporary texture to hold flushed depth\n");
644 return false;
645 }
646
647 (*flushed_depth_texture)->is_flushing_texture = TRUE;
648 (*flushed_depth_texture)->non_disp_tiling = false;
649 return true;
650 }
651
652 static void *r600_texture_transfer_map(struct pipe_context *ctx,
653 struct pipe_resource *texture,
654 unsigned level,
655 unsigned usage,
656 const struct pipe_box *box,
657 struct pipe_transfer **ptransfer)
658 {
659 struct r600_context *rctx = (struct r600_context*)ctx;
660 struct r600_texture *rtex = (struct r600_texture*)texture;
661 struct pipe_resource resource;
662 struct r600_transfer *trans;
663 boolean use_staging_texture = FALSE;
664 enum pipe_format format = texture->format;
665 struct radeon_winsys_cs_handle *buf;
666 unsigned offset = 0;
667 char *map;
668
669 if ((texture->bind & PIPE_BIND_GLOBAL) && texture->target == PIPE_BUFFER) {
670 return r600_compute_global_transfer_map(ctx, texture, level, usage, box, ptransfer);
671 }
672
673 /* We cannot map a tiled texture directly because the data is
674 * in a different order, therefore we do detiling using a blit.
675 *
676 * Also, use a temporary in GTT memory for read transfers, as
677 * the CPU is much happier reading out of cached system memory
678 * than uncached VRAM.
679 */
680 if (R600_TEX_IS_TILED(rtex, level)) {
681 use_staging_texture = TRUE;
682 }
683
684 /* Use a staging texture for uploads if the underlying BO is busy. */
685 if (!(usage & PIPE_TRANSFER_READ) &&
686 (rctx->ws->cs_is_buffer_referenced(rctx->cs, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) ||
687 rctx->ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE))) {
688 use_staging_texture = TRUE;
689 }
690
691 if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) {
692 use_staging_texture = FALSE;
693 }
694
695 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) {
696 return NULL;
697 }
698
699 trans = CALLOC_STRUCT(r600_transfer);
700 if (trans == NULL)
701 return NULL;
702 trans->transfer.resource = texture;
703 trans->transfer.level = level;
704 trans->transfer.usage = usage;
705 trans->transfer.box = *box;
706 if (rtex->is_depth) {
707 /* XXX: only readback the rectangle which is being mapped?
708 */
709 /* XXX: when discard is true, no need to read back from depth texture
710 */
711 struct r600_texture *staging_depth;
712
713 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
714 R600_ERR("failed to create temporary texture to hold untiled copy\n");
715 FREE(trans);
716 return NULL;
717 }
718
719 r600_blit_decompress_depth(ctx, rtex, staging_depth,
720 level, level,
721 box->z, box->z + box->depth - 1,
722 0, 0);
723
724 trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
725 trans->offset = r600_texture_get_offset(staging_depth, level, box->z);
726 trans->staging = (struct r600_resource*)staging_depth;
727 } else if (use_staging_texture) {
728 resource.target = PIPE_TEXTURE_2D;
729 resource.format = texture->format;
730 resource.width0 = box->width;
731 resource.height0 = box->height;
732 resource.depth0 = 1;
733 resource.array_size = 1;
734 resource.last_level = 0;
735 resource.nr_samples = 0;
736 resource.usage = PIPE_USAGE_STAGING;
737 resource.bind = 0;
738 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
739 /* For texture reading, the temporary (detiled) texture is used as
740 * a render target when blitting from a tiled texture. */
741 if (usage & PIPE_TRANSFER_READ) {
742 resource.bind |= PIPE_BIND_RENDER_TARGET;
743 }
744 /* For texture writing, the temporary texture is used as a sampler
745 * when blitting into a tiled texture. */
746 if (usage & PIPE_TRANSFER_WRITE) {
747 resource.bind |= PIPE_BIND_SAMPLER_VIEW;
748 }
749 /* Create the temporary texture. */
750 trans->staging = (struct r600_resource*)ctx->screen->resource_create(ctx->screen, &resource);
751 if (trans->staging == NULL) {
752 R600_ERR("failed to create temporary texture to hold untiled copy\n");
753 FREE(trans);
754 return NULL;
755 }
756
757 trans->transfer.stride =
758 ((struct r600_texture *)trans->staging)->surface.level[0].pitch_bytes;
759 if (usage & PIPE_TRANSFER_READ) {
760 r600_copy_to_staging_texture(ctx, trans);
761 /* Always referenced in the blit. */
762 r600_flush(ctx, NULL, 0);
763 }
764 } else {
765 trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
766 trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
767 trans->offset = r600_texture_get_offset(rtex, level, box->z);
768 }
769
770 if (trans->staging) {
771 buf = ((struct r600_resource *)trans->staging)->cs_buf;
772 } else {
773 buf = ((struct r600_resource *)texture)->cs_buf;
774 }
775
776 if (rtex->is_depth || !trans->staging)
777 offset = trans->offset +
778 box->y / util_format_get_blockheight(format) * trans->transfer.stride +
779 box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
780
781 if (!(map = rctx->ws->buffer_map(buf, rctx->cs, usage))) {
782 pipe_resource_reference((struct pipe_resource**)&trans->staging, NULL);
783 FREE(trans);
784 return NULL;
785 }
786
787 *ptransfer = &trans->transfer;
788 return map + offset;
789 }
790
791 static void r600_texture_transfer_unmap(struct pipe_context *ctx,
792 struct pipe_transfer* transfer)
793 {
794 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
795 struct r600_context *rctx = (struct r600_context*)ctx;
796 struct radeon_winsys_cs_handle *buf;
797 struct pipe_resource *texture = transfer->resource;
798 struct r600_texture *rtex = (struct r600_texture*)texture;
799
800 if ((transfer->resource->bind & PIPE_BIND_GLOBAL) && transfer->resource->target == PIPE_BUFFER) {
801 return r600_compute_global_transfer_unmap(ctx, transfer);
802 }
803
804 if (rtransfer->staging) {
805 buf = ((struct r600_resource *)rtransfer->staging)->cs_buf;
806 } else {
807 buf = ((struct r600_resource *)transfer->resource)->cs_buf;
808 }
809 rctx->ws->buffer_unmap(buf);
810
811 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
812 if (rtex->is_depth) {
813 ctx->resource_copy_region(ctx, texture, transfer->level,
814 transfer->box.x, transfer->box.y, transfer->box.z,
815 &rtransfer->staging->b.b, transfer->level,
816 &transfer->box);
817 } else {
818 r600_copy_from_staging_texture(ctx, rtransfer);
819 }
820 }
821
822 if (rtransfer->staging)
823 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
824
825 FREE(transfer);
826 }
827
828 void r600_init_surface_functions(struct r600_context *r600)
829 {
830 r600->context.create_surface = r600_create_surface;
831 r600->context.surface_destroy = r600_surface_destroy;
832 }
833
834 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
835 const unsigned char *swizzle_view)
836 {
837 unsigned i;
838 unsigned char swizzle[4];
839 unsigned result = 0;
840 const uint32_t swizzle_shift[4] = {
841 16, 19, 22, 25,
842 };
843 const uint32_t swizzle_bit[4] = {
844 0, 1, 2, 3,
845 };
846
847 if (swizzle_view) {
848 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
849 } else {
850 memcpy(swizzle, swizzle_format, 4);
851 }
852
853 /* Get swizzle. */
854 for (i = 0; i < 4; i++) {
855 switch (swizzle[i]) {
856 case UTIL_FORMAT_SWIZZLE_Y:
857 result |= swizzle_bit[1] << swizzle_shift[i];
858 break;
859 case UTIL_FORMAT_SWIZZLE_Z:
860 result |= swizzle_bit[2] << swizzle_shift[i];
861 break;
862 case UTIL_FORMAT_SWIZZLE_W:
863 result |= swizzle_bit[3] << swizzle_shift[i];
864 break;
865 case UTIL_FORMAT_SWIZZLE_0:
866 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
867 break;
868 case UTIL_FORMAT_SWIZZLE_1:
869 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
870 break;
871 default: /* UTIL_FORMAT_SWIZZLE_X */
872 result |= swizzle_bit[0] << swizzle_shift[i];
873 }
874 }
875 return result;
876 }
877
878 /* texture format translate */
879 uint32_t r600_translate_texformat(struct pipe_screen *screen,
880 enum pipe_format format,
881 const unsigned char *swizzle_view,
882 uint32_t *word4_p, uint32_t *yuv_format_p)
883 {
884 uint32_t result = 0, word4 = 0, yuv_format = 0;
885 const struct util_format_description *desc;
886 boolean uniform = TRUE;
887 static int r600_enable_s3tc = -1;
888 bool is_srgb_valid = FALSE;
889
890 int i;
891 const uint32_t sign_bit[4] = {
892 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
893 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
894 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
895 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
896 };
897 desc = util_format_description(format);
898
899 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
900
901 /* Colorspace (return non-RGB formats directly). */
902 switch (desc->colorspace) {
903 /* Depth stencil formats */
904 case UTIL_FORMAT_COLORSPACE_ZS:
905 switch (format) {
906 case PIPE_FORMAT_Z16_UNORM:
907 result = FMT_16;
908 goto out_word4;
909 case PIPE_FORMAT_X24S8_UINT:
910 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
911 case PIPE_FORMAT_Z24X8_UNORM:
912 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
913 result = FMT_8_24;
914 goto out_word4;
915 case PIPE_FORMAT_S8X24_UINT:
916 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
917 case PIPE_FORMAT_X8Z24_UNORM:
918 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
919 result = FMT_24_8;
920 goto out_word4;
921 case PIPE_FORMAT_S8_UINT:
922 result = FMT_8;
923 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
924 goto out_word4;
925 case PIPE_FORMAT_Z32_FLOAT:
926 result = FMT_32_FLOAT;
927 goto out_word4;
928 case PIPE_FORMAT_X32_S8X24_UINT:
929 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
930 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
931 result = FMT_X24_8_32_FLOAT;
932 goto out_word4;
933 default:
934 goto out_unknown;
935 }
936
937 case UTIL_FORMAT_COLORSPACE_YUV:
938 yuv_format |= (1 << 30);
939 switch (format) {
940 case PIPE_FORMAT_UYVY:
941 case PIPE_FORMAT_YUYV:
942 default:
943 break;
944 }
945 goto out_unknown; /* XXX */
946
947 case UTIL_FORMAT_COLORSPACE_SRGB:
948 word4 |= S_038010_FORCE_DEGAMMA(1);
949 break;
950
951 default:
952 break;
953 }
954
955 if (r600_enable_s3tc == -1) {
956 struct r600_screen *rscreen = (struct r600_screen *)screen;
957 if (rscreen->info.drm_minor >= 9)
958 r600_enable_s3tc = 1;
959 else
960 r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
961 }
962
963 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
964 if (!r600_enable_s3tc)
965 goto out_unknown;
966
967 switch (format) {
968 case PIPE_FORMAT_RGTC1_SNORM:
969 case PIPE_FORMAT_LATC1_SNORM:
970 word4 |= sign_bit[0];
971 case PIPE_FORMAT_RGTC1_UNORM:
972 case PIPE_FORMAT_LATC1_UNORM:
973 result = FMT_BC4;
974 goto out_word4;
975 case PIPE_FORMAT_RGTC2_SNORM:
976 case PIPE_FORMAT_LATC2_SNORM:
977 word4 |= sign_bit[0] | sign_bit[1];
978 case PIPE_FORMAT_RGTC2_UNORM:
979 case PIPE_FORMAT_LATC2_UNORM:
980 result = FMT_BC5;
981 goto out_word4;
982 default:
983 goto out_unknown;
984 }
985 }
986
987 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
988
989 if (!r600_enable_s3tc)
990 goto out_unknown;
991
992 if (!util_format_s3tc_enabled) {
993 goto out_unknown;
994 }
995
996 switch (format) {
997 case PIPE_FORMAT_DXT1_RGB:
998 case PIPE_FORMAT_DXT1_RGBA:
999 case PIPE_FORMAT_DXT1_SRGB:
1000 case PIPE_FORMAT_DXT1_SRGBA:
1001 result = FMT_BC1;
1002 is_srgb_valid = TRUE;
1003 goto out_word4;
1004 case PIPE_FORMAT_DXT3_RGBA:
1005 case PIPE_FORMAT_DXT3_SRGBA:
1006 result = FMT_BC2;
1007 is_srgb_valid = TRUE;
1008 goto out_word4;
1009 case PIPE_FORMAT_DXT5_RGBA:
1010 case PIPE_FORMAT_DXT5_SRGBA:
1011 result = FMT_BC3;
1012 is_srgb_valid = TRUE;
1013 goto out_word4;
1014 default:
1015 goto out_unknown;
1016 }
1017 }
1018
1019 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1020 switch (format) {
1021 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1022 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1023 result = FMT_GB_GR;
1024 goto out_word4;
1025 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1026 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1027 result = FMT_BG_RG;
1028 goto out_word4;
1029 default:
1030 goto out_unknown;
1031 }
1032 }
1033
1034 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1035 result = FMT_5_9_9_9_SHAREDEXP;
1036 goto out_word4;
1037 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1038 result = FMT_10_11_11_FLOAT;
1039 goto out_word4;
1040 }
1041
1042
1043 for (i = 0; i < desc->nr_channels; i++) {
1044 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1045 word4 |= sign_bit[i];
1046 }
1047 }
1048
1049 /* R8G8Bx_SNORM - XXX CxV8U8 */
1050
1051 /* See whether the components are of the same size. */
1052 for (i = 1; i < desc->nr_channels; i++) {
1053 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1054 }
1055
1056 /* Non-uniform formats. */
1057 if (!uniform) {
1058 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1059 desc->channel[0].pure_integer)
1060 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1061 switch(desc->nr_channels) {
1062 case 3:
1063 if (desc->channel[0].size == 5 &&
1064 desc->channel[1].size == 6 &&
1065 desc->channel[2].size == 5) {
1066 result = FMT_5_6_5;
1067 goto out_word4;
1068 }
1069 goto out_unknown;
1070 case 4:
1071 if (desc->channel[0].size == 5 &&
1072 desc->channel[1].size == 5 &&
1073 desc->channel[2].size == 5 &&
1074 desc->channel[3].size == 1) {
1075 result = FMT_1_5_5_5;
1076 goto out_word4;
1077 }
1078 if (desc->channel[0].size == 10 &&
1079 desc->channel[1].size == 10 &&
1080 desc->channel[2].size == 10 &&
1081 desc->channel[3].size == 2) {
1082 result = FMT_2_10_10_10;
1083 goto out_word4;
1084 }
1085 goto out_unknown;
1086 }
1087 goto out_unknown;
1088 }
1089
1090 /* Find the first non-VOID channel. */
1091 for (i = 0; i < 4; i++) {
1092 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1093 break;
1094 }
1095 }
1096
1097 if (i == 4)
1098 goto out_unknown;
1099
1100 /* uniform formats */
1101 switch (desc->channel[i].type) {
1102 case UTIL_FORMAT_TYPE_UNSIGNED:
1103 case UTIL_FORMAT_TYPE_SIGNED:
1104 #if 0
1105 if (!desc->channel[i].normalized &&
1106 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
1107 goto out_unknown;
1108 }
1109 #endif
1110 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1111 desc->channel[i].pure_integer)
1112 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1113
1114 switch (desc->channel[i].size) {
1115 case 4:
1116 switch (desc->nr_channels) {
1117 case 2:
1118 result = FMT_4_4;
1119 goto out_word4;
1120 case 4:
1121 result = FMT_4_4_4_4;
1122 goto out_word4;
1123 }
1124 goto out_unknown;
1125 case 8:
1126 switch (desc->nr_channels) {
1127 case 1:
1128 result = FMT_8;
1129 goto out_word4;
1130 case 2:
1131 result = FMT_8_8;
1132 goto out_word4;
1133 case 4:
1134 result = FMT_8_8_8_8;
1135 is_srgb_valid = TRUE;
1136 goto out_word4;
1137 }
1138 goto out_unknown;
1139 case 16:
1140 switch (desc->nr_channels) {
1141 case 1:
1142 result = FMT_16;
1143 goto out_word4;
1144 case 2:
1145 result = FMT_16_16;
1146 goto out_word4;
1147 case 4:
1148 result = FMT_16_16_16_16;
1149 goto out_word4;
1150 }
1151 goto out_unknown;
1152 case 32:
1153 switch (desc->nr_channels) {
1154 case 1:
1155 result = FMT_32;
1156 goto out_word4;
1157 case 2:
1158 result = FMT_32_32;
1159 goto out_word4;
1160 case 4:
1161 result = FMT_32_32_32_32;
1162 goto out_word4;
1163 }
1164 }
1165 goto out_unknown;
1166
1167 case UTIL_FORMAT_TYPE_FLOAT:
1168 switch (desc->channel[i].size) {
1169 case 16:
1170 switch (desc->nr_channels) {
1171 case 1:
1172 result = FMT_16_FLOAT;
1173 goto out_word4;
1174 case 2:
1175 result = FMT_16_16_FLOAT;
1176 goto out_word4;
1177 case 4:
1178 result = FMT_16_16_16_16_FLOAT;
1179 goto out_word4;
1180 }
1181 goto out_unknown;
1182 case 32:
1183 switch (desc->nr_channels) {
1184 case 1:
1185 result = FMT_32_FLOAT;
1186 goto out_word4;
1187 case 2:
1188 result = FMT_32_32_FLOAT;
1189 goto out_word4;
1190 case 4:
1191 result = FMT_32_32_32_32_FLOAT;
1192 goto out_word4;
1193 }
1194 }
1195 goto out_unknown;
1196 }
1197
1198 out_word4:
1199
1200 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid)
1201 return ~0;
1202 if (word4_p)
1203 *word4_p = word4;
1204 if (yuv_format_p)
1205 *yuv_format_p = yuv_format;
1206 return result;
1207 out_unknown:
1208 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1209 return ~0;
1210 }
1211
1212 static const struct u_resource_vtbl r600_texture_vtbl =
1213 {
1214 r600_texture_get_handle, /* get_handle */
1215 r600_texture_destroy, /* resource_destroy */
1216 r600_texture_transfer_map, /* transfer_map */
1217 NULL, /* transfer_flush_region */
1218 r600_texture_transfer_unmap, /* transfer_unmap */
1219 NULL /* transfer_inline_write */
1220 };