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r600g: rework vertex buffer uploads
[mesa.git] / src / gallium / drivers / r600 / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include <errno.h>
28 #include <pipe/p_screen.h>
29 #include <util/u_format.h>
30 #include <util/u_math.h>
31 #include <util/u_inlines.h>
32 #include <util/u_memory.h>
33 #include "state_tracker/drm_driver.h"
34 #include "pipebuffer/pb_buffer.h"
35 #include "r600_pipe.h"
36 #include "r600_resource.h"
37 #include "r600_state_inlines.h"
38 #include "r600d.h"
39 #include "r600_formats.h"
40
41 extern struct u_resource_vtbl r600_texture_vtbl;
42
43 /* Copy from a full GPU texture to a transfer's staging one. */
44 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
45 {
46 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
47 struct pipe_resource *texture = transfer->resource;
48
49 ctx->resource_copy_region(ctx, rtransfer->staging_texture,
50 0, 0, 0, 0, texture, transfer->level,
51 &transfer->box);
52 }
53
54
55 /* Copy from a transfer's staging texture to a full GPU one. */
56 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
57 {
58 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
59 struct pipe_resource *texture = transfer->resource;
60 struct pipe_box sbox;
61
62 sbox.x = sbox.y = sbox.z = 0;
63 sbox.width = transfer->box.width;
64 sbox.height = transfer->box.height;
65 /* XXX that might be wrong */
66 sbox.depth = 1;
67 ctx->resource_copy_region(ctx, texture, transfer->level,
68 transfer->box.x, transfer->box.y, transfer->box.z,
69 rtransfer->staging_texture,
70 0, &sbox);
71
72 ctx->flush(ctx, 0, NULL);
73 }
74
75 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
76 unsigned level, unsigned layer)
77 {
78 unsigned offset = rtex->offset[level];
79
80 switch (rtex->resource.base.b.target) {
81 case PIPE_TEXTURE_3D:
82 case PIPE_TEXTURE_CUBE:
83 return offset + layer * rtex->layer_size[level];
84 default:
85 assert(layer == 0);
86 return offset;
87 }
88 }
89
90 static unsigned r600_get_pixel_alignment(struct pipe_screen *screen,
91 enum pipe_format format,
92 unsigned array_mode)
93 {
94 struct r600_screen* rscreen = (struct r600_screen *)screen;
95 unsigned pixsize = util_format_get_blocksize(format);
96 int p_align;
97
98 switch(array_mode) {
99 case V_038000_ARRAY_1D_TILED_THIN1:
100 p_align = MAX2(8,
101 ((rscreen->tiling_info->group_bytes / 8 / pixsize)));
102 break;
103 case V_038000_ARRAY_2D_TILED_THIN1:
104 p_align = MAX2(rscreen->tiling_info->num_banks,
105 (((rscreen->tiling_info->group_bytes / 8 / pixsize)) *
106 rscreen->tiling_info->num_banks)) * 8;
107 break;
108 case V_038000_ARRAY_LINEAR_GENERAL:
109 default:
110 p_align = rscreen->tiling_info->group_bytes / pixsize;
111 break;
112 }
113 return p_align;
114 }
115
116 static unsigned r600_get_height_alignment(struct pipe_screen *screen,
117 unsigned array_mode)
118 {
119 struct r600_screen* rscreen = (struct r600_screen *)screen;
120 int h_align;
121
122 switch (array_mode) {
123 case V_038000_ARRAY_2D_TILED_THIN1:
124 h_align = rscreen->tiling_info->num_channels * 8;
125 break;
126 case V_038000_ARRAY_1D_TILED_THIN1:
127 h_align = 8;
128 break;
129 default:
130 h_align = 1;
131 break;
132 }
133 return h_align;
134 }
135
136 static unsigned r600_get_base_alignment(struct pipe_screen *screen,
137 enum pipe_format format,
138 unsigned array_mode)
139 {
140 struct r600_screen* rscreen = (struct r600_screen *)screen;
141 unsigned pixsize = util_format_get_blocksize(format);
142 int p_align = r600_get_pixel_alignment(screen, format, array_mode);
143 int h_align = r600_get_height_alignment(screen, array_mode);
144 int b_align;
145
146 switch (array_mode) {
147 case V_038000_ARRAY_2D_TILED_THIN1:
148 b_align = MAX2(rscreen->tiling_info->num_banks * rscreen->tiling_info->num_channels * 8 * 8 * pixsize,
149 p_align * pixsize * h_align);
150 break;
151 case V_038000_ARRAY_1D_TILED_THIN1:
152 default:
153 b_align = rscreen->tiling_info->group_bytes;
154 break;
155 }
156 return b_align;
157 }
158
159 static unsigned mip_minify(unsigned size, unsigned level)
160 {
161 unsigned val;
162 val = u_minify(size, level);
163 if (level > 0)
164 val = util_next_power_of_two(val);
165 return val;
166 }
167
168 static unsigned r600_texture_get_stride(struct pipe_screen *screen,
169 struct r600_resource_texture *rtex,
170 unsigned level)
171 {
172 struct pipe_resource *ptex = &rtex->resource.base.b;
173 unsigned width, stride, tile_width;
174
175 if (rtex->pitch_override)
176 return rtex->pitch_override;
177
178 width = mip_minify(ptex->width0, level);
179 if (util_format_is_plain(ptex->format)) {
180 tile_width = r600_get_pixel_alignment(screen, ptex->format,
181 rtex->array_mode[level]);
182 width = align(width, tile_width);
183 }
184 stride = util_format_get_stride(ptex->format, width);
185
186 return stride;
187 }
188
189 static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen,
190 struct r600_resource_texture *rtex,
191 unsigned level)
192 {
193 struct pipe_resource *ptex = &rtex->resource.base.b;
194 unsigned height, tile_height;
195
196 height = mip_minify(ptex->height0, level);
197 if (util_format_is_plain(ptex->format)) {
198 tile_height = r600_get_height_alignment(screen,
199 rtex->array_mode[level]);
200 height = align(height, tile_height);
201 }
202 return util_format_get_nblocksy(ptex->format, height);
203 }
204
205 /* Get a width in pixels from a stride in bytes. */
206 static unsigned pitch_to_width(enum pipe_format format, unsigned pitch_in_bytes)
207 {
208 return (pitch_in_bytes / util_format_get_blocksize(format)) *
209 util_format_get_blockwidth(format);
210 }
211
212 static void r600_texture_set_array_mode(struct pipe_screen *screen,
213 struct r600_resource_texture *rtex,
214 unsigned level, unsigned array_mode)
215 {
216 struct pipe_resource *ptex = &rtex->resource.base.b;
217
218 switch (array_mode) {
219 case V_0280A0_ARRAY_LINEAR_GENERAL:
220 case V_0280A0_ARRAY_LINEAR_ALIGNED:
221 case V_0280A0_ARRAY_1D_TILED_THIN1:
222 default:
223 rtex->array_mode[level] = array_mode;
224 break;
225 case V_0280A0_ARRAY_2D_TILED_THIN1:
226 {
227 unsigned w, h, tile_height, tile_width;
228
229 tile_height = r600_get_height_alignment(screen, array_mode);
230 tile_width = r600_get_pixel_alignment(screen, ptex->format, array_mode);
231
232 w = mip_minify(ptex->width0, level);
233 h = mip_minify(ptex->height0, level);
234 if (w < tile_width || h < tile_height)
235 rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1;
236 else
237 rtex->array_mode[level] = array_mode;
238 }
239 break;
240 }
241 }
242
243 static void r600_setup_miptree(struct pipe_screen *screen,
244 struct r600_resource_texture *rtex,
245 unsigned array_mode)
246 {
247 struct pipe_resource *ptex = &rtex->resource.base.b;
248 struct radeon *radeon = (struct radeon *)screen->winsys;
249 enum chip_class chipc = r600_get_family_class(radeon);
250 unsigned pitch, size, layer_size, i, offset;
251 unsigned nblocksy;
252
253 for (i = 0, offset = 0; i <= ptex->last_level; i++) {
254 r600_texture_set_array_mode(screen, rtex, i, array_mode);
255
256 pitch = r600_texture_get_stride(screen, rtex, i);
257 nblocksy = r600_texture_get_nblocksy(screen, rtex, i);
258
259 layer_size = pitch * nblocksy;
260
261 if (ptex->target == PIPE_TEXTURE_CUBE) {
262 if (chipc >= R700)
263 size = layer_size * 8;
264 else
265 size = layer_size * 6;
266 }
267 else
268 size = layer_size * u_minify(ptex->depth0, i);
269 /* align base image and start of miptree */
270 if ((i == 0) || (i == 1))
271 offset = align(offset, r600_get_base_alignment(screen, ptex->format, array_mode));
272 rtex->offset[i] = offset;
273 rtex->layer_size[i] = layer_size;
274 rtex->pitch_in_bytes[i] = pitch;
275 rtex->pitch_in_pixels[i] = pitch_to_width(ptex->format, pitch);
276 offset += size;
277 }
278 rtex->size = offset;
279 }
280
281 static struct r600_resource_texture *
282 r600_texture_create_object(struct pipe_screen *screen,
283 const struct pipe_resource *base,
284 unsigned array_mode,
285 unsigned pitch_in_bytes_override,
286 unsigned max_buffer_size,
287 struct r600_bo *bo)
288 {
289 struct r600_resource_texture *rtex;
290 struct r600_resource *resource;
291 struct radeon *radeon = (struct radeon *)screen->winsys;
292
293 rtex = CALLOC_STRUCT(r600_resource_texture);
294 if (rtex == NULL)
295 return NULL;
296
297 resource = &rtex->resource;
298 resource->base.b = *base;
299 resource->base.vtbl = &r600_texture_vtbl;
300 pipe_reference_init(&resource->base.b.reference, 1);
301 resource->base.b.screen = screen;
302 resource->bo = bo;
303 rtex->pitch_override = pitch_in_bytes_override;
304
305 if (array_mode)
306 rtex->tiled = 1;
307 r600_setup_miptree(screen, rtex, array_mode);
308
309 resource->size = rtex->size;
310
311 if (!resource->bo) {
312 struct pipe_resource *ptex = &rtex->resource.base.b;
313 int base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
314
315 resource->bo = r600_bo(radeon, rtex->size, base_align, base->bind, base->usage);
316 if (!resource->bo) {
317 FREE(rtex);
318 return NULL;
319 }
320 }
321 return rtex;
322 }
323
324 /* Figure out whether u_blitter will fallback to a transfer operation.
325 * If so, don't use a staging resource.
326 */
327 static boolean permit_hardware_blit(struct pipe_screen *screen,
328 const struct pipe_resource *res)
329 {
330 unsigned bind;
331
332 if (util_format_is_depth_or_stencil(res->format))
333 bind = PIPE_BIND_DEPTH_STENCIL;
334 else
335 bind = PIPE_BIND_RENDER_TARGET;
336
337 /* See r600_resource_copy_region: there is something wrong
338 * with depth resource copies at the moment so avoid them for
339 * now.
340 */
341 if (util_format_get_component_bits(res->format,
342 UTIL_FORMAT_COLORSPACE_ZS,
343 0) != 0)
344 return FALSE;
345
346 if (!screen->is_format_supported(screen,
347 res->format,
348 res->target,
349 res->nr_samples,
350 bind, 0))
351 return FALSE;
352
353 if (!screen->is_format_supported(screen,
354 res->format,
355 res->target,
356 res->nr_samples,
357 PIPE_BIND_SAMPLER_VIEW, 0))
358 return FALSE;
359
360 return TRUE;
361 }
362
363 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
364 const struct pipe_resource *templ)
365 {
366 unsigned array_mode = 0;
367 static int force_tiling = -1;
368
369 /* Would like some magic "get_bool_option_once" routine.
370 */
371 if (force_tiling == -1)
372 force_tiling = debug_get_bool_option("R600_FORCE_TILING", FALSE);
373
374 if (force_tiling && permit_hardware_blit(screen, templ)) {
375 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
376 !(templ->bind & PIPE_BIND_SCANOUT)) {
377 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
378 }
379 }
380
381 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
382 0, 0, NULL);
383
384 }
385
386 static void r600_texture_destroy(struct pipe_screen *screen,
387 struct pipe_resource *ptex)
388 {
389 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
390 struct r600_resource *resource = &rtex->resource;
391 struct radeon *radeon = (struct radeon *)screen->winsys;
392
393 if (rtex->flushed_depth_texture)
394 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
395
396 if (resource->bo) {
397 r600_bo_reference(radeon, &resource->bo, NULL);
398 }
399 FREE(rtex);
400 }
401
402 static boolean r600_texture_get_handle(struct pipe_screen* screen,
403 struct pipe_resource *ptex,
404 struct winsys_handle *whandle)
405 {
406 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
407 struct r600_resource *resource = &rtex->resource;
408 struct radeon *radeon = (struct radeon *)screen->winsys;
409
410 return r600_bo_get_winsys_handle(radeon, resource->bo,
411 rtex->pitch_in_bytes[0], whandle);
412 }
413
414 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
415 struct pipe_resource *texture,
416 const struct pipe_surface *surf_tmpl)
417 {
418 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
419 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
420 unsigned tile_height;
421 unsigned level = surf_tmpl->u.tex.level;
422
423 assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
424 if (surface == NULL)
425 return NULL;
426 /* XXX no offset */
427 /* offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/
428 pipe_reference_init(&surface->base.reference, 1);
429 pipe_resource_reference(&surface->base.texture, texture);
430 surface->base.context = pipe;
431 surface->base.format = surf_tmpl->format;
432 surface->base.width = mip_minify(texture->width0, level);
433 surface->base.height = mip_minify(texture->height0, level);
434 surface->base.usage = surf_tmpl->usage;
435 surface->base.texture = texture;
436 surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
437 surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
438 surface->base.u.tex.level = level;
439
440 tile_height = r600_get_height_alignment(pipe->screen, rtex->array_mode[level]);
441 surface->aligned_height = align(surface->base.height, tile_height);
442 return &surface->base;
443 }
444
445 static void r600_surface_destroy(struct pipe_context *pipe,
446 struct pipe_surface *surface)
447 {
448 pipe_resource_reference(&surface->texture, NULL);
449 FREE(surface);
450 }
451
452
453 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
454 const struct pipe_resource *templ,
455 struct winsys_handle *whandle)
456 {
457 struct radeon *rw = (struct radeon*)screen->winsys;
458 struct r600_bo *bo = NULL;
459 unsigned array_mode = 0;
460
461 /* Support only 2D textures without mipmaps */
462 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
463 templ->depth0 != 1 || templ->last_level != 0)
464 return NULL;
465
466 bo = r600_bo_handle(rw, whandle->handle, &array_mode);
467 if (bo == NULL) {
468 return NULL;
469 }
470
471 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
472 whandle->stride,
473 0,
474 bo);
475 }
476
477 static unsigned int r600_texture_is_referenced(struct pipe_context *context,
478 struct pipe_resource *texture,
479 unsigned level, int layer)
480 {
481 /* FIXME */
482 return PIPE_REFERENCED_FOR_READ | PIPE_REFERENCED_FOR_WRITE;
483 }
484
485 int r600_texture_depth_flush(struct pipe_context *ctx,
486 struct pipe_resource *texture)
487 {
488 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
489 struct pipe_resource resource;
490
491 if (rtex->flushed_depth_texture)
492 goto out;
493
494 resource.target = PIPE_TEXTURE_2D;
495 resource.format = texture->format;
496 resource.width0 = texture->width0;
497 resource.height0 = texture->height0;
498 resource.depth0 = 1;
499 resource.last_level = 0;
500 resource.nr_samples = 0;
501 resource.usage = PIPE_USAGE_DYNAMIC;
502 resource.bind = 0;
503 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
504
505 resource.bind |= PIPE_BIND_DEPTH_STENCIL;
506
507 rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
508 if (rtex->flushed_depth_texture == NULL) {
509 R600_ERR("failed to create temporary texture to hold untiled copy\n");
510 return -ENOMEM;
511 }
512
513 out:
514 /* XXX: only do this if the depth texture has actually changed:
515 */
516 r600_blit_uncompress_depth(ctx, rtex);
517 return 0;
518 }
519
520 /* Needs adjustment for pixelformat:
521 */
522 static INLINE unsigned u_box_volume( const struct pipe_box *box )
523 {
524 return box->width * box->depth * box->height;
525 };
526
527 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
528 struct pipe_resource *texture,
529 unsigned level,
530 unsigned usage,
531 const struct pipe_box *box)
532 {
533 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
534 struct pipe_resource resource;
535 struct r600_transfer *trans;
536 int r;
537 boolean use_staging_texture = FALSE;
538
539 /* We cannot map a tiled texture directly because the data is
540 * in a different order, therefore we do detiling using a blit.
541 *
542 * Also, use a temporary in GTT memory for read transfers, as
543 * the CPU is much happier reading out of cached system memory
544 * than uncached VRAM.
545 */
546 if (rtex->tiled)
547 use_staging_texture = TRUE;
548
549 if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024)
550 use_staging_texture = TRUE;
551
552 /* XXX: Use a staging texture for uploads if the underlying BO
553 * is busy. No interface for checking that currently? so do
554 * it eagerly whenever the transfer doesn't require a readback
555 * and might block.
556 */
557 if ((usage & PIPE_TRANSFER_WRITE) &&
558 !(usage & (PIPE_TRANSFER_READ |
559 PIPE_TRANSFER_DONTBLOCK |
560 PIPE_TRANSFER_UNSYNCHRONIZED)))
561 use_staging_texture = TRUE;
562
563 if (!permit_hardware_blit(ctx->screen, texture) ||
564 (texture->flags & R600_RESOURCE_FLAG_TRANSFER))
565 use_staging_texture = FALSE;
566
567 trans = CALLOC_STRUCT(r600_transfer);
568 if (trans == NULL)
569 return NULL;
570 pipe_resource_reference(&trans->transfer.resource, texture);
571 trans->transfer.level = level;
572 trans->transfer.usage = usage;
573 trans->transfer.box = *box;
574 if (rtex->depth) {
575 /* XXX: only readback the rectangle which is being mapped?
576 */
577 /* XXX: when discard is true, no need to read back from depth texture
578 */
579 r = r600_texture_depth_flush(ctx, texture);
580 if (r < 0) {
581 R600_ERR("failed to create temporary texture to hold untiled copy\n");
582 pipe_resource_reference(&trans->transfer.resource, NULL);
583 FREE(trans);
584 return NULL;
585 }
586 } else if (use_staging_texture) {
587 resource.target = PIPE_TEXTURE_2D;
588 resource.format = texture->format;
589 resource.width0 = box->width;
590 resource.height0 = box->height;
591 resource.depth0 = 1;
592 resource.array_size = 1;
593 resource.last_level = 0;
594 resource.nr_samples = 0;
595 resource.usage = PIPE_USAGE_STAGING;
596 resource.bind = 0;
597 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
598 /* For texture reading, the temporary (detiled) texture is used as
599 * a render target when blitting from a tiled texture. */
600 if (usage & PIPE_TRANSFER_READ) {
601 resource.bind |= PIPE_BIND_RENDER_TARGET;
602 }
603 /* For texture writing, the temporary texture is used as a sampler
604 * when blitting into a tiled texture. */
605 if (usage & PIPE_TRANSFER_WRITE) {
606 resource.bind |= PIPE_BIND_SAMPLER_VIEW;
607 }
608 /* Create the temporary texture. */
609 trans->staging_texture = ctx->screen->resource_create(ctx->screen, &resource);
610 if (trans->staging_texture == NULL) {
611 R600_ERR("failed to create temporary texture to hold untiled copy\n");
612 pipe_resource_reference(&trans->transfer.resource, NULL);
613 FREE(trans);
614 return NULL;
615 }
616
617 trans->transfer.stride =
618 ((struct r600_resource_texture *)trans->staging_texture)->pitch_in_bytes[0];
619 if (usage & PIPE_TRANSFER_READ) {
620 r600_copy_to_staging_texture(ctx, trans);
621 /* Always referenced in the blit. */
622 ctx->flush(ctx, 0, NULL);
623 }
624 return &trans->transfer;
625 }
626 trans->transfer.stride = rtex->pitch_in_bytes[level];
627 trans->offset = r600_texture_get_offset(rtex, level, box->z);
628 return &trans->transfer;
629 }
630
631 void r600_texture_transfer_destroy(struct pipe_context *ctx,
632 struct pipe_transfer *transfer)
633 {
634 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
635 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
636
637 if (rtransfer->staging_texture) {
638 if (transfer->usage & PIPE_TRANSFER_WRITE) {
639 r600_copy_from_staging_texture(ctx, rtransfer);
640 }
641 pipe_resource_reference(&rtransfer->staging_texture, NULL);
642 }
643 if (rtex->flushed_depth_texture) {
644 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
645 }
646 pipe_resource_reference(&transfer->resource, NULL);
647 FREE(transfer);
648 }
649
650 void* r600_texture_transfer_map(struct pipe_context *ctx,
651 struct pipe_transfer* transfer)
652 {
653 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
654 struct r600_bo *bo;
655 enum pipe_format format = transfer->resource->format;
656 struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
657 unsigned offset = 0;
658 unsigned usage = 0;
659 char *map;
660
661 if (rtransfer->staging_texture) {
662 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
663 } else {
664 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
665
666 if (rtex->flushed_depth_texture)
667 bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
668 else
669 bo = ((struct r600_resource *)transfer->resource)->bo;
670
671 offset = rtransfer->offset +
672 transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
673 transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
674 }
675
676 if (transfer->usage & PIPE_TRANSFER_WRITE) {
677 usage |= PB_USAGE_CPU_WRITE;
678
679 if (transfer->usage & PIPE_TRANSFER_DISCARD) {
680 }
681
682 if (transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT) {
683 }
684 }
685
686 if (transfer->usage & PIPE_TRANSFER_READ) {
687 usage |= PB_USAGE_CPU_READ;
688 }
689
690 if (transfer->usage & PIPE_TRANSFER_DONTBLOCK) {
691 usage |= PB_USAGE_DONTBLOCK;
692 }
693
694 if (transfer->usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
695 usage |= PB_USAGE_UNSYNCHRONIZED;
696 }
697
698 map = r600_bo_map(radeon, bo, usage, ctx);
699 if (!map) {
700 return NULL;
701 }
702
703 return map + offset;
704 }
705
706 void r600_texture_transfer_unmap(struct pipe_context *ctx,
707 struct pipe_transfer* transfer)
708 {
709 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
710 struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
711 struct r600_bo *bo;
712
713 if (rtransfer->staging_texture) {
714 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
715 } else {
716 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
717
718 if (rtex->flushed_depth_texture) {
719 bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
720 } else {
721 bo = ((struct r600_resource *)transfer->resource)->bo;
722 }
723 }
724 r600_bo_unmap(radeon, bo);
725 }
726
727 struct u_resource_vtbl r600_texture_vtbl =
728 {
729 r600_texture_get_handle, /* get_handle */
730 r600_texture_destroy, /* resource_destroy */
731 r600_texture_is_referenced, /* is_resource_referenced */
732 r600_texture_get_transfer, /* get_transfer */
733 r600_texture_transfer_destroy, /* transfer_destroy */
734 r600_texture_transfer_map, /* transfer_map */
735 u_default_transfer_flush_region,/* transfer_flush_region */
736 r600_texture_transfer_unmap, /* transfer_unmap */
737 u_default_transfer_inline_write /* transfer_inline_write */
738 };
739
740 void r600_init_surface_functions(struct r600_pipe_context *r600)
741 {
742 r600->context.create_surface = r600_create_surface;
743 r600->context.surface_destroy = r600_surface_destroy;
744 }
745
746 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
747 const unsigned char *swizzle_view)
748 {
749 unsigned i;
750 unsigned char swizzle[4];
751 unsigned result = 0;
752 const uint32_t swizzle_shift[4] = {
753 16, 19, 22, 25,
754 };
755 const uint32_t swizzle_bit[4] = {
756 0, 1, 2, 3,
757 };
758
759 if (swizzle_view) {
760 /* Combine two sets of swizzles. */
761 for (i = 0; i < 4; i++) {
762 swizzle[i] = swizzle_view[i] <= UTIL_FORMAT_SWIZZLE_W ?
763 swizzle_format[swizzle_view[i]] : swizzle_view[i];
764 }
765 } else {
766 memcpy(swizzle, swizzle_format, 4);
767 }
768
769 /* Get swizzle. */
770 for (i = 0; i < 4; i++) {
771 switch (swizzle[i]) {
772 case UTIL_FORMAT_SWIZZLE_Y:
773 result |= swizzle_bit[1] << swizzle_shift[i];
774 break;
775 case UTIL_FORMAT_SWIZZLE_Z:
776 result |= swizzle_bit[2] << swizzle_shift[i];
777 break;
778 case UTIL_FORMAT_SWIZZLE_W:
779 result |= swizzle_bit[3] << swizzle_shift[i];
780 break;
781 case UTIL_FORMAT_SWIZZLE_0:
782 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
783 break;
784 case UTIL_FORMAT_SWIZZLE_1:
785 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
786 break;
787 default: /* UTIL_FORMAT_SWIZZLE_X */
788 result |= swizzle_bit[0] << swizzle_shift[i];
789 }
790 }
791 return result;
792 }
793
794 /* texture format translate */
795 uint32_t r600_translate_texformat(enum pipe_format format,
796 const unsigned char *swizzle_view,
797 uint32_t *word4_p, uint32_t *yuv_format_p)
798 {
799 uint32_t result = 0, word4 = 0, yuv_format = 0;
800 const struct util_format_description *desc;
801 boolean uniform = TRUE;
802 int i;
803 const uint32_t sign_bit[4] = {
804 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
805 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
806 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
807 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
808 };
809 desc = util_format_description(format);
810
811 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
812
813 /* Colorspace (return non-RGB formats directly). */
814 switch (desc->colorspace) {
815 /* Depth stencil formats */
816 case UTIL_FORMAT_COLORSPACE_ZS:
817 switch (format) {
818 case PIPE_FORMAT_Z16_UNORM:
819 result = FMT_16;
820 goto out_word4;
821 case PIPE_FORMAT_X24S8_USCALED:
822 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
823 case PIPE_FORMAT_Z24X8_UNORM:
824 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
825 result = FMT_8_24;
826 goto out_word4;
827 case PIPE_FORMAT_S8X24_USCALED:
828 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
829 case PIPE_FORMAT_X8Z24_UNORM:
830 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
831 result = FMT_24_8;
832 goto out_word4;
833 case PIPE_FORMAT_S8_USCALED:
834 result = FMT_8;
835 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
836 goto out_word4;
837 default:
838 goto out_unknown;
839 }
840
841 case UTIL_FORMAT_COLORSPACE_YUV:
842 yuv_format |= (1 << 30);
843 switch (format) {
844 case PIPE_FORMAT_UYVY:
845 case PIPE_FORMAT_YUYV:
846 default:
847 break;
848 }
849 goto out_unknown; /* TODO */
850
851 case UTIL_FORMAT_COLORSPACE_SRGB:
852 word4 |= S_038010_FORCE_DEGAMMA(1);
853 if (format == PIPE_FORMAT_L8A8_SRGB || format == PIPE_FORMAT_L8_SRGB)
854 goto out_unknown; /* fails for some reason - TODO */
855 break;
856
857 default:
858 break;
859 }
860
861 /* S3TC formats. TODO */
862 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
863 static int r600_enable_s3tc = -1;
864
865 if (r600_enable_s3tc == -1)
866 r600_enable_s3tc =
867 debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
868
869 if (!r600_enable_s3tc)
870 goto out_unknown;
871
872 switch (format) {
873 case PIPE_FORMAT_DXT1_RGB:
874 case PIPE_FORMAT_DXT1_RGBA:
875 result = FMT_BC1;
876 goto out_word4;
877 case PIPE_FORMAT_DXT3_RGBA:
878 result = FMT_BC2;
879 goto out_word4;
880 case PIPE_FORMAT_DXT5_RGBA:
881 result = FMT_BC3;
882 goto out_word4;
883 default:
884 goto out_unknown;
885 }
886 }
887
888
889 for (i = 0; i < desc->nr_channels; i++) {
890 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
891 word4 |= sign_bit[i];
892 }
893 }
894
895 /* R8G8Bx_SNORM - TODO CxV8U8 */
896
897 /* RGTC - TODO */
898
899 /* See whether the components are of the same size. */
900 for (i = 1; i < desc->nr_channels; i++) {
901 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
902 }
903
904 /* Non-uniform formats. */
905 if (!uniform) {
906 switch(desc->nr_channels) {
907 case 3:
908 if (desc->channel[0].size == 5 &&
909 desc->channel[1].size == 6 &&
910 desc->channel[2].size == 5) {
911 result = FMT_5_6_5;
912 goto out_word4;
913 }
914 goto out_unknown;
915 case 4:
916 if (desc->channel[0].size == 5 &&
917 desc->channel[1].size == 5 &&
918 desc->channel[2].size == 5 &&
919 desc->channel[3].size == 1) {
920 result = FMT_1_5_5_5;
921 goto out_word4;
922 }
923 if (desc->channel[0].size == 10 &&
924 desc->channel[1].size == 10 &&
925 desc->channel[2].size == 10 &&
926 desc->channel[3].size == 2) {
927 result = FMT_10_10_10_2;
928 goto out_word4;
929 }
930 goto out_unknown;
931 }
932 goto out_unknown;
933 }
934
935 /* Find the first non-VOID channel. */
936 for (i = 0; i < 4; i++) {
937 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
938 break;
939 }
940 }
941
942 if (i == 4)
943 goto out_unknown;
944
945 /* uniform formats */
946 switch (desc->channel[i].type) {
947 case UTIL_FORMAT_TYPE_UNSIGNED:
948 case UTIL_FORMAT_TYPE_SIGNED:
949 if (!desc->channel[i].normalized &&
950 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
951 goto out_unknown;
952 }
953
954 switch (desc->channel[i].size) {
955 case 4:
956 switch (desc->nr_channels) {
957 case 2:
958 result = FMT_4_4;
959 goto out_word4;
960 case 4:
961 result = FMT_4_4_4_4;
962 goto out_word4;
963 }
964 goto out_unknown;
965 case 8:
966 switch (desc->nr_channels) {
967 case 1:
968 result = FMT_8;
969 goto out_word4;
970 case 2:
971 result = FMT_8_8;
972 goto out_word4;
973 case 4:
974 result = FMT_8_8_8_8;
975 goto out_word4;
976 }
977 goto out_unknown;
978 case 16:
979 switch (desc->nr_channels) {
980 case 1:
981 result = FMT_16;
982 goto out_word4;
983 case 2:
984 result = FMT_16_16;
985 goto out_word4;
986 case 4:
987 result = FMT_16_16_16_16;
988 goto out_word4;
989 }
990 }
991 goto out_unknown;
992
993 case UTIL_FORMAT_TYPE_FLOAT:
994 switch (desc->channel[i].size) {
995 case 16:
996 switch (desc->nr_channels) {
997 case 1:
998 result = FMT_16_FLOAT;
999 goto out_word4;
1000 case 2:
1001 result = FMT_16_16_FLOAT;
1002 goto out_word4;
1003 case 4:
1004 result = FMT_16_16_16_16_FLOAT;
1005 goto out_word4;
1006 }
1007 goto out_unknown;
1008 case 32:
1009 switch (desc->nr_channels) {
1010 case 1:
1011 result = FMT_32_FLOAT;
1012 goto out_word4;
1013 case 2:
1014 result = FMT_32_32_FLOAT;
1015 goto out_word4;
1016 case 4:
1017 result = FMT_32_32_32_32_FLOAT;
1018 goto out_word4;
1019 }
1020 }
1021
1022 }
1023 out_word4:
1024 if (word4_p)
1025 *word4_p = word4;
1026 if (yuv_format_p)
1027 *yuv_format_p = yuv_format;
1028 return result;
1029 out_unknown:
1030 // R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format));
1031 return ~0;
1032 }