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r600g: hack around a problem with texture alignment
[mesa.git] / src / gallium / drivers / r600 / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include <errno.h>
28 #include <pipe/p_screen.h>
29 #include <util/u_format.h>
30 #include <util/u_format_s3tc.h>
31 #include <util/u_math.h>
32 #include <util/u_inlines.h>
33 #include <util/u_memory.h>
34 #include "pipebuffer/pb_buffer.h"
35 #include "r600_pipe.h"
36 #include "r600_resource.h"
37 #include "r600d.h"
38 #include "r600_formats.h"
39
40 /* Copy from a full GPU texture to a transfer's staging one. */
41 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
42 {
43 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
44 struct pipe_resource *texture = transfer->resource;
45
46 ctx->resource_copy_region(ctx, rtransfer->staging_texture,
47 0, 0, 0, 0, texture, transfer->level,
48 &transfer->box);
49 }
50
51
52 /* Copy from a transfer's staging texture to a full GPU one. */
53 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
54 {
55 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
56 struct pipe_resource *texture = transfer->resource;
57 struct pipe_box sbox;
58
59 sbox.x = sbox.y = sbox.z = 0;
60 sbox.width = transfer->box.width;
61 sbox.height = transfer->box.height;
62 /* XXX that might be wrong */
63 sbox.depth = 1;
64 ctx->resource_copy_region(ctx, texture, transfer->level,
65 transfer->box.x, transfer->box.y, transfer->box.z,
66 rtransfer->staging_texture,
67 0, &sbox);
68
69 r600_flush(ctx, NULL, RADEON_FLUSH_ASYNC);
70 }
71
72 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
73 unsigned level, unsigned layer)
74 {
75 unsigned offset = rtex->offset[level];
76
77 switch (rtex->resource.b.b.b.target) {
78 case PIPE_TEXTURE_3D:
79 case PIPE_TEXTURE_CUBE:
80 default:
81 return offset + layer * rtex->layer_size[level];
82 }
83 }
84
85 static unsigned r600_get_block_alignment(struct pipe_screen *screen,
86 enum pipe_format format,
87 unsigned array_mode)
88 {
89 struct r600_screen* rscreen = (struct r600_screen *)screen;
90 unsigned pixsize = util_format_get_blocksize(format);
91 int p_align;
92
93 switch(array_mode) {
94 case V_038000_ARRAY_1D_TILED_THIN1:
95 p_align = MAX2(8,
96 ((rscreen->tiling_info->group_bytes / 8 / pixsize)));
97 break;
98 case V_038000_ARRAY_2D_TILED_THIN1:
99 p_align = MAX2(rscreen->tiling_info->num_banks,
100 (((rscreen->tiling_info->group_bytes / 8 / pixsize)) *
101 rscreen->tiling_info->num_banks)) * 8;
102 break;
103 case V_038000_ARRAY_LINEAR_ALIGNED:
104 p_align = MAX2(64, rscreen->tiling_info->group_bytes / pixsize);
105 break;
106 case V_038000_ARRAY_LINEAR_GENERAL:
107 default:
108 p_align = rscreen->tiling_info->group_bytes / pixsize;
109 break;
110 }
111 return p_align;
112 }
113
114 static unsigned r600_get_height_alignment(struct pipe_screen *screen,
115 unsigned array_mode)
116 {
117 struct r600_screen* rscreen = (struct r600_screen *)screen;
118 int h_align;
119
120 switch (array_mode) {
121 case V_038000_ARRAY_2D_TILED_THIN1:
122 h_align = rscreen->tiling_info->num_channels * 8;
123 break;
124 case V_038000_ARRAY_1D_TILED_THIN1:
125 case V_038000_ARRAY_LINEAR_ALIGNED:
126 h_align = 8;
127 break;
128 case V_038000_ARRAY_LINEAR_GENERAL:
129 default:
130 h_align = 1;
131 break;
132 }
133 return h_align;
134 }
135
136 static unsigned r600_get_base_alignment(struct pipe_screen *screen,
137 enum pipe_format format,
138 unsigned array_mode)
139 {
140 struct r600_screen* rscreen = (struct r600_screen *)screen;
141 unsigned pixsize = util_format_get_blocksize(format);
142 int p_align = r600_get_block_alignment(screen, format, array_mode);
143 int h_align = r600_get_height_alignment(screen, array_mode);
144 int b_align;
145
146 switch (array_mode) {
147 case V_038000_ARRAY_2D_TILED_THIN1:
148 b_align = MAX2(rscreen->tiling_info->num_banks * rscreen->tiling_info->num_channels * 8 * 8 * pixsize,
149 p_align * pixsize * h_align);
150 break;
151 case V_038000_ARRAY_1D_TILED_THIN1:
152 case V_038000_ARRAY_LINEAR_ALIGNED:
153 case V_038000_ARRAY_LINEAR_GENERAL:
154 default:
155 b_align = rscreen->tiling_info->group_bytes;
156 break;
157 }
158 return b_align;
159 }
160
161 static unsigned mip_minify(unsigned size, unsigned level)
162 {
163 unsigned val;
164 val = u_minify(size, level);
165 if (level > 0)
166 val = util_next_power_of_two(val);
167 return val;
168 }
169
170 static unsigned r600_texture_get_nblocksx(struct pipe_screen *screen,
171 struct r600_resource_texture *rtex,
172 unsigned level)
173 {
174 struct pipe_resource *ptex = &rtex->resource.b.b.b;
175 unsigned nblocksx, block_align, width;
176 unsigned blocksize = util_format_get_blocksize(rtex->real_format);
177
178 if (rtex->pitch_override)
179 return rtex->pitch_override / blocksize;
180
181 width = mip_minify(ptex->width0, level);
182 nblocksx = util_format_get_nblocksx(rtex->real_format, width);
183
184 block_align = r600_get_block_alignment(screen, rtex->real_format,
185 rtex->array_mode[level]);
186 nblocksx = align(nblocksx, block_align);
187 return nblocksx;
188 }
189
190 static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen,
191 struct r600_resource_texture *rtex,
192 unsigned level)
193 {
194 struct pipe_resource *ptex = &rtex->resource.b.b.b;
195 unsigned height, tile_height;
196
197 height = mip_minify(ptex->height0, level);
198 height = util_format_get_nblocksy(rtex->real_format, height);
199 tile_height = r600_get_height_alignment(screen,
200 rtex->array_mode[level]);
201
202 /* XXX Hack around an alignment issue. Less tests fail with this.
203 *
204 * The thing is depth-stencil buffers should be tiled, i.e.
205 * the alignment should be >=8. If I make them tiled, stencil starts
206 * working because it no longer overlaps with the depth buffer
207 * in memory, but texturing like drawpix-stencil breaks. */
208 if (util_format_is_depth_or_stencil(rtex->real_format) && tile_height < 8)
209 tile_height = 8;
210
211 height = align(height, tile_height);
212 return height;
213 }
214
215 static void r600_texture_set_array_mode(struct pipe_screen *screen,
216 struct r600_resource_texture *rtex,
217 unsigned level, unsigned array_mode)
218 {
219 struct pipe_resource *ptex = &rtex->resource.b.b.b;
220
221 switch (array_mode) {
222 case V_0280A0_ARRAY_LINEAR_GENERAL:
223 case V_0280A0_ARRAY_LINEAR_ALIGNED:
224 case V_0280A0_ARRAY_1D_TILED_THIN1:
225 default:
226 rtex->array_mode[level] = array_mode;
227 break;
228 case V_0280A0_ARRAY_2D_TILED_THIN1:
229 {
230 unsigned w, h, tile_height, tile_width;
231
232 tile_height = r600_get_height_alignment(screen, array_mode);
233 tile_width = r600_get_block_alignment(screen, rtex->real_format, array_mode);
234
235 w = mip_minify(ptex->width0, level);
236 h = mip_minify(ptex->height0, level);
237 if (w <= tile_width || h <= tile_height)
238 rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1;
239 else
240 rtex->array_mode[level] = array_mode;
241 }
242 break;
243 }
244 }
245
246 static void r600_setup_miptree(struct pipe_screen *screen,
247 struct r600_resource_texture *rtex,
248 unsigned array_mode)
249 {
250 struct pipe_resource *ptex = &rtex->resource.b.b.b;
251 struct radeon *radeon = ((struct r600_screen*)screen)->radeon;
252 enum chip_class chipc = r600_get_family_class(radeon);
253 unsigned size, layer_size, i, offset;
254 unsigned nblocksx, nblocksy;
255
256 for (i = 0, offset = 0; i <= ptex->last_level; i++) {
257 unsigned blocksize = util_format_get_blocksize(rtex->real_format);
258 unsigned base_align = r600_get_base_alignment(screen, rtex->real_format, array_mode);
259
260 r600_texture_set_array_mode(screen, rtex, i, array_mode);
261
262 nblocksx = r600_texture_get_nblocksx(screen, rtex, i);
263 nblocksy = r600_texture_get_nblocksy(screen, rtex, i);
264
265 layer_size = nblocksx * nblocksy * blocksize;
266 if (ptex->target == PIPE_TEXTURE_CUBE) {
267 if (chipc >= R700)
268 size = layer_size * 8;
269 else
270 size = layer_size * 6;
271 }
272 else if (ptex->target == PIPE_TEXTURE_3D)
273 size = layer_size * u_minify(ptex->depth0, i);
274 else
275 size = layer_size * ptex->array_size;
276
277 /* align base image and start of miptree */
278 if ((i == 0) || (i == 1))
279 offset = align(offset, base_align);
280 rtex->offset[i] = offset;
281 rtex->layer_size[i] = layer_size;
282 rtex->pitch_in_blocks[i] = nblocksx; /* CB talks in elements */
283 rtex->pitch_in_bytes[i] = nblocksx * blocksize;
284
285 offset += size;
286 }
287 rtex->size = offset;
288 }
289
290 /* Figure out whether u_blitter will fallback to a transfer operation.
291 * If so, don't use a staging resource.
292 */
293 static boolean permit_hardware_blit(struct pipe_screen *screen,
294 const struct pipe_resource *res)
295 {
296 unsigned bind;
297
298 if (util_format_is_depth_or_stencil(res->format))
299 bind = PIPE_BIND_DEPTH_STENCIL;
300 else
301 bind = PIPE_BIND_RENDER_TARGET;
302
303 /* hackaround for S3TC */
304 if (util_format_is_compressed(res->format))
305 return TRUE;
306
307 if (!screen->is_format_supported(screen,
308 res->format,
309 res->target,
310 res->nr_samples,
311 bind))
312 return FALSE;
313
314 if (!screen->is_format_supported(screen,
315 res->format,
316 res->target,
317 res->nr_samples,
318 PIPE_BIND_SAMPLER_VIEW))
319 return FALSE;
320
321 switch (res->usage) {
322 case PIPE_USAGE_STREAM:
323 case PIPE_USAGE_STAGING:
324 return FALSE;
325
326 default:
327 return TRUE;
328 }
329 }
330
331 static boolean r600_texture_get_handle(struct pipe_screen* screen,
332 struct pipe_resource *ptex,
333 struct winsys_handle *whandle)
334 {
335 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
336 struct r600_resource *resource = &rtex->resource;
337 struct radeon *radeon = ((struct r600_screen*)screen)->radeon;
338
339 return r600_bo_get_winsys_handle(radeon, resource->bo,
340 rtex->pitch_in_bytes[0], whandle);
341 }
342
343 static void r600_texture_destroy(struct pipe_screen *screen,
344 struct pipe_resource *ptex)
345 {
346 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
347 struct r600_resource *resource = &rtex->resource;
348
349 if (rtex->flushed_depth_texture)
350 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
351
352 if (resource->bo) {
353 r600_bo_reference(&resource->bo, NULL);
354 }
355 FREE(rtex);
356 }
357
358 static const struct u_resource_vtbl r600_texture_vtbl =
359 {
360 r600_texture_get_handle, /* get_handle */
361 r600_texture_destroy, /* resource_destroy */
362 r600_texture_get_transfer, /* get_transfer */
363 r600_texture_transfer_destroy, /* transfer_destroy */
364 r600_texture_transfer_map, /* transfer_map */
365 u_default_transfer_flush_region,/* transfer_flush_region */
366 r600_texture_transfer_unmap, /* transfer_unmap */
367 u_default_transfer_inline_write /* transfer_inline_write */
368 };
369
370 static struct r600_resource_texture *
371 r600_texture_create_object(struct pipe_screen *screen,
372 const struct pipe_resource *base,
373 unsigned array_mode,
374 unsigned pitch_in_bytes_override,
375 unsigned max_buffer_size,
376 struct r600_bo *bo,
377 boolean alloc_bo)
378 {
379 struct r600_resource_texture *rtex;
380 struct r600_resource *resource;
381 struct radeon *radeon = ((struct r600_screen*)screen)->radeon;
382
383 rtex = CALLOC_STRUCT(r600_resource_texture);
384 if (rtex == NULL)
385 return NULL;
386
387 resource = &rtex->resource;
388 resource->b.b.b = *base;
389 resource->b.b.vtbl = &r600_texture_vtbl;
390 pipe_reference_init(&resource->b.b.b.reference, 1);
391 resource->b.b.b.screen = screen;
392 resource->bo = bo;
393 rtex->pitch_override = pitch_in_bytes_override;
394 rtex->real_format = base->format;
395
396 /* We must split depth and stencil into two separate buffers on Evergreen. */
397 if (r600_get_family_class(((struct r600_screen*)screen)->radeon) >= EVERGREEN &&
398 util_format_is_depth_and_stencil(base->format)) {
399 struct pipe_resource stencil;
400 unsigned stencil_pitch_override = 0;
401
402 switch (base->format) {
403 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
404 rtex->real_format = PIPE_FORMAT_Z24X8_UNORM;
405 break;
406 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
407 rtex->real_format = PIPE_FORMAT_X8Z24_UNORM;
408 break;
409 case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
410 rtex->real_format = PIPE_FORMAT_Z32_FLOAT;
411 break;
412 default:
413 assert(0);
414 FREE(rtex);
415 return NULL;
416 }
417
418 /* Divide the pitch in bytes by 4 for stencil, because it has a smaller pixel size. */
419 if (pitch_in_bytes_override) {
420 assert(base->format == PIPE_FORMAT_Z24_UNORM_S8_USCALED ||
421 base->format == PIPE_FORMAT_S8_USCALED_Z24_UNORM);
422 stencil_pitch_override = pitch_in_bytes_override / 4;
423 }
424
425 /* Allocate the stencil buffer. */
426 stencil = *base;
427 stencil.format = PIPE_FORMAT_S8_USCALED;
428 rtex->stencil = r600_texture_create_object(screen, &stencil, array_mode,
429 stencil_pitch_override,
430 max_buffer_size, NULL, FALSE);
431 if (!rtex->stencil) {
432 FREE(rtex);
433 return NULL;
434 }
435 /* Proceed in creating the depth buffer. */
436 }
437
438 /* only mark depth textures the HW can hit as depth textures */
439 if (util_format_is_depth_or_stencil(rtex->real_format) && permit_hardware_blit(screen, base))
440 rtex->depth = 1;
441
442 r600_setup_miptree(screen, rtex, array_mode);
443
444 /* If we initialized separate stencil for Evergreen. place it after depth. */
445 if (rtex->stencil) {
446 unsigned stencil_align, stencil_offset;
447
448 stencil_align = r600_get_base_alignment(screen, rtex->stencil->real_format, array_mode);
449 stencil_offset = align(rtex->size, stencil_align);
450
451 for (unsigned i = 0; i <= rtex->stencil->resource.b.b.b.last_level; i++)
452 rtex->stencil->offset[i] += stencil_offset;
453
454 rtex->size = stencil_offset + rtex->stencil->size;
455 }
456
457 resource->size = rtex->size;
458
459 /* Now create the backing buffer. */
460 if (!resource->bo && alloc_bo) {
461 struct pipe_resource *ptex = &rtex->resource.b.b.b;
462 unsigned base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
463
464 resource->bo = r600_bo(radeon, rtex->size, base_align, base->bind, base->usage);
465 if (!resource->bo) {
466 pipe_resource_reference((struct pipe_resource**)&rtex->stencil, NULL);
467 FREE(rtex);
468 return NULL;
469 }
470 }
471
472 if (rtex->stencil)
473 rtex->stencil->resource.bo = rtex->resource.bo;
474 return rtex;
475 }
476
477 DEBUG_GET_ONCE_BOOL_OPTION(tiling_enabled, "R600_TILING", FALSE);
478
479 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
480 const struct pipe_resource *templ)
481 {
482 struct radeon *radeon = ((struct r600_screen*)screen)->radeon;
483 unsigned array_mode = 0;
484
485 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
486 !(templ->bind & PIPE_BIND_SCANOUT)) {
487 if (util_format_is_compressed(templ->format)) {
488 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
489 }
490 else if (debug_get_option_tiling_enabled() &&
491 r600_get_minor_version(radeon) >= 9 &&
492 permit_hardware_blit(screen, templ)) {
493 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
494 }
495 }
496
497 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
498 0, 0, NULL, TRUE);
499 }
500
501 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
502 struct pipe_resource *texture,
503 const struct pipe_surface *surf_tmpl)
504 {
505 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
506 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
507 unsigned level = surf_tmpl->u.tex.level;
508
509 assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
510 if (surface == NULL)
511 return NULL;
512 /* XXX no offset */
513 /* offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/
514 pipe_reference_init(&surface->base.reference, 1);
515 pipe_resource_reference(&surface->base.texture, texture);
516 surface->base.context = pipe;
517 surface->base.format = surf_tmpl->format;
518 surface->base.width = mip_minify(texture->width0, level);
519 surface->base.height = mip_minify(texture->height0, level);
520 surface->base.usage = surf_tmpl->usage;
521 surface->base.texture = texture;
522 surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
523 surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
524 surface->base.u.tex.level = level;
525
526 surface->aligned_height = r600_texture_get_nblocksy(pipe->screen,
527 rtex, level);
528 return &surface->base;
529 }
530
531 static void r600_surface_destroy(struct pipe_context *pipe,
532 struct pipe_surface *surface)
533 {
534 pipe_resource_reference(&surface->texture, NULL);
535 FREE(surface);
536 }
537
538
539 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
540 const struct pipe_resource *templ,
541 struct winsys_handle *whandle)
542 {
543 struct radeon *rw = ((struct r600_screen*)screen)->radeon;
544 struct r600_bo *bo = NULL;
545 unsigned stride = 0;
546 unsigned array_mode = 0;
547
548 /* Support only 2D textures without mipmaps */
549 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
550 templ->depth0 != 1 || templ->last_level != 0)
551 return NULL;
552
553 bo = r600_bo_handle(rw, whandle, &stride, &array_mode);
554 if (bo == NULL) {
555 return NULL;
556 }
557
558 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
559 stride, 0, bo, FALSE);
560 }
561
562 int r600_texture_depth_flush(struct pipe_context *ctx,
563 struct pipe_resource *texture, boolean just_create)
564 {
565 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
566 struct pipe_resource resource;
567
568 if (rtex->flushed_depth_texture)
569 goto out;
570
571 resource.target = PIPE_TEXTURE_2D;
572 resource.format = texture->format;
573 resource.width0 = texture->width0;
574 resource.height0 = texture->height0;
575 resource.depth0 = 1;
576 resource.array_size = 1;
577 resource.last_level = texture->last_level;
578 resource.nr_samples = 0;
579 resource.usage = PIPE_USAGE_DYNAMIC;
580 resource.bind = 0;
581 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
582
583 resource.bind |= PIPE_BIND_DEPTH_STENCIL;
584
585 rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
586 if (rtex->flushed_depth_texture == NULL) {
587 R600_ERR("failed to create temporary texture to hold untiled copy\n");
588 return -ENOMEM;
589 }
590
591 ((struct r600_resource_texture *)rtex->flushed_depth_texture)->is_flushing_texture = TRUE;
592 out:
593 if (just_create)
594 return 0;
595
596 /* XXX: only do this if the depth texture has actually changed:
597 */
598 r600_blit_uncompress_depth(ctx, rtex);
599 return 0;
600 }
601
602 /* Needs adjustment for pixelformat:
603 */
604 static INLINE unsigned u_box_volume( const struct pipe_box *box )
605 {
606 return box->width * box->depth * box->height;
607 };
608
609 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
610 struct pipe_resource *texture,
611 unsigned level,
612 unsigned usage,
613 const struct pipe_box *box)
614 {
615 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
616 struct pipe_resource resource;
617 struct r600_transfer *trans;
618 int r;
619 boolean use_staging_texture = FALSE;
620
621 /* We cannot map a tiled texture directly because the data is
622 * in a different order, therefore we do detiling using a blit.
623 *
624 * Also, use a temporary in GTT memory for read transfers, as
625 * the CPU is much happier reading out of cached system memory
626 * than uncached VRAM.
627 */
628 if (R600_TEX_IS_TILED(rtex, level))
629 use_staging_texture = TRUE;
630
631 if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024)
632 use_staging_texture = TRUE;
633
634 /* XXX: Use a staging texture for uploads if the underlying BO
635 * is busy. No interface for checking that currently? so do
636 * it eagerly whenever the transfer doesn't require a readback
637 * and might block.
638 */
639 if ((usage & PIPE_TRANSFER_WRITE) &&
640 !(usage & (PIPE_TRANSFER_READ |
641 PIPE_TRANSFER_DONTBLOCK |
642 PIPE_TRANSFER_UNSYNCHRONIZED)))
643 use_staging_texture = TRUE;
644
645 if (!permit_hardware_blit(ctx->screen, texture) ||
646 (texture->flags & R600_RESOURCE_FLAG_TRANSFER))
647 use_staging_texture = FALSE;
648
649 trans = CALLOC_STRUCT(r600_transfer);
650 if (trans == NULL)
651 return NULL;
652 pipe_resource_reference(&trans->transfer.resource, texture);
653 trans->transfer.level = level;
654 trans->transfer.usage = usage;
655 trans->transfer.box = *box;
656 if (rtex->depth) {
657 /* XXX: only readback the rectangle which is being mapped?
658 */
659 /* XXX: when discard is true, no need to read back from depth texture
660 */
661 r = r600_texture_depth_flush(ctx, texture, FALSE);
662 if (r < 0) {
663 R600_ERR("failed to create temporary texture to hold untiled copy\n");
664 pipe_resource_reference(&trans->transfer.resource, NULL);
665 FREE(trans);
666 return NULL;
667 }
668 trans->transfer.stride = rtex->flushed_depth_texture->pitch_in_bytes[level];
669 trans->offset = r600_texture_get_offset(rtex->flushed_depth_texture, level, box->z);
670 return &trans->transfer;
671 } else if (use_staging_texture) {
672 resource.target = PIPE_TEXTURE_2D;
673 resource.format = texture->format;
674 resource.width0 = box->width;
675 resource.height0 = box->height;
676 resource.depth0 = 1;
677 resource.array_size = 1;
678 resource.last_level = 0;
679 resource.nr_samples = 0;
680 resource.usage = PIPE_USAGE_STAGING;
681 resource.bind = 0;
682 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
683 /* For texture reading, the temporary (detiled) texture is used as
684 * a render target when blitting from a tiled texture. */
685 if (usage & PIPE_TRANSFER_READ) {
686 resource.bind |= PIPE_BIND_RENDER_TARGET;
687 }
688 /* For texture writing, the temporary texture is used as a sampler
689 * when blitting into a tiled texture. */
690 if (usage & PIPE_TRANSFER_WRITE) {
691 resource.bind |= PIPE_BIND_SAMPLER_VIEW;
692 }
693 /* Create the temporary texture. */
694 trans->staging_texture = ctx->screen->resource_create(ctx->screen, &resource);
695 if (trans->staging_texture == NULL) {
696 R600_ERR("failed to create temporary texture to hold untiled copy\n");
697 pipe_resource_reference(&trans->transfer.resource, NULL);
698 FREE(trans);
699 return NULL;
700 }
701
702 trans->transfer.stride =
703 ((struct r600_resource_texture *)trans->staging_texture)->pitch_in_bytes[0];
704 if (usage & PIPE_TRANSFER_READ) {
705 r600_copy_to_staging_texture(ctx, trans);
706 /* Always referenced in the blit. */
707 r600_flush(ctx, NULL, 0);
708 }
709 return &trans->transfer;
710 }
711 trans->transfer.stride = rtex->pitch_in_bytes[level];
712 trans->transfer.layer_stride = rtex->layer_size[level];
713 trans->offset = r600_texture_get_offset(rtex, level, box->z);
714 return &trans->transfer;
715 }
716
717 void r600_texture_transfer_destroy(struct pipe_context *ctx,
718 struct pipe_transfer *transfer)
719 {
720 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
721 struct pipe_resource *texture = transfer->resource;
722 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
723
724 if (rtransfer->staging_texture) {
725 if (transfer->usage & PIPE_TRANSFER_WRITE) {
726 r600_copy_from_staging_texture(ctx, rtransfer);
727 }
728 pipe_resource_reference(&rtransfer->staging_texture, NULL);
729 }
730
731 if (rtex->depth && !rtex->is_flushing_texture) {
732 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtex->flushed_depth_texture)
733 r600_blit_push_depth(ctx, rtex);
734 }
735
736 pipe_resource_reference(&transfer->resource, NULL);
737 FREE(transfer);
738 }
739
740 void* r600_texture_transfer_map(struct pipe_context *ctx,
741 struct pipe_transfer* transfer)
742 {
743 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
744 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
745 struct r600_bo *bo;
746 enum pipe_format format = transfer->resource->format;
747 struct radeon *radeon = rctx->screen->radeon;
748 unsigned offset = 0;
749 char *map;
750
751 if (rtransfer->staging_texture) {
752 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
753 } else {
754 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
755
756 if (rtex->flushed_depth_texture)
757 bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
758 else
759 bo = ((struct r600_resource *)transfer->resource)->bo;
760
761 offset = rtransfer->offset +
762 transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
763 transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
764 }
765
766 if (!(map = r600_bo_map(radeon, bo, rctx->ctx.cs, transfer->usage))) {
767 return NULL;
768 }
769
770 return map + offset;
771 }
772
773 void r600_texture_transfer_unmap(struct pipe_context *ctx,
774 struct pipe_transfer* transfer)
775 {
776 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
777 struct radeon *radeon = ((struct r600_screen*)ctx->screen)->radeon;
778 struct r600_bo *bo;
779
780 if (rtransfer->staging_texture) {
781 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
782 } else {
783 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
784
785 if (rtex->flushed_depth_texture) {
786 bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
787 } else {
788 bo = ((struct r600_resource *)transfer->resource)->bo;
789 }
790 }
791 r600_bo_unmap(radeon, bo);
792 }
793
794 void r600_init_surface_functions(struct r600_pipe_context *r600)
795 {
796 r600->context.create_surface = r600_create_surface;
797 r600->context.surface_destroy = r600_surface_destroy;
798 }
799
800 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
801 const unsigned char *swizzle_view)
802 {
803 unsigned i;
804 unsigned char swizzle[4];
805 unsigned result = 0;
806 const uint32_t swizzle_shift[4] = {
807 16, 19, 22, 25,
808 };
809 const uint32_t swizzle_bit[4] = {
810 0, 1, 2, 3,
811 };
812
813 if (swizzle_view) {
814 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
815 } else {
816 memcpy(swizzle, swizzle_format, 4);
817 }
818
819 /* Get swizzle. */
820 for (i = 0; i < 4; i++) {
821 switch (swizzle[i]) {
822 case UTIL_FORMAT_SWIZZLE_Y:
823 result |= swizzle_bit[1] << swizzle_shift[i];
824 break;
825 case UTIL_FORMAT_SWIZZLE_Z:
826 result |= swizzle_bit[2] << swizzle_shift[i];
827 break;
828 case UTIL_FORMAT_SWIZZLE_W:
829 result |= swizzle_bit[3] << swizzle_shift[i];
830 break;
831 case UTIL_FORMAT_SWIZZLE_0:
832 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
833 break;
834 case UTIL_FORMAT_SWIZZLE_1:
835 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
836 break;
837 default: /* UTIL_FORMAT_SWIZZLE_X */
838 result |= swizzle_bit[0] << swizzle_shift[i];
839 }
840 }
841 return result;
842 }
843
844 /* texture format translate */
845 uint32_t r600_translate_texformat(struct pipe_screen *screen,
846 enum pipe_format format,
847 const unsigned char *swizzle_view,
848 uint32_t *word4_p, uint32_t *yuv_format_p)
849 {
850 uint32_t result = 0, word4 = 0, yuv_format = 0;
851 const struct util_format_description *desc;
852 boolean uniform = TRUE;
853 static int r600_enable_s3tc = -1;
854
855 int i;
856 const uint32_t sign_bit[4] = {
857 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
858 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
859 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
860 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
861 };
862 desc = util_format_description(format);
863
864 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
865
866 /* Colorspace (return non-RGB formats directly). */
867 switch (desc->colorspace) {
868 /* Depth stencil formats */
869 case UTIL_FORMAT_COLORSPACE_ZS:
870 switch (format) {
871 case PIPE_FORMAT_Z16_UNORM:
872 result = FMT_16;
873 goto out_word4;
874 case PIPE_FORMAT_X24S8_USCALED:
875 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
876 case PIPE_FORMAT_Z24X8_UNORM:
877 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
878 result = FMT_8_24;
879 goto out_word4;
880 case PIPE_FORMAT_S8X24_USCALED:
881 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
882 case PIPE_FORMAT_X8Z24_UNORM:
883 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
884 result = FMT_24_8;
885 goto out_word4;
886 case PIPE_FORMAT_S8_USCALED:
887 result = FMT_8;
888 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
889 goto out_word4;
890 case PIPE_FORMAT_Z32_FLOAT:
891 result = FMT_32_FLOAT;
892 goto out_word4;
893 case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
894 result = FMT_X24_8_32_FLOAT;
895 goto out_word4;
896 default:
897 goto out_unknown;
898 }
899
900 case UTIL_FORMAT_COLORSPACE_YUV:
901 yuv_format |= (1 << 30);
902 switch (format) {
903 case PIPE_FORMAT_UYVY:
904 case PIPE_FORMAT_YUYV:
905 default:
906 break;
907 }
908 goto out_unknown; /* TODO */
909
910 case UTIL_FORMAT_COLORSPACE_SRGB:
911 word4 |= S_038010_FORCE_DEGAMMA(1);
912 break;
913
914 default:
915 break;
916 }
917
918 if (r600_enable_s3tc == -1) {
919 struct r600_screen *rscreen = (struct r600_screen *)screen;
920 if (r600_get_minor_version(rscreen->radeon) >= 9)
921 r600_enable_s3tc = 1;
922 else
923 r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
924 }
925
926 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
927 if (!r600_enable_s3tc)
928 goto out_unknown;
929
930 switch (format) {
931 case PIPE_FORMAT_RGTC1_SNORM:
932 case PIPE_FORMAT_LATC1_SNORM:
933 word4 |= sign_bit[0];
934 case PIPE_FORMAT_RGTC1_UNORM:
935 case PIPE_FORMAT_LATC1_UNORM:
936 result = FMT_BC4;
937 goto out_word4;
938 case PIPE_FORMAT_RGTC2_SNORM:
939 case PIPE_FORMAT_LATC2_SNORM:
940 word4 |= sign_bit[0] | sign_bit[1];
941 case PIPE_FORMAT_RGTC2_UNORM:
942 case PIPE_FORMAT_LATC2_UNORM:
943 result = FMT_BC5;
944 goto out_word4;
945 default:
946 goto out_unknown;
947 }
948 }
949
950 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
951
952 if (!r600_enable_s3tc)
953 goto out_unknown;
954
955 if (!util_format_s3tc_enabled) {
956 goto out_unknown;
957 }
958
959 switch (format) {
960 case PIPE_FORMAT_DXT1_RGB:
961 case PIPE_FORMAT_DXT1_RGBA:
962 case PIPE_FORMAT_DXT1_SRGB:
963 case PIPE_FORMAT_DXT1_SRGBA:
964 result = FMT_BC1;
965 goto out_word4;
966 case PIPE_FORMAT_DXT3_RGBA:
967 case PIPE_FORMAT_DXT3_SRGBA:
968 result = FMT_BC2;
969 goto out_word4;
970 case PIPE_FORMAT_DXT5_RGBA:
971 case PIPE_FORMAT_DXT5_SRGBA:
972 result = FMT_BC3;
973 goto out_word4;
974 default:
975 goto out_unknown;
976 }
977 }
978
979 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
980 result = FMT_5_9_9_9_SHAREDEXP;
981 goto out_word4;
982 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
983 result = FMT_10_11_11_FLOAT;
984 goto out_word4;
985 }
986
987
988 for (i = 0; i < desc->nr_channels; i++) {
989 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
990 word4 |= sign_bit[i];
991 }
992 }
993
994 /* R8G8Bx_SNORM - TODO CxV8U8 */
995
996 /* See whether the components are of the same size. */
997 for (i = 1; i < desc->nr_channels; i++) {
998 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
999 }
1000
1001 /* Non-uniform formats. */
1002 if (!uniform) {
1003 switch(desc->nr_channels) {
1004 case 3:
1005 if (desc->channel[0].size == 5 &&
1006 desc->channel[1].size == 6 &&
1007 desc->channel[2].size == 5) {
1008 result = FMT_5_6_5;
1009 goto out_word4;
1010 }
1011 goto out_unknown;
1012 case 4:
1013 if (desc->channel[0].size == 5 &&
1014 desc->channel[1].size == 5 &&
1015 desc->channel[2].size == 5 &&
1016 desc->channel[3].size == 1) {
1017 result = FMT_1_5_5_5;
1018 goto out_word4;
1019 }
1020 if (desc->channel[0].size == 10 &&
1021 desc->channel[1].size == 10 &&
1022 desc->channel[2].size == 10 &&
1023 desc->channel[3].size == 2) {
1024 result = FMT_2_10_10_10;
1025 goto out_word4;
1026 }
1027 goto out_unknown;
1028 }
1029 goto out_unknown;
1030 }
1031
1032 /* Find the first non-VOID channel. */
1033 for (i = 0; i < 4; i++) {
1034 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1035 break;
1036 }
1037 }
1038
1039 if (i == 4)
1040 goto out_unknown;
1041
1042 /* uniform formats */
1043 switch (desc->channel[i].type) {
1044 case UTIL_FORMAT_TYPE_UNSIGNED:
1045 case UTIL_FORMAT_TYPE_SIGNED:
1046 if (!desc->channel[i].normalized &&
1047 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
1048 goto out_unknown;
1049 }
1050
1051 switch (desc->channel[i].size) {
1052 case 4:
1053 switch (desc->nr_channels) {
1054 case 2:
1055 result = FMT_4_4;
1056 goto out_word4;
1057 case 4:
1058 result = FMT_4_4_4_4;
1059 goto out_word4;
1060 }
1061 goto out_unknown;
1062 case 8:
1063 switch (desc->nr_channels) {
1064 case 1:
1065 result = FMT_8;
1066 goto out_word4;
1067 case 2:
1068 result = FMT_8_8;
1069 goto out_word4;
1070 case 4:
1071 result = FMT_8_8_8_8;
1072 goto out_word4;
1073 }
1074 goto out_unknown;
1075 case 16:
1076 switch (desc->nr_channels) {
1077 case 1:
1078 result = FMT_16;
1079 goto out_word4;
1080 case 2:
1081 result = FMT_16_16;
1082 goto out_word4;
1083 case 4:
1084 result = FMT_16_16_16_16;
1085 goto out_word4;
1086 }
1087 goto out_unknown;
1088 case 32:
1089 switch (desc->nr_channels) {
1090 case 1:
1091 result = FMT_32;
1092 goto out_word4;
1093 case 2:
1094 result = FMT_32_32;
1095 goto out_word4;
1096 case 4:
1097 result = FMT_32_32_32_32;
1098 goto out_word4;
1099 }
1100 }
1101 goto out_unknown;
1102
1103 case UTIL_FORMAT_TYPE_FLOAT:
1104 switch (desc->channel[i].size) {
1105 case 16:
1106 switch (desc->nr_channels) {
1107 case 1:
1108 result = FMT_16_FLOAT;
1109 goto out_word4;
1110 case 2:
1111 result = FMT_16_16_FLOAT;
1112 goto out_word4;
1113 case 4:
1114 result = FMT_16_16_16_16_FLOAT;
1115 goto out_word4;
1116 }
1117 goto out_unknown;
1118 case 32:
1119 switch (desc->nr_channels) {
1120 case 1:
1121 result = FMT_32_FLOAT;
1122 goto out_word4;
1123 case 2:
1124 result = FMT_32_32_FLOAT;
1125 goto out_word4;
1126 case 4:
1127 result = FMT_32_32_32_32_FLOAT;
1128 goto out_word4;
1129 }
1130 }
1131 goto out_unknown;
1132 }
1133
1134 out_word4:
1135 if (word4_p)
1136 *word4_p = word4;
1137 if (yuv_format_p)
1138 *yuv_format_p = yuv_format;
1139 return result;
1140 out_unknown:
1141 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1142 return ~0;
1143 }