src/gallium/drivers/r600/r600_texture.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  *      Corbin Simpson
  26  */
  27 #include <errno.h>
  28 #include <pipe/p_screen.h>
  29 #include <util/u_format.h>
  30 #include <util/u_math.h>
  31 #include <util/u_inlines.h>
  32 #include <util/u_memory.h>
  33 #include "state_tracker/drm_driver.h"
  34 #include "pipebuffer/pb_buffer.h"
  35 #include "r600_pipe.h"
  36 #include "r600_resource.h"
  37 #include "r600_state_inlines.h"
  38 #include "r600d.h"
  39 #include "r600_formats.h"
  40
  41 extern struct u_resource_vtbl r600_texture_vtbl;
  42
  43 /* Copy from a full GPU texture to a transfer's staging one. */
  44 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
  45 {
  46         struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
  47         struct pipe_resource *texture = transfer->resource;
  48
  49         ctx->resource_copy_region(ctx, rtransfer->staging_texture,
  50                                 0, 0, 0, 0, texture, transfer->level,
  51                                 &transfer->box);
  52 }
  53
  54
  55 /* Copy from a transfer's staging texture to a full GPU one. */
  56 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
  57 {
  58         struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
  59         struct pipe_resource *texture = transfer->resource;
  60         struct pipe_box sbox;
  61
  62         sbox.x = sbox.y = sbox.z = 0;
  63         sbox.width = transfer->box.width;
  64         sbox.height = transfer->box.height;
  65         /* XXX that might be wrong */
  66         sbox.depth = 1;
  67         ctx->resource_copy_region(ctx, texture, transfer->level,
  68                                   transfer->box.x, transfer->box.y, transfer->box.z,
  69                                   rtransfer->staging_texture,
  70                                   0, &sbox);
  71
  72         ctx->flush(ctx, 0, NULL);
  73 }
  74
  75 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
  76                                         unsigned level, unsigned layer)
  77 {
  78         unsigned offset = rtex->offset[level];
  79
  80         switch (rtex->resource.base.b.target) {
  81         case PIPE_TEXTURE_3D:
  82         case PIPE_TEXTURE_CUBE:
  83                 return offset + layer * rtex->layer_size[level];
  84         default:
  85                 assert(layer == 0);
  86                 return offset;
  87         }
  88 }
  89
  90 static unsigned r600_get_pixel_alignment(struct pipe_screen *screen,
  91                                          enum pipe_format format,
  92                                          unsigned array_mode)
  93 {
  94         struct r600_screen* rscreen = (struct r600_screen *)screen;
  95         unsigned pixsize = util_format_get_blocksize(format);
  96         int p_align;
  97
  98         switch(array_mode) {
  99         case V_038000_ARRAY_1D_TILED_THIN1:
 100                 p_align = MAX2(8,
 101                                ((rscreen->tiling_info->group_bytes / 8 / pixsize)));
 102                 break;
 103         case V_038000_ARRAY_2D_TILED_THIN1:
 104                 p_align = MAX2(rscreen->tiling_info->num_banks,
 105                                (((rscreen->tiling_info->group_bytes / 8 / pixsize)) *
 106                                 rscreen->tiling_info->num_banks)) * 8;
 107                 break;
 108         case V_038000_ARRAY_LINEAR_GENERAL:
 109         default:
 110                 p_align = rscreen->tiling_info->group_bytes / pixsize;
 111                 break;
 112         }
 113         return p_align;
 114 }
 115
 116 static unsigned r600_get_height_alignment(struct pipe_screen *screen,
 117                                           unsigned array_mode)
 118 {
 119         struct r600_screen* rscreen = (struct r600_screen *)screen;
 120         int h_align;
 121
 122         switch (array_mode) {
 123         case V_038000_ARRAY_2D_TILED_THIN1:
 124                 h_align = rscreen->tiling_info->num_channels * 8;
 125                 break;
 126         case V_038000_ARRAY_1D_TILED_THIN1:
 127                 h_align = 8;
 128                 break;
 129         default:
 130                 h_align = 1;
 131                 break;
 132         }
 133         return h_align;
 134 }
 135
 136 static unsigned r600_get_base_alignment(struct pipe_screen *screen,
 137                                         enum pipe_format format,
 138                                         unsigned array_mode)
 139 {
 140         struct r600_screen* rscreen = (struct r600_screen *)screen;
 141         unsigned pixsize = util_format_get_blocksize(format);
 142         int p_align = r600_get_pixel_alignment(screen, format, array_mode);
 143         int h_align = r600_get_height_alignment(screen, array_mode);
 144         int b_align;
 145
 146         switch (array_mode) {
 147         case V_038000_ARRAY_2D_TILED_THIN1:
 148                 b_align = MAX2(rscreen->tiling_info->num_banks * rscreen->tiling_info->num_channels * 8 * 8 * pixsize,
 149                                p_align * pixsize * h_align);
 150                 break;
 151         case V_038000_ARRAY_1D_TILED_THIN1:
 152         default:
 153                 b_align = rscreen->tiling_info->group_bytes;
 154                 break;
 155         }
 156         return b_align;
 157 }
 158
 159 static unsigned mip_minify(unsigned size, unsigned level)
 160 {
 161         unsigned val;
 162         val = u_minify(size, level);
 163         if (level > 0)
 164                 val = util_next_power_of_two(val);
 165         return val;
 166 }
 167
 168 static unsigned r600_texture_get_stride(struct pipe_screen *screen,
 169                                         struct r600_resource_texture *rtex,
 170                                         unsigned level)
 171 {
 172         struct pipe_resource *ptex = &rtex->resource.base.b;
 173         struct radeon *radeon = (struct radeon *)screen->winsys;
 174         enum chip_class chipc = r600_get_family_class(radeon);
 175         unsigned width, stride, tile_width;
 176
 177         if (rtex->pitch_override)
 178                 return rtex->pitch_override;
 179
 180         width = mip_minify(ptex->width0, level);
 181         if (util_format_is_plain(ptex->format)) {
 182                 tile_width = r600_get_pixel_alignment(screen, ptex->format,
 183                                                       rtex->array_mode[level]);
 184                 width = align(width, tile_width);
 185         }
 186         stride = util_format_get_stride(ptex->format, width);
 187
 188         return stride;
 189 }
 190
 191 static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen,
 192                                           struct r600_resource_texture *rtex,
 193                                           unsigned level)
 194 {
 195         struct pipe_resource *ptex = &rtex->resource.base.b;
 196         unsigned height, tile_height;
 197
 198         height = mip_minify(ptex->height0, level);
 199         if (util_format_is_plain(ptex->format)) {
 200                 tile_height = r600_get_height_alignment(screen,
 201                                                         rtex->array_mode[level]);
 202                 height = align(height, tile_height);
 203         }
 204         return util_format_get_nblocksy(ptex->format, height);
 205 }
 206
 207 /* Get a width in pixels from a stride in bytes. */
 208 static unsigned pitch_to_width(enum pipe_format format,
 209                                 unsigned pitch_in_bytes)
 210 {
 211     return (pitch_in_bytes / util_format_get_blocksize(format)) *
 212             util_format_get_blockwidth(format);
 213 }
 214
 215 static void r600_texture_set_array_mode(struct pipe_screen *screen,
 216                                         struct r600_resource_texture *rtex,
 217                                         unsigned level, unsigned array_mode)
 218 {
 219         struct pipe_resource *ptex = &rtex->resource.base.b;
 220
 221         switch (array_mode) {
 222         case V_0280A0_ARRAY_LINEAR_GENERAL:
 223         case V_0280A0_ARRAY_LINEAR_ALIGNED:
 224         case V_0280A0_ARRAY_1D_TILED_THIN1:
 225         default:
 226                 rtex->array_mode[level] = array_mode;
 227                 break;
 228         case V_0280A0_ARRAY_2D_TILED_THIN1:
 229         {
 230                 unsigned w, h, tile_height, tile_width;
 231
 232                 tile_height = r600_get_height_alignment(screen, array_mode);
 233                 tile_width = r600_get_pixel_alignment(screen, ptex->format, array_mode);
 234
 235                 w = mip_minify(ptex->width0, level);
 236                 h = mip_minify(ptex->height0, level);
 237                 if (w < tile_width || h < tile_height)
 238                         rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1;
 239                 else
 240                         rtex->array_mode[level] = array_mode;
 241         }
 242         break;
 243         }
 244 }
 245
 246 static void r600_setup_miptree(struct pipe_screen *screen,
 247                                struct r600_resource_texture *rtex,
 248                                unsigned array_mode)
 249 {
 250         struct pipe_resource *ptex = &rtex->resource.base.b;
 251         struct radeon *radeon = (struct radeon *)screen->winsys;
 252         enum chip_class chipc = r600_get_family_class(radeon);
 253         unsigned pitch, size, layer_size, i, offset;
 254         unsigned nblocksy;
 255
 256         for (i = 0, offset = 0; i <= ptex->last_level; i++) {
 257                 r600_texture_set_array_mode(screen, rtex, i, array_mode);
 258
 259                 pitch = r600_texture_get_stride(screen, rtex, i);
 260                 nblocksy = r600_texture_get_nblocksy(screen, rtex, i);
 261
 262                 layer_size = pitch * nblocksy;
 263
 264                 if (ptex->target == PIPE_TEXTURE_CUBE) {
 265                         if (chipc >= R700)
 266                                 size = layer_size * 8;
 267                         else
 268                                 size = layer_size * 6;
 269                 }
 270                 else
 271                         size = layer_size * u_minify(ptex->depth0, i);
 272                 /* align base image and start of miptree */
 273                 if ((i == 0) || (i == 1))
 274                         offset = align(offset, r600_get_base_alignment(screen, ptex->format, array_mode));
 275                 rtex->offset[i] = offset;
 276                 rtex->layer_size[i] = layer_size;
 277                 rtex->pitch_in_bytes[i] = pitch;
 278                 rtex->pitch_in_pixels[i] = pitch_to_width(ptex->format, pitch);
 279                 offset += size;
 280         }
 281         rtex->size = offset;
 282 }
 283
 284 static struct r600_resource_texture *
 285 r600_texture_create_object(struct pipe_screen *screen,
 286                            const struct pipe_resource *base,
 287                            unsigned array_mode,
 288                            unsigned pitch_in_bytes_override,
 289                            unsigned max_buffer_size,
 290                            struct r600_bo *bo)
 291 {
 292         struct r600_resource_texture *rtex;
 293         struct r600_resource *resource;
 294         struct radeon *radeon = (struct radeon *)screen->winsys;
 295
 296         rtex = CALLOC_STRUCT(r600_resource_texture);
 297         if (rtex == NULL)
 298                 return NULL;
 299
 300         resource = &rtex->resource;
 301         resource->base.b = *base;
 302         resource->base.vtbl = &r600_texture_vtbl;
 303         pipe_reference_init(&resource->base.b.reference, 1);
 304         resource->base.b.screen = screen;
 305         resource->bo = bo;
 306         rtex->pitch_override = pitch_in_bytes_override;
 307
 308         if (array_mode)
 309                 rtex->tiled = 1;
 310         r600_setup_miptree(screen, rtex, array_mode);
 311
 312         resource->size = rtex->size;
 313
 314         if (!resource->bo) {
 315                 struct pipe_resource *ptex = &rtex->resource.base.b;
 316                 int base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
 317
 318                 resource->bo = r600_bo(radeon, rtex->size, base_align, base->bind, base->usage);
 319                 if (!resource->bo) {
 320                         FREE(rtex);
 321                         return NULL;
 322                 }
 323         }
 324         return rtex;
 325 }
 326
 327 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 328                                                 const struct pipe_resource *templ)
 329 {
 330         unsigned array_mode = 0;
 331         static int force_tiling = -1;
 332
 333         /* Would like some magic "get_bool_option_once" routine.
 334          */
 335         if (force_tiling == -1)
 336                 force_tiling = debug_get_bool_option("R600_FORCE_TILING", FALSE);
 337
 338         if (force_tiling) {
 339                 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
 340                     !(templ->bind & PIPE_BIND_SCANOUT)) {
 341                         array_mode = V_038000_ARRAY_2D_TILED_THIN1;
 342                 }
 343         }
 344
 345         return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
 346                                                                   0, 0, NULL);
 347
 348 }
 349
 350 static void r600_texture_destroy(struct pipe_screen *screen,
 351                                  struct pipe_resource *ptex)
 352 {
 353         struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 354         struct r600_resource *resource = &rtex->resource;
 355         struct radeon *radeon = (struct radeon *)screen->winsys;
 356
 357         if (rtex->flushed_depth_texture)
 358                 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
 359
 360         if (resource->bo) {
 361                 r600_bo_reference(radeon, &resource->bo, NULL);
 362         }
 363         FREE(rtex);
 364 }
 365
 366 static boolean r600_texture_get_handle(struct pipe_screen* screen,
 367                                        struct pipe_resource *ptex,
 368                                        struct winsys_handle *whandle)
 369 {
 370         struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 371         struct r600_resource *resource = &rtex->resource;
 372         struct radeon *radeon = (struct radeon *)screen->winsys;
 373
 374         return r600_bo_get_winsys_handle(radeon, resource->bo,
 375                         rtex->pitch_in_bytes[0], whandle);
 376 }
 377
 378 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
 379                                                 struct pipe_resource *texture,
 380                                                 const struct pipe_surface *surf_tmpl)
 381 {
 382         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 383         struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
 384         unsigned tile_height;
 385         unsigned level = surf_tmpl->u.tex.level;
 386
 387         assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
 388         if (surface == NULL)
 389                 return NULL;
 390         /* XXX no offset */
 391 /*      offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/
 392         pipe_reference_init(&surface->base.reference, 1);
 393         pipe_resource_reference(&surface->base.texture, texture);
 394         surface->base.context = pipe;
 395         surface->base.format = surf_tmpl->format;
 396         surface->base.width = mip_minify(texture->width0, level);
 397         surface->base.height = mip_minify(texture->height0, level);
 398         surface->base.usage = surf_tmpl->usage;
 399         surface->base.texture = texture;
 400         surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
 401         surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
 402         surface->base.u.tex.level = level;
 403
 404         tile_height = r600_get_height_alignment(pipe->screen, rtex->array_mode[level]);
 405         surface->aligned_height = align(surface->base.height, tile_height);
 406         return &surface->base;
 407 }
 408
 409 static void r600_surface_destroy(struct pipe_context *pipe,
 410                                  struct pipe_surface *surface)
 411 {
 412         pipe_resource_reference(&surface->texture, NULL);
 413         FREE(surface);
 414 }
 415
 416
 417 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
 418                                                const struct pipe_resource *templ,
 419                                                struct winsys_handle *whandle)
 420 {
 421         struct radeon *rw = (struct radeon*)screen->winsys;
 422         struct r600_bo *bo = NULL;
 423         unsigned array_mode = 0;
 424
 425         /* Support only 2D textures without mipmaps */
 426         if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
 427               templ->depth0 != 1 || templ->last_level != 0)
 428                 return NULL;
 429
 430         bo = r600_bo_handle(rw, whandle->handle, &array_mode);
 431         if (bo == NULL) {
 432                 return NULL;
 433         }
 434
 435         return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
 436                                                                   whandle->stride,
 437                                                                   0,
 438                                                                   bo);
 439 }
 440
 441 static unsigned int r600_texture_is_referenced(struct pipe_context *context,
 442                                                 struct pipe_resource *texture,
 443                                                 unsigned level, int layer)
 444 {
 445         /* FIXME */
 446         return PIPE_REFERENCED_FOR_READ | PIPE_REFERENCED_FOR_WRITE;
 447 }
 448
 449 int (*r600_blit_uncompress_depth_ptr)(struct pipe_context *ctx, struct r600_resource_texture *texture);
 450
 451 int r600_texture_depth_flush(struct pipe_context *ctx,
 452                              struct pipe_resource *texture)
 453 {
 454         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 455         struct pipe_resource resource;
 456
 457         if (rtex->flushed_depth_texture)
 458                 goto out;
 459
 460         resource.target = PIPE_TEXTURE_2D;
 461         resource.format = texture->format;
 462         resource.width0 = texture->width0;
 463         resource.height0 = texture->height0;
 464         resource.depth0 = 1;
 465         resource.last_level = 0;
 466         resource.nr_samples = 0;
 467         resource.usage = PIPE_USAGE_DYNAMIC;
 468         resource.bind = 0;
 469         resource.flags = R600_RESOURCE_FLAG_TRANSFER;
 470
 471         resource.bind |= PIPE_BIND_DEPTH_STENCIL;
 472
 473         rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
 474         if (rtex->flushed_depth_texture == NULL) {
 475                 R600_ERR("failed to create temporary texture to hold untiled copy\n");
 476                 return -ENOMEM;
 477         }
 478
 479 out:
 480         /* XXX: only do this if the depth texture has actually changed:
 481          */
 482         r600_blit_uncompress_depth_ptr(ctx, rtex);
 483         return 0;
 484 }
 485
 486 /* Needs adjustment for pixelformat:
 487  */
 488 static INLINE unsigned u_box_volume( const struct pipe_box *box )
 489 {
 490         return box->width * box->depth * box->height;
 491 };
 492
 493
 494 /* Figure out whether u_blitter will fallback to a transfer operation.
 495  * If so, don't use a staging resource.
 496  */
 497 static boolean permit_hardware_blit(struct pipe_screen *screen,
 498                                     struct pipe_resource *res)
 499 {
 500         unsigned bind;
 501
 502         if (util_format_is_depth_or_stencil(res->format))
 503                 bind = PIPE_BIND_DEPTH_STENCIL;
 504         else
 505                 bind = PIPE_BIND_RENDER_TARGET;
 506
 507         /* See r600_resource_copy_region: there is something wrong
 508          * with depth resource copies at the moment so avoid them for
 509          * now.
 510          */
 511         if (util_format_get_component_bits(res->format,
 512                                            UTIL_FORMAT_COLORSPACE_ZS,
 513                                            0) != 0)
 514                 return FALSE;
 515
 516         if (!screen->is_format_supported(screen,
 517                                          res->format,
 518                                          res->target,
 519                                          res->nr_samples,
 520                                          bind, 0))
 521                 return FALSE;
 522
 523         if (!screen->is_format_supported(screen,
 524                                          res->format,
 525                                          res->target,
 526                                          res->nr_samples,
 527                                          PIPE_BIND_SAMPLER_VIEW, 0))
 528                 return FALSE;
 529
 530         return TRUE;
 531 }
 532
 533 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 534                                                 struct pipe_resource *texture,
 535                                                 unsigned level,
 536                                                 unsigned usage,
 537                                                 const struct pipe_box *box)
 538 {
 539         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 540         struct pipe_resource resource;
 541         struct r600_transfer *trans;
 542         int r;
 543         boolean use_staging_texture = FALSE;
 544
 545         /* We cannot map a tiled texture directly because the data is
 546          * in a different order, therefore we do detiling using a blit.
 547          *
 548          * Also, use a temporary in GTT memory for read transfers, as
 549          * the CPU is much happier reading out of cached system memory
 550          * than uncached VRAM.
 551          */
 552         if (rtex->tiled)
 553                 use_staging_texture = TRUE;
 554
 555         if ((usage & PIPE_TRANSFER_READ) &&
 556             u_box_volume(box) > 1024)
 557                 use_staging_texture = TRUE;
 558
 559         /* XXX: Use a staging texture for uploads if the underlying BO
 560          * is busy.  No interface for checking that currently? so do
 561          * it eagerly whenever the transfer doesn't require a readback
 562          * and might block.
 563          */
 564         if ((usage & PIPE_TRANSFER_WRITE) &&
 565             !(usage & (PIPE_TRANSFER_READ |
 566                        PIPE_TRANSFER_DONTBLOCK |
 567                        PIPE_TRANSFER_UNSYNCHRONIZED)))
 568                 use_staging_texture = TRUE;
 569
 570         if (!permit_hardware_blit(ctx->screen, texture) ||
 571             (texture->flags & R600_RESOURCE_FLAG_TRANSFER))
 572                 use_staging_texture = FALSE;
 573
 574         trans = CALLOC_STRUCT(r600_transfer);
 575         if (trans == NULL)
 576                 return NULL;
 577         pipe_resource_reference(&trans->transfer.resource, texture);
 578         trans->transfer.level = level;
 579         trans->transfer.usage = usage;
 580         trans->transfer.box = *box;
 581         if (rtex->depth) {
 582                 /* XXX: only readback the rectangle which is being mapped?
 583                  */
 584                 /* XXX: when discard is true, no need to read back from depth texture
 585                  */
 586                 r = r600_texture_depth_flush(ctx, texture);
 587                 if (r < 0) {
 588                         R600_ERR("failed to create temporary texture to hold untiled copy\n");
 589                         pipe_resource_reference(&trans->transfer.resource, NULL);
 590                         FREE(trans);
 591                         return NULL;
 592                 }
 593         } else if (use_staging_texture) {
 594                 resource.target = PIPE_TEXTURE_2D;
 595                 resource.format = texture->format;
 596                 resource.width0 = box->width;
 597                 resource.height0 = box->height;
 598                 resource.depth0 = 1;
 599                 resource.array_size = 1;
 600                 resource.last_level = 0;
 601                 resource.nr_samples = 0;
 602                 resource.usage = PIPE_USAGE_STAGING;
 603                 resource.bind = 0;
 604                 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
 605                 /* For texture reading, the temporary (detiled) texture is used as
 606                  * a render target when blitting from a tiled texture. */
 607                 if (usage & PIPE_TRANSFER_READ) {
 608                         resource.bind |= PIPE_BIND_RENDER_TARGET;
 609                 }
 610                 /* For texture writing, the temporary texture is used as a sampler
 611                  * when blitting into a tiled texture. */
 612                 if (usage & PIPE_TRANSFER_WRITE) {
 613                         resource.bind |= PIPE_BIND_SAMPLER_VIEW;
 614                 }
 615                 /* Create the temporary texture. */
 616                 trans->staging_texture = ctx->screen->resource_create(ctx->screen, &resource);
 617                 if (trans->staging_texture == NULL) {
 618                         R600_ERR("failed to create temporary texture to hold untiled copy\n");
 619                         pipe_resource_reference(&trans->transfer.resource, NULL);
 620                         FREE(trans);
 621                         return NULL;
 622                 }
 623
 624                 trans->transfer.stride =
 625                         ((struct r600_resource_texture *)trans->staging_texture)->pitch_in_bytes[0];
 626                 if (usage & PIPE_TRANSFER_READ) {
 627                         r600_copy_to_staging_texture(ctx, trans);
 628                         /* Always referenced in the blit. */
 629                         ctx->flush(ctx, 0, NULL);
 630                 }
 631                 return &trans->transfer;
 632         }
 633         trans->transfer.stride = rtex->pitch_in_bytes[level];
 634         trans->offset = r600_texture_get_offset(rtex, level, box->z);
 635         return &trans->transfer;
 636 }
 637
 638 void r600_texture_transfer_destroy(struct pipe_context *ctx,
 639                                    struct pipe_transfer *transfer)
 640 {
 641         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 642         struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 643
 644         if (rtransfer->staging_texture) {
 645                 if (transfer->usage & PIPE_TRANSFER_WRITE) {
 646                         r600_copy_from_staging_texture(ctx, rtransfer);
 647                 }
 648                 pipe_resource_reference(&rtransfer->staging_texture, NULL);
 649         }
 650         if (rtex->flushed_depth_texture) {
 651                 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
 652         }
 653         pipe_resource_reference(&transfer->resource, NULL);
 654         FREE(transfer);
 655 }
 656
 657 void* r600_texture_transfer_map(struct pipe_context *ctx,
 658                                 struct pipe_transfer* transfer)
 659 {
 660         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 661         struct r600_bo *bo;
 662         enum pipe_format format = transfer->resource->format;
 663         struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
 664         unsigned offset = 0;
 665         unsigned usage = 0;
 666         char *map;
 667
 668         if (rtransfer->staging_texture) {
 669                 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
 670         } else {
 671                 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 672
 673                 if (rtex->flushed_depth_texture)
 674                         bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
 675                 else
 676                         bo = ((struct r600_resource *)transfer->resource)->bo;
 677
 678                 offset = rtransfer->offset +
 679                         transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
 680                         transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
 681         }
 682
 683         if (transfer->usage & PIPE_TRANSFER_WRITE) {
 684                 usage |= PB_USAGE_CPU_WRITE;
 685
 686                 if (transfer->usage & PIPE_TRANSFER_DISCARD) {
 687                 }
 688
 689                 if (transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT) {
 690                 }
 691         }
 692
 693         if (transfer->usage & PIPE_TRANSFER_READ) {
 694                 usage |= PB_USAGE_CPU_READ;
 695         }
 696
 697         if (transfer->usage & PIPE_TRANSFER_DONTBLOCK) {
 698                 usage |= PB_USAGE_DONTBLOCK;
 699         }
 700
 701         if (transfer->usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
 702                 usage |= PB_USAGE_UNSYNCHRONIZED;
 703         }
 704
 705         map = r600_bo_map(radeon, bo, usage, ctx);
 706         if (!map) {
 707                 return NULL;
 708         }
 709
 710         return map + offset;
 711 }
 712
 713 void r600_texture_transfer_unmap(struct pipe_context *ctx,
 714                                  struct pipe_transfer* transfer)
 715 {
 716         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 717         struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
 718         struct r600_bo *bo;
 719
 720         if (rtransfer->staging_texture) {
 721                 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
 722         } else {
 723                 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 724
 725                 if (rtex->flushed_depth_texture) {
 726                         bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
 727                 } else {
 728                         bo = ((struct r600_resource *)transfer->resource)->bo;
 729                 }
 730         }
 731         r600_bo_unmap(radeon, bo);
 732 }
 733
 734 struct u_resource_vtbl r600_texture_vtbl =
 735 {
 736         r600_texture_get_handle,        /* get_handle */
 737         r600_texture_destroy,           /* resource_destroy */
 738         r600_texture_is_referenced,     /* is_resource_referenced */
 739         r600_texture_get_transfer,      /* get_transfer */
 740         r600_texture_transfer_destroy,  /* transfer_destroy */
 741         r600_texture_transfer_map,      /* transfer_map */
 742         u_default_transfer_flush_region,/* transfer_flush_region */
 743         r600_texture_transfer_unmap,    /* transfer_unmap */
 744         u_default_transfer_inline_write /* transfer_inline_write */
 745 };
 746
 747 void r600_init_surface_functions(struct r600_pipe_context *r600)
 748 {
 749         r600->context.create_surface = r600_create_surface;
 750         r600->context.surface_destroy = r600_surface_destroy;
 751 }
 752
 753 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
 754                 const unsigned char *swizzle_view)
 755 {
 756         unsigned i;
 757         unsigned char swizzle[4];
 758         unsigned result = 0;
 759         const uint32_t swizzle_shift[4] = {
 760                 16, 19, 22, 25,
 761         };
 762         const uint32_t swizzle_bit[4] = {
 763                 0, 1, 2, 3,
 764         };
 765
 766         if (swizzle_view) {
 767                 /* Combine two sets of swizzles. */
 768                 for (i = 0; i < 4; i++) {
 769                         swizzle[i] = swizzle_view[i] <= UTIL_FORMAT_SWIZZLE_W ?
 770                                 swizzle_format[swizzle_view[i]] : swizzle_view[i];
 771                 }
 772         } else {
 773                 memcpy(swizzle, swizzle_format, 4);
 774         }
 775
 776         /* Get swizzle. */
 777         for (i = 0; i < 4; i++) {
 778                 switch (swizzle[i]) {
 779                 case UTIL_FORMAT_SWIZZLE_Y:
 780                         result |= swizzle_bit[1] << swizzle_shift[i];
 781                         break;
 782                 case UTIL_FORMAT_SWIZZLE_Z:
 783                         result |= swizzle_bit[2] << swizzle_shift[i];
 784                         break;
 785                 case UTIL_FORMAT_SWIZZLE_W:
 786                         result |= swizzle_bit[3] << swizzle_shift[i];
 787                         break;
 788                 case UTIL_FORMAT_SWIZZLE_0:
 789                         result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
 790                         break;
 791                 case UTIL_FORMAT_SWIZZLE_1:
 792                         result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
 793                         break;
 794                 default: /* UTIL_FORMAT_SWIZZLE_X */
 795                         result |= swizzle_bit[0] << swizzle_shift[i];
 796                 }
 797         }
 798         return result;
 799 }
 800
 801 /* texture format translate */
 802 uint32_t r600_translate_texformat(enum pipe_format format,
 803                                   const unsigned char *swizzle_view,
 804                                   uint32_t *word4_p, uint32_t *yuv_format_p)
 805 {
 806         uint32_t result = 0, word4 = 0, yuv_format = 0;
 807         const struct util_format_description *desc;
 808         boolean uniform = TRUE;
 809         int i;
 810         const uint32_t sign_bit[4] = {
 811                 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
 812                 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
 813                 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
 814                 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
 815         };
 816         desc = util_format_description(format);
 817
 818         word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
 819
 820         /* Colorspace (return non-RGB formats directly). */
 821         switch (desc->colorspace) {
 822                 /* Depth stencil formats */
 823         case UTIL_FORMAT_COLORSPACE_ZS:
 824                 switch (format) {
 825                 case PIPE_FORMAT_Z16_UNORM:
 826                         result = FMT_16;
 827                         goto out_word4;
 828                 case PIPE_FORMAT_X24S8_USCALED:
 829                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 830                 case PIPE_FORMAT_Z24X8_UNORM:
 831                 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
 832                         result = FMT_8_24;
 833                         goto out_word4;
 834                 case PIPE_FORMAT_S8X24_USCALED:
 835                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 836                 case PIPE_FORMAT_X8Z24_UNORM:
 837                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 838                         result = FMT_24_8;
 839                         goto out_word4;
 840                 case PIPE_FORMAT_S8_USCALED:
 841                         result = FMT_8;
 842                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 843                         goto out_word4;
 844                 default:
 845                         goto out_unknown;
 846                 }
 847
 848         case UTIL_FORMAT_COLORSPACE_YUV:
 849                 yuv_format |= (1 << 30);
 850                 switch (format) {
 851                 case PIPE_FORMAT_UYVY:
 852                 case PIPE_FORMAT_YUYV:
 853                 default:
 854                         break;
 855                 }
 856                 goto out_unknown; /* TODO */
 857
 858         case UTIL_FORMAT_COLORSPACE_SRGB:
 859                 word4 |= S_038010_FORCE_DEGAMMA(1);
 860                 if (format == PIPE_FORMAT_L8A8_SRGB || format == PIPE_FORMAT_L8_SRGB)
 861                         goto out_unknown; /* fails for some reason - TODO */
 862                 break;
 863
 864         default:
 865                 break;
 866         }
 867
 868         /* S3TC formats. TODO */
 869         if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
 870                 static int r600_enable_s3tc = -1;
 871
 872                 if (r600_enable_s3tc == -1)
 873                         r600_enable_s3tc =
 874                                 debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
 875
 876                 if (!r600_enable_s3tc)
 877                         goto out_unknown;
 878
 879                 switch (format) {
 880                 case PIPE_FORMAT_DXT1_RGB:
 881                 case PIPE_FORMAT_DXT1_RGBA:
 882                         result = FMT_BC1;
 883                         goto out_word4;
 884                 case PIPE_FORMAT_DXT3_RGBA:
 885                         result = FMT_BC2;
 886                         goto out_word4;
 887                 case PIPE_FORMAT_DXT5_RGBA:
 888                         result = FMT_BC3;
 889                         goto out_word4;
 890                 default:
 891                         goto out_unknown;
 892                 }
 893         }
 894
 895
 896         for (i = 0; i < desc->nr_channels; i++) {
 897                 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
 898                         word4 |= sign_bit[i];
 899                 }
 900         }
 901
 902         /* R8G8Bx_SNORM - TODO CxV8U8 */
 903
 904         /* RGTC - TODO */
 905
 906         /* See whether the components are of the same size. */
 907         for (i = 1; i < desc->nr_channels; i++) {
 908                 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
 909         }
 910
 911         /* Non-uniform formats. */
 912         if (!uniform) {
 913                 switch(desc->nr_channels) {
 914                 case 3:
 915                         if (desc->channel[0].size == 5 &&
 916                             desc->channel[1].size == 6 &&
 917                             desc->channel[2].size == 5) {
 918                                 result = FMT_5_6_5;
 919                                 goto out_word4;
 920                         }
 921                         goto out_unknown;
 922                 case 4:
 923                         if (desc->channel[0].size == 5 &&
 924                             desc->channel[1].size == 5 &&
 925                             desc->channel[2].size == 5 &&
 926                             desc->channel[3].size == 1) {
 927                                 result = FMT_1_5_5_5;
 928                                 goto out_word4;
 929                         }
 930                         if (desc->channel[0].size == 10 &&
 931                             desc->channel[1].size == 10 &&
 932                             desc->channel[2].size == 10 &&
 933                             desc->channel[3].size == 2) {
 934                                 result = FMT_10_10_10_2;
 935                                 goto out_word4;
 936                         }
 937                         goto out_unknown;
 938                 }
 939                 goto out_unknown;
 940         }
 941
 942         /* Find the first non-VOID channel. */
 943         for (i = 0; i < 4; i++) {
 944                 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
 945                         break;
 946                 }
 947         }
 948
 949         if (i == 4)
 950                 goto out_unknown;
 951
 952         /* uniform formats */
 953         switch (desc->channel[i].type) {
 954         case UTIL_FORMAT_TYPE_UNSIGNED:
 955         case UTIL_FORMAT_TYPE_SIGNED:
 956                 if (!desc->channel[i].normalized &&
 957                     desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
 958                         goto out_unknown;
 959                 }
 960
 961                 switch (desc->channel[i].size) {
 962                 case 4:
 963                         switch (desc->nr_channels) {
 964                         case 2:
 965                                 result = FMT_4_4;
 966                                 goto out_word4;
 967                         case 4:
 968                                 result = FMT_4_4_4_4;
 969                                 goto out_word4;
 970                         }
 971                         goto out_unknown;
 972                 case 8:
 973                         switch (desc->nr_channels) {
 974                         case 1:
 975                                 result = FMT_8;
 976                                 goto out_word4;
 977                         case 2:
 978                                 result = FMT_8_8;
 979                                 goto out_word4;
 980                         case 4:
 981                                 result = FMT_8_8_8_8;
 982                                 goto out_word4;
 983                         }
 984                         goto out_unknown;
 985                 case 16:
 986                         switch (desc->nr_channels) {
 987                         case 1:
 988                                 result = FMT_16;
 989                                 goto out_word4;
 990                         case 2:
 991                                 result = FMT_16_16;
 992                                 goto out_word4;
 993                         case 4:
 994                                 result = FMT_16_16_16_16;
 995                                 goto out_word4;
 996                         }
 997                 }
 998                 goto out_unknown;
 999
1000         case UTIL_FORMAT_TYPE_FLOAT:
1001                 switch (desc->channel[i].size) {
1002                 case 16:
1003                         switch (desc->nr_channels) {
1004                         case 1:
1005                                 result = FMT_16_FLOAT;
1006                                 goto out_word4;
1007                         case 2:
1008                                 result = FMT_16_16_FLOAT;
1009                                 goto out_word4;
1010                         case 4:
1011                                 result = FMT_16_16_16_16_FLOAT;
1012                                 goto out_word4;
1013                         }
1014                         goto out_unknown;
1015                 case 32:
1016                         switch (desc->nr_channels) {
1017                         case 1:
1018                                 result = FMT_32_FLOAT;
1019                                 goto out_word4;
1020                         case 2:
1021                                 result = FMT_32_32_FLOAT;
1022                                 goto out_word4;
1023                         case 4:
1024                                 result = FMT_32_32_32_32_FLOAT;
1025                                 goto out_word4;
1026                         }
1027                 }
1028
1029         }
1030 out_word4:
1031         if (word4_p)
1032                 *word4_p = word4;
1033         if (yuv_format_p)
1034                 *yuv_format_p = yuv_format;
1035         return result;
1036 out_unknown:
1037 //      R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format));
1038         return ~0;
1039 }