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winsys/radeon: add usage parameter to cs_is_buffer_referenced
[mesa.git] / src / gallium / drivers / r600 / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include <errno.h>
28 #include "pipe/p_screen.h"
29 #include "util/u_format.h"
30 #include "util/u_format_s3tc.h"
31 #include "util/u_math.h"
32 #include "util/u_inlines.h"
33 #include "util/u_memory.h"
34 #include "pipebuffer/pb_buffer.h"
35 #include "r600_pipe.h"
36 #include "r600_resource.h"
37 #include "r600d.h"
38 #include "r600_formats.h"
39
40 /* Copy from a full GPU texture to a transfer's staging one. */
41 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
42 {
43 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
44 struct pipe_resource *texture = transfer->resource;
45
46 ctx->resource_copy_region(ctx, &rtransfer->staging->b.b.b,
47 0, 0, 0, 0, texture, transfer->level,
48 &transfer->box);
49 }
50
51
52 /* Copy from a transfer's staging texture to a full GPU one. */
53 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
54 {
55 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
56 struct pipe_resource *texture = transfer->resource;
57 struct pipe_box sbox;
58
59 sbox.x = sbox.y = sbox.z = 0;
60 sbox.width = transfer->box.width;
61 sbox.height = transfer->box.height;
62 /* XXX that might be wrong */
63 sbox.depth = 1;
64 ctx->resource_copy_region(ctx, texture, transfer->level,
65 transfer->box.x, transfer->box.y, transfer->box.z,
66 &rtransfer->staging->b.b.b,
67 0, &sbox);
68 }
69
70 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
71 unsigned level, unsigned layer)
72 {
73 unsigned offset = rtex->offset[level];
74
75 switch (rtex->resource.b.b.b.target) {
76 case PIPE_TEXTURE_3D:
77 case PIPE_TEXTURE_CUBE:
78 default:
79 return offset + layer * rtex->layer_size[level];
80 }
81 }
82
83 static unsigned r600_get_block_alignment(struct pipe_screen *screen,
84 enum pipe_format format,
85 unsigned array_mode)
86 {
87 struct r600_screen* rscreen = (struct r600_screen *)screen;
88 unsigned pixsize = util_format_get_blocksize(format);
89 int p_align;
90
91 switch(array_mode) {
92 case V_038000_ARRAY_1D_TILED_THIN1:
93 p_align = MAX2(8,
94 ((rscreen->tiling_info.group_bytes / 8 / pixsize)));
95 break;
96 case V_038000_ARRAY_2D_TILED_THIN1:
97 p_align = MAX2(rscreen->tiling_info.num_banks,
98 (((rscreen->tiling_info.group_bytes / 8 / pixsize)) *
99 rscreen->tiling_info.num_banks)) * 8;
100 break;
101 case V_038000_ARRAY_LINEAR_ALIGNED:
102 p_align = MAX2(64, rscreen->tiling_info.group_bytes / pixsize);
103 break;
104 case V_038000_ARRAY_LINEAR_GENERAL:
105 default:
106 p_align = rscreen->tiling_info.group_bytes / pixsize;
107 break;
108 }
109 return p_align;
110 }
111
112 static unsigned r600_get_height_alignment(struct pipe_screen *screen,
113 unsigned array_mode)
114 {
115 struct r600_screen* rscreen = (struct r600_screen *)screen;
116 int h_align;
117
118 switch (array_mode) {
119 case V_038000_ARRAY_2D_TILED_THIN1:
120 h_align = rscreen->tiling_info.num_channels * 8;
121 break;
122 case V_038000_ARRAY_1D_TILED_THIN1:
123 case V_038000_ARRAY_LINEAR_ALIGNED:
124 h_align = 8;
125 break;
126 case V_038000_ARRAY_LINEAR_GENERAL:
127 default:
128 h_align = 1;
129 break;
130 }
131 return h_align;
132 }
133
134 static unsigned r600_get_base_alignment(struct pipe_screen *screen,
135 enum pipe_format format,
136 unsigned array_mode)
137 {
138 struct r600_screen* rscreen = (struct r600_screen *)screen;
139 unsigned pixsize = util_format_get_blocksize(format);
140 int p_align = r600_get_block_alignment(screen, format, array_mode);
141 int h_align = r600_get_height_alignment(screen, array_mode);
142 int b_align;
143
144 switch (array_mode) {
145 case V_038000_ARRAY_2D_TILED_THIN1:
146 b_align = MAX2(rscreen->tiling_info.num_banks * rscreen->tiling_info.num_channels * 8 * 8 * pixsize,
147 p_align * pixsize * h_align);
148 break;
149 case V_038000_ARRAY_1D_TILED_THIN1:
150 case V_038000_ARRAY_LINEAR_ALIGNED:
151 case V_038000_ARRAY_LINEAR_GENERAL:
152 default:
153 b_align = rscreen->tiling_info.group_bytes;
154 break;
155 }
156 return b_align;
157 }
158
159 static unsigned mip_minify(unsigned size, unsigned level)
160 {
161 unsigned val;
162 val = u_minify(size, level);
163 if (level > 0)
164 val = util_next_power_of_two(val);
165 return val;
166 }
167
168 static unsigned r600_texture_get_nblocksx(struct pipe_screen *screen,
169 struct r600_resource_texture *rtex,
170 unsigned level)
171 {
172 struct pipe_resource *ptex = &rtex->resource.b.b.b;
173 unsigned nblocksx, block_align, width;
174 unsigned blocksize = util_format_get_blocksize(rtex->real_format);
175
176 if (rtex->pitch_override)
177 return rtex->pitch_override / blocksize;
178
179 width = mip_minify(ptex->width0, level);
180 nblocksx = util_format_get_nblocksx(rtex->real_format, width);
181
182 block_align = r600_get_block_alignment(screen, rtex->real_format,
183 rtex->array_mode[level]);
184 nblocksx = align(nblocksx, block_align);
185 return nblocksx;
186 }
187
188 static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen,
189 struct r600_resource_texture *rtex,
190 unsigned level)
191 {
192 struct pipe_resource *ptex = &rtex->resource.b.b.b;
193 unsigned height, tile_height;
194
195 height = mip_minify(ptex->height0, level);
196 height = util_format_get_nblocksy(rtex->real_format, height);
197 tile_height = r600_get_height_alignment(screen,
198 rtex->array_mode[level]);
199
200 /* XXX Hack around an alignment issue. Less tests fail with this.
201 *
202 * The thing is depth-stencil buffers should be tiled, i.e.
203 * the alignment should be >=8. If I make them tiled, stencil starts
204 * working because it no longer overlaps with the depth buffer
205 * in memory, but texturing like drawpix-stencil breaks. */
206 if (util_format_is_depth_or_stencil(rtex->real_format) && tile_height < 8)
207 tile_height = 8;
208
209 height = align(height, tile_height);
210 return height;
211 }
212
213 static void r600_texture_set_array_mode(struct pipe_screen *screen,
214 struct r600_resource_texture *rtex,
215 unsigned level, unsigned array_mode)
216 {
217 struct pipe_resource *ptex = &rtex->resource.b.b.b;
218
219 switch (array_mode) {
220 case V_0280A0_ARRAY_LINEAR_GENERAL:
221 case V_0280A0_ARRAY_LINEAR_ALIGNED:
222 case V_0280A0_ARRAY_1D_TILED_THIN1:
223 default:
224 rtex->array_mode[level] = array_mode;
225 break;
226 case V_0280A0_ARRAY_2D_TILED_THIN1:
227 {
228 unsigned w, h, tile_height, tile_width;
229
230 tile_height = r600_get_height_alignment(screen, array_mode);
231 tile_width = r600_get_block_alignment(screen, rtex->real_format, array_mode);
232
233 w = mip_minify(ptex->width0, level);
234 h = mip_minify(ptex->height0, level);
235 if (w <= tile_width || h <= tile_height)
236 rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1;
237 else
238 rtex->array_mode[level] = array_mode;
239 }
240 break;
241 }
242 }
243
244 static int r600_init_surface(struct radeon_surface *surface,
245 const struct pipe_resource *ptex,
246 unsigned array_mode)
247 {
248 surface->npix_x = ptex->width0;
249 surface->npix_y = ptex->height0;
250 surface->npix_z = ptex->depth0;
251 surface->blk_w = util_format_get_blockwidth(ptex->format);
252 surface->blk_h = util_format_get_blockheight(ptex->format);
253 surface->blk_d = 1;
254 surface->array_size = 1;
255 surface->last_level = ptex->last_level;
256 surface->bpe = util_format_get_blocksize(ptex->format);
257 /* align byte per element on dword */
258 if (surface->bpe == 3) {
259 surface->bpe = 4;
260 }
261 surface->nsamples = 1;
262 surface->flags = 0;
263 switch (array_mode) {
264 case V_038000_ARRAY_1D_TILED_THIN1:
265 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
266 break;
267 case V_038000_ARRAY_2D_TILED_THIN1:
268 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
269 break;
270 case V_038000_ARRAY_LINEAR_ALIGNED:
271 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
272 break;
273 case V_038000_ARRAY_LINEAR_GENERAL:
274 default:
275 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE);
276 break;
277 }
278 switch (ptex->target) {
279 case PIPE_TEXTURE_1D:
280 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
281 break;
282 case PIPE_TEXTURE_RECT:
283 case PIPE_TEXTURE_2D:
284 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
285 break;
286 case PIPE_TEXTURE_3D:
287 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
288 break;
289 case PIPE_TEXTURE_1D_ARRAY:
290 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
291 surface->array_size = ptex->array_size;
292 break;
293 case PIPE_TEXTURE_2D_ARRAY:
294 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
295 surface->array_size = ptex->array_size;
296 break;
297 case PIPE_TEXTURE_CUBE:
298 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
299 break;
300 case PIPE_BUFFER:
301 default:
302 return -EINVAL;
303 }
304 if (ptex->bind & PIPE_BIND_SCANOUT) {
305 surface->flags |= RADEON_SURF_SCANOUT;
306 }
307 if (util_format_is_depth_and_stencil(ptex->format)) {
308 surface->flags |= RADEON_SURF_ZBUFFER;
309 surface->flags |= RADEON_SURF_SBUFFER;
310 }
311
312 return 0;
313 }
314
315 static int r600_setup_surface(struct pipe_screen *screen,
316 struct r600_resource_texture *rtex,
317 unsigned array_mode,
318 unsigned pitch_in_bytes_override)
319 {
320 struct pipe_resource *ptex = &rtex->resource.b.b.b;
321 struct r600_screen *rscreen = (struct r600_screen*)screen;
322 unsigned i;
323 int r;
324
325 if (util_format_is_depth_or_stencil(rtex->real_format)) {
326 rtex->surface.flags |= RADEON_SURF_ZBUFFER;
327 rtex->surface.flags |= RADEON_SURF_SBUFFER;
328 }
329
330 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
331 if (r) {
332 return r;
333 }
334 rtex->size = rtex->surface.bo_size;
335 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
336 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
337 * for those
338 */
339 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
340 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
341 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
342 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
343 rtex->surface.stencil_offset = rtex->surface.level[0].slice_size;
344 }
345 }
346 for (i = 0; i <= ptex->last_level; i++) {
347 rtex->offset[i] = rtex->surface.level[i].offset;
348 rtex->layer_size[i] = rtex->surface.level[i].slice_size;
349 rtex->pitch_in_bytes[i] = rtex->surface.level[i].pitch_bytes;
350 switch (rtex->surface.level[i].mode) {
351 case RADEON_SURF_MODE_LINEAR_ALIGNED:
352 rtex->array_mode[i] = V_038000_ARRAY_LINEAR_ALIGNED;
353 break;
354 case RADEON_SURF_MODE_1D:
355 rtex->array_mode[i] = V_038000_ARRAY_1D_TILED_THIN1;
356 break;
357 case RADEON_SURF_MODE_2D:
358 rtex->array_mode[i] = V_038000_ARRAY_2D_TILED_THIN1;
359 break;
360 default:
361 case RADEON_SURF_MODE_LINEAR:
362 rtex->array_mode[i] = 0;
363 break;
364 }
365 }
366 return 0;
367 }
368
369 static void r600_setup_miptree(struct pipe_screen *screen,
370 struct r600_resource_texture *rtex,
371 unsigned array_mode)
372 {
373 struct pipe_resource *ptex = &rtex->resource.b.b.b;
374 enum chip_class chipc = ((struct r600_screen*)screen)->chip_class;
375 unsigned size, layer_size, i, offset;
376 unsigned nblocksx, nblocksy;
377
378 for (i = 0, offset = 0; i <= ptex->last_level; i++) {
379 unsigned blocksize = util_format_get_blocksize(rtex->real_format);
380 unsigned base_align = r600_get_base_alignment(screen, rtex->real_format, array_mode);
381
382 r600_texture_set_array_mode(screen, rtex, i, array_mode);
383
384 nblocksx = r600_texture_get_nblocksx(screen, rtex, i);
385 nblocksy = r600_texture_get_nblocksy(screen, rtex, i);
386
387 if (chipc >= EVERGREEN && array_mode == V_038000_ARRAY_LINEAR_GENERAL)
388 layer_size = align(nblocksx, 64) * nblocksy * blocksize;
389 else
390 layer_size = nblocksx * nblocksy * blocksize;
391
392 if (ptex->target == PIPE_TEXTURE_CUBE) {
393 if (chipc >= R700)
394 size = layer_size * 8;
395 else
396 size = layer_size * 6;
397 }
398 else if (ptex->target == PIPE_TEXTURE_3D)
399 size = layer_size * u_minify(ptex->depth0, i);
400 else
401 size = layer_size * ptex->array_size;
402
403 /* align base image and start of miptree */
404 if ((i == 0) || (i == 1))
405 offset = align(offset, base_align);
406 rtex->offset[i] = offset;
407 rtex->layer_size[i] = layer_size;
408 rtex->pitch_in_blocks[i] = nblocksx; /* CB talks in elements */
409 rtex->pitch_in_bytes[i] = nblocksx * blocksize;
410
411 offset += size;
412 }
413 rtex->size = offset;
414 }
415
416 /* Figure out whether u_blitter will fallback to a transfer operation.
417 * If so, don't use a staging resource.
418 */
419 static boolean permit_hardware_blit(struct pipe_screen *screen,
420 const struct pipe_resource *res)
421 {
422 unsigned bind;
423
424 if (util_format_is_depth_or_stencil(res->format))
425 bind = PIPE_BIND_DEPTH_STENCIL;
426 else
427 bind = PIPE_BIND_RENDER_TARGET;
428
429 /* hackaround for S3TC */
430 if (util_format_is_compressed(res->format))
431 return TRUE;
432
433 if (!screen->is_format_supported(screen,
434 res->format,
435 res->target,
436 res->nr_samples,
437 bind))
438 return FALSE;
439
440 if (!screen->is_format_supported(screen,
441 res->format,
442 res->target,
443 res->nr_samples,
444 PIPE_BIND_SAMPLER_VIEW))
445 return FALSE;
446
447 return TRUE;
448 }
449
450 static boolean r600_texture_get_handle(struct pipe_screen* screen,
451 struct pipe_resource *ptex,
452 struct winsys_handle *whandle)
453 {
454 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
455 struct r600_resource *resource = &rtex->resource;
456 struct r600_screen *rscreen = (struct r600_screen*)screen;
457
458 return rscreen->ws->buffer_get_handle(resource->buf,
459 rtex->pitch_in_bytes[0], whandle);
460 }
461
462 static void r600_texture_destroy(struct pipe_screen *screen,
463 struct pipe_resource *ptex)
464 {
465 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
466 struct r600_resource *resource = &rtex->resource;
467
468 if (rtex->flushed_depth_texture)
469 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
470
471 if (rtex->stencil)
472 pipe_resource_reference((struct pipe_resource **)&rtex->stencil, NULL);
473
474 pb_reference(&resource->buf, NULL);
475 FREE(rtex);
476 }
477
478 static const struct u_resource_vtbl r600_texture_vtbl =
479 {
480 r600_texture_get_handle, /* get_handle */
481 r600_texture_destroy, /* resource_destroy */
482 r600_texture_get_transfer, /* get_transfer */
483 r600_texture_transfer_destroy, /* transfer_destroy */
484 r600_texture_transfer_map, /* transfer_map */
485 NULL, /* transfer_flush_region */
486 r600_texture_transfer_unmap, /* transfer_unmap */
487 NULL /* transfer_inline_write */
488 };
489
490 static struct r600_resource_texture *
491 r600_texture_create_object(struct pipe_screen *screen,
492 const struct pipe_resource *base,
493 unsigned array_mode,
494 unsigned pitch_in_bytes_override,
495 unsigned max_buffer_size,
496 struct pb_buffer *buf,
497 boolean alloc_bo,
498 struct radeon_surface *surface)
499 {
500 struct r600_resource_texture *rtex;
501 struct r600_resource *resource;
502 struct r600_screen *rscreen = (struct r600_screen*)screen;
503 int r;
504
505 rtex = CALLOC_STRUCT(r600_resource_texture);
506 if (rtex == NULL)
507 return NULL;
508
509 resource = &rtex->resource;
510 resource->b.b.b = *base;
511 resource->b.b.vtbl = &r600_texture_vtbl;
512 pipe_reference_init(&resource->b.b.b.reference, 1);
513 resource->b.b.b.screen = screen;
514 rtex->pitch_override = pitch_in_bytes_override;
515 rtex->real_format = base->format;
516
517 /* We must split depth and stencil into two separate buffers on Evergreen. */
518 if (!(base->flags & R600_RESOURCE_FLAG_TRANSFER) &&
519 ((struct r600_screen*)screen)->chip_class >= EVERGREEN &&
520 util_format_is_depth_and_stencil(base->format) &&
521 !rscreen->use_surface_alloc) {
522 struct pipe_resource stencil;
523 unsigned stencil_pitch_override = 0;
524
525 switch (base->format) {
526 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
527 rtex->real_format = PIPE_FORMAT_Z24X8_UNORM;
528 break;
529 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
530 rtex->real_format = PIPE_FORMAT_X8Z24_UNORM;
531 break;
532 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
533 rtex->real_format = PIPE_FORMAT_Z32_FLOAT;
534 break;
535 default:
536 assert(0);
537 FREE(rtex);
538 return NULL;
539 }
540
541 /* Divide the pitch in bytes by 4 for stencil, because it has a smaller pixel size. */
542 if (pitch_in_bytes_override) {
543 assert(base->format == PIPE_FORMAT_Z24_UNORM_S8_UINT ||
544 base->format == PIPE_FORMAT_S8_UINT_Z24_UNORM);
545 stencil_pitch_override = pitch_in_bytes_override / 4;
546 }
547
548 /* Allocate the stencil buffer. */
549 stencil = *base;
550 stencil.format = PIPE_FORMAT_S8_UINT;
551 rtex->stencil = r600_texture_create_object(screen, &stencil, array_mode,
552 stencil_pitch_override,
553 max_buffer_size, NULL, FALSE, surface);
554 if (!rtex->stencil) {
555 FREE(rtex);
556 return NULL;
557 }
558 /* Proceed in creating the depth buffer. */
559 }
560
561 /* only mark depth textures the HW can hit as depth textures */
562 if (util_format_is_depth_or_stencil(rtex->real_format) && permit_hardware_blit(screen, base))
563 rtex->is_depth = true;
564
565 r600_setup_miptree(screen, rtex, array_mode);
566 if (rscreen->use_surface_alloc) {
567 rtex->surface = *surface;
568 r = r600_setup_surface(screen, rtex, array_mode, pitch_in_bytes_override);
569 if (r) {
570 FREE(rtex);
571 return NULL;
572 }
573 }
574
575 /* If we initialized separate stencil for Evergreen. place it after depth. */
576 if (rtex->stencil) {
577 unsigned stencil_align, stencil_offset;
578
579 stencil_align = r600_get_base_alignment(screen, rtex->stencil->real_format, array_mode);
580 stencil_offset = align(rtex->size, stencil_align);
581
582 for (unsigned i = 0; i <= rtex->stencil->resource.b.b.b.last_level; i++)
583 rtex->stencil->offset[i] += stencil_offset;
584
585 rtex->size = stencil_offset + rtex->stencil->size;
586 }
587
588 /* Now create the backing buffer. */
589 if (!buf && alloc_bo) {
590 struct pipe_resource *ptex = &rtex->resource.b.b.b;
591 unsigned base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
592
593 if (rscreen->use_surface_alloc) {
594 base_align = rtex->surface.bo_alignment;
595 } else if (util_format_is_depth_or_stencil(rtex->real_format)) {
596 /* ugly work around depth buffer need stencil room at end of bo */
597 rtex->size += ptex->width0 * ptex->height0;
598 }
599 if (!r600_init_resource(rscreen, resource, rtex->size, base_align, base->bind, base->usage)) {
600 pipe_resource_reference((struct pipe_resource**)&rtex->stencil, NULL);
601 FREE(rtex);
602 return NULL;
603 }
604 } else if (buf) {
605 resource->buf = buf;
606 resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);
607 resource->domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM;
608 }
609
610 if (rtex->stencil) {
611 pb_reference(&rtex->stencil->resource.buf, rtex->resource.buf);
612 rtex->stencil->resource.cs_buf = rtex->resource.cs_buf;
613 rtex->stencil->resource.domains = rtex->resource.domains;
614 }
615 return rtex;
616 }
617
618 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
619 const struct pipe_resource *templ)
620 {
621 struct r600_screen *rscreen = (struct r600_screen*)screen;
622 struct radeon_surface surface;
623 unsigned array_mode = 0;
624 int r;
625
626 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
627 !(templ->bind & PIPE_BIND_SCANOUT)) {
628 if (rscreen->use_surface_alloc) {
629 if (permit_hardware_blit(screen, templ)) {
630 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
631 }
632 } else if (util_format_is_compressed(templ->format)) {
633 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
634 }
635 }
636
637 r = r600_init_surface(&surface, templ, array_mode);
638 if (r) {
639 return NULL;
640 }
641 r = rscreen->ws->surface_best(rscreen->ws, &surface);
642 if (r) {
643 return NULL;
644 }
645 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
646 0, 0, NULL, TRUE, &surface);
647 }
648
649 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
650 struct pipe_resource *texture,
651 const struct pipe_surface *surf_tmpl)
652 {
653 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
654 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
655 unsigned level = surf_tmpl->u.tex.level;
656
657 assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
658 if (surface == NULL)
659 return NULL;
660 pipe_reference_init(&surface->base.reference, 1);
661 pipe_resource_reference(&surface->base.texture, texture);
662 surface->base.context = pipe;
663 surface->base.format = surf_tmpl->format;
664 surface->base.width = mip_minify(texture->width0, level);
665 surface->base.height = mip_minify(texture->height0, level);
666 surface->base.usage = surf_tmpl->usage;
667 surface->base.texture = texture;
668 surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
669 surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
670 surface->base.u.tex.level = level;
671
672 surface->aligned_height = r600_texture_get_nblocksy(pipe->screen,
673 rtex, level);
674 return &surface->base;
675 }
676
677 static void r600_surface_destroy(struct pipe_context *pipe,
678 struct pipe_surface *surface)
679 {
680 pipe_resource_reference(&surface->texture, NULL);
681 FREE(surface);
682 }
683
684 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
685 const struct pipe_resource *templ,
686 struct winsys_handle *whandle)
687 {
688 struct r600_screen *rscreen = (struct r600_screen*)screen;
689 struct pb_buffer *buf = NULL;
690 unsigned stride = 0;
691 unsigned array_mode = 0;
692 enum radeon_bo_layout micro, macro;
693 struct radeon_surface surface;
694 int r;
695
696 /* Support only 2D textures without mipmaps */
697 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
698 templ->depth0 != 1 || templ->last_level != 0)
699 return NULL;
700
701 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
702 if (!buf)
703 return NULL;
704
705 rscreen->ws->buffer_get_tiling(buf, &micro, &macro,
706 &surface.bankw, &surface.bankh,
707 &surface.tile_split,
708 &surface.stencil_tile_split,
709 &surface.mtilea);
710
711 if (macro == RADEON_LAYOUT_TILED)
712 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
713 else if (micro == RADEON_LAYOUT_TILED)
714 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
715 else
716 array_mode = 0;
717
718 r = r600_init_surface(&surface, templ, array_mode);
719 if (r) {
720 return NULL;
721 }
722 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
723 stride, 0, buf, FALSE, &surface);
724 }
725
726 int r600_texture_depth_flush(struct pipe_context *ctx,
727 struct pipe_resource *texture, boolean just_create)
728 {
729 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
730 struct pipe_resource resource;
731
732 if (rtex->flushed_depth_texture)
733 goto out;
734
735 resource.target = texture->target;
736 resource.format = texture->format;
737 resource.width0 = texture->width0;
738 resource.height0 = texture->height0;
739 resource.depth0 = texture->depth0;
740 resource.array_size = texture->array_size;
741 resource.last_level = texture->last_level;
742 resource.nr_samples = texture->nr_samples;
743 resource.usage = PIPE_USAGE_DYNAMIC;
744 resource.bind = texture->bind | PIPE_BIND_DEPTH_STENCIL;
745 resource.flags = R600_RESOURCE_FLAG_TRANSFER | texture->flags;
746
747 rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
748 if (rtex->flushed_depth_texture == NULL) {
749 R600_ERR("failed to create temporary texture to hold untiled copy\n");
750 return -ENOMEM;
751 }
752
753 ((struct r600_resource_texture *)rtex->flushed_depth_texture)->is_flushing_texture = TRUE;
754 out:
755 if (just_create)
756 return 0;
757
758 /* XXX: only do this if the depth texture has actually changed:
759 */
760 r600_blit_uncompress_depth(ctx, rtex);
761 return 0;
762 }
763
764 /* Needs adjustment for pixelformat:
765 */
766 static INLINE unsigned u_box_volume( const struct pipe_box *box )
767 {
768 return box->width * box->depth * box->height;
769 };
770
771 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
772 struct pipe_resource *texture,
773 unsigned level,
774 unsigned usage,
775 const struct pipe_box *box)
776 {
777 struct r600_context *rctx = (struct r600_context*)ctx;
778 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
779 struct pipe_resource resource;
780 struct r600_transfer *trans;
781 int r;
782 boolean use_staging_texture = FALSE;
783
784 /* We cannot map a tiled texture directly because the data is
785 * in a different order, therefore we do detiling using a blit.
786 *
787 * Also, use a temporary in GTT memory for read transfers, as
788 * the CPU is much happier reading out of cached system memory
789 * than uncached VRAM.
790 */
791 if (R600_TEX_IS_TILED(rtex, level))
792 use_staging_texture = TRUE;
793
794 if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024)
795 use_staging_texture = TRUE;
796
797 /* Use a staging texture for uploads if the underlying BO is busy. */
798 if (!(usage & PIPE_TRANSFER_READ) &&
799 (rctx->ws->cs_is_buffer_referenced(rctx->cs, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) ||
800 rctx->ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE)))
801 use_staging_texture = TRUE;
802
803 if (!permit_hardware_blit(ctx->screen, texture) ||
804 (texture->flags & R600_RESOURCE_FLAG_TRANSFER))
805 use_staging_texture = FALSE;
806
807 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY))
808 return NULL;
809
810 trans = CALLOC_STRUCT(r600_transfer);
811 if (trans == NULL)
812 return NULL;
813 pipe_resource_reference(&trans->transfer.resource, texture);
814 trans->transfer.level = level;
815 trans->transfer.usage = usage;
816 trans->transfer.box = *box;
817 if (rtex->is_depth) {
818 /* XXX: only readback the rectangle which is being mapped?
819 */
820 /* XXX: when discard is true, no need to read back from depth texture
821 */
822 r = r600_texture_depth_flush(ctx, texture, FALSE);
823 if (r < 0) {
824 R600_ERR("failed to create temporary texture to hold untiled copy\n");
825 pipe_resource_reference(&trans->transfer.resource, NULL);
826 FREE(trans);
827 return NULL;
828 }
829 trans->transfer.stride = rtex->flushed_depth_texture->pitch_in_bytes[level];
830 trans->offset = r600_texture_get_offset(rtex->flushed_depth_texture, level, box->z);
831 return &trans->transfer;
832 } else if (use_staging_texture) {
833 resource.target = PIPE_TEXTURE_2D;
834 resource.format = texture->format;
835 resource.width0 = box->width;
836 resource.height0 = box->height;
837 resource.depth0 = 1;
838 resource.array_size = 1;
839 resource.last_level = 0;
840 resource.nr_samples = 0;
841 resource.usage = PIPE_USAGE_STAGING;
842 resource.bind = 0;
843 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
844 /* For texture reading, the temporary (detiled) texture is used as
845 * a render target when blitting from a tiled texture. */
846 if (usage & PIPE_TRANSFER_READ) {
847 resource.bind |= PIPE_BIND_RENDER_TARGET;
848 }
849 /* For texture writing, the temporary texture is used as a sampler
850 * when blitting into a tiled texture. */
851 if (usage & PIPE_TRANSFER_WRITE) {
852 resource.bind |= PIPE_BIND_SAMPLER_VIEW;
853 }
854 /* Create the temporary texture. */
855 trans->staging = (struct r600_resource*)ctx->screen->resource_create(ctx->screen, &resource);
856 if (trans->staging == NULL) {
857 R600_ERR("failed to create temporary texture to hold untiled copy\n");
858 pipe_resource_reference(&trans->transfer.resource, NULL);
859 FREE(trans);
860 return NULL;
861 }
862
863 trans->transfer.stride =
864 ((struct r600_resource_texture *)trans->staging)->pitch_in_bytes[0];
865 if (usage & PIPE_TRANSFER_READ) {
866 r600_copy_to_staging_texture(ctx, trans);
867 /* Always referenced in the blit. */
868 r600_flush(ctx, NULL, 0);
869 }
870 return &trans->transfer;
871 }
872 trans->transfer.stride = rtex->pitch_in_bytes[level];
873 trans->transfer.layer_stride = rtex->layer_size[level];
874 trans->offset = r600_texture_get_offset(rtex, level, box->z);
875 return &trans->transfer;
876 }
877
878 void r600_texture_transfer_destroy(struct pipe_context *ctx,
879 struct pipe_transfer *transfer)
880 {
881 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
882 struct pipe_resource *texture = transfer->resource;
883 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
884
885 if (rtransfer->staging) {
886 if (transfer->usage & PIPE_TRANSFER_WRITE) {
887 r600_copy_from_staging_texture(ctx, rtransfer);
888 }
889 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
890 }
891
892 if (rtex->is_depth && !rtex->is_flushing_texture) {
893 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtex->flushed_depth_texture)
894 r600_blit_push_depth(ctx, rtex);
895 }
896
897 pipe_resource_reference(&transfer->resource, NULL);
898 FREE(transfer);
899 }
900
901 void* r600_texture_transfer_map(struct pipe_context *ctx,
902 struct pipe_transfer* transfer)
903 {
904 struct r600_context *rctx = (struct r600_context *)ctx;
905 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
906 struct pb_buffer *buf;
907 enum pipe_format format = transfer->resource->format;
908 unsigned offset = 0;
909 char *map;
910
911 if (rtransfer->staging) {
912 buf = ((struct r600_resource *)rtransfer->staging)->buf;
913 } else {
914 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
915
916 if (rtex->flushed_depth_texture)
917 buf = ((struct r600_resource *)rtex->flushed_depth_texture)->buf;
918 else
919 buf = ((struct r600_resource *)transfer->resource)->buf;
920
921 offset = rtransfer->offset +
922 transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
923 transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
924 }
925
926 if (!(map = rctx->ws->buffer_map(buf, rctx->cs, transfer->usage))) {
927 return NULL;
928 }
929
930 return map + offset;
931 }
932
933 void r600_texture_transfer_unmap(struct pipe_context *ctx,
934 struct pipe_transfer* transfer)
935 {
936 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
937 struct r600_context *rctx = (struct r600_context*)ctx;
938 struct pb_buffer *buf;
939
940 if (rtransfer->staging) {
941 buf = ((struct r600_resource *)rtransfer->staging)->buf;
942 } else {
943 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
944
945 if (rtex->flushed_depth_texture) {
946 buf = ((struct r600_resource *)rtex->flushed_depth_texture)->buf;
947 } else {
948 buf = ((struct r600_resource *)transfer->resource)->buf;
949 }
950 }
951 rctx->ws->buffer_unmap(buf);
952 }
953
954 void r600_init_surface_functions(struct r600_context *r600)
955 {
956 r600->context.create_surface = r600_create_surface;
957 r600->context.surface_destroy = r600_surface_destroy;
958 }
959
960 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
961 const unsigned char *swizzle_view)
962 {
963 unsigned i;
964 unsigned char swizzle[4];
965 unsigned result = 0;
966 const uint32_t swizzle_shift[4] = {
967 16, 19, 22, 25,
968 };
969 const uint32_t swizzle_bit[4] = {
970 0, 1, 2, 3,
971 };
972
973 if (swizzle_view) {
974 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
975 } else {
976 memcpy(swizzle, swizzle_format, 4);
977 }
978
979 /* Get swizzle. */
980 for (i = 0; i < 4; i++) {
981 switch (swizzle[i]) {
982 case UTIL_FORMAT_SWIZZLE_Y:
983 result |= swizzle_bit[1] << swizzle_shift[i];
984 break;
985 case UTIL_FORMAT_SWIZZLE_Z:
986 result |= swizzle_bit[2] << swizzle_shift[i];
987 break;
988 case UTIL_FORMAT_SWIZZLE_W:
989 result |= swizzle_bit[3] << swizzle_shift[i];
990 break;
991 case UTIL_FORMAT_SWIZZLE_0:
992 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
993 break;
994 case UTIL_FORMAT_SWIZZLE_1:
995 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
996 break;
997 default: /* UTIL_FORMAT_SWIZZLE_X */
998 result |= swizzle_bit[0] << swizzle_shift[i];
999 }
1000 }
1001 return result;
1002 }
1003
1004 /* texture format translate */
1005 uint32_t r600_translate_texformat(struct pipe_screen *screen,
1006 enum pipe_format format,
1007 const unsigned char *swizzle_view,
1008 uint32_t *word4_p, uint32_t *yuv_format_p)
1009 {
1010 uint32_t result = 0, word4 = 0, yuv_format = 0;
1011 const struct util_format_description *desc;
1012 boolean uniform = TRUE;
1013 static int r600_enable_s3tc = -1;
1014 bool is_srgb_valid = FALSE;
1015
1016 int i;
1017 const uint32_t sign_bit[4] = {
1018 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
1019 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
1020 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
1021 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
1022 };
1023 desc = util_format_description(format);
1024
1025 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
1026
1027 /* Colorspace (return non-RGB formats directly). */
1028 switch (desc->colorspace) {
1029 /* Depth stencil formats */
1030 case UTIL_FORMAT_COLORSPACE_ZS:
1031 switch (format) {
1032 case PIPE_FORMAT_Z16_UNORM:
1033 result = FMT_16;
1034 goto out_word4;
1035 case PIPE_FORMAT_X24S8_UINT:
1036 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1037 case PIPE_FORMAT_Z24X8_UNORM:
1038 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1039 result = FMT_8_24;
1040 goto out_word4;
1041 case PIPE_FORMAT_S8X24_UINT:
1042 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1043 case PIPE_FORMAT_X8Z24_UNORM:
1044 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1045 result = FMT_24_8;
1046 goto out_word4;
1047 case PIPE_FORMAT_S8_UINT:
1048 result = FMT_8;
1049 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1050 goto out_word4;
1051 case PIPE_FORMAT_Z32_FLOAT:
1052 result = FMT_32_FLOAT;
1053 goto out_word4;
1054 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1055 result = FMT_X24_8_32_FLOAT;
1056 goto out_word4;
1057 default:
1058 goto out_unknown;
1059 }
1060
1061 case UTIL_FORMAT_COLORSPACE_YUV:
1062 yuv_format |= (1 << 30);
1063 switch (format) {
1064 case PIPE_FORMAT_UYVY:
1065 case PIPE_FORMAT_YUYV:
1066 default:
1067 break;
1068 }
1069 goto out_unknown; /* XXX */
1070
1071 case UTIL_FORMAT_COLORSPACE_SRGB:
1072 word4 |= S_038010_FORCE_DEGAMMA(1);
1073 break;
1074
1075 default:
1076 break;
1077 }
1078
1079 if (r600_enable_s3tc == -1) {
1080 struct r600_screen *rscreen = (struct r600_screen *)screen;
1081 if (rscreen->info.drm_minor >= 9)
1082 r600_enable_s3tc = 1;
1083 else
1084 r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
1085 }
1086
1087 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1088 if (!r600_enable_s3tc)
1089 goto out_unknown;
1090
1091 switch (format) {
1092 case PIPE_FORMAT_RGTC1_SNORM:
1093 case PIPE_FORMAT_LATC1_SNORM:
1094 word4 |= sign_bit[0];
1095 case PIPE_FORMAT_RGTC1_UNORM:
1096 case PIPE_FORMAT_LATC1_UNORM:
1097 result = FMT_BC4;
1098 goto out_word4;
1099 case PIPE_FORMAT_RGTC2_SNORM:
1100 case PIPE_FORMAT_LATC2_SNORM:
1101 word4 |= sign_bit[0] | sign_bit[1];
1102 case PIPE_FORMAT_RGTC2_UNORM:
1103 case PIPE_FORMAT_LATC2_UNORM:
1104 result = FMT_BC5;
1105 goto out_word4;
1106 default:
1107 goto out_unknown;
1108 }
1109 }
1110
1111 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1112
1113 if (!r600_enable_s3tc)
1114 goto out_unknown;
1115
1116 if (!util_format_s3tc_enabled) {
1117 goto out_unknown;
1118 }
1119
1120 switch (format) {
1121 case PIPE_FORMAT_DXT1_RGB:
1122 case PIPE_FORMAT_DXT1_RGBA:
1123 case PIPE_FORMAT_DXT1_SRGB:
1124 case PIPE_FORMAT_DXT1_SRGBA:
1125 result = FMT_BC1;
1126 is_srgb_valid = TRUE;
1127 goto out_word4;
1128 case PIPE_FORMAT_DXT3_RGBA:
1129 case PIPE_FORMAT_DXT3_SRGBA:
1130 result = FMT_BC2;
1131 is_srgb_valid = TRUE;
1132 goto out_word4;
1133 case PIPE_FORMAT_DXT5_RGBA:
1134 case PIPE_FORMAT_DXT5_SRGBA:
1135 result = FMT_BC3;
1136 is_srgb_valid = TRUE;
1137 goto out_word4;
1138 default:
1139 goto out_unknown;
1140 }
1141 }
1142
1143 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1144 result = FMT_5_9_9_9_SHAREDEXP;
1145 goto out_word4;
1146 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1147 result = FMT_10_11_11_FLOAT;
1148 goto out_word4;
1149 }
1150
1151
1152 for (i = 0; i < desc->nr_channels; i++) {
1153 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1154 word4 |= sign_bit[i];
1155 }
1156 }
1157
1158 /* R8G8Bx_SNORM - XXX CxV8U8 */
1159
1160 /* See whether the components are of the same size. */
1161 for (i = 1; i < desc->nr_channels; i++) {
1162 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1163 }
1164
1165 /* Non-uniform formats. */
1166 if (!uniform) {
1167 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1168 desc->channel[0].pure_integer)
1169 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1170 switch(desc->nr_channels) {
1171 case 3:
1172 if (desc->channel[0].size == 5 &&
1173 desc->channel[1].size == 6 &&
1174 desc->channel[2].size == 5) {
1175 result = FMT_5_6_5;
1176 goto out_word4;
1177 }
1178 goto out_unknown;
1179 case 4:
1180 if (desc->channel[0].size == 5 &&
1181 desc->channel[1].size == 5 &&
1182 desc->channel[2].size == 5 &&
1183 desc->channel[3].size == 1) {
1184 result = FMT_1_5_5_5;
1185 goto out_word4;
1186 }
1187 if (desc->channel[0].size == 10 &&
1188 desc->channel[1].size == 10 &&
1189 desc->channel[2].size == 10 &&
1190 desc->channel[3].size == 2) {
1191 result = FMT_2_10_10_10;
1192 goto out_word4;
1193 }
1194 goto out_unknown;
1195 }
1196 goto out_unknown;
1197 }
1198
1199 /* Find the first non-VOID channel. */
1200 for (i = 0; i < 4; i++) {
1201 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1202 break;
1203 }
1204 }
1205
1206 if (i == 4)
1207 goto out_unknown;
1208
1209 /* uniform formats */
1210 switch (desc->channel[i].type) {
1211 case UTIL_FORMAT_TYPE_UNSIGNED:
1212 case UTIL_FORMAT_TYPE_SIGNED:
1213 #if 0
1214 if (!desc->channel[i].normalized &&
1215 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
1216 goto out_unknown;
1217 }
1218 #endif
1219 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1220 desc->channel[i].pure_integer)
1221 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1222
1223 switch (desc->channel[i].size) {
1224 case 4:
1225 switch (desc->nr_channels) {
1226 case 2:
1227 result = FMT_4_4;
1228 goto out_word4;
1229 case 4:
1230 result = FMT_4_4_4_4;
1231 goto out_word4;
1232 }
1233 goto out_unknown;
1234 case 8:
1235 switch (desc->nr_channels) {
1236 case 1:
1237 result = FMT_8;
1238 goto out_word4;
1239 case 2:
1240 result = FMT_8_8;
1241 goto out_word4;
1242 case 4:
1243 result = FMT_8_8_8_8;
1244 is_srgb_valid = TRUE;
1245 goto out_word4;
1246 }
1247 goto out_unknown;
1248 case 16:
1249 switch (desc->nr_channels) {
1250 case 1:
1251 result = FMT_16;
1252 goto out_word4;
1253 case 2:
1254 result = FMT_16_16;
1255 goto out_word4;
1256 case 4:
1257 result = FMT_16_16_16_16;
1258 goto out_word4;
1259 }
1260 goto out_unknown;
1261 case 32:
1262 switch (desc->nr_channels) {
1263 case 1:
1264 result = FMT_32;
1265 goto out_word4;
1266 case 2:
1267 result = FMT_32_32;
1268 goto out_word4;
1269 case 4:
1270 result = FMT_32_32_32_32;
1271 goto out_word4;
1272 }
1273 }
1274 goto out_unknown;
1275
1276 case UTIL_FORMAT_TYPE_FLOAT:
1277 switch (desc->channel[i].size) {
1278 case 16:
1279 switch (desc->nr_channels) {
1280 case 1:
1281 result = FMT_16_FLOAT;
1282 goto out_word4;
1283 case 2:
1284 result = FMT_16_16_FLOAT;
1285 goto out_word4;
1286 case 4:
1287 result = FMT_16_16_16_16_FLOAT;
1288 goto out_word4;
1289 }
1290 goto out_unknown;
1291 case 32:
1292 switch (desc->nr_channels) {
1293 case 1:
1294 result = FMT_32_FLOAT;
1295 goto out_word4;
1296 case 2:
1297 result = FMT_32_32_FLOAT;
1298 goto out_word4;
1299 case 4:
1300 result = FMT_32_32_32_32_FLOAT;
1301 goto out_word4;
1302 }
1303 }
1304 goto out_unknown;
1305 }
1306
1307 out_word4:
1308
1309 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid)
1310 return ~0;
1311 if (word4_p)
1312 *word4_p = word4;
1313 if (yuv_format_p)
1314 *yuv_format_p = yuv_format;
1315 return result;
1316 out_unknown:
1317 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1318 return ~0;
1319 }