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radeon/llvm: Use correct opcocde for BREAK_LOGICALNZ_i32
[mesa.git] / src / gallium / drivers / r600 / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_formats.h"
28 #include "r600d.h"
29
30 #include <errno.h>
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33
34 /* Copy from a full GPU texture to a transfer's staging one. */
35 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
36 {
37 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
38 struct pipe_resource *texture = transfer->resource;
39
40 ctx->resource_copy_region(ctx, &rtransfer->staging->b.b,
41 0, 0, 0, 0, texture, transfer->level,
42 &transfer->box);
43 }
44
45
46 /* Copy from a transfer's staging texture to a full GPU one. */
47 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
48 {
49 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
50 struct pipe_resource *texture = transfer->resource;
51 struct pipe_box sbox;
52
53 u_box_origin_2d(transfer->box.width, transfer->box.height, &sbox);
54
55 ctx->resource_copy_region(ctx, texture, transfer->level,
56 transfer->box.x, transfer->box.y, transfer->box.z,
57 &rtransfer->staging->b.b,
58 0, &sbox);
59 }
60
61 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
62 unsigned level, unsigned layer)
63 {
64 return rtex->offset[level] + layer * rtex->layer_size[level];
65 }
66
67 static int r600_init_surface(struct r600_screen *rscreen,
68 struct radeon_surface *surface,
69 const struct pipe_resource *ptex,
70 unsigned array_mode,
71 bool is_transfer, bool is_flushed_depth)
72 {
73 const struct util_format_description *desc =
74 util_format_description(ptex->format);
75 bool is_depth, is_stencil;
76
77 is_depth = util_format_has_depth(desc);
78 is_stencil = util_format_has_stencil(desc);
79
80 surface->npix_x = ptex->width0;
81 surface->npix_y = ptex->height0;
82 surface->npix_z = ptex->depth0;
83 surface->blk_w = util_format_get_blockwidth(ptex->format);
84 surface->blk_h = util_format_get_blockheight(ptex->format);
85 surface->blk_d = 1;
86 surface->array_size = 1;
87 surface->last_level = ptex->last_level;
88
89 if (rscreen->chip_class >= EVERGREEN &&
90 !is_transfer && !is_flushed_depth &&
91 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
92 surface->bpe = 4; /* stencil is allocated separately on evergreen */
93 } else {
94 surface->bpe = util_format_get_blocksize(ptex->format);
95 /* align byte per element on dword */
96 if (surface->bpe == 3) {
97 surface->bpe = 4;
98 }
99 }
100
101 surface->nsamples = 1;
102 surface->flags = 0;
103 switch (array_mode) {
104 case V_038000_ARRAY_1D_TILED_THIN1:
105 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
106 break;
107 case V_038000_ARRAY_2D_TILED_THIN1:
108 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
109 break;
110 case V_038000_ARRAY_LINEAR_ALIGNED:
111 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
112 break;
113 case V_038000_ARRAY_LINEAR_GENERAL:
114 default:
115 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE);
116 break;
117 }
118 switch (ptex->target) {
119 case PIPE_TEXTURE_1D:
120 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
121 break;
122 case PIPE_TEXTURE_RECT:
123 case PIPE_TEXTURE_2D:
124 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
125 break;
126 case PIPE_TEXTURE_3D:
127 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
128 break;
129 case PIPE_TEXTURE_1D_ARRAY:
130 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
131 surface->array_size = ptex->array_size;
132 break;
133 case PIPE_TEXTURE_2D_ARRAY:
134 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
135 surface->array_size = ptex->array_size;
136 break;
137 case PIPE_TEXTURE_CUBE:
138 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
139 break;
140 case PIPE_BUFFER:
141 default:
142 return -EINVAL;
143 }
144 if (ptex->bind & PIPE_BIND_SCANOUT) {
145 surface->flags |= RADEON_SURF_SCANOUT;
146 }
147
148 if (!is_transfer && !is_flushed_depth && is_depth) {
149 surface->flags |= RADEON_SURF_ZBUFFER;
150
151 if (is_stencil) {
152 surface->flags |= RADEON_SURF_SBUFFER;
153 }
154 }
155 return 0;
156 }
157
158 static int r600_setup_surface(struct pipe_screen *screen,
159 struct r600_resource_texture *rtex,
160 unsigned pitch_in_bytes_override)
161 {
162 struct pipe_resource *ptex = &rtex->resource.b.b;
163 struct r600_screen *rscreen = (struct r600_screen*)screen;
164 unsigned i;
165 int r;
166
167 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
168 if (r) {
169 return r;
170 }
171 rtex->size = rtex->surface.bo_size;
172 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
173 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
174 * for those
175 */
176 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
177 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
178 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
179 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
180 rtex->surface.stencil_offset = rtex->surface.level[0].slice_size;
181 }
182 }
183 for (i = 0; i <= ptex->last_level; i++) {
184 rtex->offset[i] = rtex->surface.level[i].offset;
185 rtex->layer_size[i] = rtex->surface.level[i].slice_size;
186 rtex->pitch_in_bytes[i] = rtex->surface.level[i].pitch_bytes;
187 switch (rtex->surface.level[i].mode) {
188 case RADEON_SURF_MODE_LINEAR_ALIGNED:
189 rtex->array_mode[i] = V_038000_ARRAY_LINEAR_ALIGNED;
190 break;
191 case RADEON_SURF_MODE_1D:
192 rtex->array_mode[i] = V_038000_ARRAY_1D_TILED_THIN1;
193 break;
194 case RADEON_SURF_MODE_2D:
195 rtex->array_mode[i] = V_038000_ARRAY_2D_TILED_THIN1;
196 break;
197 default:
198 case RADEON_SURF_MODE_LINEAR:
199 rtex->array_mode[i] = 0;
200 break;
201 }
202 }
203 return 0;
204 }
205
206 static boolean r600_texture_get_handle(struct pipe_screen* screen,
207 struct pipe_resource *ptex,
208 struct winsys_handle *whandle)
209 {
210 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
211 struct r600_resource *resource = &rtex->resource;
212 struct radeon_surface *surface = &rtex->surface;
213 struct r600_screen *rscreen = (struct r600_screen*)screen;
214
215 rscreen->ws->buffer_set_tiling(resource->buf,
216 NULL,
217 surface->level[0].mode >= RADEON_SURF_MODE_1D ?
218 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
219 surface->level[0].mode >= RADEON_SURF_MODE_2D ?
220 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
221 surface->bankw, surface->bankh,
222 surface->tile_split,
223 surface->stencil_tile_split,
224 surface->mtilea,
225 rtex->pitch_in_bytes[0]);
226
227 return rscreen->ws->buffer_get_handle(resource->buf,
228 rtex->pitch_in_bytes[0], whandle);
229 }
230
231 static void r600_texture_destroy(struct pipe_screen *screen,
232 struct pipe_resource *ptex)
233 {
234 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
235 struct r600_resource *resource = &rtex->resource;
236
237 if (rtex->flushed_depth_texture)
238 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
239
240 pb_reference(&resource->buf, NULL);
241 FREE(rtex);
242 }
243
244 static const struct u_resource_vtbl r600_texture_vtbl =
245 {
246 r600_texture_get_handle, /* get_handle */
247 r600_texture_destroy, /* resource_destroy */
248 r600_texture_get_transfer, /* get_transfer */
249 r600_texture_transfer_destroy, /* transfer_destroy */
250 r600_texture_transfer_map, /* transfer_map */
251 NULL, /* transfer_flush_region */
252 r600_texture_transfer_unmap, /* transfer_unmap */
253 NULL /* transfer_inline_write */
254 };
255
256 static struct r600_resource_texture *
257 r600_texture_create_object(struct pipe_screen *screen,
258 const struct pipe_resource *base,
259 unsigned array_mode,
260 unsigned pitch_in_bytes_override,
261 struct pb_buffer *buf,
262 boolean alloc_bo,
263 struct radeon_surface *surface)
264 {
265 struct r600_resource_texture *rtex;
266 struct r600_resource *resource;
267 struct r600_screen *rscreen = (struct r600_screen*)screen;
268 int r;
269
270 rtex = CALLOC_STRUCT(r600_resource_texture);
271 if (rtex == NULL)
272 return NULL;
273
274 resource = &rtex->resource;
275 resource->b.b = *base;
276 resource->b.vtbl = &r600_texture_vtbl;
277 pipe_reference_init(&resource->b.b.reference, 1);
278 resource->b.b.screen = screen;
279 rtex->pitch_override = pitch_in_bytes_override;
280 rtex->real_format = base->format;
281
282 /* don't include stencil-only formats which we don't support for rendering */
283 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
284
285 rtex->surface = *surface;
286 r = r600_setup_surface(screen, rtex,
287 pitch_in_bytes_override);
288 if (r) {
289 FREE(rtex);
290 return NULL;
291 }
292
293 /* Now create the backing buffer. */
294 if (!buf && alloc_bo) {
295 unsigned base_align = rtex->surface.bo_alignment;
296
297 if (!r600_init_resource(rscreen, resource, rtex->size, base_align, base->bind, base->usage)) {
298 FREE(rtex);
299 return NULL;
300 }
301 } else if (buf) {
302 resource->buf = buf;
303 resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);
304 resource->domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM;
305 }
306 return rtex;
307 }
308
309 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
310 const struct pipe_resource *templ)
311 {
312 struct r600_screen *rscreen = (struct r600_screen*)screen;
313 struct radeon_surface surface;
314 unsigned array_mode = 0;
315 int r;
316
317 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER)) {
318 if (!(templ->bind & PIPE_BIND_SCANOUT) &&
319 templ->usage != PIPE_USAGE_STAGING &&
320 templ->usage != PIPE_USAGE_STREAM) {
321 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
322 } else if (util_format_is_compressed(templ->format)) {
323 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
324 }
325 }
326
327 r = r600_init_surface(rscreen, &surface, templ, array_mode,
328 templ->flags & R600_RESOURCE_FLAG_TRANSFER,
329 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
330 if (r) {
331 return NULL;
332 }
333 r = rscreen->ws->surface_best(rscreen->ws, &surface);
334 if (r) {
335 return NULL;
336 }
337 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
338 0, NULL, TRUE, &surface);
339 }
340
341 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
342 struct pipe_resource *texture,
343 const struct pipe_surface *templ)
344 {
345 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
346 unsigned level = templ->u.tex.level;
347
348 assert(templ->u.tex.first_layer == templ->u.tex.last_layer);
349 if (surface == NULL)
350 return NULL;
351 pipe_reference_init(&surface->base.reference, 1);
352 pipe_resource_reference(&surface->base.texture, texture);
353 surface->base.context = pipe;
354 surface->base.format = templ->format;
355 surface->base.width = u_minify(texture->width0, level);
356 surface->base.height = u_minify(texture->height0, level);
357 surface->base.usage = templ->usage;
358 surface->base.u = templ->u;
359 return &surface->base;
360 }
361
362 static void r600_surface_destroy(struct pipe_context *pipe,
363 struct pipe_surface *surface)
364 {
365 pipe_resource_reference(&surface->texture, NULL);
366 FREE(surface);
367 }
368
369 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
370 const struct pipe_resource *templ,
371 struct winsys_handle *whandle)
372 {
373 struct r600_screen *rscreen = (struct r600_screen*)screen;
374 struct pb_buffer *buf = NULL;
375 unsigned stride = 0;
376 unsigned array_mode = 0;
377 enum radeon_bo_layout micro, macro;
378 struct radeon_surface surface;
379 int r;
380
381 /* Support only 2D textures without mipmaps */
382 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
383 templ->depth0 != 1 || templ->last_level != 0)
384 return NULL;
385
386 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
387 if (!buf)
388 return NULL;
389
390 rscreen->ws->buffer_get_tiling(buf, &micro, &macro,
391 &surface.bankw, &surface.bankh,
392 &surface.tile_split,
393 &surface.stencil_tile_split,
394 &surface.mtilea);
395
396 if (macro == RADEON_LAYOUT_TILED)
397 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
398 else if (micro == RADEON_LAYOUT_TILED)
399 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
400 else
401 array_mode = 0;
402
403 r = r600_init_surface(rscreen, &surface, templ, array_mode, false, false);
404 if (r) {
405 return NULL;
406 }
407 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
408 stride, buf, FALSE, &surface);
409 }
410
411 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
412 struct pipe_resource *texture,
413 struct r600_resource_texture **staging)
414 {
415 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
416 struct pipe_resource resource;
417 struct r600_resource_texture **flushed_depth_texture = staging ?
418 staging : &rtex->flushed_depth_texture;
419
420 if (!staging && rtex->flushed_depth_texture)
421 return true; /* it's ready */
422
423 resource.target = texture->target;
424 resource.format = texture->format;
425 resource.width0 = texture->width0;
426 resource.height0 = texture->height0;
427 resource.depth0 = texture->depth0;
428 resource.array_size = texture->array_size;
429 resource.last_level = texture->last_level;
430 resource.nr_samples = texture->nr_samples;
431 resource.usage = staging ? PIPE_USAGE_DYNAMIC : PIPE_USAGE_DEFAULT;
432 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
433 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
434
435 if (staging)
436 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
437
438 *flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
439 if (*flushed_depth_texture == NULL) {
440 R600_ERR("failed to create temporary texture to hold flushed depth\n");
441 return false;
442 }
443
444 (*flushed_depth_texture)->is_flushing_texture = TRUE;
445 return true;
446 }
447
448 /* Needs adjustment for pixelformat:
449 */
450 static INLINE unsigned u_box_volume( const struct pipe_box *box )
451 {
452 return box->width * box->depth * box->height;
453 }
454
455 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
456 struct pipe_resource *texture,
457 unsigned level,
458 unsigned usage,
459 const struct pipe_box *box)
460 {
461 struct r600_context *rctx = (struct r600_context*)ctx;
462 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
463 struct pipe_resource resource;
464 struct r600_transfer *trans;
465 boolean use_staging_texture = FALSE;
466
467 /* We cannot map a tiled texture directly because the data is
468 * in a different order, therefore we do detiling using a blit.
469 *
470 * Also, use a temporary in GTT memory for read transfers, as
471 * the CPU is much happier reading out of cached system memory
472 * than uncached VRAM.
473 */
474 if (R600_TEX_IS_TILED(rtex, level)) {
475 use_staging_texture = TRUE;
476 }
477
478 if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024)
479 use_staging_texture = TRUE;
480
481 /* Use a staging texture for uploads if the underlying BO is busy. */
482 if (!(usage & PIPE_TRANSFER_READ) &&
483 (rctx->ws->cs_is_buffer_referenced(rctx->cs, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) ||
484 rctx->ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE))) {
485 use_staging_texture = TRUE;
486 }
487
488 if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) {
489 use_staging_texture = FALSE;
490 }
491
492 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) {
493 return NULL;
494 }
495
496 trans = CALLOC_STRUCT(r600_transfer);
497 if (trans == NULL)
498 return NULL;
499 pipe_resource_reference(&trans->transfer.resource, texture);
500 trans->transfer.level = level;
501 trans->transfer.usage = usage;
502 trans->transfer.box = *box;
503 if (rtex->is_depth) {
504 /* XXX: only readback the rectangle which is being mapped?
505 */
506 /* XXX: when discard is true, no need to read back from depth texture
507 */
508 struct r600_resource_texture *staging_depth;
509
510 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
511 R600_ERR("failed to create temporary texture to hold untiled copy\n");
512 pipe_resource_reference(&trans->transfer.resource, NULL);
513 FREE(trans);
514 return NULL;
515 }
516
517 r600_blit_uncompress_depth(ctx, rtex, staging_depth,
518 level, level,
519 box->z, box->z + box->depth - 1);
520
521 trans->transfer.stride = staging_depth->pitch_in_bytes[level];
522 trans->offset = r600_texture_get_offset(staging_depth, level, box->z);
523 trans->staging = (struct r600_resource*)staging_depth;
524 return &trans->transfer;
525 } else if (use_staging_texture) {
526 resource.target = PIPE_TEXTURE_2D;
527 resource.format = texture->format;
528 resource.width0 = box->width;
529 resource.height0 = box->height;
530 resource.depth0 = 1;
531 resource.array_size = 1;
532 resource.last_level = 0;
533 resource.nr_samples = 0;
534 resource.usage = PIPE_USAGE_STAGING;
535 resource.bind = 0;
536 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
537 /* For texture reading, the temporary (detiled) texture is used as
538 * a render target when blitting from a tiled texture. */
539 if (usage & PIPE_TRANSFER_READ) {
540 resource.bind |= PIPE_BIND_RENDER_TARGET;
541 }
542 /* For texture writing, the temporary texture is used as a sampler
543 * when blitting into a tiled texture. */
544 if (usage & PIPE_TRANSFER_WRITE) {
545 resource.bind |= PIPE_BIND_SAMPLER_VIEW;
546 }
547 /* Create the temporary texture. */
548 trans->staging = (struct r600_resource*)ctx->screen->resource_create(ctx->screen, &resource);
549 if (trans->staging == NULL) {
550 R600_ERR("failed to create temporary texture to hold untiled copy\n");
551 pipe_resource_reference(&trans->transfer.resource, NULL);
552 FREE(trans);
553 return NULL;
554 }
555
556 trans->transfer.stride =
557 ((struct r600_resource_texture *)trans->staging)->pitch_in_bytes[0];
558 if (usage & PIPE_TRANSFER_READ) {
559 r600_copy_to_staging_texture(ctx, trans);
560 /* Always referenced in the blit. */
561 r600_flush(ctx, NULL, 0);
562 }
563 return &trans->transfer;
564 }
565 trans->transfer.stride = rtex->pitch_in_bytes[level];
566 trans->transfer.layer_stride = rtex->layer_size[level];
567 trans->offset = r600_texture_get_offset(rtex, level, box->z);
568 return &trans->transfer;
569 }
570
571 void r600_texture_transfer_destroy(struct pipe_context *ctx,
572 struct pipe_transfer *transfer)
573 {
574 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
575 struct pipe_resource *texture = transfer->resource;
576 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
577
578 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
579 if (rtex->is_depth) {
580 ctx->resource_copy_region(ctx, texture, transfer->level,
581 transfer->box.x, transfer->box.y, transfer->box.z,
582 &rtransfer->staging->b.b, transfer->level,
583 &transfer->box);
584 } else {
585 r600_copy_from_staging_texture(ctx, rtransfer);
586 }
587 }
588
589 if (rtransfer->staging)
590 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
591
592 pipe_resource_reference(&transfer->resource, NULL);
593 FREE(transfer);
594 }
595
596 void* r600_texture_transfer_map(struct pipe_context *ctx,
597 struct pipe_transfer* transfer)
598 {
599 struct r600_context *rctx = (struct r600_context *)ctx;
600 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
601 struct radeon_winsys_cs_handle *buf;
602 struct r600_resource_texture *rtex =
603 (struct r600_resource_texture*)transfer->resource;
604 enum pipe_format format = transfer->resource->format;
605 unsigned offset = 0;
606 char *map;
607
608 if ((transfer->resource->bind & PIPE_BIND_GLOBAL) && transfer->resource->target == PIPE_BUFFER) {
609 return r600_compute_global_transfer_map(ctx, transfer);
610 }
611
612 if (rtransfer->staging) {
613 buf = ((struct r600_resource *)rtransfer->staging)->cs_buf;
614 } else {
615 buf = ((struct r600_resource *)transfer->resource)->cs_buf;
616 }
617
618 if (rtex->is_depth || !rtransfer->staging)
619 offset = rtransfer->offset +
620 transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
621 transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
622
623 if (!(map = rctx->ws->buffer_map(buf, rctx->cs, transfer->usage))) {
624 return NULL;
625 }
626
627 return map + offset;
628 }
629
630 void r600_texture_transfer_unmap(struct pipe_context *ctx,
631 struct pipe_transfer* transfer)
632 {
633 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
634 struct r600_context *rctx = (struct r600_context*)ctx;
635 struct radeon_winsys_cs_handle *buf;
636
637 if ((transfer->resource->bind & PIPE_BIND_GLOBAL) && transfer->resource->target == PIPE_BUFFER) {
638 return r600_compute_global_transfer_unmap(ctx, transfer);
639 }
640
641 if (rtransfer->staging) {
642 buf = ((struct r600_resource *)rtransfer->staging)->cs_buf;
643 } else {
644 buf = ((struct r600_resource *)transfer->resource)->cs_buf;
645 }
646 rctx->ws->buffer_unmap(buf);
647 }
648
649 void r600_init_surface_functions(struct r600_context *r600)
650 {
651 r600->context.create_surface = r600_create_surface;
652 r600->context.surface_destroy = r600_surface_destroy;
653 }
654
655 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
656 const unsigned char *swizzle_view)
657 {
658 unsigned i;
659 unsigned char swizzle[4];
660 unsigned result = 0;
661 const uint32_t swizzle_shift[4] = {
662 16, 19, 22, 25,
663 };
664 const uint32_t swizzle_bit[4] = {
665 0, 1, 2, 3,
666 };
667
668 if (swizzle_view) {
669 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
670 } else {
671 memcpy(swizzle, swizzle_format, 4);
672 }
673
674 /* Get swizzle. */
675 for (i = 0; i < 4; i++) {
676 switch (swizzle[i]) {
677 case UTIL_FORMAT_SWIZZLE_Y:
678 result |= swizzle_bit[1] << swizzle_shift[i];
679 break;
680 case UTIL_FORMAT_SWIZZLE_Z:
681 result |= swizzle_bit[2] << swizzle_shift[i];
682 break;
683 case UTIL_FORMAT_SWIZZLE_W:
684 result |= swizzle_bit[3] << swizzle_shift[i];
685 break;
686 case UTIL_FORMAT_SWIZZLE_0:
687 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
688 break;
689 case UTIL_FORMAT_SWIZZLE_1:
690 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
691 break;
692 default: /* UTIL_FORMAT_SWIZZLE_X */
693 result |= swizzle_bit[0] << swizzle_shift[i];
694 }
695 }
696 return result;
697 }
698
699 /* texture format translate */
700 uint32_t r600_translate_texformat(struct pipe_screen *screen,
701 enum pipe_format format,
702 const unsigned char *swizzle_view,
703 uint32_t *word4_p, uint32_t *yuv_format_p)
704 {
705 uint32_t result = 0, word4 = 0, yuv_format = 0;
706 const struct util_format_description *desc;
707 boolean uniform = TRUE;
708 static int r600_enable_s3tc = -1;
709 bool is_srgb_valid = FALSE;
710
711 int i;
712 const uint32_t sign_bit[4] = {
713 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
714 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
715 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
716 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
717 };
718 desc = util_format_description(format);
719
720 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
721
722 /* Colorspace (return non-RGB formats directly). */
723 switch (desc->colorspace) {
724 /* Depth stencil formats */
725 case UTIL_FORMAT_COLORSPACE_ZS:
726 switch (format) {
727 case PIPE_FORMAT_Z16_UNORM:
728 result = FMT_16;
729 goto out_word4;
730 case PIPE_FORMAT_X24S8_UINT:
731 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
732 case PIPE_FORMAT_Z24X8_UNORM:
733 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
734 result = FMT_8_24;
735 goto out_word4;
736 case PIPE_FORMAT_S8X24_UINT:
737 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
738 case PIPE_FORMAT_X8Z24_UNORM:
739 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
740 result = FMT_24_8;
741 goto out_word4;
742 case PIPE_FORMAT_S8_UINT:
743 result = FMT_8;
744 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
745 goto out_word4;
746 case PIPE_FORMAT_Z32_FLOAT:
747 result = FMT_32_FLOAT;
748 goto out_word4;
749 case PIPE_FORMAT_X32_S8X24_UINT:
750 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
751 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
752 result = FMT_X24_8_32_FLOAT;
753 goto out_word4;
754 default:
755 goto out_unknown;
756 }
757
758 case UTIL_FORMAT_COLORSPACE_YUV:
759 yuv_format |= (1 << 30);
760 switch (format) {
761 case PIPE_FORMAT_UYVY:
762 case PIPE_FORMAT_YUYV:
763 default:
764 break;
765 }
766 goto out_unknown; /* XXX */
767
768 case UTIL_FORMAT_COLORSPACE_SRGB:
769 word4 |= S_038010_FORCE_DEGAMMA(1);
770 break;
771
772 default:
773 break;
774 }
775
776 if (r600_enable_s3tc == -1) {
777 struct r600_screen *rscreen = (struct r600_screen *)screen;
778 if (rscreen->info.drm_minor >= 9)
779 r600_enable_s3tc = 1;
780 else
781 r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
782 }
783
784 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
785 if (!r600_enable_s3tc)
786 goto out_unknown;
787
788 switch (format) {
789 case PIPE_FORMAT_RGTC1_SNORM:
790 case PIPE_FORMAT_LATC1_SNORM:
791 word4 |= sign_bit[0];
792 case PIPE_FORMAT_RGTC1_UNORM:
793 case PIPE_FORMAT_LATC1_UNORM:
794 result = FMT_BC4;
795 goto out_word4;
796 case PIPE_FORMAT_RGTC2_SNORM:
797 case PIPE_FORMAT_LATC2_SNORM:
798 word4 |= sign_bit[0] | sign_bit[1];
799 case PIPE_FORMAT_RGTC2_UNORM:
800 case PIPE_FORMAT_LATC2_UNORM:
801 result = FMT_BC5;
802 goto out_word4;
803 default:
804 goto out_unknown;
805 }
806 }
807
808 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
809
810 if (!r600_enable_s3tc)
811 goto out_unknown;
812
813 if (!util_format_s3tc_enabled) {
814 goto out_unknown;
815 }
816
817 switch (format) {
818 case PIPE_FORMAT_DXT1_RGB:
819 case PIPE_FORMAT_DXT1_RGBA:
820 case PIPE_FORMAT_DXT1_SRGB:
821 case PIPE_FORMAT_DXT1_SRGBA:
822 result = FMT_BC1;
823 is_srgb_valid = TRUE;
824 goto out_word4;
825 case PIPE_FORMAT_DXT3_RGBA:
826 case PIPE_FORMAT_DXT3_SRGBA:
827 result = FMT_BC2;
828 is_srgb_valid = TRUE;
829 goto out_word4;
830 case PIPE_FORMAT_DXT5_RGBA:
831 case PIPE_FORMAT_DXT5_SRGBA:
832 result = FMT_BC3;
833 is_srgb_valid = TRUE;
834 goto out_word4;
835 default:
836 goto out_unknown;
837 }
838 }
839
840 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
841 switch (format) {
842 case PIPE_FORMAT_R8G8_B8G8_UNORM:
843 case PIPE_FORMAT_G8R8_B8R8_UNORM:
844 result = FMT_GB_GR;
845 goto out_word4;
846 case PIPE_FORMAT_G8R8_G8B8_UNORM:
847 case PIPE_FORMAT_R8G8_R8B8_UNORM:
848 result = FMT_BG_RG;
849 goto out_word4;
850 default:
851 goto out_unknown;
852 }
853 }
854
855 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
856 result = FMT_5_9_9_9_SHAREDEXP;
857 goto out_word4;
858 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
859 result = FMT_10_11_11_FLOAT;
860 goto out_word4;
861 }
862
863
864 for (i = 0; i < desc->nr_channels; i++) {
865 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
866 word4 |= sign_bit[i];
867 }
868 }
869
870 /* R8G8Bx_SNORM - XXX CxV8U8 */
871
872 /* See whether the components are of the same size. */
873 for (i = 1; i < desc->nr_channels; i++) {
874 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
875 }
876
877 /* Non-uniform formats. */
878 if (!uniform) {
879 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
880 desc->channel[0].pure_integer)
881 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
882 switch(desc->nr_channels) {
883 case 3:
884 if (desc->channel[0].size == 5 &&
885 desc->channel[1].size == 6 &&
886 desc->channel[2].size == 5) {
887 result = FMT_5_6_5;
888 goto out_word4;
889 }
890 goto out_unknown;
891 case 4:
892 if (desc->channel[0].size == 5 &&
893 desc->channel[1].size == 5 &&
894 desc->channel[2].size == 5 &&
895 desc->channel[3].size == 1) {
896 result = FMT_1_5_5_5;
897 goto out_word4;
898 }
899 if (desc->channel[0].size == 10 &&
900 desc->channel[1].size == 10 &&
901 desc->channel[2].size == 10 &&
902 desc->channel[3].size == 2) {
903 result = FMT_2_10_10_10;
904 goto out_word4;
905 }
906 goto out_unknown;
907 }
908 goto out_unknown;
909 }
910
911 /* Find the first non-VOID channel. */
912 for (i = 0; i < 4; i++) {
913 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
914 break;
915 }
916 }
917
918 if (i == 4)
919 goto out_unknown;
920
921 /* uniform formats */
922 switch (desc->channel[i].type) {
923 case UTIL_FORMAT_TYPE_UNSIGNED:
924 case UTIL_FORMAT_TYPE_SIGNED:
925 #if 0
926 if (!desc->channel[i].normalized &&
927 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
928 goto out_unknown;
929 }
930 #endif
931 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
932 desc->channel[i].pure_integer)
933 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
934
935 switch (desc->channel[i].size) {
936 case 4:
937 switch (desc->nr_channels) {
938 case 2:
939 result = FMT_4_4;
940 goto out_word4;
941 case 4:
942 result = FMT_4_4_4_4;
943 goto out_word4;
944 }
945 goto out_unknown;
946 case 8:
947 switch (desc->nr_channels) {
948 case 1:
949 result = FMT_8;
950 goto out_word4;
951 case 2:
952 result = FMT_8_8;
953 goto out_word4;
954 case 4:
955 result = FMT_8_8_8_8;
956 is_srgb_valid = TRUE;
957 goto out_word4;
958 }
959 goto out_unknown;
960 case 16:
961 switch (desc->nr_channels) {
962 case 1:
963 result = FMT_16;
964 goto out_word4;
965 case 2:
966 result = FMT_16_16;
967 goto out_word4;
968 case 4:
969 result = FMT_16_16_16_16;
970 goto out_word4;
971 }
972 goto out_unknown;
973 case 32:
974 switch (desc->nr_channels) {
975 case 1:
976 result = FMT_32;
977 goto out_word4;
978 case 2:
979 result = FMT_32_32;
980 goto out_word4;
981 case 4:
982 result = FMT_32_32_32_32;
983 goto out_word4;
984 }
985 }
986 goto out_unknown;
987
988 case UTIL_FORMAT_TYPE_FLOAT:
989 switch (desc->channel[i].size) {
990 case 16:
991 switch (desc->nr_channels) {
992 case 1:
993 result = FMT_16_FLOAT;
994 goto out_word4;
995 case 2:
996 result = FMT_16_16_FLOAT;
997 goto out_word4;
998 case 4:
999 result = FMT_16_16_16_16_FLOAT;
1000 goto out_word4;
1001 }
1002 goto out_unknown;
1003 case 32:
1004 switch (desc->nr_channels) {
1005 case 1:
1006 result = FMT_32_FLOAT;
1007 goto out_word4;
1008 case 2:
1009 result = FMT_32_32_FLOAT;
1010 goto out_word4;
1011 case 4:
1012 result = FMT_32_32_32_32_FLOAT;
1013 goto out_word4;
1014 }
1015 }
1016 goto out_unknown;
1017 }
1018
1019 out_word4:
1020
1021 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid)
1022 return ~0;
1023 if (word4_p)
1024 *word4_p = word4;
1025 if (yuv_format_p)
1026 *yuv_format_p = yuv_format;
1027 return result;
1028 out_unknown:
1029 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1030 return ~0;
1031 }