2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "r600_formats.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
34 /* Copy from a full GPU texture to a transfer's staging one. */
35 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
37 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
38 struct pipe_resource
*texture
= transfer
->resource
;
40 ctx
->resource_copy_region(ctx
, &rtransfer
->staging
->b
.b
,
41 0, 0, 0, 0, texture
, transfer
->level
,
46 /* Copy from a transfer's staging texture to a full GPU one. */
47 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
49 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
50 struct pipe_resource
*texture
= transfer
->resource
;
53 u_box_origin_2d(transfer
->box
.width
, transfer
->box
.height
, &sbox
);
55 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
56 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
57 &rtransfer
->staging
->b
.b
,
61 unsigned r600_texture_get_offset(struct r600_texture
*rtex
,
62 unsigned level
, unsigned layer
)
64 return rtex
->surface
.level
[level
].offset
+
65 layer
* rtex
->surface
.level
[level
].slice_size
;
68 static int r600_init_surface(struct r600_screen
*rscreen
,
69 struct radeon_surface
*surface
,
70 const struct pipe_resource
*ptex
,
72 bool is_transfer
, bool is_flushed_depth
)
74 const struct util_format_description
*desc
=
75 util_format_description(ptex
->format
);
76 bool is_depth
, is_stencil
;
78 is_depth
= util_format_has_depth(desc
);
79 is_stencil
= util_format_has_stencil(desc
);
81 surface
->npix_x
= ptex
->width0
;
82 surface
->npix_y
= ptex
->height0
;
83 surface
->npix_z
= ptex
->depth0
;
84 surface
->blk_w
= util_format_get_blockwidth(ptex
->format
);
85 surface
->blk_h
= util_format_get_blockheight(ptex
->format
);
87 surface
->array_size
= 1;
88 surface
->last_level
= ptex
->last_level
;
90 if (rscreen
->chip_class
>= EVERGREEN
&&
91 !is_transfer
&& !is_flushed_depth
&&
92 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
93 surface
->bpe
= 4; /* stencil is allocated separately on evergreen */
95 surface
->bpe
= util_format_get_blocksize(ptex
->format
);
96 /* align byte per element on dword */
97 if (surface
->bpe
== 3) {
102 surface
->nsamples
= ptex
->nr_samples
? ptex
->nr_samples
: 1;
105 switch (array_mode
) {
106 case V_038000_ARRAY_1D_TILED_THIN1
:
107 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_1D
, MODE
);
109 case V_038000_ARRAY_2D_TILED_THIN1
:
110 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_2D
, MODE
);
112 case V_038000_ARRAY_LINEAR_ALIGNED
:
113 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED
, MODE
);
115 case V_038000_ARRAY_LINEAR_GENERAL
:
117 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR
, MODE
);
120 switch (ptex
->target
) {
121 case PIPE_TEXTURE_1D
:
122 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D
, TYPE
);
124 case PIPE_TEXTURE_RECT
:
125 case PIPE_TEXTURE_2D
:
126 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D
, TYPE
);
128 case PIPE_TEXTURE_3D
:
129 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_3D
, TYPE
);
131 case PIPE_TEXTURE_1D_ARRAY
:
132 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY
, TYPE
);
133 surface
->array_size
= ptex
->array_size
;
135 case PIPE_TEXTURE_2D_ARRAY
:
136 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY
, TYPE
);
137 surface
->array_size
= ptex
->array_size
;
139 case PIPE_TEXTURE_CUBE
:
140 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP
, TYPE
);
146 if (ptex
->bind
& PIPE_BIND_SCANOUT
) {
147 surface
->flags
|= RADEON_SURF_SCANOUT
;
150 if (!is_transfer
&& !is_flushed_depth
&& is_depth
) {
151 surface
->flags
|= RADEON_SURF_ZBUFFER
;
154 surface
->flags
|= RADEON_SURF_SBUFFER
;
160 static int r600_setup_surface(struct pipe_screen
*screen
,
161 struct r600_texture
*rtex
,
162 unsigned pitch_in_bytes_override
)
164 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
;
165 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
169 r
= rscreen
->ws
->surface_init(rscreen
->ws
, &rtex
->surface
);
173 rtex
->size
= rtex
->surface
.bo_size
;
174 if (pitch_in_bytes_override
&& pitch_in_bytes_override
!= rtex
->surface
.level
[0].pitch_bytes
) {
175 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
178 rtex
->surface
.level
[0].nblk_x
= pitch_in_bytes_override
/ rtex
->surface
.bpe
;
179 rtex
->surface
.level
[0].pitch_bytes
= pitch_in_bytes_override
;
180 rtex
->surface
.level
[0].slice_size
= pitch_in_bytes_override
* rtex
->surface
.level
[0].nblk_y
;
181 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
182 rtex
->surface
.stencil_offset
= rtex
->surface
.level
[0].slice_size
;
185 for (i
= 0; i
<= ptex
->last_level
; i
++) {
186 switch (rtex
->surface
.level
[i
].mode
) {
187 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
188 rtex
->array_mode
[i
] = V_038000_ARRAY_LINEAR_ALIGNED
;
190 case RADEON_SURF_MODE_1D
:
191 rtex
->array_mode
[i
] = V_038000_ARRAY_1D_TILED_THIN1
;
193 case RADEON_SURF_MODE_2D
:
194 rtex
->array_mode
[i
] = V_038000_ARRAY_2D_TILED_THIN1
;
197 case RADEON_SURF_MODE_LINEAR
:
198 rtex
->array_mode
[i
] = 0;
205 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
206 struct pipe_resource
*ptex
,
207 struct winsys_handle
*whandle
)
209 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
210 struct r600_resource
*resource
= &rtex
->resource
;
211 struct radeon_surface
*surface
= &rtex
->surface
;
212 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
214 rscreen
->ws
->buffer_set_tiling(resource
->buf
,
216 surface
->level
[0].mode
>= RADEON_SURF_MODE_1D
?
217 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
,
218 surface
->level
[0].mode
>= RADEON_SURF_MODE_2D
?
219 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
,
220 surface
->bankw
, surface
->bankh
,
222 surface
->stencil_tile_split
,
224 rtex
->surface
.level
[0].pitch_bytes
);
226 return rscreen
->ws
->buffer_get_handle(resource
->buf
,
227 rtex
->surface
.level
[0].pitch_bytes
, whandle
);
230 static void r600_texture_destroy(struct pipe_screen
*screen
,
231 struct pipe_resource
*ptex
)
233 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
234 struct r600_resource
*resource
= &rtex
->resource
;
236 if (rtex
->flushed_depth_texture
)
237 pipe_resource_reference((struct pipe_resource
**)&rtex
->flushed_depth_texture
, NULL
);
239 pb_reference(&resource
->buf
, NULL
);
243 static const struct u_resource_vtbl r600_texture_vtbl
=
245 r600_texture_get_handle
, /* get_handle */
246 r600_texture_destroy
, /* resource_destroy */
247 r600_texture_get_transfer
, /* get_transfer */
248 r600_texture_transfer_destroy
, /* transfer_destroy */
249 r600_texture_transfer_map
, /* transfer_map */
250 NULL
, /* transfer_flush_region */
251 r600_texture_transfer_unmap
, /* transfer_unmap */
252 NULL
/* transfer_inline_write */
255 /* The number of samples can be specified independently of the texture. */
256 void r600_texture_get_fmask_info(struct r600_screen
*rscreen
,
257 struct r600_texture
*rtex
,
259 struct r600_fmask_info
*out
)
261 /* FMASK is allocated pretty much like an ordinary texture.
262 * Here we use bpe in the units of bits, not bytes. */
263 struct radeon_surface fmask
= rtex
->surface
;
265 switch (nr_samples
) {
267 /* This should be 8,1, but we should set nsamples > 1
268 * for the allocator to treat it as a multisample surface.
269 * Let's set 4,2 then. */
283 R600_ERR("Invalid sample count for FMASK allocation.\n");
287 /* R600-R700 errata? Anyway, this fixes colorbuffer corruption. */
288 if (rscreen
->chip_class
<= R700
) {
292 if (rscreen
->chip_class
>= EVERGREEN
) {
293 fmask
.bankh
= nr_samples
<= 4 ? 4 : 1;
296 if (rscreen
->ws
->surface_init(rscreen
->ws
, &fmask
)) {
297 R600_ERR("Got error in surface_init while allocating FMASK.\n");
300 assert(fmask
.level
[0].mode
== RADEON_SURF_MODE_2D
);
302 out
->bank_height
= fmask
.bankh
;
303 out
->alignment
= MAX2(256, fmask
.bo_alignment
);
304 out
->size
= (fmask
.bo_size
+ 7) / 8;
307 static void r600_texture_allocate_fmask(struct r600_screen
*rscreen
,
308 struct r600_texture
*rtex
)
310 struct r600_fmask_info fmask
;
312 r600_texture_get_fmask_info(rscreen
, rtex
,
313 rtex
->resource
.b
.b
.nr_samples
, &fmask
);
315 /* Reserve space for FMASK while converting bits back to bytes. */
316 rtex
->fmask_bank_height
= fmask
.bank_height
;
317 rtex
->fmask_offset
= align(rtex
->size
, fmask
.alignment
);
318 rtex
->fmask_size
= fmask
.size
;
319 rtex
->size
= rtex
->fmask_offset
+ rtex
->fmask_size
;
321 printf("FMASK width=%u, height=%i, bits=%u, size=%u\n",
322 fmask
.npix_x
, fmask
.npix_y
, fmask
.bpe
* fmask
.nsamples
, rtex
->fmask_size
);
326 void r600_texture_get_cmask_info(struct r600_screen
*rscreen
,
327 struct r600_texture
*rtex
,
328 struct r600_cmask_info
*out
)
330 unsigned cmask_tile_width
= 8;
331 unsigned cmask_tile_height
= 8;
332 unsigned cmask_tile_elements
= cmask_tile_width
* cmask_tile_height
;
333 unsigned element_bits
= 4;
334 unsigned cmask_cache_bits
= 1024;
335 unsigned num_pipes
= rscreen
->tiling_info
.num_channels
;
336 unsigned pipe_interleave_bytes
= rscreen
->tiling_info
.group_bytes
;
338 unsigned elements_per_macro_tile
= (cmask_cache_bits
/ element_bits
) * num_pipes
;
339 unsigned pixels_per_macro_tile
= elements_per_macro_tile
* cmask_tile_elements
;
340 unsigned sqrt_pixels_per_macro_tile
= sqrt(pixels_per_macro_tile
);
341 unsigned macro_tile_width
= util_next_power_of_two(sqrt_pixels_per_macro_tile
);
342 unsigned macro_tile_height
= pixels_per_macro_tile
/ macro_tile_width
;
344 unsigned pitch_elements
= align(rtex
->surface
.npix_x
, macro_tile_width
);
345 unsigned height
= align(rtex
->surface
.npix_y
, macro_tile_height
);
347 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
348 unsigned slice_bytes
=
349 ((pitch_elements
* height
* element_bits
+ 7) / 8) / cmask_tile_elements
;
351 assert(macro_tile_width
% 128 == 0);
352 assert(macro_tile_height
% 128 == 0);
354 out
->slice_tile_max
= ((pitch_elements
* height
) / (128*128)) - 1;
355 out
->alignment
= MAX2(256, base_align
);
356 out
->size
= rtex
->surface
.array_size
* align(slice_bytes
, base_align
);
359 static void r600_texture_allocate_cmask(struct r600_screen
*rscreen
,
360 struct r600_texture
*rtex
)
362 struct r600_cmask_info cmask
;
364 r600_texture_get_cmask_info(rscreen
, rtex
, &cmask
);
366 rtex
->cmask_slice_tile_max
= cmask
.slice_tile_max
;
367 rtex
->cmask_offset
= align(rtex
->size
, cmask
.alignment
);
368 rtex
->cmask_size
= cmask
.size
;
369 rtex
->size
= rtex
->cmask_offset
+ rtex
->cmask_size
;
371 printf("CMASK: macro tile width = %u, macro tile height = %u, "
372 "pitch elements = %u, height = %u, slice tile max = %u\n",
373 macro_tile_width
, macro_tile_height
, pitch_elements
, height
,
374 rtex
->cmask_slice_tile_max
);
378 static struct r600_texture
*
379 r600_texture_create_object(struct pipe_screen
*screen
,
380 const struct pipe_resource
*base
,
381 unsigned pitch_in_bytes_override
,
382 struct pb_buffer
*buf
,
384 struct radeon_surface
*surface
)
386 struct r600_texture
*rtex
;
387 struct r600_resource
*resource
;
388 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
391 rtex
= CALLOC_STRUCT(r600_texture
);
395 resource
= &rtex
->resource
;
396 resource
->b
.b
= *base
;
397 resource
->b
.vtbl
= &r600_texture_vtbl
;
398 pipe_reference_init(&resource
->b
.b
.reference
, 1);
399 resource
->b
.b
.screen
= screen
;
400 rtex
->pitch_override
= pitch_in_bytes_override
;
402 /* don't include stencil-only formats which we don't support for rendering */
403 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
405 rtex
->surface
= *surface
;
406 r
= r600_setup_surface(screen
, rtex
,
407 pitch_in_bytes_override
);
413 if (base
->nr_samples
> 1 && !rtex
->is_depth
&& alloc_bo
) {
414 r600_texture_allocate_cmask(rscreen
, rtex
);
415 r600_texture_allocate_fmask(rscreen
, rtex
);
418 if (!rtex
->is_depth
&& base
->nr_samples
> 1 &&
419 (!rtex
->fmask_size
|| !rtex
->cmask_size
)) {
424 /* Now create the backing buffer. */
425 if (!buf
&& alloc_bo
) {
426 unsigned base_align
= rtex
->surface
.bo_alignment
;
427 unsigned usage
= R600_TEX_IS_TILED(rtex
, 0) ? PIPE_USAGE_STATIC
: base
->usage
;
429 if (!r600_init_resource(rscreen
, resource
, rtex
->size
, base_align
, base
->bind
, usage
)) {
435 resource
->cs_buf
= rscreen
->ws
->buffer_get_cs_handle(buf
);
436 resource
->domains
= RADEON_DOMAIN_GTT
| RADEON_DOMAIN_VRAM
;
439 if (rtex
->cmask_size
) {
440 /* Initialize the cmask to 0xCC (= compressed state). */
441 char *ptr
= rscreen
->ws
->buffer_map(resource
->cs_buf
, NULL
, PIPE_TRANSFER_WRITE
);
442 memset(ptr
+ rtex
->cmask_offset
, 0xCC, rtex
->cmask_size
);
443 rscreen
->ws
->buffer_unmap(resource
->cs_buf
);
448 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
449 const struct pipe_resource
*templ
)
451 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
452 struct radeon_surface surface
;
453 unsigned array_mode
= 0;
456 if (!(templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)) {
457 if (!(templ
->bind
& PIPE_BIND_SCANOUT
) &&
458 templ
->usage
!= PIPE_USAGE_STAGING
&&
459 templ
->usage
!= PIPE_USAGE_STREAM
) {
460 array_mode
= V_038000_ARRAY_2D_TILED_THIN1
;
461 } else if (util_format_is_compressed(templ
->format
)) {
462 array_mode
= V_038000_ARRAY_1D_TILED_THIN1
;
466 /* XXX tiling is broken for the 422 formats */
467 if (util_format_description(templ
->format
)->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
468 array_mode
= V_038000_ARRAY_LINEAR_ALIGNED
;
470 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
,
471 templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
,
472 templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
);
476 r
= rscreen
->ws
->surface_best(rscreen
->ws
, &surface
);
480 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
,
481 0, NULL
, TRUE
, &surface
);
484 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
485 struct pipe_resource
*texture
,
486 const struct pipe_surface
*templ
)
488 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
489 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
490 unsigned level
= templ
->u
.tex
.level
;
492 assert(templ
->u
.tex
.first_layer
== templ
->u
.tex
.last_layer
);
495 pipe_reference_init(&surface
->base
.reference
, 1);
496 pipe_resource_reference(&surface
->base
.texture
, texture
);
497 surface
->base
.context
= pipe
;
498 surface
->base
.format
= templ
->format
;
499 surface
->base
.width
= rtex
->surface
.level
[level
].npix_x
;
500 surface
->base
.height
= rtex
->surface
.level
[level
].npix_y
;
501 surface
->base
.usage
= templ
->usage
;
502 surface
->base
.u
= templ
->u
;
503 return &surface
->base
;
506 static void r600_surface_destroy(struct pipe_context
*pipe
,
507 struct pipe_surface
*surface
)
509 struct r600_surface
*surf
= (struct r600_surface
*)surface
;
510 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_fmask
, NULL
);
511 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_cmask
, NULL
);
512 pipe_resource_reference(&surface
->texture
, NULL
);
516 struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
517 const struct pipe_resource
*templ
,
518 struct winsys_handle
*whandle
)
520 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
521 struct pb_buffer
*buf
= NULL
;
523 unsigned array_mode
= 0;
524 enum radeon_bo_layout micro
, macro
;
525 struct radeon_surface surface
;
528 /* Support only 2D textures without mipmaps */
529 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
530 templ
->depth0
!= 1 || templ
->last_level
!= 0)
533 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
);
537 rscreen
->ws
->buffer_get_tiling(buf
, µ
, ¯o
,
538 &surface
.bankw
, &surface
.bankh
,
540 &surface
.stencil_tile_split
,
543 if (macro
== RADEON_LAYOUT_TILED
)
544 array_mode
= V_0280A0_ARRAY_2D_TILED_THIN1
;
545 else if (micro
== RADEON_LAYOUT_TILED
)
546 array_mode
= V_0280A0_ARRAY_1D_TILED_THIN1
;
550 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
, false, false);
554 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
,
555 stride
, buf
, FALSE
, &surface
);
558 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
559 struct pipe_resource
*texture
,
560 struct r600_texture
**staging
)
562 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
563 struct pipe_resource resource
;
564 struct r600_texture
**flushed_depth_texture
= staging
?
565 staging
: &rtex
->flushed_depth_texture
;
567 if (!staging
&& rtex
->flushed_depth_texture
)
568 return true; /* it's ready */
570 resource
.target
= texture
->target
;
571 resource
.format
= texture
->format
;
572 resource
.width0
= texture
->width0
;
573 resource
.height0
= texture
->height0
;
574 resource
.depth0
= texture
->depth0
;
575 resource
.array_size
= texture
->array_size
;
576 resource
.last_level
= texture
->last_level
;
577 resource
.nr_samples
= texture
->nr_samples
;
578 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_STATIC
;
579 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
580 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
583 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
585 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
586 if (*flushed_depth_texture
== NULL
) {
587 R600_ERR("failed to create temporary texture to hold flushed depth\n");
591 (*flushed_depth_texture
)->is_flushing_texture
= TRUE
;
595 /* Needs adjustment for pixelformat:
597 static INLINE
unsigned u_box_volume( const struct pipe_box
*box
)
599 return box
->width
* box
->depth
* box
->height
;
602 struct pipe_transfer
* r600_texture_get_transfer(struct pipe_context
*ctx
,
603 struct pipe_resource
*texture
,
606 const struct pipe_box
*box
)
608 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
609 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
610 struct pipe_resource resource
;
611 struct r600_transfer
*trans
;
612 boolean use_staging_texture
= FALSE
;
614 /* We cannot map a tiled texture directly because the data is
615 * in a different order, therefore we do detiling using a blit.
617 * Also, use a temporary in GTT memory for read transfers, as
618 * the CPU is much happier reading out of cached system memory
619 * than uncached VRAM.
621 if (R600_TEX_IS_TILED(rtex
, level
)) {
622 use_staging_texture
= TRUE
;
625 if ((usage
& PIPE_TRANSFER_READ
) && u_box_volume(box
) > 1024)
626 use_staging_texture
= TRUE
;
628 /* Use a staging texture for uploads if the underlying BO is busy. */
629 if (!(usage
& PIPE_TRANSFER_READ
) &&
630 (rctx
->ws
->cs_is_buffer_referenced(rctx
->cs
, rtex
->resource
.cs_buf
, RADEON_USAGE_READWRITE
) ||
631 rctx
->ws
->buffer_is_busy(rtex
->resource
.buf
, RADEON_USAGE_READWRITE
))) {
632 use_staging_texture
= TRUE
;
635 if (texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
) {
636 use_staging_texture
= FALSE
;
639 if (use_staging_texture
&& (usage
& PIPE_TRANSFER_MAP_DIRECTLY
)) {
643 trans
= CALLOC_STRUCT(r600_transfer
);
646 pipe_resource_reference(&trans
->transfer
.resource
, texture
);
647 trans
->transfer
.level
= level
;
648 trans
->transfer
.usage
= usage
;
649 trans
->transfer
.box
= *box
;
650 if (rtex
->is_depth
) {
651 /* XXX: only readback the rectangle which is being mapped?
653 /* XXX: when discard is true, no need to read back from depth texture
655 struct r600_texture
*staging_depth
;
657 if (!r600_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
658 R600_ERR("failed to create temporary texture to hold untiled copy\n");
659 pipe_resource_reference(&trans
->transfer
.resource
, NULL
);
664 r600_blit_decompress_depth(ctx
, rtex
, staging_depth
,
666 box
->z
, box
->z
+ box
->depth
- 1,
669 trans
->transfer
.stride
= staging_depth
->surface
.level
[level
].pitch_bytes
;
670 trans
->offset
= r600_texture_get_offset(staging_depth
, level
, box
->z
);
671 trans
->staging
= (struct r600_resource
*)staging_depth
;
672 return &trans
->transfer
;
673 } else if (use_staging_texture
) {
674 resource
.target
= PIPE_TEXTURE_2D
;
675 resource
.format
= texture
->format
;
676 resource
.width0
= box
->width
;
677 resource
.height0
= box
->height
;
679 resource
.array_size
= 1;
680 resource
.last_level
= 0;
681 resource
.nr_samples
= 0;
682 resource
.usage
= PIPE_USAGE_STAGING
;
684 resource
.flags
= R600_RESOURCE_FLAG_TRANSFER
;
685 /* For texture reading, the temporary (detiled) texture is used as
686 * a render target when blitting from a tiled texture. */
687 if (usage
& PIPE_TRANSFER_READ
) {
688 resource
.bind
|= PIPE_BIND_RENDER_TARGET
;
690 /* For texture writing, the temporary texture is used as a sampler
691 * when blitting into a tiled texture. */
692 if (usage
& PIPE_TRANSFER_WRITE
) {
693 resource
.bind
|= PIPE_BIND_SAMPLER_VIEW
;
695 /* Create the temporary texture. */
696 trans
->staging
= (struct r600_resource
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
697 if (trans
->staging
== NULL
) {
698 R600_ERR("failed to create temporary texture to hold untiled copy\n");
699 pipe_resource_reference(&trans
->transfer
.resource
, NULL
);
704 trans
->transfer
.stride
=
705 ((struct r600_texture
*)trans
->staging
)->surface
.level
[0].pitch_bytes
;
706 if (usage
& PIPE_TRANSFER_READ
) {
707 r600_copy_to_staging_texture(ctx
, trans
);
708 /* Always referenced in the blit. */
709 r600_flush(ctx
, NULL
, 0);
711 return &trans
->transfer
;
713 trans
->transfer
.stride
= rtex
->surface
.level
[level
].pitch_bytes
;
714 trans
->transfer
.layer_stride
= rtex
->surface
.level
[level
].slice_size
;
715 trans
->offset
= r600_texture_get_offset(rtex
, level
, box
->z
);
716 return &trans
->transfer
;
719 void r600_texture_transfer_destroy(struct pipe_context
*ctx
,
720 struct pipe_transfer
*transfer
)
722 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
723 struct pipe_resource
*texture
= transfer
->resource
;
724 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
726 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
727 if (rtex
->is_depth
) {
728 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
729 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
730 &rtransfer
->staging
->b
.b
, transfer
->level
,
733 r600_copy_from_staging_texture(ctx
, rtransfer
);
737 if (rtransfer
->staging
)
738 pipe_resource_reference((struct pipe_resource
**)&rtransfer
->staging
, NULL
);
740 pipe_resource_reference(&transfer
->resource
, NULL
);
744 void* r600_texture_transfer_map(struct pipe_context
*ctx
,
745 struct pipe_transfer
* transfer
)
747 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
748 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
749 struct radeon_winsys_cs_handle
*buf
;
750 struct r600_texture
*rtex
=
751 (struct r600_texture
*)transfer
->resource
;
752 enum pipe_format format
= transfer
->resource
->format
;
756 if ((transfer
->resource
->bind
& PIPE_BIND_GLOBAL
) && transfer
->resource
->target
== PIPE_BUFFER
) {
757 return r600_compute_global_transfer_map(ctx
, transfer
);
760 if (rtransfer
->staging
) {
761 buf
= ((struct r600_resource
*)rtransfer
->staging
)->cs_buf
;
763 buf
= ((struct r600_resource
*)transfer
->resource
)->cs_buf
;
766 if (rtex
->is_depth
|| !rtransfer
->staging
)
767 offset
= rtransfer
->offset
+
768 transfer
->box
.y
/ util_format_get_blockheight(format
) * transfer
->stride
+
769 transfer
->box
.x
/ util_format_get_blockwidth(format
) * util_format_get_blocksize(format
);
771 if (!(map
= rctx
->ws
->buffer_map(buf
, rctx
->cs
, transfer
->usage
))) {
778 void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
779 struct pipe_transfer
* transfer
)
781 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
782 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
783 struct radeon_winsys_cs_handle
*buf
;
785 if ((transfer
->resource
->bind
& PIPE_BIND_GLOBAL
) && transfer
->resource
->target
== PIPE_BUFFER
) {
786 return r600_compute_global_transfer_unmap(ctx
, transfer
);
789 if (rtransfer
->staging
) {
790 buf
= ((struct r600_resource
*)rtransfer
->staging
)->cs_buf
;
792 buf
= ((struct r600_resource
*)transfer
->resource
)->cs_buf
;
794 rctx
->ws
->buffer_unmap(buf
);
797 void r600_init_surface_functions(struct r600_context
*r600
)
799 r600
->context
.create_surface
= r600_create_surface
;
800 r600
->context
.surface_destroy
= r600_surface_destroy
;
803 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
804 const unsigned char *swizzle_view
)
807 unsigned char swizzle
[4];
809 const uint32_t swizzle_shift
[4] = {
812 const uint32_t swizzle_bit
[4] = {
817 util_format_compose_swizzles(swizzle_format
, swizzle_view
, swizzle
);
819 memcpy(swizzle
, swizzle_format
, 4);
823 for (i
= 0; i
< 4; i
++) {
824 switch (swizzle
[i
]) {
825 case UTIL_FORMAT_SWIZZLE_Y
:
826 result
|= swizzle_bit
[1] << swizzle_shift
[i
];
828 case UTIL_FORMAT_SWIZZLE_Z
:
829 result
|= swizzle_bit
[2] << swizzle_shift
[i
];
831 case UTIL_FORMAT_SWIZZLE_W
:
832 result
|= swizzle_bit
[3] << swizzle_shift
[i
];
834 case UTIL_FORMAT_SWIZZLE_0
:
835 result
|= V_038010_SQ_SEL_0
<< swizzle_shift
[i
];
837 case UTIL_FORMAT_SWIZZLE_1
:
838 result
|= V_038010_SQ_SEL_1
<< swizzle_shift
[i
];
840 default: /* UTIL_FORMAT_SWIZZLE_X */
841 result
|= swizzle_bit
[0] << swizzle_shift
[i
];
847 /* texture format translate */
848 uint32_t r600_translate_texformat(struct pipe_screen
*screen
,
849 enum pipe_format format
,
850 const unsigned char *swizzle_view
,
851 uint32_t *word4_p
, uint32_t *yuv_format_p
)
853 uint32_t result
= 0, word4
= 0, yuv_format
= 0;
854 const struct util_format_description
*desc
;
855 boolean uniform
= TRUE
;
856 static int r600_enable_s3tc
= -1;
857 bool is_srgb_valid
= FALSE
;
860 const uint32_t sign_bit
[4] = {
861 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED
),
862 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED
),
863 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED
),
864 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED
)
866 desc
= util_format_description(format
);
868 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
);
870 /* Colorspace (return non-RGB formats directly). */
871 switch (desc
->colorspace
) {
872 /* Depth stencil formats */
873 case UTIL_FORMAT_COLORSPACE_ZS
:
875 case PIPE_FORMAT_Z16_UNORM
:
878 case PIPE_FORMAT_X24S8_UINT
:
879 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
880 case PIPE_FORMAT_Z24X8_UNORM
:
881 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
884 case PIPE_FORMAT_S8X24_UINT
:
885 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
886 case PIPE_FORMAT_X8Z24_UNORM
:
887 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
890 case PIPE_FORMAT_S8_UINT
:
892 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
894 case PIPE_FORMAT_Z32_FLOAT
:
895 result
= FMT_32_FLOAT
;
897 case PIPE_FORMAT_X32_S8X24_UINT
:
898 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
899 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
900 result
= FMT_X24_8_32_FLOAT
;
906 case UTIL_FORMAT_COLORSPACE_YUV
:
907 yuv_format
|= (1 << 30);
909 case PIPE_FORMAT_UYVY
:
910 case PIPE_FORMAT_YUYV
:
914 goto out_unknown
; /* XXX */
916 case UTIL_FORMAT_COLORSPACE_SRGB
:
917 word4
|= S_038010_FORCE_DEGAMMA(1);
924 if (r600_enable_s3tc
== -1) {
925 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
926 if (rscreen
->info
.drm_minor
>= 9)
927 r600_enable_s3tc
= 1;
929 r600_enable_s3tc
= debug_get_bool_option("R600_ENABLE_S3TC", FALSE
);
932 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
933 if (!r600_enable_s3tc
)
937 case PIPE_FORMAT_RGTC1_SNORM
:
938 case PIPE_FORMAT_LATC1_SNORM
:
939 word4
|= sign_bit
[0];
940 case PIPE_FORMAT_RGTC1_UNORM
:
941 case PIPE_FORMAT_LATC1_UNORM
:
944 case PIPE_FORMAT_RGTC2_SNORM
:
945 case PIPE_FORMAT_LATC2_SNORM
:
946 word4
|= sign_bit
[0] | sign_bit
[1];
947 case PIPE_FORMAT_RGTC2_UNORM
:
948 case PIPE_FORMAT_LATC2_UNORM
:
956 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
958 if (!r600_enable_s3tc
)
961 if (!util_format_s3tc_enabled
) {
966 case PIPE_FORMAT_DXT1_RGB
:
967 case PIPE_FORMAT_DXT1_RGBA
:
968 case PIPE_FORMAT_DXT1_SRGB
:
969 case PIPE_FORMAT_DXT1_SRGBA
:
971 is_srgb_valid
= TRUE
;
973 case PIPE_FORMAT_DXT3_RGBA
:
974 case PIPE_FORMAT_DXT3_SRGBA
:
976 is_srgb_valid
= TRUE
;
978 case PIPE_FORMAT_DXT5_RGBA
:
979 case PIPE_FORMAT_DXT5_SRGBA
:
981 is_srgb_valid
= TRUE
;
988 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
990 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
991 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
994 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
995 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
1003 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1004 result
= FMT_5_9_9_9_SHAREDEXP
;
1006 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1007 result
= FMT_10_11_11_FLOAT
;
1012 for (i
= 0; i
< desc
->nr_channels
; i
++) {
1013 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1014 word4
|= sign_bit
[i
];
1018 /* R8G8Bx_SNORM - XXX CxV8U8 */
1020 /* See whether the components are of the same size. */
1021 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1022 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1025 /* Non-uniform formats. */
1027 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
1028 desc
->channel
[0].pure_integer
)
1029 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1030 switch(desc
->nr_channels
) {
1032 if (desc
->channel
[0].size
== 5 &&
1033 desc
->channel
[1].size
== 6 &&
1034 desc
->channel
[2].size
== 5) {
1040 if (desc
->channel
[0].size
== 5 &&
1041 desc
->channel
[1].size
== 5 &&
1042 desc
->channel
[2].size
== 5 &&
1043 desc
->channel
[3].size
== 1) {
1044 result
= FMT_1_5_5_5
;
1047 if (desc
->channel
[0].size
== 10 &&
1048 desc
->channel
[1].size
== 10 &&
1049 desc
->channel
[2].size
== 10 &&
1050 desc
->channel
[3].size
== 2) {
1051 result
= FMT_2_10_10_10
;
1059 /* Find the first non-VOID channel. */
1060 for (i
= 0; i
< 4; i
++) {
1061 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1069 /* uniform formats */
1070 switch (desc
->channel
[i
].type
) {
1071 case UTIL_FORMAT_TYPE_UNSIGNED
:
1072 case UTIL_FORMAT_TYPE_SIGNED
:
1074 if (!desc
->channel
[i
].normalized
&&
1075 desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
) {
1079 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
1080 desc
->channel
[i
].pure_integer
)
1081 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1083 switch (desc
->channel
[i
].size
) {
1085 switch (desc
->nr_channels
) {
1090 result
= FMT_4_4_4_4
;
1095 switch (desc
->nr_channels
) {
1103 result
= FMT_8_8_8_8
;
1104 is_srgb_valid
= TRUE
;
1109 switch (desc
->nr_channels
) {
1117 result
= FMT_16_16_16_16
;
1122 switch (desc
->nr_channels
) {
1130 result
= FMT_32_32_32_32
;
1136 case UTIL_FORMAT_TYPE_FLOAT
:
1137 switch (desc
->channel
[i
].size
) {
1139 switch (desc
->nr_channels
) {
1141 result
= FMT_16_FLOAT
;
1144 result
= FMT_16_16_FLOAT
;
1147 result
= FMT_16_16_16_16_FLOAT
;
1152 switch (desc
->nr_channels
) {
1154 result
= FMT_32_FLOAT
;
1157 result
= FMT_32_32_FLOAT
;
1160 result
= FMT_32_32_32_32_FLOAT
;
1169 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
&& !is_srgb_valid
)
1174 *yuv_format_p
= yuv_format
;
1177 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */